JP4386851B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4386851B2 JP4386851B2 JP2005044820A JP2005044820A JP4386851B2 JP 4386851 B2 JP4386851 B2 JP 4386851B2 JP 2005044820 A JP2005044820 A JP 2005044820A JP 2005044820 A JP2005044820 A JP 2005044820A JP 4386851 B2 JP4386851 B2 JP 4386851B2
- Authority
- JP
- Japan
- Prior art keywords
- switch
- output
- pads
- input
- switches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005044820A JP4386851B2 (ja) | 2005-02-21 | 2005-02-21 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005044820A JP4386851B2 (ja) | 2005-02-21 | 2005-02-21 | 半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006229175A JP2006229175A (ja) | 2006-08-31 |
| JP2006229175A5 JP2006229175A5 (https=) | 2007-07-05 |
| JP4386851B2 true JP4386851B2 (ja) | 2009-12-16 |
Family
ID=36990225
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005044820A Expired - Fee Related JP4386851B2 (ja) | 2005-02-21 | 2005-02-21 | 半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4386851B2 (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016162925A (ja) * | 2015-03-03 | 2016-09-05 | 力晶科技股▲ふん▼有限公司 | Momキャパシタ回路及び半導体装置 |
| CN113225953B (zh) * | 2021-05-07 | 2022-12-13 | 江西雕视信息技术股份有限公司 | 一种可支持高分辨率点对点显示编码解码的装置及方法 |
-
2005
- 2005-02-21 JP JP2005044820A patent/JP4386851B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2006229175A (ja) | 2006-08-31 |
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