JP4376897B2 - プロセッサ電力状態を考慮するメモリコントローラ - Google Patents
プロセッサ電力状態を考慮するメモリコントローラ Download PDFInfo
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- JP4376897B2 JP4376897B2 JP2006500783A JP2006500783A JP4376897B2 JP 4376897 B2 JP4376897 B2 JP 4376897B2 JP 2006500783 A JP2006500783 A JP 2006500783A JP 2006500783 A JP2006500783 A JP 2006500783A JP 4376897 B2 JP4376897 B2 JP 4376897B2
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- 238000000034 method Methods 0.000 claims description 29
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- 230000008569 process Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 230000009467 reduction Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
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- 239000000284 extract Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3275—Power saving in memory, e.g. RAM, cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
- Controls And Circuits For Display Device (AREA)
- Exchange Systems With Centralized Control (AREA)
Description
本発明は、コンピュータシステム技術に関し、より詳細には、コンピュータシステムの電力消費を低減する方法及び装置に関する。
携帯情報端末(PDA)や携帯電話などの小型携帯電子装置からセットトップボックス、デジタルカメラや他の家電機器などの特定用途向け電子装置、ノートブック、サブノートブックやタブレットコンピュータなどの中型モバイルシステム、及びデスクトップシステム、ワークステーションやサーバまでのあらゆるシステムを含むコンピュータシステムが、世界中で普及している。
コンピュータシステムの電力消費を制御するための方法及びシステムが開示される。一実施例では、コンピュータシステムのプロセッサが低電力モードにあるとき、プロセッサに接続されるメモリの1以上のコンポーネント、及びメモリにリクエストを与えるに関するコントローラを有する他のシステムコンポーネントの電力消費は低減されるかもしれない。
Claims (3)
- プロセッサが低電力モードにおかれると、前記プロセッサに接続されるメモリの1以上のコンポーネントと、前記メモリを実行するのに必要なグラフィックコントローラの1以上のコンポーネントの電力消費を低減するため、チップセットが前記メモリと前記グラフィックコントローラとを低電力モードにおくステップと、
前記メモリと前記グラフィックコントローラとを低電力モードにおく前に、前記プロセッサが前記メモリから抽出される表示データのデータ量を増加するステップと、
から構成され、
前記表示データのデータ量は、前記メモリと前記グラフィックコントローラとに係るウェークアップ遅延時間に基づき決定され、
前記ウェークアップ遅延時間は、前記メモリから抽出される表示データを処理する時間より短く、前記メモリと前記グラフィックコントローラとを前記低電力モードから通常電力モードに復帰させるのに必要とされる時間を含む、
ことを特徴とする方法。 - 処理システムで実行されるとき、
プロセッサが低電力モードにおかれると、前記プロセッサに接続されるメモリの1以上のコンポーネントと前記メモリを前記プロセッサと共有するグラフィックコントローラの1以上のコンポーネントの電力消費を低減するため、チップセットが前記メモリと前記グラフィックコントローラとを低電力モードにおくステップと、
前記メモリと前記グラフィックコントローラとを低電力モードにおく前に、前記プロセッサが前記メモリから抽出される表示データのデータ量を増加するステップと、
から構成される方法を前記処理システムに実行させる実行可能な命令を有することを特徴とするコンピュータ可読媒体であって、
前記表示データのデータ量は、前記メモリと前記グラフィックコントローラとに係るウェークアップ遅延時間に基づき決定され、
前記ウェークアップ遅延時間は、前記メモリから抽出される表示データを処理する時間より短く、前記メモリと前記グラフィックコントローラとを前記低電力モードから通常電力モードに復帰させるのに必要とされる時間を含む、
ことを特徴とするコンピュータ可読媒体。 - プロセッサと、
前記プロセッサに接続されるメモリと、
前記プロセッサと前記メモリとに接続されるグラフィックコントローラと、
から構成されるシステムであって、
前記グラフィックコントローラと前記プロセッサは前記メモリを共有し、
前記プロセッサが低電力モードにおかれると、前記メモリの1以上のコンポーネントと前記グラフィックコントローラの1以上のコンポーネントの電力消費を低減するため、チップセットによって前記グラフィックコントローラと前記メモリとが低電力モードにおかれ、
前記グラフィックコントローラと前記メモリとを低電力モードにおく前に、前記プロセッサによって前記メモリから抽出される表示データのデータ量が増加され、
前記表示データのデータ量は、前記メモリと前記グラフィックコントローラとに係るウェークアップ遅延時間に基づき決定され、
前記ウェークアップ遅延時間は、前記メモリから抽出される表示データを処理する時間より短く、前記メモリと前記グラフィックコントローラとを前記低電力モードから通常電力モードに復帰させるのに必要とされる時間を含む、
ことを特徴とするシステム。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/340,020 US6971034B2 (en) | 2003-01-09 | 2003-01-09 | Power/performance optimized memory controller considering processor power states |
PCT/US2004/000092 WO2004063916A2 (en) | 2003-01-09 | 2004-01-02 | Memory controller considering processor power states |
Publications (2)
Publication Number | Publication Date |
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JP2006517315A JP2006517315A (ja) | 2006-07-20 |
JP4376897B2 true JP4376897B2 (ja) | 2009-12-02 |
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JP2006500783A Expired - Fee Related JP4376897B2 (ja) | 2003-01-09 | 2004-01-02 | プロセッサ電力状態を考慮するメモリコントローラ |
Country Status (10)
Country | Link |
---|---|
US (1) | US6971034B2 (ja) |
EP (1) | EP1581856B1 (ja) |
JP (1) | JP4376897B2 (ja) |
KR (1) | KR100692345B1 (ja) |
CN (1) | CN100399235C (ja) |
AT (1) | ATE451644T1 (ja) |
DE (1) | DE602004024499D1 (ja) |
HK (1) | HK1075520A1 (ja) |
TW (1) | TWI245180B (ja) |
WO (1) | WO2004063916A2 (ja) |
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-
2003
- 2003-01-09 US US10/340,020 patent/US6971034B2/en not_active Expired - Lifetime
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2004
- 2004-01-02 WO PCT/US2004/000092 patent/WO2004063916A2/en active Application Filing
- 2004-01-02 AT AT04700069T patent/ATE451644T1/de not_active IP Right Cessation
- 2004-01-02 DE DE602004024499T patent/DE602004024499D1/de not_active Expired - Lifetime
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- 2004-01-02 JP JP2006500783A patent/JP4376897B2/ja not_active Expired - Fee Related
- 2004-01-02 KR KR1020057012853A patent/KR100692345B1/ko not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
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US6971034B2 (en) | 2005-11-29 |
DE602004024499D1 (de) | 2010-01-21 |
EP1581856A2 (en) | 2005-10-05 |
JP2006517315A (ja) | 2006-07-20 |
EP1581856B1 (en) | 2009-12-09 |
KR100692345B1 (ko) | 2007-03-12 |
KR20050091777A (ko) | 2005-09-15 |
WO2004063916A2 (en) | 2004-07-29 |
CN100399235C (zh) | 2008-07-02 |
TWI245180B (en) | 2005-12-11 |
WO2004063916A3 (en) | 2005-04-14 |
TW200421077A (en) | 2004-10-16 |
HK1075520A1 (en) | 2005-12-16 |
ATE451644T1 (de) | 2009-12-15 |
CN1723430A (zh) | 2006-01-18 |
US20040139359A1 (en) | 2004-07-15 |
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