JP4371088B2 - Ferroelectric memory - Google Patents

Description

  The present invention relates to a ferroelectric memory (FeRAM) using a ferroelectric capacitor as a storage medium. More specifically, the present invention relates to a data reading technique in a ferroelectric memory.

  FIG. 7 is a block circuit diagram of a main part of an example of a conventional ferroelectric memory, and FIG. 8 is a detailed circuit diagram thereof (see, for example, Patent Document 1). 7 and 8, 1 is a 2-transistor / 2-capacitor (2T / 2C-type) memory cell, WL is a word line, PL is a plate line, BL and BLX are bit lines, 2 and 3 are pre-sense amplifiers, 4 Is a threshold generation circuit, 5 is a negative voltage generation circuit, 6 is a sense amplifier, 7 and 8 are Schmitt trigger circuits, and 9 is a NAND gate.

  Actually, a large number of memory cells are arranged vertically and horizontally, but only one memory cell is shown here, and the other memory cells are not shown. The pre-sense amplifiers 2 and 3, the sense amplifier 6, the Schmitt trigger circuits 7 and 8, and the NAND gate 9 constitute a read circuit. Although there are actually a plurality of such read circuits, FIG. The illustration is omitted except for the readout circuit shown in FIG. The threshold value generation circuit 4 and the negative voltage generation circuit 5 are shared by a plurality of readout circuits.

  The memory cell 1 includes ferroelectric capacitors F1 and F2 that form a storage medium, and access transistors N1 and N2 including N-channel MOS transistors (hereinafter referred to as NMOS transistors).

  The access transistor N1 has a gate connected to the word line WL, a drain connected to one end of the ferroelectric capacitor F1, a source connected to the bit line BL, and the ferroelectric capacitor F1 connected to the plate line PL. Connected. The access transistor N2 has a gate connected to the word line WL, a drain connected to one end of the ferroelectric capacitor F2, a source connected to the bit line BLX, and the other end connected to the plate line PL. Connected.

  In this example, the writing circuit is not shown, but complementary data is written in the ferroelectric capacitors F1 and F2. That is, when data “0” is written to the ferroelectric capacitor F1, data “1” is written to the ferroelectric capacitor F2, and data “1” is written to the ferroelectric capacitor F1. In the ferroelectric capacitor F2, data “0” is written.

  Here, the data “0” is written to the ferroelectric capacitor F1 by setting the potential of the word line WL = VDD potential (for example, 3V), turning on the access transistor N1, and the potential of the bit line BL = GND potential (0V). This is done by setting the potential of the plate line PL = VDD potential and applying a positive voltage to the ferroelectric capacitor F1.

  On the other hand, in writing data “1” to the ferroelectric capacitor F2, the potential of the word line WL = VDD potential, the access transistor N2 is turned on, the potential of the bit line BLX = VDD potential, and the potential of the plate line PL. = GND potential, and a negative voltage is applied to the ferroelectric capacitor F2.

  In addition, data “1” is written to the ferroelectric capacitor F1 by setting the potential of the word line WL = VDD potential, turning on the access transistor N1, the potential of the bit line BL = VDD potential, and the potential of the plate line PL = GND potential. And by applying a negative voltage to the ferroelectric capacitor F1.

  On the other hand, when data “0” is written to the ferroelectric capacitor F2, the potential of the word line WL = VDD potential, the access transistor N2 is turned on, the potential of the bit line BLX = GND potential, and the potential of the plate line PL. = VDD potential, and a positive voltage is applied to the ferroelectric capacitor F2.

  The pre-sense amplifier 2 includes switches S1 and S3, a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) P1, and capacitors C1 and C3. The switch S1 has one end connected to the bit line BL and the other end grounded. The switch S1 is turned on when the bit line BL is reset, and turned off otherwise. The switch S3 has one end connected to the node MINUS and the other end connected to the output terminal 5A of the minus voltage generation circuit 5, and is turned on when the node MINUS is reset and turned off otherwise.

  The PMOS transistor P1 has a source connected to the bit line BL, a gate connected to the output terminal 4A of the threshold value generation circuit 4, and a drain connected to the node MINUS. The capacitor C1 has one end connected to the node MINUS and the other end grounded. The capacitor C3 has one end connected to the node MINUS and the other end connected to the node OUT.

  The pre-sense amplifier 3 has switches S2 and S4, a PMOS transistor P2, and capacitors C2 and C4. The switch S2 has one end connected to the bit line BLX and the other end grounded. The switch S2 is ON when the bit line BLX is reset, and is OFF otherwise. The switch S4 has one end connected to the node MINUSX and the other end connected to the output terminal 5A of the negative voltage generating circuit 5, and is turned on when the node MINUSX is reset, and is turned off otherwise.

  The PMOS transistor P2 has a source connected to the bit line BLX, a gate connected to the output terminal 4A of the threshold value generation circuit 4, and a drain connected to the node MINUSX. The capacitor C2 has one end connected to the node MINUSX and the other end grounded. The capacitor C4 has one end connected to the node MINUSX and the other end connected to the node OUTX.

  The threshold generation circuit 4 generates a potential equal to the threshold VTHP of the PMOS transistor when the bit lines BL and BLX are at the GND potential, that is, when the sources of the PMOS transistors P1 and P2 are at the GND potential. The potential VTHP output by 4 is a potential lower than the GND potential. The negative voltage generation circuit 5 generates a negative potential VMINUS (for example, −3 V).

  The sense amplifier 6 is a latch-type sense amplifier, and includes PMOS transistors P3, P4, P5, P6, and P7, NMOS transistors N3, N4, N5, N6, and N7, switches S5 and S6, and an inverter IB1. .

  The PMOS transistor P4 and the NMOS transistor N4 have drains connected to each other and gates connected to each other to constitute an inverter IB2. Further, the PMOS transistor P5 and the NMOS transistor N5 have drains connected to each other and gates connected to each other to constitute an inverter IB3.

  The inverters IB2 and IB3 connect the input terminal of the inverter IB2 to the output terminal of the inverter IB3 and the node SAOUTX, and connect the input terminal of the inverter IB3 to the output terminal of the inverter IB2 and the node SAOUT. It is configured to amplify the potential difference.

  The PMOS transistor P3 has a source connected to the VDD power supply, a drain connected to the sources of the PMOS transistors P4 and P5, and a gate connected to the output terminal of the inverter IB1, thereby disconnecting the inverters IB2 and IB3 from the VDD power supply. I am doing. The inverter IB1 inverts the latch activation signal SAPOWER output from the NAND gate 9.

  The NMOS transistor N3 has a power switch that disconnects the inverters IB2 and IB3 from the GND power supply by connecting the drain to the sources of the NMOS transistors N4 and N5, grounding the source, and connecting the gate to the output terminal of the NAND gate 9. ing.

  The PMOS transistor P6 and the NMOS transistor N6 constitute a transfer gate TG1, and the transfer gate TG1 has an input terminal connected to the node OUT and an output terminal connected to the node SAOUT. The gate of the PMOS transistor P6 is connected to the output terminal of the NAND gate 9, and the gate of the NMOS transistor N6 is connected to the output terminal of the inverter IB1.

  The PMOS transistor P7 and the NMOS transistor N7 constitute a transfer gate TG2. The transfer gate TG2 has an input terminal connected to the node OUTX and an output terminal connected to the node SAOUTX. The gate of the PMOS transistor P7 is connected to the output terminal of the NAND gate 9, and the gate of the NMOS transistor N7 is connected to the output terminal of the inverter IB1.

  The switch S5 has one end connected to the node OUT and the other end grounded, and is turned on when the node OUT is reset, and is turned off otherwise. The switch S6 has one end connected to the node OUTX and the other end grounded. The switch S6 is turned on when the node OUTX is reset, and is turned off otherwise.

  The Schmitt trigger circuit 7 includes PMOS transistors P8, P9, and P10 and an NMOS transistor N8. The input terminal 7A is connected to the node OUT, and the output terminal 7B is connected to one input terminal of the NAND gate 9. .

  The PMOS transistor P8 has a gate connected to the input terminal 7A and a source connected to the VDD power source. The PMOS transistor P9 has a gate connected to the input terminal 7A, a source connected to the drain of the PMOS transistor P8, and a drain connected to the output terminal 7B.

  The NMOS transistor N8 has a gate connected to the input terminal 7A, a drain connected to the output terminal 7B, and a source grounded. The PMOS transistor P10 has a source connected to the drain of the PMOS transistor P8, a drain grounded, and a gate connected to the drain of the PMOS transistor P9.

  The Schmitt trigger circuit 8 includes PMOS transistors P11, P12, P13 and an NMOS transistor N9. The Schmitt trigger circuit 8 connects the input terminal 8A to the node OUTX, and outputs the output terminal 8B to the other input of the NAND gate 9. Connected to the terminal.

  The PMOS transistor P11 has a gate connected to the input terminal 8A and a source connected to the VDD power source. The PMOS transistor P12 has a gate connected to the input terminal 8A, a source connected to the drain of the PMOS transistor P11, and a drain connected to the output terminal 8B.

  The NMOS transistor N9 has a gate connected to the input terminal 8A, a drain connected to the output terminal 8B, and a source grounded. The PMOS transistor P13 has a source connected to the drain of the PMOS transistor P11, a drain grounded, and a gate connected to the drain of the PMOS transistor P12.

  The NAND gate 9 performs NAND processing on the output TRG1 of the Schmitt trigger circuit 7 and the output TRG2 of the Schmitt trigger circuit 8 and outputs a latch activation signal SAPOWER. The latch activation signal SAPOWER is applied to the input terminal of the inverter IB1 and the gates of the PMOS transistors P6 and P7.

  FIG. 9 is a waveform diagram showing the data read operation of the conventional ferroelectric memory shown in FIG. 7 (FIG. 8). The word line WL, the plate line PL, the bit lines BL and BLX, the nodes MINUS, MINUSX, the node OUT, Although the potential changes of OUTX, latch activation signal SAPOWER, and nodes SAOUT and SAOUTX are shown, when the amount of polarization of the ferroelectric capacitors F1 and F2 has not decreased, data “1” is stored in the ferroelectric capacitor F1. In this example, data “0” is written in the ferroelectric capacitor F2, and this is read.

  In the conventional ferroelectric memory shown in FIG. 7 (FIG. 8), when data is read from the memory cell 1, the switches S1 and S2 in the pre-sense amplifiers 2 and 3 are kept ON until time TRES. As shown in (C), the bit lines BL and BLX are fixed to the GND potential. However, after the time TRES, the switches S1 and S2 are turned OFF to open the bit lines BL and BLX.

  The threshold generation circuit 4 generates a potential equal to the threshold VTHP of the PMOS transistor when the bit lines BL and BLX are at the GND potential, that is, when the sources of the PMOS transistors P1 and P2 are at the GND potential. Supply to the gate of P2.

  Further, the switches S3 and S4 in the pre-sense amplifiers 2 and 3 are kept ON until time TRES, and the nodes MINUS and MINUSX are lowered to the negative potential VMINUS (for example, −3 V) output from the negative voltage generation circuit 5. However, after the time TRES, it is turned OFF, and the nodes MINUS and MINUSX are released. Note that from time TRES to time TWLPL, the potentials of the nodes MINUS and MINUSX are kept at the negative potential VMINUS by the capacitors C1 and C2.

  At time TWLPL, as shown in FIGS. 9A and 9B, the potentials of the word line WL and the plate line PL are raised to the VDD potential, the access transistors N1 and N2 are turned on, and the ferroelectric capacitors F1 and F2 are turned on. A positive voltage is applied to. Here, since the voltage applied to the ferroelectric capacitor F1 storing the data “1” has a polarity opposite to that at the time of writing, polarization inversion occurs in the ferroelectric capacitor F1, and the ferroelectric capacitor F1. Therefore, a relatively large inversion charge flows to the bit line BL.

  At this time, the potential of the bit line BL tends to rise, but since the threshold value VTHP is applied to the gate of the PMOS transistor P1, when the potential of the bit line BL slightly increases as shown in FIG. 9C, The PMOS transistor P1 is turned on, a charge equal to the inverted charge flows from the bit line BL to the node MINUS via the source and drain of the PMOS transistor P1, the potential of the bit line BL is kept near the GND potential, and the capacitance C1 As a result, the potential of the node MINUS held at the minus potential VMINUS greatly increases as shown by a one-dot chain line in FIG.

  On the other hand, since the voltage applied to the ferroelectric capacitor F2 storing the data “0” has the same polarity as that at the time of writing, no polarization inversion occurs in the ferroelectric capacitor F2, and the ferroelectric capacitor A relatively small charge flows from the body capacitance F2 to the bit line BLX.

  At this time, the potential of the bit line BLX also tends to rise, but since the threshold value VTHP is applied to the gate of the PMOS transistor P2, when the potential of the bit line BLX slightly increases as shown in FIG. 9C, The PMOS transistor P2 is turned on, and electric charge flows from the bit line BLX to the node MINUSX via the source and drain of the PMOS transistor P2, and the potential of the bit line BLX is kept near the GND potential, and the negative potential VMINUS is caused by the capacitor C2. The potential of the node MINUSX held at the point of time increases as shown by a two-dot chain line in FIG. 9D, but is smaller than the increase of the node MINUS.

  The switches S5 and S6 in the sense amplifier 6 are turned ON until time TRES, and the nodes OUT and OUTX are fixed to the GND potential until time TRES, and the nodes MINUS and MINUSX are as described above. In addition, the negative potential VMINUS is fixed until time TRES.

  After the time TRES, the switches S5 and S6 are turned off and the nodes OUT and OUTX are opened, but the capacitors C3 and C4 maintain the potential difference between both ends thereof, so that the nodes OUT and OUT are changed according to the potential changes of the nodes MINUS and MINUSX. OUTX will also move. Therefore, as shown in FIG. 9D, when the potentials of the nodes MINUS and MINUSX rise, the potentials of the nodes OUT and OUTX are the same as the waveforms of the nodes MINUS and MINUSX as shown in FIG. , The potential is shifted upward by | VMINUS |, resulting in a positive potential waveform with respect to the GND potential.

  The input terminals 7A and 8A of the Schmitt trigger circuits 7 and 8 are connected to the nodes OUT and OUTX, respectively. However, since the potentials of the nodes OUT and OUTX are set to the GND potential before reading, the Schmitt trigger circuit 7 is used. , 8 outputs TRG1, TRG2 are at VDD potential before reading, and the latch activation signal SAPOWER output from the NAND gate 9 is at GND potential before reading.

  When reading starts, the potentials of the nodes OUT and OUTX rise. In this example, as shown in FIG. 9E, the node OUT is on the input rising side of the Schmitt trigger circuit 7 at time T2 before the node OUTX. The threshold value VSCHMIDT will be reached. As a result, the output TRG1 of the Schmitt trigger circuit 7 is switched from the VDD potential to the GND potential, and the latch activation signal SAPOWER output from the NAND gate 9 is switched from the GND potential to the VDD potential as shown in FIG.

  Although the potentials of the nodes OUT and OUTX rise gently, the Schmitt trigger circuits 7 and 8 do not switch even if the input fluctuates once the output is switched. The output will never change due to fluctuations.

  Further, until the time T2 when the potential of the node OUT reaches the threshold value VSCHMIDT on the input rising side of the Schmitt trigger circuit 7, the latch activation signal SAPOWER output from the NAND gate 9 maintains the GND potential, and the cross-coupled inverters IB2 and IB3 Is disconnected from the VDD power supply and the GND power supply and is inactive. The transfer gates TG1 and TG2 are ON, the node OUT is connected to the node SAOUT, and the node OUTX is connected to the node SAOUTX.

  At time T2, as shown in FIG. 9 (F), when the latch activation signal SAPOWER becomes the VDD potential, the transfer gates TG1 and TG2 are turned off, and VDD and GND power are supplied to the inverters IB2 and IB3, and the inverter IB2, IB3 enters an active state, and as shown in FIG. 9G, the potential difference between the nodes SAOUT and SAOUTX is amplified to the VDD potential-GND potential and becomes a read output.

  As described above, in the conventional ferroelectric memory shown in FIG. 7 (FIG. 8), the Schmitt trigger circuits 7 and 8 detect the potentials of the nodes OUT and OUTX as potential detection means, and the NAND gate 9 latches the latch activation signal SAPOWER. Is generated so that the latch operation of the sense amplifier 6 can be started at time T2 when the potential difference between the nodes OUT and OUTX is large.

  If the Schmitt trigger circuits 7 and 8 are not provided and the latch operation of the sense amplifier 6 is started at a predetermined time, the characteristics of the ferroelectric capacitors F1 and F2 have large variations, temperature dependence, and time degradation. It is necessary to set a sufficiently long time as at time T1 shown in FIG. 9, and in this case, the potential difference ΔV1 between the nodes OUT and OUTX becomes small.

In this example, the case where the data “1” is written in the ferroelectric capacitor F1 and the data “0” is written in the ferroelectric capacitor F2, the data “0” is stored in the ferroelectric capacitor F1. The same applies to the case where data “1” is written in the ferroelectric capacitor F2. The capacitors C1, C2, C3, and C4 may be ferroelectric capacitors or other capacitors.
JP 2005-129151 A JP 2002-133857 A S. Kawashima, et. al. , IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 5, MAY 2002, p592-598

  FIG. 10 is a waveform diagram for explaining the problems of the conventional ferroelectric memory shown in FIG. 7 (FIG. 8). FIG. 10 (A) shows potential changes at nodes OUT and OUTX, and FIG. 10 (B). Indicates a latch activation signal SAPOWER. However, the potential change at the node OUT indicated by the alternate long and short dash line and the potential change at the node OUTX indicated by the alternate long and two short dashes line in FIG. 2 is an enlarged view of potential changes at nodes OUT and OUTX. The potential waveform of the node OUT indicated by the solid line and the potential change of the node OUTX indicated by the dotted line are the potential waveform when the polarization amounts of the ferroelectric capacitors F1 and F2 are decreased.

  Generally, the amount of polarization of a ferroelectric capacitor decreases at a temperature higher than normal temperature. In addition, if it is left for a long time after writing, the amount of polarization called depolarization decreases. Further, repeated reading / writing, that is, polarization reversal, causes a decrease in the amount of polarization called fatigue (fatigue characteristics). When the amount of polarization decreases due to any of these or a complex factor, as shown by the solid line in FIG. 10A, the readout waveform of the data “1” from the ferroelectric capacitor F1 falls and as shown by the dotted line. The read waveform of data “0” from the ferroelectric capacitor F2 rises.

  In the conventional ferroelectric memory shown in FIG. 7 (FIG. 8), data “1” is written in the ferroelectric capacitor F1 and data “0” is written in the ferroelectric capacitor F2 in the initial state at room temperature. If this occurs, the potential at the node OUT reaches the threshold value VSCHMIDT on the input rising side of the Schmitt trigger circuit 7 first, and at time T2, the latch activation signal SAPOWER becomes the VDD potential, and the sense amplifier 6 starts the latch operation. In this case, the sense amplifier 6 is given a potential difference ΔV2 larger than the potential difference ΔV1 when the latch is activated at a fixed time T1 set with a sufficient margin.

  However, when the amount of polarization of the ferroelectric capacitors F1 and F2 decreases due to any one of high temperature, depolarization, fatigue, etc., or a composite factor, the potential change at the node OUT is a waveform indicated by a solid line in FIG. Thus, the time when the Schmitt trigger circuit 7 reaches the threshold value VSCHMIDT on the input rising side is T3, and latching by the sense amplifier 6 is started at this time.

  At this time, since the potential of the node OUTX also increases due to the decrease in the polarization amount of the ferroelectric film F2, the potential difference between the nodes OUT and OUTX becomes a potential difference ΔV3 smaller than ΔV2. In this case, the sense amplifier 6 may cause erroneous reading because the input potential difference is small. However, as shown in FIG. 10A, before time T3, there is a time T4 when a potential difference ΔV4 larger than the potential difference ΔV3 occurs, and if the latch can be started at the time T4, a larger input potential difference can be obtained and a malfunction occurs. Can be prevented.

  SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a ferroelectric memory capable of preventing an erroneous read operation of a sense amplifier even when the amount of polarization of a ferroelectric capacitor is reduced. To do.

  The ferroelectric memory of the present invention includes a 2T / 2C type memory cell having first and second ferroelectric capacitors in which complementary data is stored, and a first ferroelectric capacitor to the first bit line. A first pre-sense amplifier that detects the read data, a second pre-sense amplifier that detects data read from the second ferroelectric capacitor to the second bit line, and a first pre-sense amplifier. First potential detection means for detecting that the output has reached a predetermined potential, second potential detection means for detecting that the output of the second pre-sense amplifier has reached a predetermined potential, and first and second And a sense amplifier that amplifies the difference between the output potentials of the first and second pre-sense amplifiers. The first potential detection means has a threshold value of the second pre-sense amplifier. Varies according to the output potential of Configured urchin, a second potential detection means is one whose threshold value is configured so as to change according to the output potential of the first pre-sense amplifier.

  According to the present invention, the first potential detection unit is configured such that the threshold value changes according to the output potential of the second pre-sense amplifier, and the second potential detection unit has the threshold value of the first pre-sense value. Since it is configured to change according to the output potential of the amplifier, even if the polarization amount of the ferroelectric capacitor is reduced and the difference between the output potentials of the first and second pre-sense amplifiers is small, the sense The amplifier can start a latching operation before the potential difference between the first and second pre-sense amplifiers becomes a small potential difference that may cause erroneous reading during data reading. Therefore, even if the amount of polarization of the ferroelectric capacitor is reduced, an erroneous read operation of the sense amplifier can be prevented.

(First embodiment)
FIG. 1 is a block circuit diagram of a main part of the first embodiment of the present invention, and FIG. 2 is a detailed circuit diagram thereof. In the first embodiment of the present invention, variable threshold Schmitt trigger circuits 10 and 11 are provided in place of the Schmitt trigger circuits 7 and 8 provided in the conventional ferroelectric memory shown in FIG. 7 (FIG. 8). This is similar to the conventional ferroelectric memory shown in FIG. 7 (FIG. 8).

  The variable threshold Schmitt trigger circuit 10 is obtained by adding an NMOS transistor N10 to the Schmitt trigger circuit 7 shown in FIG. 7 (FIG. 8), and has PMOS transistors P8, P9, P10 and NMOS transistors N8, N10. The input terminal 10A is connected to the node OUT, and the output terminal 10B is connected to one input terminal of the NAND gate 9.

  Here, the PMOS transistor P8 has a gate connected to the input terminal 10A and a source connected to the VDD power source. The PMOS transistor P9 has a gate connected to the input terminal 10A, a source connected to the drain of the PMOS transistor P8, and a drain connected to the output terminal 10B. The NMOS transistor N8 has a gate connected to the input terminal 10A, a drain connected to the output terminal 10B, and a source grounded.

  The PMOS transistor P10 has a source connected to the drain of the PMOS transistor P8, a drain grounded, and a gate connected to the drain of the PMOS transistor P9. The NMOS transistor N10 has a drain connected to the drain of the NMOS transistor N8, a source grounded, and a gate connected to the node OUTX.

  The variable threshold Schmitt trigger circuit 11 is obtained by adding an NMOS transistor 11 to the Schmitt trigger circuit 8 shown in FIG. 7 (FIG. 8), and includes PMOS transistors P11, P12, P13 and NMOS transistors N9, N11. The input terminal 11A is connected to the node OUTX, and the output terminal 11B is connected to the other input terminal of the NAND gate 9.

  The PMOS transistor P11 has a gate connected to the input terminal 11A and a source connected to the VDD power source. The PMOS transistor P12 has a gate connected to the input terminal 11A, a source connected to the drain of the PMOS transistor P11, and a drain connected to the output terminal 11B. The NMOS transistor N9 has a gate connected to the input terminal 11A, a drain connected to the output terminal 11B, and a source grounded.

  The PMOS transistor P13 has a source connected to the drain of the PMOS transistor P11, a drain grounded, and a gate connected to the drain of the PMOS transistor P12. The NMOS transistor N11 has a drain connected to the drain of the NMOS transistor N9, a source grounded, and a gate connected to the node OUT.

  That is, the variable threshold Schmitt trigger circuit 10 is configured such that the threshold value decreases in response to an increase in the output potential of the pre-sense amplifier 3, that is, the potential of the node OUTX, and the variable threshold Schmitt trigger circuit 11 has a threshold value that is pre-sensed. The output potential of the amplifier 2, that is, the potential at the node OUT is lowered in accordance with the rise.

  FIG. 3 is a waveform diagram showing a data read operation according to the first embodiment of the present invention. The word line WL, the plate line PL, the bit lines BL, BLX, the nodes MINUS, MINUSX, the nodes OUT, OUTX, the latch activation signal SAPOWER, and FIG. Although the potential changes of the nodes SAOUT and SAOUTX are shown, when the polarization amounts of the ferroelectric capacitors F1 and F2 are not decreased, the data “1” is stored in the ferroelectric capacitor F1, and the ferroelectric capacitor F2 is displayed. In this example, data “0” is written and this is read.

  In the first embodiment of the present invention, when data is read from the memory cell 1, the switches S1 and S2 in the pre-sense amplifiers 2 and 3 are kept ON until time TRES, as shown in FIG. Although the bit lines BL and BLX are fixed at the GND potential, after the time TRES, the switches S1 and S2 are turned OFF and the bit lines BL and BLX are opened.

  The threshold generation circuit 4 generates a potential equal to the threshold VTHP of the PMOS transistor when the bit lines BL and BLX are at the GND potential, that is, when the sources of the PMOS transistors P1 and P2 are at the GND potential. Supply to the gate of P2.

  Further, the switches S3 and S4 in the pre-sense amplifiers 2 and 3 are kept ON until time TRES, and the nodes MINUS and MINUSX are lowered to the negative potential VMINUS (for example, −3 V) output from the negative voltage generation circuit 5. However, after the time TRES, it is turned OFF, and the nodes MINUS and MINUSX are released. Note that from time TRES to time TWLPL, the potentials of the nodes MINUS and MINUSX are kept at the negative potential VMINUS by the capacitors C1 and C2.

  At time TWLPL, as shown in FIGS. 3A and 3B, the potentials of the word line WL and the plate line PL are raised to the VDD potential, the access transistors N1 and N2 are turned on, and the ferroelectric capacitors F1 and F2 are turned on. A positive voltage is applied to. Here, since the voltage applied to the ferroelectric capacitor F1 storing the data “1” has a polarity opposite to that at the time of writing, polarization inversion occurs in the ferroelectric capacitor F1, and the ferroelectric capacitor F1. Therefore, a relatively large inversion charge flows to the bit line BL.

  At this time, the potential of the bit line BL tends to rise, but since the threshold value VTHP is applied to the gate of the PMOS transistor P1, if the potential of the bit line BL slightly increases as shown in FIG. The PMOS transistor P1 is turned on, a charge equal to the inverted charge flows from the bit line BL to the node MINUS via the source and drain of the PMOS transistor P1, the potential of the bit line BL is kept near the GND potential, and the capacitance C1 As a result, the potential of the node MINUS held at the minus potential VMINUS greatly increases as shown by a one-dot chain line in FIG.

  On the other hand, since the voltage applied to the ferroelectric capacitor F2 storing the data “0” has the same polarity as that at the time of writing, no polarization inversion occurs in the ferroelectric capacitor F2, and the ferroelectric capacitor A relatively small charge flows from the body capacitance F2 to the bit line BLX.

  At this time, the potential of the bit line BLX also tends to rise, but since the threshold value VTHP is applied to the gate of the PMOS transistor P2, when the potential of the bit line BLX slightly increases as shown in FIG. The PMOS transistor P2 is turned on, and electric charge flows from the bit line BLX to the node MINUSX via the source and drain of the PMOS transistor P2, and the potential of the bit line BLX is kept near the GND potential, and the negative potential VMINUS is caused by the capacitor C2. The potential of the node MINUSX held at 上昇 increases as shown by a two-dot chain line in Fig. 3D, but is smaller than the increase of the node MINUS.

  The switches S5 and S6 in the sense amplifier 6 are turned ON until time TRES, and the nodes OUT and OUTX are fixed to the GND potential until time TRES, and the nodes MINUS and MINUSX are as described above. In addition, the negative potential VMINUS is fixed until time TRES.

  After the time TRES, the switches S5 and S6 are turned off and the nodes OUT and OUTX are opened, but the capacitors C3 and C4 maintain the potential difference between both ends thereof, so that the nodes OUT and OUT are changed according to the potential changes of the nodes MINUS and MINUSX. OUTX will also move. Therefore, as shown in FIG. 3D, when the potentials of the nodes MINUS and MINUSX rise, the potentials of the nodes OUT and OUTX are the same as the waveforms of the nodes MINUS and MINUSX as shown in FIG. , The potential is shifted upward by | VMINUS |, resulting in a positive potential waveform with respect to the GND potential.

  The input terminals 10A and 11A of the variable threshold Schmitt trigger circuits 10 and 11 are connected to the nodes OUT and OUTX, respectively. However, since the potentials of the nodes OUT and OUTX are set to the GND potential before reading, the variable thresholds The outputs TRG1 and TRG2 of the Schmitt trigger circuits 10 and 11 are set to the VDD potential before reading, and the latch activation signal SAPOWER output from the NAND gate 9 is set to the GND potential before reading.

  Here, since the gate of the NMOS transistor 10 is connected to the node OUTX, and the gate of the NMOS transistor 11 is connected to the node OUT, the NMOS transistors 10 and 11 are applied with a voltage higher than the threshold value of the NMOS transistor. Then, at the beginning, an electric current is applied to lower the nodes TRG1 and TRG2. As a result, the threshold values of the variable threshold Schmitt trigger circuits 10 and 11 are lowered as the gate voltages of the NMOS transistors N10 and N11 are higher.

  After time TWLPL, reading starts and at time T2, the potential of the node OUTX is still low. Therefore, the threshold of the variable threshold Schmitt trigger circuit 10 is approximately a Schmitt trigger circuit composed of PMOS transistors P8, P9, P10 and an NMOS transistor N8. Since the input rising threshold VSCHMIDT of the Schmitt trigger circuit 7 shown in FIG. 8 remains unchanged and the potential of the node OUT reaches the input rising threshold VSCHMIDT of the variable threshold Schmitt trigger circuit 10, the variable threshold Schmitt trigger circuit 10 output TRG1 falls to the GND potential, and the latch activation signal SAPOWER switches to the VDD potential.

  That is, when reading starts, the potentials of the nodes OUT and OUTX rise. In this example, as shown in FIG. 3E, the variable threshold Schmitt trigger circuit 10 is connected at the time T2 before the node OUTX. Will reach the threshold value VSCHMIDT on the input rising side. As a result, the output TRG1 of the variable threshold Schmitt trigger circuit 10 is switched from the VDD potential to the GND potential, and the latch activation signal SAPOWER output from the NAND gate 9 is switched from the GND potential to the VDD potential as shown in FIG. .

  Although the potentials of the nodes OUT and OUTX rise gently, the variable threshold Schmitt trigger circuits 10 and 11 do not switch even if the input is slightly changed once the output is switched. There is no possibility of the output changing with a slight fluctuation).

  Further, until time T2 when the potential of the node OUT reaches the threshold value VSCHMIDT on the input rising side of the variable threshold value Schmitt trigger circuit 10, the latch activation signal SAPOWER output from the NAND gate 9 maintains the GND potential and the cross-coupled inverter IB2 IB3 is disconnected from the VDD power supply and the GND power supply and is inactive. Further, the transfer gates TG1 and TG2 are ON, and the nodes OUT and OUTX are connected to the nodes SAOUT and SAOUTX.

  At time T2, as shown in FIG. 3F, when the latch activation signal SAPOWER becomes the VDD potential, the transfer gates TG1 and TG2 are turned OFF, and the VDD power and the GND power are supplied to the inverters IB2 and IB3. IB2 and IB3 are activated, and as shown in FIG. 3G, the potential difference between the nodes SAOUT and SAOUTX is amplified to the VDD potential−GND potential to be a read output.

  As described above, in the first embodiment of the present invention, the variable threshold Schmitt trigger circuits 10 and 11 detect the potentials of the nodes OUT and OUTX as potential detection means, and the NAND gate 9 generates the latch activation signal SAPOWER. When the polarization amounts of the ferroelectric capacitors F1 and F2 are not decreased, the sense is performed at time T2 when the potential difference between the nodes OUT and OUTX is large, as in the conventional ferroelectric memory shown in FIG. 7 (FIG. 8). The latch operation of the amplifier 6 can be started.

  4A and 4B are waveform diagrams for explaining the effect of the first embodiment of the present invention. FIG. 4A shows potential changes of the nodes OUT and OUTX, and FIG. 4B shows the latch activation signal SAPOWER. However, the potential change at the node OUT indicated by the one-dot chain line and the potential change at the node OUTX indicated by the two-dot chain line in FIG. 2 is an enlarged view of potential changes at nodes OUT and OUTX. The potential waveform of the node OUT indicated by the solid line and the potential change of the node OUTX indicated by the dotted line are the potential waveform when the polarization amounts of the ferroelectric capacitors F1 and F2 are decreased.

  Here, the threshold value of the variable threshold value Schmitt trigger circuit 10 at time T4 decreases according to an increase in the potential of the node OUTX from VSCHMIDT at time T2, and becomes VARIABLE_VSCHMIDT. As a result, even when the polarization amounts of the ferroelectric capacitors F1 and F2 are decreased, if the potential of the node OUT becomes VARIABLE_VSCHMIDT, the output TG1 of the variable threshold Schmitt trigger circuit 10 becomes the GND potential, and the NAND The latch activation signal SAPOWER output from the gate 9 becomes the VDD potential, and the sense amplifier 6 starts the latch operation.

  As described above, in the first embodiment of the present invention, the sense amplifier 6 starts a latch operation at time T4. In this case, the sense amplifier 6 has a conventional strong power shown in FIG. 7 (FIG. 8). In the case of a dielectric memory, a potential difference ΔV4 larger than the potential difference ΔV3 given at time T3 is given. Therefore, according to the first embodiment of the present invention, even if the polarization amount of the ferroelectric capacitors F1 and F2 decreases due to any one of high temperature, depolarization, fatigue, etc., or a composite factor, the sense amplifier 6 An erroneous read operation can be prevented.

(Second Embodiment)
FIG. 5 is a circuit diagram of the main part of the second embodiment of the present invention. The second embodiment of the present invention is a circuit shown in FIG. 1 (FIG. 2) as potential detection means for detecting that the output potentials of the pre-sense amplifiers 2 and 3, that is, the potentials of the nodes OUT and OUTX have reached a predetermined potential. Instead of the variable threshold Schmitt trigger circuits 10 and 11 provided in the first embodiment of the invention, variable threshold inverters 12 and 13 are provided, and the others are configured in the same manner as in the first embodiment of the present invention.

  The variable threshold inverter 12 includes a PMOS transistor P14 and NMOS transistors N12 and N13. The input terminal 12A is connected to the node OUT, and the output terminal 12B is connected to one input terminal of the NAND gate 9.

  The PMOS transistor P14 has a gate connected to the input terminal 12A, a source connected to the VDD power supply, and a drain connected to the output terminal 12B. The NMOS transistor 12 has a gate connected to the input terminal 12A, a drain connected to the output terminal 12B, and a source grounded. The NMOS transistor N13 has a drain connected to the drain of the NMOS transistor N12, a source grounded, and a gate connected to the node OUTX.

  The variable threshold inverter 13 includes a PMOS transistor P15 and NMOS transistors N14 and N15. The input terminal 13A is connected to the node OUTX, and the output terminal 13B is connected to the other input terminal of the NAND gate 9.

  The PMOS transistor P15 has a gate connected to the input terminal 13A, a source connected to the VDD power supply, and a drain connected to the output terminal 13B. The NMOS transistor 14 has a gate connected to the input terminal 13A, a drain connected to the output terminal 13B, and a source grounded. The NMOS transistor N15 has a drain connected to the drain of the NMOS transistor N14, a source grounded, and a gate connected to the node OUT.

  That is, the variable threshold inverter 12 is configured such that the threshold value decreases in response to an increase in the output potential of the pre-sense amplifier 3, that is, the potential of the node OUTX, and the variable threshold inverter 13 has the threshold value output from the pre-sense amplifier 2. The electric potential, that is, the electric potential at the node OUT is increased in accordance with the increase.

  In the second embodiment of the present invention configured as described above, the variable threshold inverters 12 and 13 are connected to the output potentials of the pre-sense amplifiers 2 and 3, that is, the nodes OUT and the same as the variable threshold Schmitt trigger circuits 10 and 11. It can function as a potential detection means for detecting that the potential of OUTX has reached a predetermined potential. Therefore, according to the second embodiment of the present invention, as in the first embodiment of the present invention, the polarization amounts of the ferroelectric capacitors F1 and F2 are reduced due to any one of high temperature, depolarization, fatigue, or a composite factor. Even in this case, the erroneous read operation of the sense amplifier 6 can be prevented.

(Third embodiment)
FIG. 6 is a circuit diagram of an essential part of the third embodiment of the present invention. In FIG. 6, reference numeral 14 denotes the first embodiment of the present invention shown in FIGS. However, BL, BLX, OUT, OUTX, SAOUT, and SAOUTX shown in FIGS. 1 and 2 are shown as BL0, BL0X, OUT0, OUT0X, SAOUT0, and SAOUT0X in FIG. 6, respectively.

  Reference numerals 15-1 and 15-m denote 1-transistor / 1-capacitor (1T / 1C-type) memory cells connected to the word line WL and the plate line PL, and are connected to the word line WL and the plate line PL. The other memory cells 15-2 to 15- (m-1) are not shown.

  The memory cell 15-1 includes a ferroelectric capacitor F3-1 serving as a storage medium and an access transistor N16-1 including an NMOS transistor. The access transistor N16-1 has a gate connected to the word line WL, a drain connected to one end of the ferroelectric capacitor F3-1, a source connected to the bit line BL1, and the ferroelectric capacitor F3-1 is The other end is connected to the plate line PL.

  The memory cell 15-m includes a ferroelectric capacitor F3-m serving as a storage medium, and an access transistor N16-m formed of an NMOS transistor. The access transistor N16-m has a gate connected to the word line WL, a drain connected to one end of the ferroelectric capacitor F3-m, and a source connected to the bit line BLm. The ferroelectric capacitor F3-m The other end is connected to the plate line PL.

  Reference numeral 16-1 denotes a pre-sense amplifier provided corresponding to the memory cell 15-1, 16-m denotes a pre-sense amplifier provided corresponding to the memory cell 15-m, and OUT1 denotes an output side of the pre-sense amplifier 16-1. The node OUTm is a node on the output side of the pre-sense amplifier 16-m. The pre-sense amplifiers 16-2 to 16- (m-1) provided corresponding to the memory cells 15-2 to 15- (m-1) are not shown. The pre-sense amplifiers 16-1 to 16-m are configured similarly to the pre-sense amplifiers 2 and 3.

  Reference numeral 17-1 denotes a sense amplifier provided corresponding to the pre-sense amplifier 16-1, 17-m denotes a sense amplifier provided corresponding to the pre-sense amplifier 16-m, and SAOUT1 and SAOUT1X denote the sense amplifier 17-1. Output side nodes SAOUTm and SAOUTmX are output side nodes of the sense amplifier 17-m. The sense amplifiers 17-2 to 17- (m-1) provided corresponding to the pre-sense amplifiers 16-2 to 16- (m-1) are not shown.

  The sense amplifiers 17-1 to 17-m have a circuit configuration similar to that of the sense amplifier 6. However, the sense amplifier 17-i (where i = 1, 2,..., M) is configured to amplify the potential difference between the output of the corresponding pre-sense amplifier 16-i and the reference potential VREF.

  The reference voltage VREF is generated by a reference voltage generation circuit (not shown), and when the amount of polarization of the ferroelectric capacitors F1 and F2 decreases, when reading data, the potential of any one of the nodes OUT0 and OUT0X is first changed to the variable threshold Schmitt. When the threshold value VARIABLE_VSCHMIDT on the input rising side of the trigger circuits 10 and 11 is reached (at time T4 shown in FIG. 4), the potential is approximately the middle potential between the nodes OUT0 and OUT0X.

  According to the third embodiment of the present invention configured as described above, an appropriate sense amplifier activation timing is provided by the variable threshold Schmitt trigger circuits 10 and 11 and the NAND gate 9 provided corresponding to the 2T2C type memory cell 1. The sense amplifier provided corresponding to the 1T1C type memory cell can be activated at that timing.

  Therefore, according to the third embodiment of the present invention, the ferroelectric capacitors including the ferroelectric capacitors F1, F2, F3-1 to F3-m due to any one of the factors such as high temperature, depolarization, fatigue, and the like. Even when the amount of polarization decreases, an erroneous read operation of the sense amplifiers 6 and 17-1 to 17-m can be prevented.

It is a block circuit diagram of the principal part of 1st Embodiment of this invention. It is a detailed circuit diagram of the principal part of 1st Embodiment of this invention. It is a wave form diagram which shows the data read-out operation | movement of 1st Embodiment of this invention. It is a wave form diagram for demonstrating the effect of 1st Embodiment of this invention. It is a circuit diagram of the principal part of 2nd Embodiment of this invention. It is a circuit diagram of the principal part of 3rd Embodiment of this invention. It is a block circuit diagram of the principal part of an example of the conventional ferroelectric memory. It is a detailed circuit diagram of the principal part of an example of a conventional ferroelectric memory. FIG. 8 is a waveform diagram showing a data read operation of the conventional ferroelectric memory shown in FIG. 7 (FIG. 8). FIG. 8 is a waveform diagram for explaining a problem that the conventional ferroelectric memory shown in FIG. 7 (FIG. 8) has.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... 2-transistor / 2 capacitor type memory cell 2, 3 ... Pre-sense amplifier 4 ... Threshold generation circuit 5 ... Negative voltage generation circuit 6 ... Sense amplifier 7, 8 ... Schmitt trigger circuit 9 ... NAND gate 10, 11 ... Variable threshold Schmitt Trigger circuits 12, 13... Variable threshold inverter 14... First embodiment of the present invention 15-1, 15-m... 1 transistor / 1 capacitor type memory cell 16-1, 16-m. -M ... sense amplifier

Claims (5)

A two-transistor / 2-capacitor type first memory cell having first and second ferroelectric capacitors for storing complementary data;
A first pre-sense amplifier for detecting data read from the first ferroelectric capacitor to the first bit line;
A second pre-sense amplifier for detecting data read from the second ferroelectric capacitor to the second bit line;
First potential detecting means for detecting that the output of the first pre-sense amplifier has reached a predetermined potential;
Second potential detecting means for detecting that the output of the second pre-sense amplifier has reached a predetermined potential;
A first sense amplifier that is activated by an output signal change of either of the first and second potential detection means and amplifies an output potential difference between the first and second pre-sense amplifiers;
The first potential detecting means is configured such that the threshold value changes according to the output potential of the second pre-sense amplifier,
The ferroelectric memory, wherein the second potential detecting means is configured such that a threshold value thereof changes in accordance with an output potential of the first pre-sense amplifier. The first potential detecting means is configured such that the threshold value decreases in response to an increase in the output potential of the second pre-sense amplifier,
2. The ferroelectric memory according to claim 1, wherein the second potential detection unit is configured such that a threshold value thereof decreases as the output potential of the first pre-sense amplifier increases. 3. The first potential detection means includes a first Schmitt trigger circuit having a first NMOS transistor for pull-down, and a second NMOS transistor,
The first Schmitt trigger circuit has an input terminal connected to an output terminal of the first pre-sense amplifier,
The second NMOS transistor has a drain connected to the drain of the first NMOS transistor, a source grounded, a gate connected to the output terminal of the second pre-sense amplifier,
The second potential detection means has a second Schmitt trigger circuit having a third NMOS transistor for pull-down, and a fourth NMOS transistor,
The second Schmitt trigger circuit has an input terminal connected to an output terminal of the second pre-sense amplifier,
The drain of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, the source is grounded, and the gate is connected to the output terminal of the first pre-sense amplifier. 2. The ferroelectric memory according to 2. The first potential detecting means includes a first inverter having a first NMOS transistor for pull-down, and a second NMOS transistor,
The first inverter has an input terminal connected to an output terminal of the first pre-sense amplifier,
The second NMOS transistor has a drain connected to the drain of the first NMOS transistor, a source grounded, a gate connected to the output terminal of the second pre-sense amplifier,
The second potential detecting means has a second inverter having a third NMOS transistor for pull-down, and a fourth NMOS transistor,
The drain of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, the source is grounded, and the gate is connected to the output terminal of the first pre-sense amplifier. 2. The ferroelectric memory according to 2. A one-transistor / one-capacitor type second memory cell having a third ferroelectric capacitor and reading data simultaneously with the first memory cell;
A third pre-sense amplifier for detecting data read from the third ferroelectric capacitor to the third bit line;
A second sense amplifier that is activated by an output signal change of either the first or second potential detection means and that amplifies a potential difference between the output potential of the third pre-sense amplifier and a reference potential; 5. The ferroelectric memory according to claim 1, 2, 3 or 4.

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