KR102652188B1 - Current-Latched Sense Amplifier And Memory Device - Google Patents

Abstract

The present disclosure provides a sense amplifier circuit that detects and amplifies a differential input voltage applied to a pair of input nodes and outputs a differential output voltage to a pair of output nodes, and when a reference voltage is applied, supplies it to the reference voltage node and the sensing node for biasing, Afterwards, the applied input voltage is transferred to the sensing node, and the offset is removed by including an offset removal circuit that applies the input voltage difference representing the voltage difference between the reference voltage and the input voltage to one of the input node pairs through coupling, thereby increasing the sensing yield. In addition, it provides a current latch sense amplifier and memory device that can operate stably in a wide input voltage range by biasing the reference voltage at the differential input stage.

Description

Current-Latched Sense Amplifier And Memory Device

The present disclosure relates to a current latch sense amplifier and memory device, and to a current latch sense amplifier and memory device capable of eliminating offset.

A sense amplifier (SA) is a circuit that detects a small differential input value and amplifies it into a digital value (1 or 0), and is typically used to read data stored in memory cells of a memory device. Sense amplifiers have the advantage of significantly reducing the power consumption required for read operations of memory devices.

Among sense amplifiers, the latch sense amplifier, which has a latch structure composed of cross-connected inverters, has positive feedback characteristics and enables low-power and high-speed read operations, so it is used in various fields as well as memory devices. Latch-type SA can be largely divided into voltage-latched sense amplifier (Voltage-Latched SA: VLSA) and current-latched sense amplifier (Current-Latched SA: CLSA). Voltage latch sense amplifiers (VLSA) have advantages over current latch sense amplifiers (CLSA) in size and operating speed. However, in order to reduce power consumption, when multiple sense amplifiers are configured to commonly share the reference voltage (V _REF ) generated in the reference voltage generation circuit and be applied to one of the differential inputs, the voltage latch sense amplifier (VLSA) uses the shared reference voltage (V REF ) to reduce power consumption. There is a problem that it is vulnerable to noise due to temporary voltage fluctuations in the reference voltage (V _REF ). Therefore, in devices using a common reference voltage (V _REF ), it is more desirable to use a current latch sense amplifier (CLSA) than a voltage latch sense amplifier (VLSA).

Figure 1 shows an example of a current latch sense amplifier.

Referring to FIG. 1, the first PMOS transistor (MP1) and the first NMOS transistor (MN1) have a common gate connected to the inverting output node (OUTB), and the second PMOS transistor (MP2) and the second NMOS transistor (MN2) ) has a common gate connected to the output node (OUT).

Therefore, the first PMOS transistor (MP1) and the first NMOS transistor (MN1) can be said to be a first inverter in which the inverting output node (OUTB) is the input terminal and the output node (OUT) is the output terminal, and the second PMOS transistor (MP2) and the second NMOS transistor (MN2) can be said to be a second inverter in which the output node (OUT) is an input terminal and the inverting output node (OUTB) is an output terminal. Since the input and output terminals of the first inverter and the second inverter are cross-connected, the two PMOS transistors (MP1, MP2) and two NMOS transistors (MN1, MN2) in the current latch sense amplifier of FIG. 1 have a latch structure. .

The third and fourth NMOS transistors (MN3, MN4) cause a difference between the current flowing through each transistor (MN3, MN4) depending on the reference voltage (V _REF ) and the input voltage (V _BL ) applied to the gate. It is an input transistor that causes a voltage difference between the output node pair (OUT, OUTB). The third and fourth PMOS transistors (MP3, MP4) are precharge transistors that precharge the output node pair (OUT, OUTB) to the power supply voltage (V _DD ) level in response to the sense amplifier enable signal (SAE), and the fifth The NMOS transistor (MNFOOT) is a foot switch transistor that activates the current latch sense amplifier in response to the sense amplifier enable signal (SAE).

As shown in FIG. 1, a current latch sense amplifier including a foot switch transistor (MNFOOT) is called FS-CLSA (Foot Switch-CLSA). FS-CLSA has a symmetrical structure to receive and amplify differential inputs (here, reference voltage (V _REF ) and input voltage (V _BL )).

As shown in FIG. 1, in FS-CLSA with a symmetrical structure, an offset voltage (V _OS ) may occur, which is mainly caused by a mismatch in the threshold voltage (V _TH ) of the transistors. The offset voltage (V _OS ) is most affected by the threshold voltage difference between the third and fourth NMOS transistors (MN3, MN4), but the threshold voltage difference between the first and second NMOS transistors (MN1, MN2) included in the latch It is also influenced by

And in a latch sensing amplifier where an offset voltage (V _OS ) exists, the voltage difference (ΔV = V _BL - V _REF ) between the input voltage (V _BL ) and the reference voltage (V _REF ) must be greater than the offset voltage (V _OS ). (ΔV > V _OS ), the input can be sensed and amplified normally. That is, sensing errors may occur due to the offset voltage (V _OS ).

Figure 2 shows the results of simulating the change in standard deviation of the offset voltage with respect to the input voltage in the current latch sense amplifier.

Figure 2 shows the change in the standard deviation (σ _OS ) of the offset voltage (V _OS ) as the input voltage (V _BL ) increases.

In FS-CLSA as shown in FIG. 1, the reference voltage (V _REF ) and the input voltage (V _BL ) must be higher than the threshold voltages of the third and fourth NMOS transistors (MN3 and MN4), respectively, in order for the fourth NMOS transistor (MN4) to turn on. and the action can be performed. The reference voltage V _REF can be easily generated and applied at a voltage greater than the threshold voltage of the third NMOS transistor MN3 by the reference voltage generator. Therefore, as shown in FIG. 2, FS-CLSA operates normally only in the section where the voltage level of the input voltage (V _BL ) is higher than the threshold voltage (here, 0.35V as an example) of the fourth NMOS transistor (MN4), and the input The section in which FS-CLSA does not operate because the voltage level of the voltage V _BL is lower than the threshold voltage of the fourth NMOS transistor MN4 is called a dead zone.

And when the input voltage (V _BL ) becomes higher than the threshold voltage of the fourth NMOS transistor (MN4), FS-CLSA operates, but a sensing error may occur due to the offset voltage (V _OS ).

As shown in FIG. 2, the sensing error caused by the offset voltage (V _OS ) is caused by increasing the size of the transistor to reduce the threshold voltage (V _TH ) difference or by increasing the voltage difference (ΔV). can be reduced. However, in order to increase the size of the transistor, the size of the sense amplifier must be increased, so it is not suitable for miniaturization.

Additionally, there is a problem that power consumption increases in order to increase the voltage difference (ΔV). In addition, in order to increase the voltage difference (ΔV), when the voltage level of the input voltage (V _BL ) increases above a certain level, the saturation current of the third and fourth NMOS transistors (MN3 and MN4) increases and becomes linear. It operates in the area. In this case, as shown in FIG. 2, the threshold voltage difference between the first and second NMOS transistors (MN1, MN2) of the latch has a greater effect on sensing, resulting in the standard deviation (σ _OS ) of the offset voltage (V _OS ). Rather, it increases.

Therefore, FS-CLSA not only has a problem in that the voltage range of the input voltage (V _BL ) that can be operated is greatly limited by the offset voltage (V _OS ) along with the presence of a dead zone, but also causes a sensing error.

Accordingly, a current latch sense amplifier that can eliminate the offset caused by the threshold voltage of the input transistors (MN3, MN4) has previously been proposed. However, in the case of the existing offset cancellation current latch sense amplifier, as shown in the graph shown as OC-CLSA in FIG. 2, the linear region of the third and fourth NMOS transistors (MN3 and MN4) still increases as the input voltage (V _BL ) increases. It can be seen that the offset voltage (V _OS ) variation due to operation increases significantly. That is, the voltage range of the input voltage (V _BL ) in which the current latch sense amplifier can operate is limited.

An object of the present disclosure relates to a current latch sense amplifier and memory device that can improve sensing yield by eliminating offset.

An object of the present disclosure relates to a current latch sense amplifier and memory device that can operate stably in a wide input voltage range by biasing a reference voltage at the differential input terminal.

According to an embodiment of the present disclosure, a current latch sense amplifier includes a sense amplifier circuit that detects and amplifies a differential input voltage applied to a pair of input nodes and outputs a differential output voltage to a pair of output nodes; And when the reference voltage is applied, it is supplied to a reference voltage node and a sensing node for biasing, and then the applied input voltage is transmitted to the sensing node, and an input voltage difference representing a voltage difference between the reference voltage and the input voltage is provided. It includes an offset removal circuit that applies to one of the input node pairs through coupling.

The offset removal circuit is a transistor in which the input node pair causes an offset of the sense amplifier circuit in the offset capture section of the operation section of the current latch sense amplifier, which is divided into a precharge section, an offset capture section, a signal input section, and a sensing section. The offset can be removed by having a voltage level according to the threshold.

The offset removal circuit may apply a voltage according to the sum of the input voltage difference and the voltage according to the threshold to one of the input node pairs having a voltage level according to the threshold to the signal input section.

The current latch sense amplifier is a first precharge signal activated in the precharge section and the first activated in the offset capture section among the operation sections of the current latch sense amplifier, which are divided into a precharge section, an offset capture section, a signal input section, and a sensing section. It may operate according to a control signal, a second control signal activated in the signal input section, a third control signal activated in the signal input section and the sensing section, and a sense amplifier enable signal activated in the sensing section.

The offset removal circuit includes a precharge circuit connected between a power supply voltage and each precharge node pair to precharge the precharge node pair to the power supply voltage level during a precharge period; first and second switches that are turned on in the precharge period and the offset capture period to electrically connect each of the precharge node pair and the input node pair; First and second capacitors respectively connected between the input node pair, the reference voltage node, and the sensing node; a third switch that is turned on during the precharge period and the offset capture period to connect the reference voltage node and the sensing node; And it may include a fourth switch that is turned on in the signal input section and transmits the applied input voltage to the sensing node.

The sense amplifier circuit includes a head transistor connected between a power supply voltage and a head node, and pulling up the head node to the power supply voltage level during a sensing period; a pull-up circuit that precharges the output node pair by pulling them up to the power supply voltage level during a signal input section; a latch circuit connected between the head node and the precharge node pair, and detecting and inverting and amplifying the voltage level of the output node pair in a sensing period; an input circuit electrically connecting the precharge node pair and the common node according to the voltage level of the input node pair; an isolation circuit that deactivates the input circuit by pulling down the output node pair to a ground voltage level during a precharge period and an offset capture period; and a foot switch transistor connected between the common node and the ground voltage and pulling down the common node to the ground voltage level during the offset capture period and the sensing period.

The latch circuit is connected in series between the head node and a first precharge node of the precharge node pair, and a first PMOS transistor and a first NMOS transistor whose gate is commonly connected to an inverting output node of the output node pair. A first inverter having a; and a second PMOS transistor and a second NMOS transistor connected in series between the head node and a second precharge node of the precharge node pair, and having a common gate connected to an output node of the output node pair. 2 May include an inverter.

The input circuit includes a first input transistor connected between a first precharge node of the precharge node pair and the common, and a gate of which is an NMOS transistor connected to an inverting input node of the input node pair; and a second input transistor connected between a second precharge node of the precharge node pair and the common, and having a gate of an NMOS transistor connected to an input node of the input node pair.

The pull-up circuit is connected between the power supply voltage and each of the output node and the inverting output node of the output node pair, and has first and second pull-up circuits that pull up the output node pair to the power supply voltage level in response to the second inverting control signal. It may include a pull-up transistor.

The isolation circuit is connected between each of the output node and the inverting output node of the output node pair and the ground voltage, and pulls down the output node pair to the ground voltage level in response to a precharge signal and a first control signal. and a second isolation transistor.

According to another embodiment of the present disclosure, a memory device includes a memory cell array including a plurality of memory cells defined by a plurality of word lines and a plurality of bit lines; and

At least one current that receives an input voltage having a voltage level according to the data stored in a memory cell connected to a word line selected from among the plurality of word lines and a bit line selected from the plurality of bit lines, and detects and amplifies the voltage difference from the reference voltage An SA module including a latch sense amplifier, wherein the current latch sense amplifier detects and amplifies a differential input voltage applied to a pair of input nodes and outputs a differential output voltage to a pair of output nodes, and the reference voltage. When this is applied, it is supplied to the reference voltage node and the sensing node for biasing, and then the applied input voltage is transmitted to the sensing node, and the input voltage difference representing the voltage difference between the reference voltage and the input voltage is coupled. It includes an offset removal circuit that applies to one of the input node pairs through.

The current latch sense amplifier and memory device of the present disclosure can not only improve sensing yield by removing offset, but also operate stably in a wide input voltage range by biasing a reference voltage at the differential input terminal.

Figure 1 shows an example of a current latch sense amplifier.
Figure 2 shows the results of simulating the change in standard deviation of the offset voltage with respect to the input voltage in the current latch sense amplifier.
Figure 3 shows an example of an offset cancellation current latch sense amplifier according to the present disclosure.
FIG. 4 shows an operation timing diagram of the current latch sense amplifier of FIG. 3.
Figure 5 shows the results of simulating the change in standard deviation of the offset voltage with respect to the input voltage in the current latch sense amplifier of the present disclosure.
Figure 6 shows a schematic structure of a semiconductor memory device including the OC-CLSA of the present disclosure.

Hereinafter, specific embodiments according to embodiments of the present disclosure will be described with reference to the drawings. The detailed description below is provided to provide a comprehensive understanding of the methods, devices and/or systems described herein. However, this is only an example and the present invention is not limited thereto.

In describing the embodiments of the present disclosure, if it is determined that detailed descriptions of known technologies related to the present invention may unnecessarily obscure the gist of the embodiments, the detailed descriptions will be omitted. In addition, the terms described below are terms defined in consideration of functions in the present invention, and may vary depending on the intention or custom of the user or operator. Therefore, the definition should be made based on the contents throughout this specification. The terminology used in the detailed description is intended to describe only one embodiment and should in no way be limiting. Unless explicitly stated otherwise, singular forms include plural meanings. In this description, expressions such as “including” or “including” are intended to indicate certain features, numbers, steps, operations, elements, parts or combinations thereof, and one or more than those described. It should not be construed to exclude the existence or possibility of any other characteristic, number, step, operation, element, or part or combination thereof. In addition, terms such as “…unit”, “…unit”, “module”, and “block” used in the specification refer to a unit that processes at least one function or operation, which is hardware, software, or hardware. and software.

FIG. 3 shows an example of an offset cancellation current latch sense amplifier according to the present disclosure, and FIG. 4 shows an operation timing diagram of the current latch sense amplifier of FIG. 3.

Referring to FIG. 3, the offset-cancelling current-latched sense amplifier (OC-CLSA) of the present disclosure may include a sense amplifier circuit 11 and an offset-cancelling circuit. You can. The sense amplifier circuit 11 detects and amplifies the differential input voltage applied to the input node pair (INB, IN) and outputs the differential output voltage to the output node pair (OUT, OUTB).

The sense amplifier circuit 11 has a latch structure circuit similar to the existing current latch sense amplifier shown in FIG. 1. The latch structure circuit consists of two inverters equipped with two PMOS transistors (MP1, MP2) and two NMOS transistors (MN1, MN2). Additionally, the sense amplifier circuit 11 includes two input transistors (MN3, MN4) to which differential inputs are applied, two pull-up transistors (MP3, MP4), and a foot switch transistor (MNFOOT). However, unlike the current latch sense amplifier in FIG. 1, the sense amplifier circuit 11 in the OC-CLSA of the present disclosure further includes a head switch transistor (MPHEAD) and two isolation transistors (MN5, MN6).

The first PMOS transistor MP1 is connected between the head node (HEAD) and the output node (OUT), and the first NMOS transistor (MN1) is connected between the output node (OUT) and the first precharge node (PCG1). , the gate is commonly connected to the inverting output node (OUTB). And the second PMOS transistor (MP2) is connected between the head node (HEAD) and the inverting output node (OUTB), and the second NMOS transistor (MN2) is connected between the inverting output node (OUTB) and the second precharge node (PCG2). It is connected to , and the gate is commonly connected to the output node (OUT). That is, the first PMOS transistor (MP1) and the first NMOS transistor (MN1) connected in series between the head node (HEAD) and the first precharge node (PCG1) constitute the first inverter of the latch, and the head node (HEAD) The second PMOS transistor (MP2) and the second NMOS transistor (MN2) connected in series between and the second precharge node (PCG2) constitute the second inverter of the latch.

The first and second input transistors (MN3, MN4) are differential input circuits of the sense amplifier circuit 11 and are implemented as NMOS transistors. The first input transistor (MN3) is connected between the first precharge node (PCG1) and the common node (COMN), and its gate is connected to the inverting input node (INB). The second input transistor MN4 is connected between the second precharge node PCG2 and the common node COMN, and its gate is connected to the input node IN.

The foot switch transistor (MNFOOT) is also implemented as an NMOS transistor and is connected between the common node (COMN) and the ground voltage (V _SS ), and the first control signal (P1) and the sense amplifier enable signal (SAE) are used as gates. approved. In the present disclosure, the foot switch transistor (MNFOOT) is turned on when the sense amplifier enable signal (SAE) as well as the first control signal (P1) is activated to the first level (here, a high level as an example), thereby connecting the common node (COMN). Pull down to the ground voltage (V _SS ) level.

Meanwhile, the head switch transistor (MPHEAD) is connected between the power supply voltage (V _DD ) and the head node (HEAD), and sends an inverting sense amplifier enable signal ( ) is implemented with a PMOS transistor that is applied. The head switch transistor (MPHEAD) activates the inverting sense amplifier enable signal ( ) becomes the second level (here, a low level as an example), that is, when the sense amplifier enable signal (SAE) is activated to the first level, it is turned on and the power supply voltage (V _DD ) is sent to the head node (HEAD). authorizes.

As described above, in the OC-CLSA of the present disclosure, for the operation of the offset removal circuit, the foot switch transistor (MNFOOT) is turned on in response to the first control signal (P1) as well as the sense amplifier enable signal (SAE). Accordingly, the head switch transistor (MPHEAD) controls the driving timing of the latch by allowing the power supply voltage (V _DD ) to be applied to the latch of the sense amplifier circuit 11 when the sense amplifier enable signal (SAE) is activated.

The first and second pull-up transistors MP3 and MP4 are connected between the power supply voltage (V _DD ) and the output node (OUT), and the second pull-up transistor (MP4) is connected to the power supply voltage (V). It is connected between _DD ) and the inversion output node (OUTB), and the gate is commonly used as a second inversion control signal ( ) is implemented with a PMOS transistor that is applied. That is, the first and second pull-up transistors (MP3, MP4) have a second inversion control signal applied to the gate ( ), it is a pull-up circuit that precharges the output node pair (OUT, OUTB) by pulling up the output node pair (OUT, OUTB) to the power supply voltage (V _DD ) level, corresponding to the two precharge transistors (MP3, MP4) in the sense amplifier shown in FIG. configuration, or the second inverting control signal (not the sense amplifier enable signal (SAE)) ) is different in that it is approved.

The first isolation transistor (MN5) is connected between the inverting output node (OUTB) and the ground voltage (V _SS ), and the second isolation transistor (MN6) is connected between the output node (OUT) and the ground voltage (V _SS ), , It is implemented as an NMOS transistor to which a precharge signal (PRE) and a first control signal (P1) are commonly applied to the gate. The first and second isolation transistors (MN5, MN6) are turned on when the pre-charge signal (PRE) and the first control signal (P1) are activated to the first level, and connect the output node pair (OUT, OUTB) to the ground voltage (V). It can be viewed as a pull-down circuit that pulls down to _{the SS} ) level. When the output node pair (OUT, OUTB) is pulled down to the ground voltage (V _SS ) level, the first and second NMOS transistors (MN1, MN2) of the latch are turned off, so the first isolation transistor (MN5) is connected to the output node pair. Ensure that the electrical connection between (OUT, OUTB) and the precharge node pair (PCG1, PCG2) is blocked.

Meanwhile, the offset removal circuit includes two precharge transistors (MP5, MP6), four switches (TG1 to TG4), and two capacitors (C1 _SA , C2 _SA ).

The first precharge transistor (MP5) is connected between the power supply voltage (V _DD ) and the first precharge node (PCG1), and the second precharge transistor (MP6) is connected between the power supply voltage (V _DD ) and the second precharge node. (PCG2), and the gate has a common inverted precharge signal ( ) is implemented with a PMOS transistor that is applied. The two precharge transistors (MP5, MP6) provide an inverted precharge signal ( ) is applied to the second level, that is, when the precharge signal (PRE) is activated to the first level, it is turned on to precharge the first and second precharge nodes (PCG1, PCG2) to the power supply voltage (V _DD ) level. It can be viewed as a precharge circuit.

The four switches (TG1 to TG4) can be implemented as transmission gates. Among the four switches (TG1 to TG4), the first switch (TG1) is connected between the first precharge node (PCG1) and the inverting input node (INB), and the second switch (TG2) is connected to the second precharge node (PCG2). ) and the input node (IN). The first and second switches (TG1, TG2) are turned on in response to the precharge signal (PRE) and the first control signal (P1), respectively, and the first and second precharge nodes (PCG1 and PCG2) and the inverting input node ( INB) and input node (IN) are electrically connected.

And the third switch (TG3) is connected between the reference voltage node (INB_VG) to which the reference voltage (V _REF ) is applied from the reference voltage generator 20 and the sensing node (IN_SC), and the first and second switches (TG1, Like TG2), it is turned on in response to the precharge signal (PRE) and the first control signal (P1) to connect the reference voltage node (INB_VG) and the sensing node (IN_SC).

The fourth switch (TG4) is connected between the sensing circuit 30, which outputs the input voltage (V _BL ) to be sensed, and the sensing node (IN_SC), and is turned on in response to the third control signal (P3) to increase the input voltage (V). _BL ) is transmitted to the sensing node (IN_SC).

The first capacitor (C1 _SA ) is connected between the inverting input node (INB) and the reference voltage node (INB_VG), and the second capacitor (C2 _SA ) is connected between the input node (IN) and the sensing node (IN_SC). The first and second capacitors C1 _SA and C2 _SA may be implemented as MOS capacitors. The first and second capacitors (C1 _SA , C2 _SA ) allow the input node pair (INB, IN), the reference voltage node (INB_VG), and the sensing node (IN_SC) to have a voltage difference, so that the reference voltage node (INB_VG) and ensures that the sensing node (IN_SC) is biased to the reference voltage (V _REF ) level, as well as the voltage difference (ΔV) between the input voltage (V _BL ) and the biased reference voltage (V _REF ) through coupling. Ensure that it is applied to the input node (IN).

The operation of the OC-CLSA of the present disclosure shown in FIG. 3 is divided into a precharge section (PCH), an offset capture section (S1), a signal input section (S2), and a sensing section (S3), as shown in FIG. 4. It can be.

In the precharge period (PCH), the precharge signal (PRE) is activated at the first level, while the first to third control signals (P1 to P3) and the sense amplifier enable signal (SAE) are deactivated at the second level. . And in the offset capture section S1, the first control signal P1 is activated at the first level, and the remaining signals (PRE, P2, P3, SAE) are deactivated at the second level. In the signal input section S2, the second and third control signals P2 and P3 are activated together at the first level. Finally, in the sensing section (S3), the second control signal (P2) is deactivated at the second level, while the third control signal (P2) remains activated at the first level, and additionally, the sense amplifier enable signal ( SAE) is activated to the first level.

Referring to FIGS. 3 and 4, when describing the operation of the OC-CLSA according to the present disclosure, first, in the precharge period (PCH), the precharge signal (PRE) is activated at the first level, and thus the first and second The precharge transistors (MP5, MP6) invert the precharge signal ( ) is turned on in response to precharge the first and second precharge nodes (PCG1, PCG2) to the power supply voltage (V _DD ) level. And the first and second switches (TG1, TG2) are also turned on in response to the activated precharge signal (PRE) to connect the first and second precharge nodes (PCG1, PCG2) and the input node pair (INB, IN). Therefore, the input node pair (INB, IN) is also precharged to the power supply voltage (V _DD ) level. Therefore, in the precharge period (PCH), the first and second input transistors (MN3, MN4) are connected in a diode structure.

Meanwhile, the first and second isolation transistors (MN5, MN6) are also turned on, pulling down the output node pair (OUT, OUTB) to the ground voltage (V _SS ) level, thereby making the first and second NMOS transistors (MN1, MN2) Turn it off. As the first and second NMOS transistors (MN1, MN2) are turned off, the output node pair (OUT, OUTB) and the first and second precharge nodes (PCG1, PCG2) are electrically cut off. Therefore, the output node pair (OUT, OUTB) is not affected by the voltage of the input node pair (INB, IN), which is precharged to the power supply voltage (V _DD ) level. At this time, the first and second PMOS transistors (MP1, MP2) are turned on, but the head switch transistor (MPHEAD) and the first and second pull-up transistors (MP3, MP4) turn on the inverting sense amplifier enable signal ( ) and the inverted second control signal ( ), so no separate voltage is applied, so the output node pair (OUT, OUTB) is in a floating state.

When the input node pair (INB, IN) is precharged to the power supply voltage (V _DD ) level, the first and second input transistors (MN3, MN4) are turned on, but the foot switch transistor (MNFOOT) is turned off, Since the first and second NMOS transistors (MN1, MN2) of the latch are turned off by the turned-on first and second isolation transistors (MN5, MN6), a current path is not formed and the first and second precharge nodes (PCG1, PCG2) maintains the precharged power supply voltage (V _DD ) level.

And the third switch (TG3) is turned on in response to the precharge signal (PRE) to transmit the reference voltage (V _REF ) generated by the reference voltage generator 20 and applied to the reference voltage node (INB_VG) to the sensing node (IN_SC). Deliver. Therefore, the precharge voltage (here, the power supply voltage (V _DD )) is applied to one end of the two capacitors (C1 _SA , C2 _SA ), and the reference voltage (V _REF ) is applied to the other end to form the two capacitors (C1 _SA , C2 _SA ). Since the voltage difference between the precharge voltage and the reference voltage (V _REF ) is charged, the reference voltage node (INB_VG) and the sensing node (IN_SC) are biased to the reference voltage (V _REF ) level.

In the offset capture period (S1), the precharge signal (PRE) is deactivated, while the first control signal (P1) is activated. Accordingly, the first and second precharge transistors (MP5, MP6) that receive only the precharge signal (PRE) as the gate are turned off, but the first precharge transistors (MP5, MP6) that receive both the precharge signal (PRE) and the first control signal (P1) are turned off. And the second isolation transistors (MN5, MN6) and the first to third switches (TG1 to TG3) remain turned on. And the foot switch transistor (MNFOOT) is additionally turned on in response to the first control signal (P1).

As the first and second precharge transistors MP5 and MP6 are turned off, the power supply voltage V _DD applied to the precharge nodes PCG1 and PCG2 is blocked. And as the foot switch transistor (MNFOOT) is turned on and the common node (COMN) is connected to the ground voltage (V _SS ), the first and second precharge nodes ( The voltage level of PCG1, PCG2) and the input node pair (INB, IN) drops.

At this time, the voltage level of the input node pair (INB, IN) gradually decreases from the power supply voltage (VDD) level by the first and second capacitors (C1 _SA , C2 _SA ). However, since the first and second input transistors (MN3, MN4) are connected in a diode structure, the voltage level of the first precharge node (PCG1) and the inverting input node (INB) is the threshold of the first input transistor (MN3). The voltage level drops to V _TH3 , and the voltage levels of the second precharge node PCG2 and the input node IN drop to the threshold voltage V _TH4 level of the second input transistor MN4.

When the voltage level of the input node pair (INB, IN) drops to the threshold voltage (V _TH3 , V _TH4 ) level of the first and second input transistors (MN3, MN4), the first and second input transistors (MN3, MN4) ) is turned off. Accordingly, the threshold voltages (V TH3, V _TH4 ) of the first and second input transistors ( _MN3 , MN4) are captured in the input node pair (INB, IN). Hereinafter, the threshold voltages (V _TH3 , V TH4) of the first and second input transistors (MN3, _MN4 ) captured in the input node pair (INB, IN) are respectively inverted to the input threshold voltage (V _{TH_INB} = V _TH3 ) and the input It is called the threshold voltage (V _{TH_IN} = V _TH4 ).

Since the precharge signal PRE is in an inactive state in the signal input section S2, the first and second precharge transistors MP5 and MP6 remain turned off. And as the first control signal P1 is deactivated to the second level, the foot switch transistor MNFOOT and the first and second isolation transistors MN5 and MN6 are turned off. At the same time, the first to third switches TG1 to TG3 are turned off. On the other hand, since the second and third control signals (P2, P3) are activated at the first level, the first and second pull-up transistors (MP3, MP4) invert the second control signal ( ), and the fourth switch TG4 is turned on in response to the third control signal P3.

Since the first and second pull-up transistors (MP3, MP4) are turned on and the first and second isolation transistors (MN5, MN6) are turned off, the output node pair (OUT, OUTB) is at the power supply voltage (V _DD ) level. It is precharged. And the first and second NMOS transistors (MN1, MN2) are turned on according to the voltage level of the output node pair (OUT, OUTB) precharged to the power supply voltage (V _DD ) level, and the output node pair (OUT, OUTB) The precharge node pair (PCG1, PCG2) is electrically connected. Since the first and second precharge transistors MP5 and MP6 are turned off, the precharge node pair PCG1 and PCG2 are also precharged to the power supply voltage V _DD level.

At this time, since the first and second switches TG1 and TG2 are turned off, the voltage change of the precharge node pair PCG1 and PCG2 does not affect the input node pair INB and IN. Instead, when the fourth switch (TG4) is turned on and the input voltage (V _BL ) is applied to the sensing node (IN_SC), the sensing node (IN_SC) having the reference voltage (V _REF ) level is applied to the applied input voltage (V _BL ). This changes by the input voltage difference (ΔV = V _BL - V _REF ), which represents the voltage difference between the input voltage (V _BL ) and the reference voltage (V _REF ). That is, the voltage of the sensing node (IN_SC) changes as V _REF + ΔV.

Accordingly, the second capacitor (C2 _SA ) transfers the voltage change of the sensing node (IN_SC) to the input node (IN) through coupling, and the input node (IN) increases the input voltage difference (V _{TH_IN) to the captured input threshold voltage (V TH_IN} ). ΔV) to have the combined voltage level (V _{TH_IN} + ΔV).

That is, in the present disclosure, the reference voltage node (INB_VG) and the sensing node (IN_SC) are already biased to the reference voltage (V _REF ) level in the offset capture section (S1), and the input node pair ( Since the inverted input threshold voltage (V _{TH_INB} ) and the input threshold voltage (V _THIN ) are captured in INB, IN), respectively, only the input voltage difference (ΔV) is applied to the input node (IN) in the signal input section (S2). .

Therefore, the inverting input node (INB) has an inverted input threshold voltage (V TH_INB) level of the same voltage level as the threshold voltage (V _TH3 ) of the first input transistor (MN3), while the input node (IN) has the same voltage level as the threshold voltage (V _TH3 ) of the first input transistor (MN3). It has a voltage level (V _{TH_IN} + ΔV) that is different from the input threshold voltage (V _{TH_IN} ) of the same level as the threshold voltage (V TH4) of (MN4) by the input voltage difference ( _ΔV ). Accordingly, the first input transistor MN3 is maintained in a turned-off state, but the second input transistor MN4 is turned on by the input voltage difference ΔV. That is, the input node IN has a voltage level of V _{TH_IN} + ΔV and the second input transistor MN4 is turned on.

Finally, since the precharge signal (PRE) and the first control signal (P1) are kept in an inactive state in the sensing section (S3), the first and second precharge transistors (MP5, MP6) and the first and second isolation The transistors MN5 and MN6 remain turned off, and the first to third switches TG1 to TG3 remain turned off. And since the second control signal (P2) is deactivated at the second level, the first and second pull-up transistors (MP3 and MP4) are turned off. However, the fourth switch TG4 is maintained in the on state because the third control signal P3 is activated. Then, the sense amplifier enable signal (SAE) is activated to the first level, and the foot switch transistor (MNFOOT) and the head switch transistor (MPHEAD) are turned on.

The first and second precharge transistors (MP5, MP6) and the first and second pull-up transistors (MP3, MP4) are maintained in the turned-off state, and the first and second isolation transistors (MN5, MN6) are turned off. Therefore, at the beginning of the sensing period (S3), the first and second PMOS transistors (MP1, MP2) are turned off according to the voltage level (power supply voltage (V _DD )) of the precharged output node pair (OUT, OUTB). state, and the first and second NMOS transistors (MN1, MN2) are turned on. Since the first and second PMOS transistors (MP1, MP2) are turned off, current does not flow to the output node pair (OUT, OUTB) at the beginning of the sensing period (S3) even if the head switch transistor (MPHEAD) is turned on.

However, when the foot switch transistor (MNFOOT) is turned on, the second input transistor (MN4) is turned on by the input voltage difference (ΔV). Since the second input transistor ( _MN4 ) is turned on, the ground voltage ( A current path up to V _SS ) is formed. Accordingly, the voltage level of the inverting output node (OUTB) falls, while the voltage level of the output node (OUT) is maintained at the power supply voltage (V _DD ). When the voltage level of the inverting output node (OUTB) begins to fall, the voltage difference between the output node pair (OUT, OUTB) increases due to a latch composed of two inverters. As a result, the output node (OUT) is output at the power voltage (V _DD ) level, and the inverted output node (OUTB) is output at the ground voltage (V _SS ) level.

In other words, OC-CLSA can detect and amplify the input voltage (V _BL ) and output a differential output signal.

In the present disclosure, the reference voltage (V _REF ) may be adjusted and applied in advance in consideration of the target voltage range of the input voltage (V _BL ) to be sensed. For example, if the target voltage range of the input voltage (V _BL ) is 0.8V < V _BL < 1.0V, the reference voltage (V _REF ) can be set to 0.9V, and the target voltage range is 0.0V < V _BL < In the case of 0.2V, the reference voltage (V _REF ) can be set to 0.1V.

Figure 5 shows the results of simulating the change in standard deviation of the offset voltage with respect to the input voltage in the current latch sense amplifier of the present disclosure.

In Figure 5, to compare the performance of the OC-CLSA of the present disclosure, FS-CLSA with an increased _size , and an input node pair ( _INB , OC-CLSA and reference voltage (V _REF ) biasing are performed by directly inputting the reference voltage (V _REF ) and input voltage (V _BL ) to IN), and applying the input voltage difference (ΔV) only to the input node (IN) An operation graph of the OC-CLSA of the present disclosure is also shown.

As shown in FIG. 5, FS-CLSA not only has a dead zone due to the threshold voltage of the input transistors (MN3, MN4), but also has an offset when the input voltage (V _BL ) rises above a certain level despite the increase in size. It can be seen that the standard deviation (σ _OS ) of the voltage (V _OS ) is greatly increased. And OC-CLSA, which does not perform reference voltage (V _REF ) biasing, captures the inverted input threshold voltage (V _{TH_INB} ) and input threshold voltage (V _THIN ) at the input node pair (INB, IN), so the dead zone can be eliminated. However, as the input voltage (V _BL ) increases, the input transistors (MN3 and MN4) operate in the linear region. As a result, the influence of the threshold voltage difference between the first and second NMOS transistors (MN1, MN2) of the latch on the offset voltage (V _OS ) increases, so that the standard deviation (σ _OS ) of the offset voltage (V _OS ) gradually increases. do.

On the other hand, in the OC-CLSA of the present disclosure, the inverted input threshold voltage (V _{TH_INB} ) and the input threshold voltage (V THIN) are captured for the input node pair (INB, IN) in the offset capture period ( _S1 ), so that the offset is removed. In addition, there is no dead zone for the input voltage (V _BL ). In addition, as the reference voltage node (INB_VG) and the sensing node (IN_SC) are already biased to the reference voltage (V _REF ) level in the offset capture section (S1), only the input voltage difference (ΔV) in the signal input section (S2) is When additionally applied to (IN), a detection amplification operation is easily performed by the latch. In particular, it can be seen that the input voltage difference (ΔV) is actually applied to the input transistor (MN4), so even if the input voltage (V _BL ) is applied with a high voltage level, the input transistor (MN4) is in the saturated region rather than the linear region. It operates in . Therefore, unlike in FIG. 2, even at a high input voltage (V _BL ) level, the influence of the threshold voltage difference between the first and second NMOS transistors (MN1, MN2) of the latch on the offset voltage (V _OS ) does not increase, OC-CLSA can operate stably over a wide range of input voltage (V _BL ).

Figure 6 shows a schematic structure of a semiconductor memory device including the OC-CLSA of the present disclosure.

The OC-CLSA of the present disclosure shown in FIG. 3 can be used in various electronic devices, but FIG. 6 shows a case where OC-CLSA is applied to the semiconductor memory device 100 as an example.

Here, the semiconductor memory device 100 includes DRAM, SDRAM (Synchronous DRAM), DDR SDRAM (Double Data Rate SDRAM), LPDDR SDRAM (Low Power Double Data Rate SDRAM), GDDR SDRAM (Graphics Double Data Rate SDRAM), DDR2 SDRAM, and DDR3. It may be volatile memory such as SDRAM, DDR4 SDRAM, Thyristor RAM (TRAM), etc., and in some cases, PRAM (Phase change Random Access Memory), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), etc. It may be a non-volatile memory.

Referring to FIG. 6, the semiconductor memory device 100 includes a memory cell array 110, a row decoder 130, a column decoder 140, an SA module 150, a voltage generation module 160, and a controller 180. It can be included.

The memory cell array 110 may include a plurality of memory cells (MC) provided in a matrix form. The memory cell array 110 may include a plurality of word lines (WL) and a plurality of bit lines (BL) each connected to a plurality of memory cells (MC). A plurality of word lines (WL) may be connected to a plurality of memory cells (MC) arranged in a row direction, and a plurality of bit lines (BL) may be connected to a plurality of memory cells (MC) arranged in a column direction.

The row decoder 130 selects at least one word line (WL) among the plurality of word lines of the memory cell array 110 according to the row address (RA) among the externally applied addresses (ADDR), and selects the selected word line (WL) WL) can be activated. The column decoder 140 selects a predetermined bit line (BL) among the plurality of bit lines of the memory cell array 110 according to the row address (CA) among the addresses (ADDR), and connects the selected bit line (BL) to the SA module. By electrically connecting at least one OC-CLSA provided at 150, the voltage of the bit line (BL) can be applied to the OC-CLSA as the input voltage (V _BL ). Therefore, the sensing circuit 30 of FIG. 3 can be viewed as being implemented with the memory cell array 110 and column decoder 140 of FIG. 6.

The SA module 150 includes at least one OC-CLSA, and the at least one OC-CLSA is a bit line (BL) selected by the column decoder 140 among a plurality of bit lines (BL) of the memory cell array 110. ) is electrically connected to. Each of at least one OC-CLSA detects the voltage of the connected bit line (BL) as the input voltage (V _BL ), amplifies it, and outputs it. At this time, each OC-CLSA may compare the applied input voltage (V _BL ) with the reference voltage (V _REF ) applied from the power supply module 160, detect and amplify the input voltage (V _BL ), and output it. In particular, the OC-CLSA according to the present disclosure can not only remove offset as described above, but also stably detect and amplify a wide range of input voltages (V _BL ) by performing reference voltage (V _REF ) biasing. The action can be performed.

The voltage generation module 160 generates various voltages for the semiconductor memory device 100 to operate. The voltage generation module 160 can not only generate a power voltage (V _DD ) and a ground voltage (V _SS ), but also generate a reference voltage (V _REF ) and apply it to the SA module 150 . The voltage generation module 160 can be viewed as a configuration corresponding to the voltage generator 20 of FIG. 3.

The controller 180 not only generates various control signals for driving the row decoder 130 and column decoder 140, but also generates a precharge signal as a control signal to control the operation of the OC-CLSA of the SA module 150. (PRE), first to third control signals (P1, P2, P3), and a sense amplifier enable signal (SAE) can be generated.

In the semiconductor memory device shown in FIG. 6, during a read operation, an input voltage (V _BL ) according to data stored in the selected memory cell (MC) is applied to the OC-CLSA of the present disclosure through the bit line (BL), The OC-CLSA of the present disclosure operates according to the control signals (PRE, P1, P2, P3, SAE) applied from the controller 180 to remove offset and biases the reference voltage (V _REF ) to provide a wide range of input voltages. A detection operation can be performed accurately for (V _BL ).

In the illustrated embodiment, each component may have different functions and capabilities in addition to those described below, and may include additional components other than those described below. Additionally, in one embodiment, each component may be implemented using one or more physically separate devices, one or more processors, or a combination of one or more processors and software, and, unlike the example shown, may be implemented in specific operations. It may not be clearly distinguished.

And the OC-CLSA shown in Figure 3 can be implemented in a logic circuit based on hardware, firmware, software, or a combination thereof, and can be implemented in a hardwired device, field programmable gate array (FPGA) ), it can be implemented using an application specific integrated circuit (ASIC), etc. Additionally, the device may be implemented as a System on Chip (SoC) including one or more processors and a controller.

In addition, the OC-CLSA and memory device may be installed in a computing device or server equipped with hardware elements in the form of software, hardware, or a combination thereof. A computing device or server includes all or part of a communication device such as a communication modem for communicating with various devices or a wired or wireless communication network, a memory for storing data to execute a program, and a microprocessor for executing a program to perform calculations and commands. It can refer to a variety of devices, including:

Claims (20)

In the current latch sense amplifier that detects and amplifies the voltage difference between the reference voltage and the input voltage and outputs,
A sense amplifier circuit that detects and amplifies the differential input voltage applied to the input node pair and outputs a differential output voltage to the output node pair; and
When the reference voltage is applied, it is supplied to the reference voltage node and the sensing node for biasing, and then the applied input voltage is transmitted to the sensing node to generate an input voltage difference representing the voltage difference between the reference voltage and the input voltage. Includes an offset removal circuit applied to one of the input node pairs through coupling,
The offset removal circuit is
Among the operation sections of the current latch sense amplifier, which are divided into a precharge section, an offset capture section, a signal input section, and a sensing section, the input node pair in the offset capture section is operated according to the threshold value of the transistor that causes the offset of the sense amplifier circuit. Remove offset by having a voltage level,
The offset removal circuit is
A current latch sense amplifier that applies a voltage according to the sum of the input voltage difference and a voltage according to the threshold to one of the input node pairs having a voltage level according to the threshold in the signal input section. delete delete The method of claim 1, wherein the current latch sense amplifier
Among the operation sections of the current latch sense amplifier, which are divided into a precharge section, an offset capture section, a signal input section, and a sensing section, a precharge signal activated in the precharge section, a first control signal activated in the offset capture section, and a signal input section. A current latch sense amplifier that operates according to a second control signal activated in the signal input section and the third control signal activated in the sensing section, and a sense amplifier enable signal activated in the sensing section. The method of claim 1, wherein the offset removal circuit is
a precharge circuit connected between the power supply voltage and each precharge node pair to precharge the precharge node pair to the power supply voltage level during a precharge period;
first and second switches that are turned on in the precharge period and the offset capture period to electrically connect each of the precharge node pair and the input node pair;
First and second capacitors respectively connected between the input node pair, the reference voltage node, and the sensing node;
a third switch that is turned on during the precharge period and the offset capture period to connect the reference voltage node and the sensing node; and
A current latch sense amplifier including a fourth switch that is turned on in a signal input section and transmits the applied input voltage to the sensing node. The method of claim 1, wherein the sense amplifier circuit is
A head transistor connected between a power supply voltage and a head node, and pulling up the head node to the power supply voltage level during a sensing period;
a pull-up circuit that precharges the output node pair by pulling them up to the power supply voltage level during a signal input section;
a latch circuit connected between the head node and the precharge node pair, and detecting and inverting and amplifying the voltage level of the output node pair in a sensing period;
an input circuit electrically connecting the precharge node pair and the common node according to the voltage level of the input node pair;
an isolation circuit that deactivates the input circuit by pulling down the output node pair to a ground voltage level during a precharge period and an offset capture period; and
A current latch sense amplifier that is connected between the common node and the ground voltage and includes a foot switch transistor that pulls down the common node to the ground voltage level during the offset capture period and the sensing period. The method of claim 6, wherein the latch circuit
a first PMOS transistor and a first NMOS transistor connected in series between the head node and a first precharge node of the precharge node pair, and having a common gate connected to an inverting output node of the output node pair. 1 inverter; and
a second PMOS transistor and a second NMOS transistor connected in series between the head node and a second precharge node of the precharge node pair, and having a common gate connected to an output node of the output node pair; Current latch sense amplifier with inverter. The method of claim 6, wherein the input circuit is
a first input transistor connected between a first precharge node of the precharge node pair and the common node, and having a gate of an NMOS transistor connected to an inverting input node of the input node pair; and
A current latch sense amplifier comprising a second input transistor connected between a second precharge node of the precharge node pair and the common node, and a gate of which is an NMOS transistor connected to an input node of the input node pair. The method of claim 6, wherein the pull-up circuit
It is connected between the power supply voltage and each of the output node and the inverting output node of the output node pair, and includes first and second pull-up transistors that pull up the output node pair to the power supply voltage level in response to a second inverting control signal. Current latch sense amplifier. The method of claim 6, wherein the isolation circuit is
First and second isolation units connected between each of the output node and the inverting output node of the output node pair and the ground voltage, and pulling down the output node pair to the ground voltage level in response to a precharge signal and a first control signal. Current latch sense amplifier with transistor. A memory cell array including a plurality of memory cells defined by a plurality of word lines and a plurality of bit lines; and
At least one current that receives an input voltage having a voltage level according to the data stored in a memory cell connected to a word line selected from among the plurality of word lines and a bit line selected from the plurality of bit lines, and detects and amplifies the voltage difference from the reference voltage Contains an SA module containing a latch sense amplifier,
The current latch sense amplifier is
A sense amplifier circuit that detects and amplifies the differential input voltage applied to the input node pair and outputs a differential output voltage to the output node pair.
When the reference voltage is applied, it is supplied to the reference voltage node and the sensing node for biasing, and then the applied input voltage is transmitted to the sensing node to generate an input voltage difference representing the voltage difference between the reference voltage and the input voltage. Includes an offset removal circuit applied to one of the input node pairs through coupling,
The offset removal circuit is
In the offset capture section of the operation section of the current latch sense amplifier, which is divided into a precharge section, an offset capture section, a signal input section, and a sensing section, the input node pair operates according to the threshold value of the transistor that causes the offset of the sense amplifier circuit. Remove offset by having a voltage level,
The offset removal circuit is
A memory device that applies a voltage according to the sum of the input voltage difference and the voltage according to the threshold to one of the input node pairs having a voltage level according to the threshold in the signal input section. delete delete 12. The method of claim 11, wherein the current latch sense amplifier
Among the operation sections of the current latch sense amplifier, which are divided into a precharge section, an offset capture section, a signal input section, and a sensing section, a precharge signal activated in the precharge section, a first control signal activated in the offset capture section, and a signal input section. A memory device that operates according to a second control signal activated in the signal input section and the sensing section, a third control signal activated in the signal input section and the sensing section, and a sense amplifier enable signal activated in the sensing section. The method of claim 11, wherein the offset removal circuit is
a precharge circuit connected between the power supply voltage and each precharge node pair to precharge the precharge node pair to the power supply voltage level during a precharge period;
first and second switches that are turned on in the precharge period and the offset capture period to electrically connect each of the precharge node pair and the input node pair;
First and second capacitors respectively connected between the input node pair, the reference voltage node, and the sensing node;
a third switch that is turned on during the precharge period and the offset capture period to connect the reference voltage node and the sensing node; and
A memory device including a fourth switch that is turned on in a signal input section and transmits the applied input voltage to the sensing node. The method of claim 11, wherein the sense amplifier circuit
A head transistor connected between a power supply voltage and a head node, and pulling up the head node to the power supply voltage level during a sensing period;
a pull-up circuit that precharges the output node pair by pulling them up to the power supply voltage level during a signal input section;
a latch circuit connected between the head node and the precharge node pair, and detecting and inverting and amplifying the voltage level of the output node pair in a sensing period;
an input circuit electrically connecting the precharge node pair and the common node according to the voltage level of the input node pair;
an isolation circuit that deactivates the input circuit by pulling down the output node pair to a ground voltage level during a precharge period and an offset capture period; and
A memory device including a foot switch transistor connected between the common node and the ground voltage and pulling down the common node to the ground voltage level during the offset capture period and the sensing period. 17. The method of claim 16, wherein the latch circuit
a first PMOS transistor and a first NMOS transistor connected in series between the head node and a first precharge node of the precharge node pair, and having a common gate connected to an inverting output node of the output node pair. 1 inverter; and
a second PMOS transistor and a second NMOS transistor connected in series between the head node and a second precharge node of the precharge node pair, and having a common gate connected to an output node of the output node pair; Memory device containing an inverter. 17. The method of claim 16, wherein the input circuit is
a first input transistor connected between a first precharge node of the precharge node pair and the common node, and having a gate of an NMOS transistor connected to an inverting input node of the input node pair; and
A memory device comprising a second input transistor connected between a second precharge node of the precharge node pair and the common node, and a gate of which is an NMOS transistor connected to an input node of the input node pair. 17. The method of claim 16, wherein the pull-up circuit
It is connected between the power supply voltage and each of the output node and the inverting output node of the output node pair, and includes first and second pull-up transistors that pull up the output node pair to the power supply voltage level in response to a second inverting control signal. memory device. 17. The method of claim 16, wherein the isolation circuit
First and second isolation units connected between each of the output node and the inverting output node of the output node pair and the ground voltage, and pulling down the output node pair to the ground voltage level in response to a precharge signal and a first control signal. A memory device containing transistors.