JP2010146689A - Semiconductor device and offset voltage cancellation method for sense amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an offset voltage cancellation method for a sense amplifier. <P>SOLUTION: The semiconductor device includes: a sense amplifier 20 for amplifying a potential difference between a signal line pair INBL and INRBL and a signal line pair INBL and INRBL; a cancel charge generation circuit 30 for generating cancel charges according to the offset voltage of the sense amplifier 20; a cancel charge storage circuit 40 for storing cancel charges; and a cancel charge supply circuit 50 for canceling the offset voltage by supplying the cancel charges stored in the cancel charge storage circuit 40 to the signal line pair INBL and INRBL. The cancel charges based on the offset voltage are temporarily stored, and supplied to the signal line pair INBL and INRBL to cancel the offset voltage. Thus, the offset voltage is canceled by a simple circuit configuration. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a sense amplifier. The present invention also relates to a method for canceling an offset voltage of a sense amplifier.

  A DRAM (Dynamic Random Access Memory), which is a typical semiconductor memory device, generates a weak potential difference between a pair of bit lines based on data held in a memory cell, and amplifies the potential difference by a sense amplifier to generate data. Is read out. Since the potential difference appearing in the bit line pair when reading data is extremely weak, the sense amplifier is designed with high sensitivity so that the weak potential difference can be amplified correctly.

  However, since the offset voltage inevitably exists in the sense amplifier due to manufacturing variations and the like, this causes a decrease in the sense margin. When the offset voltage is generated in the sense amplifier, the same state as when a predetermined potential difference is generated due to the difference in the capability of the transistors constituting the sense amplifier even though the bit line pair is actually at the same potential. Become. This “predetermined potential difference” is an offset voltage.

  As methods for canceling the offset voltage of the sense amplifier, methods described in Non-Patent Documents 1 to 3 are known.

Takayuki Kawahara, Takeshi Sakata, Kiyoo ltoh, Yoshiki Kawajiri, Takesada Akiba, Goro Kitsukawa, and Masakazu Aoki, A High-speed, Small-Area, Threshold- Voltage-Mismatch Compensation Sense Amplifier for Gigabit-Scale DRAM Arrays, lEEE JOURNAL OF SOLID -STATE CIRCUITS, VOL. 28, NO. 7, JULY 1993 Yohji Watanabe, Nobuo Nakamura, and Shigeyoshi Watanabe, Offset Compensating Bit-Line sensing Scheme for High Density DRAM's SHUNICHI SUZUKI AND MASAKI HIRATA, Threshold Difference Compensated Sense Amplifier, IEEE JSSC, 1979

  However, the methods described in Non-Patent Documents 1 to 3 have a problem that the chip area is greatly increased because the circuit configuration for canceling the offset voltage is complicated. The problem related to the offset voltage of the sense amplifier is not limited to the DRAM, but is a problem common to all semiconductor memories having the sense amplifier.

  A semiconductor device according to the present invention generates first and second signal lines, a sense amplifier that amplifies a potential difference generated in the first and second signal lines, and a cancel charge corresponding to the offset voltage of the sense amplifier. A cancel charge generation circuit, a cancel charge storage circuit for storing the cancel charge, and a cancel charge supply for canceling the offset voltage by supplying the cancel charge stored in the cancel charge storage circuit to the first and second signal lines And a circuit.

  The sense amplifier offset voltage canceling method according to the present invention is a sense amplifier offset voltage canceling method for amplifying a potential difference generated in the first and second signal lines, and cancels according to the offset voltage of the sense amplifier. A first step of generating and storing the charge, and a second step of canceling the offset voltage by supplying the stored cancel charge to the first and second signal lines. To do.

  According to the present invention, since the cancel charge corresponding to the offset voltage is temporarily accumulated and supplied to the first and second signal lines, the offset voltage is canceled. Can be canceled.

1 is a block diagram showing an outline of a semiconductor device according to a preferred first embodiment of the present invention. 1 is a circuit diagram showing in detail a main part of a semiconductor device according to a first embodiment of the present invention; It is a figure which shows the variation of capacitive element C1. FIG. 6 is a timing chart for explaining the operation of the semiconductor device according to the first embodiment of the present invention. It is a simulation result which shows the effect of the 1st Embodiment of this invention. It is another simulation result which shows the effect of the 1st Embodiment of this invention. FIG. 6 is a circuit diagram according to a modified example in which the timing signal φ2 is omitted by sharing the timing signals φ1 and φ2. FIG. 8 is a timing chart showing an operation of the circuit shown in FIG. 7. It is a circuit diagram which shows the principal part of the semiconductor device by preferable 2nd Embodiment of this invention. FIG. 10 is a timing diagram for explaining an operation of the semiconductor device according to the second embodiment of the present invention. It is a circuit diagram which shows the principal part of the semiconductor device by preferable 3rd Embodiment of this invention. FIG. 10 is a timing diagram for explaining an operation of the semiconductor device according to the third embodiment of the present invention. It is a simulation result which shows the effect of the 3rd Embodiment of this invention. It is another simulation result which shows the effect of the 3rd Embodiment of this invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing an outline of a semiconductor device according to a preferred first embodiment of the present invention. The present embodiment shows a preferable example when the present invention is applied to a DRAM.

  As shown in FIG. 1, the semiconductor memory 10 according to the present embodiment includes a memory cell array 11 composed of a plurality of memory cells MC, a word driver 12 that activates one of the plurality of word lines WL, and a plurality of bit line pairs. And a column switch 13 for selecting either BL or RBL. The plurality of word lines WL and the plurality of bit line pairs BL and RBL intersect at the memory cell array 11, and memory cells MC are arranged at the intersections. Selection of the word line WL by the word driver 12 is performed based on the row address RA, and selection of the bit line pair BL, RBL by the column switch 13 is performed based on the column address CA. Data DQ is input / output to / from the bit line pair BL, RBL selected by the column switch 13.

  The bit line pair BL, RBL is a complementary signal line pair, and is connected to the sense circuit 15 via the switch circuit 14. In the present specification, the bit line pair BL, RBL on the sense circuit 15 side when viewed from the switch circuit 14 may be referred to as “signal lines INBL, INRBL”. A bit line precharge circuit 16 is also connected to the bit line pair BL, RBL. Various control signals generated by the control circuit 17 are supplied to the switch circuit 14, the sense circuit 15, and the bit line precharge circuit 16.

  The switch circuit 14, the sense circuit 15, and the bit line precharge circuit 16 are respectively configured by unit circuits 14a, 15a, and 16a provided for the bit line pairs BL and RBL. Hereinafter, focusing on the unit circuits 14a, 15a, and 16a corresponding to the predetermined bit line pair BL and RBL, the circuit configuration and operation will be described in detail.

  FIG. 2 is a circuit diagram showing in more detail the main part of the semiconductor device according to the present embodiment.

  As shown in FIG. 2, the memory cell MC constituting the memory cell array 11 has a configuration in which a cell transistor CT and a cell capacitor CC are connected in series between a bit line BL or RBL and a plate electrode VPLT. The cell transistor CT is composed of an N-channel MOS transistor, and its gate electrode is connected to the corresponding word line WL. With this configuration, when any word line WL is activated to a high level, the corresponding cell transistor CT is turned on, and the cell capacitor CC and the bit line BL or RBL are connected. For this reason, the potential of the bit line BL or RBL changes according to the contents held in the cell capacitor CC.

  One end of the bit lines BL and RBL is connected to a pair of signal lines INBL and INRBL via a unit circuit 14 a included in the switch circuit 14, and the other end is connected to the unit circuit 16 a included in the bit line precharge circuit 16. It is connected.

  The unit circuit 14a of the switch circuit 14 includes N-channel MOS transistors N3 and N4 connected between a pair of bit lines BL and RBL and a pair of signal lines INBL and INRBL, respectively. A pass signal PASSEN is commonly supplied from the control circuit 17 to the gate electrodes. Thus, when the pass signal PASSEN is activated to a high level, the pair of bit lines BL and RBL and the pair of signal lines INBL and INRBL are short-circuited. On the other hand, when the pass signal PASSEN is at a low level, the pair of bit lines BL and RBL and the pair of signal lines INBL and INRBL are disconnected, so that the sense amplifier 20 has a parasitic capacitance of the bit lines BL and RBL. Disappears.

  The bit line precharge circuit 16 is a circuit for precharging the bit lines BL and RBL to an intermediate potential, and the unit circuit 16a is composed of N channel type MOS transistors N5 to N7. As shown in FIG. 2, the transistor N5 is connected between the intermediate potential VHF and the bit line BL, the transistor N6 is connected between the intermediate potential VHF and the bit line RBL, and the transistor N7 is connected to the bit line BL and the bit line BL. Connected to RBL. A precharge signal PREBL is commonly supplied to the gate electrodes of the transistors N5 to N7. Accordingly, when the precharge signal PREBL is activated to a high level, the bit lines BL and RBL are precharged to the intermediate potential VHF. The intermediate potential VHF is set to an intermediate value between the activation level (VDA) of the sense amplifier activation signal SAP and the activation level (VSS) of the sense amplifier activation signal SAN.

  As shown in FIG. 2, the unit circuit 15 a of the sense circuit 15 includes a sense amplifier 20, a cancel charge generation circuit 30, a cancel charge storage circuit 40, and a cancel charge supply circuit 50.

  The sense amplifier 20 is a circuit that amplifies a potential difference generated in the signal lines INBL and INRBL, and has a so-called flip-flop configuration. Specifically, it is constituted by pull-up transistors P1 and P2 that pull up the signal lines INBL and INRBL, respectively, and pull-down transistors N1 and N2 that pull down the signal lines INBL and INRBL, respectively, and these are cross-coupled. The pull-up transistors P1 and P2 are configured by P-channel MOS transistors, and the pull-down transistors N1 and N2 are configured by N-channel MOS transistors. The pull-up transistor P1 and the pull-down transistor N1 that drive the signal line INBL constitute a first drive circuit unit, and the gate electrodes thereof are commonly connected to the signal line INRBL. Similarly, the pull-up transistor P2 and the pull-down transistor N2 that drive the signal line INRBL constitute a second drive circuit unit, and the gate electrodes thereof are commonly connected to the signal line INBL.

  A sense amplifier activation signal SAP is supplied to the sources of the pull-up transistors P1 and P2. Therefore, when the sense amplifier activation signal SAP is activated to a high level, an operating voltage is supplied to the pull-up transistors P1 and P2, and a pull-up operation is possible. On the other hand, the sense amplifier activation signal SAN is supplied to the sources of the pull-down transistors N1 and N2. Therefore, when the sense amplifier activation signal SAN is activated to a low level, an operating voltage is supplied to the pull-down transistors N1 and N2, and a pull-down operation is possible.

  The cancel charge generation circuit 30 is a circuit that generates a cancel charge corresponding to the offset voltage of the sense amplifier 20. The offset of the sense amplifier 20 is an imbalance caused by manufacturing variations. When an offset occurs in the sense amplifier 20, a predetermined potential difference is generated due to the difference in the capabilities of the transistors constituting the sense amplifier 20 even though the pair of signal lines INBL and INRBL are actually at the same potential. It becomes the same state as the case. As already described, this predetermined potential difference is the offset voltage.

  The cancel charge generation circuit 30 of the present embodiment detects an offset voltage based on the difference in capability between the pull-up transistor P1 included in the first drive circuit unit and the pull-up transistor P2 included in the second drive circuit unit, Based on this, a cancel charge is generated. The reason why the capability difference of the pull-up transistor is a problem in the present embodiment is because a case is assumed in which the capability difference of the pull-up transistor is more likely to vary than the capability difference of the pull-down transistor. A case where the capability difference of the pull-down transistor is more likely to vary than the capability difference of the pull-up transistor will be described in another embodiment.

  The cancel charge generation circuit 30 includes a cancel charge input transistor P3 that connects the signal line INBL and the node A, a cancel charge input transistor P4 that connects the signal line INRBL and the node B, and the signal line INBL and the signal line INRBL. The short-circuit equalizing transistors P5 and P6 and pre-discharge transistors N8 and N9 for pre-discharging the signal lines INBL and INRBL, respectively. Of these, the transistors P3 to P6 are P-channel MOS transistors, and the transistors N8 and N9 are N-channel MOS transistors.

  A timing signal φ1 is commonly supplied to the gate electrodes of the transistors P3 and P5. Thus, when the timing signal φ1 is activated to a low level, the signal line INBL is connected to the node A, and the signal line INBL and the signal line INRBL are short-circuited. Similarly, a timing signal φ2 is commonly supplied to the gate electrodes of the transistors P4 and P6. Thus, when the timing signal φ2 is activated to a low level, the signal line INRBL is connected to the node B, and the signal line INBL and the signal line INRBL are short-circuited.

  A pre-discharge signal PD is commonly supplied to the gate electrodes of the transistors N8 and N9. As a result, when the pre-discharge signal PD is activated to a high level, the signal lines INBL and INRBL are discharged.

  The cancel charge accumulation circuit 40 is a circuit for accumulating cancel charges, and includes a capacitive element C1 connected between nodes A and B. That is, the capacitive element C1 includes the first electrode CE1 and the second electrode CE2, and the first electrode CE1 is connected to the node A and the second electrode CE2 is connected to the node B. The circuit configuration of the capacitive element C1 may be a normal capacitive element as shown in FIG. 3A, or the gate capacitance of the depletion type MOS transistor M1 as shown in FIG. Alternatively, it may be the source-drain capacitance of the MOS transistor M2 as shown in FIG. In the example shown in FIG. 3C, a P-channel type MOS transistor M2 is used, and its gate electrode is fixed to the power supply potential VDD so that it is always turned off.

  The cancel charge supply circuit 50 is a circuit that supplies a cancel charge to the signal lines INBL and INRBL, and a cancel charge output transistor P7 that connects the signal line INBL and the node B, and a cancel that connects the signal line INRBL and the node A. The charge output transistor P8 is used. These transistors P7 and P8 are P-channel MOS transistors. A timing signal φ3 is commonly supplied to the gate electrodes of the transistors P7 and P8. Thus, when the timing signal φ3 is activated to a low level, the signal line INBL is connected to the node B and the signal line INRBL is connected to the node A.

  The above is the circuit diagram of the main part of the semiconductor device according to the present embodiment. Next, the operation of the semiconductor device according to the present embodiment will be explained.

  FIG. 4 is a timing chart for explaining the operation of the semiconductor device according to the present embodiment. Times t1 to t15 described below are times that pass in this order as shown in FIG.

  First, in a state before time t1, the pass signal PASSEN is at a low level (VSS), and the bit line precharge signal PREBL is at a high level (VDD). Therefore, the bit line pair BL, RBL and the signal line pair INBL, INRBL are disconnected by the switch circuit 14, and the bit line pair BL, RBL is precharged to the intermediate potential VHF by the bit line precharge circuit 16. Further, during this period, the sense amplifier activation signal SAP is activated to a high level (VDA), so that an operating voltage is supplied to the pull-up transistors P1 and P2 included in the sense amplifier 20. As a result, the signal line INBL is lowered by a threshold voltage Vtp1 of the pull-up transistor P1 from the power supply potential VDA, and the signal line INRBL is lowered by a threshold voltage Vtp2 of the pull-up transistor P2 from the power supply potential VDA. Although the threshold voltage Vtp1 and the threshold voltage Vtp2 are designed to be the same level, they are not completely matched due to manufacturing variations, and the difference causes an offset in the sense amplifier 20.

  During this period, the sense amplifier activation signal SAN is inactive, so that the sense amplifier 20 cannot perform a pull-down operation. In other words, the sense amplifier 20 is not activated yet and can perform only a pull-up operation.

  Next, the pre-discharge signal PD is activated during the period from time t1 to t3. As a result, the signal line pair INBL, INRBL is temporarily discharged. The signal line pair INBL and INRBL need not be temporarily lowered to the power supply potential VSS (low power supply) as the discharge level, but at least from the power supply potential VDA (high power supply) to the thresholds of the pull-up transistors P1 and P2. It is sufficient that the voltage is lowered to a level lower than the voltages Vtp1 and Vtp2. As described above, since the pass signal PASSEN is at a low level at this point, the precharge state is maintained for the bit line pair BL and RBL.

  When the signal line pair INBL, INRBL is discharged, the timing signal φ1 is activated during the period from time t2 to t5. When the timing signal φ1 is activated, the transistors P3 and P5 constituting the cancel charge generation circuit 30 are turned on. When the transistor P5 is turned on, the signal line pair INBL, INRBL is short-circuited, so that the gate and drain of the pull-up transistor P1 are short-circuited. That is, the pull-up transistor P1 is diode-connected. For this reason, after the precharge transistor N8 is turned off, the signal line INBL rises from the discharge level to a level (VDA−Vtp1) lower than the power supply potential VDA by the threshold voltage Vtp1 of the pull-up transistor P1. The rising speed depends on the capability of the pull-up transistor P1. For this reason, when the transistor P3 is changed from on to off by deactivating the timing signal φ1 at a time t5 when a predetermined time has elapsed, a predetermined amount of charge is generated in the node A, that is, on the signal line INBL side. Cancellation charge is accumulated.

  The same operation is performed on the signal line INRBL side. That is, the pre-discharge signal PD is activated during the period from time t6 to t8, and the timing signal φ2 is activated during the period from time t7 to t9. When the timing signal φ2 is activated, the transistors P4 and P6 constituting the cancel charge generation circuit 30 are turned on. As a result, the pull-up transistor P2 is diode-connected, so that the signal line INRBL is switched from the power supply potential VDA to the threshold voltage Vtp2 of the pull-up transistor P2 from the discharge level after the precharge transistor N9 is turned off. It rises toward the lower level (VDA-Vtp2). The rising speed depends on the capability of the pull-up transistor P2. For this reason, when the transistor P4 is changed from on to off by deactivating the timing signal φ2 at time t9 when a predetermined time has elapsed, a predetermined amount of charge is generated at the node B, that is, on the signal line INRBL side. Cancellation charge is accumulated.

  In this way, the cancel charge generated on the signal line INBL side is stored in the first electrode CE1 of the capacitive element C1 constituting the cancel charge storage circuit 40, and the second electrode CE2 is stored on the signal line INRBL side. The generated cancel charge is accumulated.

  During the generation of the cancel charge, the bit line precharge signal PREBL is deactivated, and then the predetermined word line WL is changed from the inactive level VKK (<VSS) to the active level VPP (> VDA). To change. As a result, the memory cell MC corresponding to the selected word line WL is connected to the bit line BL or RBL, and its potential changes according to the stored contents. The activation of the word line WL is performed by the control circuit 17 supplying the activation signal ACT1 to the word driver 12. In the example shown in FIG. 4, the bit line precharge signal PREBL is deactivated at time t4 and the word line WL is activated at time t6. However, these timings are not limited to this. Thus, the cancel charge generation operation and the memory cell MC selection operation can be executed in parallel. This is because the switch circuit 14 separates the bit line pair BL, RBL from the signal line pair INBL, INRBL.

  When the generation operation of the cancel charge and the reading from the memory cell MC are completed in this way, the sense amplifier activation signal SAP is temporarily deactivated at time t10, and the pass signal PASSEN is activated during the period from time t11 to t12. Make it. The activation level of the pass signal PASSEN is VPP. As a result, the bit line pair BL, RBL and the signal line pair INBL, INRBL are short-circuited, and the electric charge read from the memory cell MC is supplied to the sense amplifier 20. However, since the sense amplifier activation signals SAP and SAN are both inactive during this period, the sense amplifier 20 does not perform a sensing operation.

  Next, the timing signal φ3 is activated at time t13. Thereby, the transistors P7 and P8 constituting the cancel charge supply circuit 50 are turned on, the node B is connected to the signal line INBL, and the node A is connected to the signal line INRBL. That is, the cancel charge generated on one side of the signal line pair INBL, INRBL is supplied to the other side. As a result, the offset of the sense amplifier 20 due to the difference in capability between the pull-up transistors P1 and P2 is canceled.

  Thereafter, when the sense amplifier activation signals SAP and SAN are activated at time t14, the sense amplifier 20 is activated and an amplification operation is performed according to the potential difference generated in the signal line pair INBL and INRBL. As described above, the activation of the sense amplifier 20 is performed in a state where the offset voltage is canceled in advance, so that the sense margin is greatly expanded. If the pass signal PASSEN is activated again at time t15, the signal amplified by the sense amplifier 20 is restored to the memory cell MC.

  Thereafter, the control circuit 17 supplies the activation signal ACT2 to the column switch 13, and thereby the signal line pair INBL, INRBL is selected based on the column address CA.

  As described above, in this embodiment, the offset caused by the difference in capability between the pull-up transistors P1 and P2 of the sense amplifier 20 is detected to generate a cancel charge, and this is supplied to the opposite signal line to thereby reduce the offset. Canceled. For this reason, it is possible to effectively cancel the offset of the sense amplifier 20 in the case where the capability difference of the pull-up transistor is more likely to vary than the capability difference of the pull-down transistor.

  In addition, since the cancel charge input to the node A and the cancel charge input to the node B are performed separately, the other cancel charge is less likely to be affected when one cancel charge is input. Each cancel charge can be accurately input to the input.

  In the present embodiment, since the transistors N3 and N4 that cut the bit line pair BL and RBL and the signal line pair INBL and INRBL are provided, the bit line precharge operation and the word line activation operation are performed in parallel. Thus, a cancel charge generation operation can be performed. In addition, when the transistors N3 and N4 are off, the parasitic capacitances of the bit lines BL and RBL cannot be seen from the sense amplifier 20, so that the cancel charge generation operation can be performed at high speed.

  Since the cancel charge is generated dynamically in the present embodiment, the charge amount of the cancel charge is not only the capacitance value of the capacitive element C1, but also the activation time of the pre-discharge signal PD, the pre-charge transistors N8 and N9. And the activation time of the timing signals φ1, φ2 and the like. Therefore, in order to cancel the offset voltage more accurately, it is desirable to set these parameters to optimum values.

  FIG. 5 is a simulation result showing the effect of this embodiment. In FIG. 5, “ΔVt” indicates the offset voltage of the sense amplifier 20, and “Temp.” Indicates the environmental temperature. In addition, the vertical axis in FIG. 5 represents a potential difference (necessary potential difference) necessary for correctly performing the sensing operation. Various parameters such as the capacitance value of the capacitive element C1 are optimum assuming that the threshold voltage difference between the pull-up transistors P1 and P2 is 40 mV and the threshold voltage difference between the pull-down transistors N1 and N2 is 20 mV. Turned into.

  As shown in FIG. 5, it can be seen that in any case, the required potential difference is greatly reduced when the offset voltage canceling operation is performed. Specifically, in case 1 (ΔVt = 47 mV, temperature 25 ° C.), the required potential difference is reduced by 30 mV by performing the offset voltage canceling operation. Cases 2 to 4 are simulation results when ΔVt = 94 mV and the temperatures are −5 ° C., 25 ° C., and 95 ° C., respectively, and the required potential differences are reduced by 35 mV, 40 mV, and 45 mV, respectively. As shown in FIG. 5, when ΔVt is large or the environmental temperature is high, the required potential difference becomes large and the sense margin tends to be reduced. However, if the offset voltage cancel operation is performed as in the present embodiment, the offset voltage cancel amount increases as the sense margin tends to decrease, so that the correct sense operation is ensured. It becomes possible.

  FIG. 6 is another simulation result showing the effect of this embodiment, and shows the relationship between the power supply voltage and the offset voltage. The conditions are set to the same conditions as in the simulation shown in FIG.

  As shown in FIG. 6, when the offset voltage cancel operation is not performed, the offset voltage increases as the power supply voltage decreases. On the other hand, when the offset voltage canceling operation is performed as in the present embodiment, the offset voltage is reduced as a whole and the dependence on the power supply voltage becomes very small. Thereby, even when the power supply voltage is low, it is possible to ensure correct sensing operation.

  In the above-described embodiment, the timing signals φ1 and φ2 are separate signals, but they may be common signals.

  FIG. 7 is a circuit diagram of a modified example in which the timing signal φ2 is omitted by sharing the timing signals φ1 and φ2. FIG. 8 is a timing chart showing the operation of the circuit shown in FIG.

  In the modification shown in FIG. 7, the transistor P6 is omitted, and the timing signal φ1 is supplied to the gate electrode of the transistor P4. Since the other points are the same as those in the above embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted. As shown in FIG. 8, since the timing signal φ2 is omitted in the modification, the pre-discharge signal is activated only once. That is, one activation of the pre-discharge signal and one activation of the timing signal φ1 cause cancellation charges to be simultaneously generated in the signal line INBL and the signal line INRBL, which are simultaneously stored in the capacitor C1.

  As described above, in the modification shown in FIGS. 7 and 8, since the cancel charge is input to the node A and the cancel charge is input to the node B at the same time, the offset voltage cancel operation is performed at high speed. Is possible.

  Next, a second embodiment of the present invention will be described. The second embodiment is an embodiment capable of canceling an offset voltage caused by a difference in capability between pull-down transistors constituting a sense amplifier.

  FIG. 9 is a circuit diagram showing the main part of the semiconductor device according to the preferred second embodiment of the present invention.

  As shown in FIG. 9, in the semiconductor device according to the present embodiment, the P-channel MOS transistors P3 to P8 used in the first embodiment described above are replaced with N-channel MOS transistors N13 to N18. This is different from the first embodiment described above in that the discharge transistors N8 and N9 are replaced by precharge transistors P18 and P19. Along with this, the polarity of the timing signals φ1 to φ3 is opposite to that of the first embodiment, and the precharge signal PC having the opposite polarity is used instead of the predischarge signal PD. Since the other points are the same as those in the first embodiment, the same reference numerals are given to the same elements, and duplicate descriptions are omitted.

  FIG. 10 is a timing chart for explaining the operation of the semiconductor device according to the present embodiment.

  As shown in FIG. 10, the operation of the semiconductor device according to the present embodiment is the same as that of the first embodiment except that the activation of the sense amplifier activation signals SAP and SAN is opposite to the waveform of the timing diagram shown in FIG. It is almost the same as the operation. That is, by activating the precharge signal PC in the period from time t1 to t3 and t6 to t8, the signal line pair INBL and INRBL are temporarily precharged, and then the timing signal φ1 is applied in the period from time t2 to t5. The timing signal φ2 is activated during the period from time t7 to t9. As a result, the signal line INBL decreases from the power supply potential VSS toward a level (VSS + Vtn1) higher by the threshold voltage Vtn1 of the pull-down transistor N1, and the signal line INRBL changes from the power supply potential VSS to the threshold voltage of the pull-down transistor N2. It decreases toward the higher level (VSS + Vtn2) by Vtn2. Since the decrease rate depends on the capabilities of the pull-down transistors N1 and N2, canceling charges are accumulated in the nodes A and B when the timing signals φ1 and φ2 are deactivated at predetermined times t5 and t9.

  The cancel charge accumulated in this way is supplied to the other signal line by activating the timing signal φ3 and turning on the transistors N17 and N18 at time t13, as in the first embodiment. Thereby, the offset of the sense amplifier 20 due to the difference in capability between the pull-down transistors N1 and N2 is canceled.

  As described above, in the present embodiment, the offset caused by the difference in capability between the pull-down transistors N1 and N2 of the sense amplifier 20 is detected to generate a cancel charge, and the offset is canceled by supplying this to the opposite signal line. is doing. For this reason, it is possible to effectively cancel the offset of the sense amplifier 20 in the case where the capability difference of the pull-down transistor is more likely to vary than the capability difference of the pull-up transistor.

  In this embodiment, since the generation of the cancel charge is dynamically performed, the charge amount of the cancel charge is not limited to the capacitance value of the capacitive element C1, but the activation time of the precharge signal PC, the precharge transistors P18, It changes depending on the ability of P19, the activation time of the timing signals φ1, φ2, and the like. Therefore, in order to cancel the offset more accurately, it is desirable to set these parameters to optimum values.

  Further, in the present embodiment, the timing signal φ2 can be omitted by sharing the timing signals φ1 and φ2.

  Next, a third embodiment of the present invention will be described. The third embodiment is an embodiment that can cancel the total offset voltage of the sense amplifier.

  FIG. 11 is a circuit diagram showing the main part of the semiconductor device according to the preferred third embodiment of the present invention.

  As shown in FIG. 11, in the semiconductor device according to the present embodiment, the N-channel MOS transistor N16 used in the second embodiment described above is replaced with a P-channel MOS transistor P6. 60 differs from the second embodiment in that 60 is added and the precharge transistors P18 and P19 are omitted. Since other circuit configurations are the same as those of the second embodiment, the same reference numerals are given to the same elements, and duplicate descriptions are omitted.

  The sense amplifier precharge circuit 60 is a circuit for precharging the signal line pair INBL, INRBL to the intermediate potential VHF, and has a circuit configuration similar to that of the unit circuit 16 a of the bit line precharge circuit 16. Specifically, it is composed of N-channel MOS transistors N21 to N23. The transistor N21 is connected between the intermediate potential VHF and the signal line INBL, and the transistor N22 is connected between the intermediate potential VHF and the signal line INRBL. The transistor N23 is connected between the signal line INBL and the signal line INRBL. A precharge signal PRESA is commonly supplied to the gate electrodes of the transistors N21 to N23. As a result, when the precharge signal PRESA is activated to a high level (VDD), the signal lines INBL and INRBL are precharged to the intermediate potential VHF.

  In the present embodiment, a parallel circuit of a P-channel type MOS transistor P6 and an N-channel type MOS transistor N15 is used as the equalizing transistor constituting the cancel charge generation circuit 30. This is to reduce the difference between the offset voltage and the cancel voltage even when the threshold values of both the P-channel MOS transistor and the N-channel MOS transistor vary. In particular, the transistor P6 is designed to have the same threshold as the pull-up transistors P1 and P2 constituting the sense amplifier 20, and the transistor N15 is designed to have the same threshold as the pull-down transistors N1 and N2 constituting the sense amplifier 20. It is preferable to do. According to this, the difference between the offset voltage and the cancel voltage becomes very small, and extremely accurate offset cancellation can be realized.

  FIG. 12 is a timing chart for explaining the operation of the semiconductor device according to the present embodiment. Times t21 to t35 described below are times that pass in this order as shown in FIG.

  First, in a state before time t21, the pass signal PASSEN is at a low level (VSS), and the bit line precharge signal PREBL and the sense amplifier precharge signal PRESA are at a high level (VDD). Therefore, the bit line pair BL, RBL and the signal line pair INBL, INRBL are disconnected by the switch circuit 14, but the bit line pair BL, RBL and the signal line pair INBL, INRBL are all precharged to the intermediate potential VHF. Is done. During this period, both sense amplifier activation signals SAP and SAN are inactive.

  Next, after deactivating the sense amplifier precharge signal PRESA at time t21, the sense amplifier activation signals SAP and SAN are activated at time t22. At time t22, since the signal line pair INBL, INRBL is precharged to the same potential (intermediate potential VHF) by the sense amplifier precharge circuit 60, it is ideal even if the sense amplifier 20 is activated. The sense amplifier 20 does not perform a sensing operation. However, the sense operation is performed at time t22 by the offset of the sense amplifier 20, and one of the signal line pairs INBL and INRBL is driven to the high level and the other is driven to the low level.

  Next, equalize signals EQ and EQB are activated at time t23. The equalize signal EQ is a signal supplied to the gate electrode of the transistor N15, and the equalize signal EQB is a signal supplied to the gate electrode of the transistor P6. As a result, the signal line pair INBL, INRBL is short-circuited. That is, the signal line pair INBL, INRBL is short-circuited in a state where the sense amplifier 20 is activated. As a result, the amplitude of the sense amplifier 20 is limited, so that a potential difference corresponding to the mismatch of the threshold voltages of the transistors constituting the sense amplifier 20 and the mismatch of the on-current Ion appears on the signal line pair INBL, INRBL. Stable in state. In this way, the potential difference ΔV appearing on the signal line pair INBL, INRBL is proportional to the offset voltage of the sense amplifier 20.

  Next, the timing signal φ1 is activated at time t24 while the potential difference ΔV appears in the signal line pair INBL, INRBL. Thereby, the signal line INBL is connected to the node A via the transistor N13, and the signal line INRBL is connected to the node B via the transistor N14. When the timing signal φ1 is deactivated at time t26, the cancel charges are accumulated in the electrodes CE1 and CE2 of the capacitive element C1, respectively. Thereafter, at time t27, the sense amplifier activation signals SAP and SAN are deactivated, and the equalization signals EQ and EQB are deactivated.

  Next, the sense amplifier precharge signal PRESA is activated again at time t28. As a result, the signal line pair INBL, INRBL is precharged again to the intermediate potential VHF. If the sense amplifier precharge signal PRESA is deactivated at time t30, the cancel charge generation operation is completed. In FIG. 12, the period during which the cancel charge generation operation is performed is indicated as T1.

  While such a cancel charge generation operation is performed, the bit line precharge signal PREBL is deactivated, and then a predetermined word line WL is activated. As a result, the memory cell MC corresponding to the selected word line WL is connected to the bit line BL or RBL, and its potential changes according to the stored contents. In the example shown in FIG. 12, the bit line precharge signal PREBL is deactivated at time t25 and the word line WL is activated at time t29. However, these timings are not limited to this. Thus, also in this embodiment, the cancel charge generation operation and the memory cell MC selection operation can be performed in parallel.

  When the cancel charge generation operation and the reading from the memory cell MC are completed in this way, the pass signal PASSEN is activated in the period from time t31 to t32. As a result, the bit line pair BL, RBL and the signal line pair INBL, INRBL are short-circuited, and the electric charge read from the memory cell MC is supplied to the sense amplifier 20. However, since the sense amplifier activation signals SAP and SAN are both inactive during this period, the sense amplifier 20 does not perform a sensing operation. In FIG. 12, the charge transfer period to the sense amplifier 20 is denoted as T2.

  Next, the timing signal φ3 is activated at time t32. Thereby, the transistors N17 and N18 constituting the cancel charge supply circuit 50 are turned on, the node B is connected to the signal line INBL, and the node A is connected to the signal line INRBL. As a result, the offset of the sense amplifier 20 is canceled. In FIG. 12, the period during which the offset voltage canceling operation is performed is indicated as T3.

  Thereafter, when the sense amplifier activation signals SAP and SAN are activated at time t34, the sense amplifier 20 is activated and an amplification operation is performed according to the potential difference generated in the signal line pair INBL and INRBL. As described above, the activation of the sense amplifier 20 is performed in a state where the offset voltage is canceled in advance, so that the sense margin is greatly expanded. In FIG. 12, the period during which the sensing operation is performed is indicated as T4.

  If the pass signal PASSEN is activated at time t35, the signal amplified by the sense amplifier 20 is restored to the memory cell MC. In FIG. 12, the period during which the restore operation is performed is indicated as T5.

  Thus, in the present embodiment, by turning on the equalizing transistors P6 and N15 while the sense amplifier 20 is activated, an offset voltage is generated between the signal line pair INBL and INRBL, and this is generated in the capacitive element C1. Accumulated. Therefore, the offset voltage of the sense amplifier 20 can be canceled almost completely by appropriately selecting the sizes of the equalizing transistors P6 and N15 and the capacitance value of the capacitive element C1.

  In addition, since the cancel charge is generated statically in this embodiment, it is not necessary to provide the pre-discharge transistor in the first example or the pre-charge transistor in the second example. Furthermore, since the cancellation charge is generated statically, it is not necessary to strictly control the timing at which the timing signal φ1 is activated or deactivated, and the design is facilitated.

  FIG. 13 is a simulation result showing the effect of this embodiment. The simulation shown in FIG. 13 is based on the offset voltage before canceling and the canceling operation according to the threshold voltage difference between the pull-up transistors P1 and P2 constituting the sense amplifier 20 and the threshold voltage difference between the pull-down transistors N1 and N2. The applied voltage and the offset voltage value after cancellation are shown.

  As shown in FIG. 13, as the threshold voltage difference increases, the offset voltage before cancellation increases in proportion to this. However, as the threshold voltage difference increases, the voltage given by the cancel operation increases in proportion to this, and as a result, the offset voltage after cancellation is almost zero regardless of the threshold voltage difference. Value. Thus, according to this embodiment, it can be seen that the offset voltage can be canceled almost completely regardless of the threshold voltage difference.

  FIG. 14 shows another simulation result showing the effect of the present embodiment. The simulation shown in FIG. 13 is canceled when both the threshold voltage difference between the pull-up transistors P1 and P2 constituting the sense amplifier 20 and the threshold voltage difference between the pull-down transistors N1 and N2 and the ambient temperature are changed. The voltage given by the operation and the value of the offset voltage after cancellation are shown.

  As shown in FIG. 14, when the threshold voltage difference is the same, the voltage given by the cancel operation increases as the environmental temperature increases, and as a result, the offset voltage after cancellation is equal to the threshold voltage difference and the environment. The value is almost zero regardless of the temperature. Thus, according to the present embodiment, it can be seen that the offset voltage can be almost completely canceled even when the environmental temperature changes.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in each of the above embodiments, the case where the present invention is applied to a DRAM has been described as an example. However, the application target of the present invention is not limited to this, and other semiconductor memories (SRAM, PRAM, flash memory) Etc.). Furthermore, the application target of the present invention is not limited to a semiconductor memory, and can be applied to all semiconductor devices including a sense amplifier.

DESCRIPTION OF SYMBOLS 10 Semiconductor memory 11 Memory cell array 12 Word driver 13 Column switch 14 Switch circuit 15 Sense circuit 16 Bit line precharge circuit 17 Control circuit 14a, 15a, 16a Unit circuit 20 Sense amplifier 30 Cancel charge generation circuit 40 Cancel charge storage circuit 50 Cancel charge Supply circuit 60 Sense amplifier precharge circuit A, B Node BL, RBL Bit line pair C1 Capacitance element CE1 Capacitance element first electrode CE2 Capacitance element second electrode INBL, INRBL Signal line pair WL Word line

Claims (19)

First and second signal lines;
A sense amplifier that amplifies a potential difference generated in the first and second signal lines;
A cancel charge generation circuit for generating a cancel charge according to the offset voltage of the sense amplifier;
A cancel charge storage circuit for storing the cancel charge;
A semiconductor device comprising: a cancel charge supply circuit that cancels the offset voltage by supplying the cancel charge stored in the cancel charge storage circuit to the first and second signal lines. The sense amplifier includes a first drive circuit unit that drives the first signal line, and a second drive circuit unit that drives the second signal line,
The cancel charge generation circuit detects an offset voltage based on a difference in capability between the first drive circuit unit and the second drive circuit unit, and generates the cancel charge based on the detected offset voltage. Item 14. The semiconductor device according to Item 1. The cancel charge includes at least a first cancel charge based on the capability of the first drive circuit unit and a second cancel charge based on at least the capability of the second drive circuit unit,
3. The semiconductor according to claim 2, wherein the cancel charge storage circuit includes a first electrode for storing the first cancel charge and a second electrode for storing the second cancel charge. apparatus.   The cancel charge supply circuit supplies the first cancel charge stored in the first electrode to the second signal line, and the second cancel charge stored in the second electrode is The semiconductor device according to claim 3, wherein the semiconductor device is supplied to the first signal line. The first drive circuit unit of the sense amplifier includes a first pull-up transistor that pulls up the first signal line, and a first pull-down transistor that pulls down the first signal line,
The second drive circuit unit of the sense amplifier includes a second pull-up transistor that pulls up the second signal line, and a second pull-down transistor that pulls down the second signal line.
5. The semiconductor according to claim 4, wherein the first pull-up transistor and the first pull-down transistor, and the second pull-up transistor and the second pull-down transistor are cross-coupled. apparatus. The cancel charge generation circuit connects an equalize transistor that short-circuits the first signal line and the second signal line, and a first cancel charge input that connects the first signal line and the first electrode. A transistor, and a second cancel charge input transistor connecting the second signal line and the second electrode,
The cancel charge supply circuit includes a first cancel charge output transistor that connects the first signal line and the second electrode, and a second signal that connects the second signal line and the first electrode. 6. The semiconductor device according to claim 5, further comprising a cancel charge output transistor. A control circuit for controlling operations of at least the sense amplifier, the cancel charge generation circuit, and the cancel charge supply circuit;
The control circuit generates the first and second cancel charges on the first and second signal lines by turning on the equalizing transistor, and turns on the first and second cancel charge input transistors. The first and second cancel charges are accumulated in the first and second electrodes, respectively, and the first and second cancel charge output transistors are turned on to turn on the first and second cancel charges. 7. The semiconductor device according to claim 6, wherein cancel charges are supplied to the second and first signal lines, respectively. The cancel charge generation circuit further includes a first pre-discharge transistor that pre-discharges the first signal line, and a second pre-discharge transistor that pre-discharges the second signal line,
The control circuit supplies the operating voltage to the first and second pull-up transistors without supplying the operating voltage to the first and second pull-down transistors included in the sense amplifier. The first and second signal lines are temporarily discharged by the second pre-discharge transistor and then the equalizing transistor is turned on to turn the first and second signal lines on the first and second signal lines, respectively. The pull-up transistor is pulled up at a speed according to the capability of the pull-up transistor, and the first and second cancel charge input transistors are changed from on to off while a potential difference is generated between the first and second signal lines. Thus, the first and second cancel charges are accumulated in the first and second electrodes, respectively. The semiconductor device according to claim 7,. The cancel charge generation circuit further includes a first precharge transistor that precharges the first signal line, and a second precharge transistor that precharges the second signal line,
The control circuit supplies the operating voltage to the first and second pull-down transistors without supplying the operating voltage to the first and second pull-up transistors included in the sense amplifier. The first and second signal lines are temporarily precharged by the first and second precharge transistors, and then the equalizing transistor is turned on to turn the first and second signal lines on the first and second signal lines, respectively. And pulling down the first and second cancel charge input transistors from on to off while a potential difference is generated between the first and second signal lines. To store the first and second cancel charges in the first and second electrodes, respectively. The semiconductor device according to Motomeko 7 or 8.   The semiconductor device according to claim 7, wherein the control circuit turns on the equalizing transistor in a state where the sense amplifier is activated. First and second bit lines connected to the first and second signal lines via a switch circuit, a plurality of word lines intersecting the first and second bit lines, and the first And a plurality of memory cells arranged at intersections of the second bit line and the plurality of word lines,
The control circuit activates one of the plurality of word lines and turns on the equalizing transistor and the first and second cancel charge input transistors before turning on the switch circuit. The semiconductor device according to any one of claims 7 to 10.   12. The semiconductor device according to claim 11, wherein the control circuit turns on the first and second cancel charge output transistors after making the switch circuit conductive. An offset voltage canceling method for a sense amplifier that amplifies a potential difference generated in first and second signal lines,
A first step of generating and storing a cancel charge according to the offset voltage of the sense amplifier; and
A second step of canceling the offset voltage by supplying the accumulated cancel charge to the first and second signal lines, and a method for canceling the offset voltage of the sense amplifier. In the first step, first and second cancel charges generated in the first and second signal lines, respectively, are generated,
14. The sense amplifier offset voltage canceling method according to claim 13, wherein in the second step, the first and second cancel charges are supplied to the second and first signal lines, respectively.   15. The sense amplifier offset voltage canceling method according to claim 14, wherein, in the first step, the first signal line and the second signal line are short-circuited.   16. The sense according to claim 15, wherein the first signal line and the second signal line are temporarily discharged or precharged before the first signal line and the second signal line are short-circuited. How to cancel the offset voltage of the amplifier.   16. The offset of the sense amplifier according to claim 15, wherein in the first step, the first signal line and the second signal line are short-circuited in a state where the sense amplifier is activated. Voltage cancellation method. The first and second signal lines are connected to the first and second bit lines through a switch circuit, respectively.
18. The sense amplifier offset voltage canceling method according to claim 13, wherein the first step is performed in a state in which the switch circuit is turned off.   19. The sense amplifier offset voltage canceling method according to claim 18, wherein the second step is performed in a state in which the switch circuit is turned on.

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