JP2007184016A - Ferroelectric memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric memory free from read errors even if there are variations in ferroelectric capacitance or in reversed electric charges in the ferroelectric capacitor. <P>SOLUTION: A reference voltage generator circuit 25 having resistors R1, R2 and R3 is formed at the post stage of pre-sense amplifiers 2, 3. Resistance values of those resistors R1, R2 and R3 are decided so that reference voltages REF, REFX outputted from the reference voltage generator circuit 25 reach values between the variation range of the potential of output terminals OUT0, OUT0X, OUT1 and OUT2 of the pre-sense amplifiers 2, 3, 12 and 13 when they have expected logical values "1", and the variation range when they have expected logical values "0". <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a ferroelectric memory (FeRAM) using a ferroelectric capacitor as a storage medium. More specifically, the present invention relates to a data read technique for a ferroelectric memory.

  FIG. 5 is a circuit diagram of a part of an example of a conventional ferroelectric memory. The conventional ferroelectric memory shown in FIG. 5 includes a read circuit called a bit line GND sense system. In FIG. 5, 1 is a 2-transistor / 2-capacitor type memory cell, and WL is a word line. PL is a plate line, BL and BLX are bit lines, 2 and 3 are pre-sense amplifiers, 4 is a threshold value generating circuit, 5 is a negative voltage generating circuit, 6 is a sense amplifier, and IB1 is an inverter.

  Although many memory cells are arranged vertically and horizontally, the memory cells other than the memory cell 1 are not shown. The pre-sense amplifiers 2 and 3 and the sense amplifier 6 constitute a read circuit. Although there are a plurality of such read circuits, illustration is omitted except for the read circuit shown in FIG.

  In addition, although a plurality of bit line pairs are connected to the read circuit shown in FIG. 5 via column switches, the bit lines other than the column switches and the bit lines BL and BLX are not shown. The threshold value generation circuit 4 and the negative voltage generation circuit 5 are shared by a plurality of readout circuits.

  In this example, the memory cell 1 includes ferroelectric capacitors F1 and F2 that form a storage medium, and access transistors N1 and N2 including N-channel MOS transistors (hereinafter referred to as NMOS transistors).

  The access transistor N1 has a gate connected to the word line WL, a source connected to the bit line BL, a drain connected to one end of the ferroelectric capacitor F1, and the ferroelectric capacitor F1 connected to the plate line PL. Connected. The access transistor N2 has a gate connected to the word line WL, a source connected to the bit line BLX, a drain connected to one end of the ferroelectric capacitor F2, and the other end of the ferroelectric capacitor F2 connected to the plate line PL. Connected.

  Although not shown in the drawing circuit, complementary data is written in the ferroelectric capacitors F1 and F2. That is, when data “0” is written to the ferroelectric capacitor F1, data “1” is written to the ferroelectric capacitor F2, and data “1” is written to the ferroelectric capacitor F1. In the ferroelectric capacitor F2, data “0” is written.

  Data “0” is written to the ferroelectric capacitor F1 by setting the potential of the word line WL = VDD potential (for example, 3V), turning on the access transistor N1, the potential of the bit line BL = GND potential (0V), and the plate line. It is performed by setting the potential of PL = VDD potential and applying a positive voltage to the ferroelectric capacitor F1.

  On the other hand, in writing data “1” to the ferroelectric capacitor F2, the potential of the word line WL = VDD potential, the access transistor N2 is turned on, the potential of the bit line BLX = VDD potential, and the potential of the plate line PL. = GND potential, and a negative voltage is applied to the ferroelectric capacitor F2.

  In addition, data “1” is written to the ferroelectric capacitor F1 by setting the potential of the word line WL = VDD potential, turning on the access transistor N1, the potential of the bit line BL = VDD potential, and the potential of the plate line PL = GND potential. And by applying a negative voltage to the ferroelectric capacitor F1.

  On the other hand, when data “0” is written to the ferroelectric capacitor F2, the potential of the word line WL = VDD potential, the access transistor N2 is turned on, the potential of the bit line BLX = GND potential, and the potential of the plate line PL. = VDD potential, and a positive voltage is applied to the ferroelectric capacitor F2.

  The pre-sense amplifier 2 has switches S1, S3, S5, a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) P1, capacitors C1, C3, an NMOS transistor N8, and a load conductance Z1. The capacitors C1 and C3 may be ferroelectric capacitors or other capacitors.

  The switch S1 has one end connected to the bit line BL and the other end grounded. The switch S1 is ON when the bit line BL is reset, and is OFF otherwise. The switch S3 has one end connected to the node MINUS and the other end connected to the output terminal 5A of the negative voltage generating circuit 5, and is turned on when the node MINUS is reset and turned off otherwise.

  The PMOS transistor P1 has a source connected to the bit line BL, a gate connected to the output terminal 4A of the threshold generation circuit 4, a drain connected to the node MINUS, and a back gate grounded. The capacitor C1 has one end connected to the node MINUS and the other end grounded. The capacitor C3 has one end connected to the node MINUS and the other end connected to the gate of the NMOS transistor N8.

  The switch S5 has one end connected to the gate of the NMOS transistor N8 and the other end grounded. The NMOS transistor N8 has a drain connected to the VDD power supply and a source connected to one end of the load conductance Z1 and the output terminal OUT of the pre-sense amplifier 2. The load conductance Z1 is grounded at the other end.

  The pre-sense amplifier 3 includes switches S2, S4, S6, a PMOS transistor P2, capacitors C2, C4, an NMOS transistor N9, and a load conductance Z2. The capacitors C2 and C4 may be ferroelectric capacitors or other capacitors.

  The switch S2 has one end connected to the bit line BLX and the other end grounded. The switch S2 is ON when the bit line BLX is reset, and is OFF otherwise. The switch S4 has one end connected to the node MINUSX and the other end connected to the output terminal 5A of the negative voltage generation circuit 5. The switch S4 is turned on when the node MINUSX is reset, and is turned off otherwise.

  The PMOS transistor P2 has a source connected to the bit line BLX, a gate connected to the output terminal 4A of the threshold value generation circuit 4, and a drain connected to the node MINUSX. The capacitor C2 has one end connected to the node MINUSX and the other end grounded. The capacitor C4 has one end connected to the node MINUSX and the other end connected to the gate of the NMOS transistor N9.

  The switch S6 has one end connected to the gate of the NMOS transistor N9 and the other end grounded. The NMOS transistor N9 has a drain connected to the VDD power supply and a source connected to one end of the load conductance Z2 and the output terminal OUTX of the pre-sense amplifier 3. The load conductance Z2 is grounded at the other end.

  The threshold generation circuit 4 generates a potential equal to the threshold VTHP of the PMOS transistor when the bit lines BL and BLX are at the GND potential, that is, when the sources of the PMOS transistors P1 and P2 are at the GND potential. The potential VTHP output by 4 is a potential lower than the GND potential. The negative voltage generation circuit 5 generates a negative potential VMINUS (for example, −3 V).

  Reference numeral 20 denotes a node to which a latch start signal SAPOWER for controlling the latch operation of the sense amplifier 6 is applied, and the inverter IB1 inverts the latch start signal SAPOWER.

  The sense amplifier 6 is a latch-type sense amplifier and includes PMOS transistors P3 to P7 and NMOS transistors N3 to N7. The PMOS transistor P4 and the NMOS transistor N4 have drains connected to each other and gates connected to each other to constitute an inverter IB2. The PMOS transistor P5 and the NMOS transistor N5 have drains connected to each other and gates connected to each other to constitute an inverter IB3.

  The inverter IB2 has an input end connected to the node SAOUTX and an output end connected to the node SAOUT. The inverter IB3 has an input end connected to the node SAOUT and an output end connected to the node SAOUTX.

  The PMOS transistor P3 has a source connected to the VDD power source, a drain connected to the sources of the PMOS transistors P4 and P5, and a gate connected to the output terminal of the inverter IB1, thereby connecting the inverters IB2 and IB3 to the VDD power source. The power switch to make.

  The NMOS transistor N3 has a drain connected to the sources of the NMOS transistors N4 and N5, a source grounded, and a gate connected to the node 20, thereby forming a power switch for connecting the inverters IB2 and IB3 to the GND power supply. Yes.

  The PMOS transistor P6 and the NMOS transistor N6 constitute a transfer gate TG1, and the transfer gate TG1 has an input terminal connected to the output terminal OUT of the pre-sense amplifier 2 and an output terminal connected to the node SAOUT. The gate of the PMOS transistor P6 is connected to the node 20, and the gate of the NMOS transistor N6 is connected to the output terminal of the inverter IB1.

  The PMOS transistor P7 and the NMOS transistor N7 constitute a transfer gate TG2, and the transfer gate TG2 has an input terminal connected to the output terminal OUTX of the pre-sense amplifier 3 and an output terminal connected to the node SAOUTX. The gate of the PMOS transistor P7 is connected to the node 20, and the gate of the NMOS transistor N7 is connected to the output terminal of the inverter IB1.

  FIG. 6 is a waveform diagram showing an operation example at the time of data reading of the conventional ferroelectric memory shown in FIG. 5. The word line WL, the plate line PL, the bit lines BL, BLX, the nodes MINUS, MINUSX, the pre-sense amplifier 2, 3 shows potential waveforms of the output terminals OUT and OUTX, the latch activation signal SAPOWER, and the nodes SAOUT and SAOUTX. The ferroelectric capacitor F1 has data “1” and the ferroelectric capacitor F2 has data “0”. An example of writing and reading this is taken as an example.

  In the conventional ferroelectric memory shown in FIG. 5, when data is read from the memory cell 1, the switches S1 and S2 in the pre-sense amplifiers 2 and 3 remain ON until time TRES, as shown in FIG. As described above, the bit lines BL and BLX are fixed to the GND potential. However, after the time TRES, the bit lines BL and BLX are turned OFF, and the bit lines BL and BLX are opened.

  The threshold generation circuit 4 generates a potential equal to the threshold VTHP of the PMOS transistor when the bit lines BL and BLX are at the GND potential, that is, when the sources of the PMOS transistors P1 and P2 are at the GND potential. Supply to the gate of P2.

  The switches S3 and S4 in the pre-sense amplifiers 2 and 3 remain ON until time TRES, and the nodes MINUS and MINUSX are lowered to the negative potential VMINUS output by the negative voltage generation circuit 5, but after time TRES. Turns off and opens the nodes MINUS and MINUSX. Note that from time TRES to time TWLPL, the potentials of the nodes MINUS and MINUSX are kept at the negative potential VMINUS by the capacitors C1 and C2.

  Further, the switches S5 and S6 in the pre-sense amplifiers 2 and 3 remain ON until time TRES, the gates of the NMOS transistors N8 and N9 are fixed to the GND potential, and the nodes OUT and OUTX are fixed to the GND potential. However, after time TRES, it is turned OFF, the gates of the NMOS transistors N8 and N9 are opened, and the nodes OUT and OUTX are opened.

  At time TWLPL, as shown in FIGS. 6A and 6B, the potentials of the word line WL and the plate line PL are raised to the VDD potential, the access transistors N1, N2 are turned on, and the ferroelectric capacitors F1, A positive voltage is applied to F2. Here, since the voltage applied to the ferroelectric capacitor F1 storing the data “1” has a polarity opposite to that at the time of writing, polarization inversion occurs in the ferroelectric capacitor F1, and the ferroelectric capacitor F1. Therefore, a relatively large inversion charge flows into the bit line BL.

  At this time, the potential of the bit line BL tends to rise due to the inverted charge flowing from the ferroelectric capacitor F1, but since the threshold value VTHP is applied to the gate of the PMOS transistor P1, as shown in FIG. When the potential of the bit line BL rises slightly, the PMOS transistor P1 is turned on, and a charge equal to the inverted charge flows from the bit line BL to the node MINUS via the source and drain of the PMOS transistor P1.

  As a result, the bit line BL is maintained in the vicinity of the GND potential, and the potential of the node MINUS held at the minus potential VMINUS by the capacitor C1 greatly increases as indicated by a one-dot chain line in FIG. .

  On the other hand, since the voltage applied to the ferroelectric capacitor F2 storing the data “0” has the same polarity as that at the time of writing, no polarization inversion occurs in the ferroelectric capacitor F2, and the ferroelectric capacitor A relatively small charge flows from the body capacitance F2 into the bit line BLX.

  At this time, the potential of the bit line BLX tends to rise due to the charge flowing from the ferroelectric capacitor F2, but since the threshold VTHP is applied to the gate of the PMOS transistor P2, as shown in FIG. When the potential of the line BLX rises slightly, the PMOS transistor P2 is turned ON, and charge flows from the bit line BLX to the node MINUSX via the source and drain of the PMOS transistor P2.

  As a result, the bit line BLX is maintained in the vicinity of the GND potential, and the potential of the node MINUSX held at the negative potential VMINUS by the capacitor C2 rises as shown by a two-dot chain line in FIG. However, it is smaller than the increase in the potential of the node MINUS.

  After the time TRES, the switches S5 and S6 are turned off and the nodes OUT and OUTX are opened, but the capacitors C3 and C4 maintain the potential difference between both ends thereof, so that the nodes OUT and MINUSX change in accordance with the potential changes at the nodes MINUS and MINUSX. , The potential of OUTX also moves.

  Therefore, after time TRES, when the potentials of the nodes MINUS and MINUSX rise as shown in FIG. 6D, the potentials of the nodes OUT and OUTX become the waveforms of the nodes MINUS and MINUSX as shown in FIG. 6E. And the waveform of the positive potential with reference to the GND potential shifted to the upper side (positive potential side) by | VMINUS | −VTHN (the threshold value of the NMOS transistors N8 and N9).

  Before the time TLATCH, the latch activation signal SAPOWER is at the GND potential as shown in FIG. 6F, and in the sense amplifier 6, the transfer gates TG1 and TG2 are ON, the PMOS transistor P3 and the NMOS transistor N3 is OFF, and the inverters IB2 and IB3 are inactive because the VDD power supply and the GND power supply are not supplied.

  As a result, after the time TWPL and before the time TLATCH, the potentials of the nodes SAOUT and SAOUTX rise in conjunction with the potentials of the nodes OUT and OUTX as shown in FIG.

  After the time TLATCH, the latch activation signal SAPOWER becomes the VDD potential as shown in FIG. As a result, the transfer gates TG1 and TG2 are turned off, the PMOS transistor P3 and the NMOS transistor N3 are turned on, and the inverters IB2 and IB3 are supplied with VDD power and GND power and are activated.

  As a result, the sense amplifier 6 amplifies the potential difference between the nodes SAOUT and SAOUTX, sets the potential of the node SAOUT = VDD potential, and the potential of the node SAOUTX = GND potential, and the data read from the ferroelectric capacitors F1 and F2 of the memory cell 1. “1” and “0” are latched.

  In this example, the case where the data “1” is written in the ferroelectric capacitor F1 and the data “0” is written in the ferroelectric capacitor F2, the data “0” is stored in the ferroelectric capacitor F1. Even in the case where data “1” is written in the capacitor F2, the circuit is symmetrical, so that the same operation is performed only by inversion of the phase.

  FIG. 7 is a circuit diagram of a part of another example of a conventional ferroelectric memory. The conventional ferroelectric memory shown in FIG. 7 includes a read circuit called a twin sense system or a dual sense system. The same elements as those in the conventional ferroelectric memory shown in FIG. In FIG. 5, BL is BL0, BLX is BL0X, OUT is OUT0, OUTX is OUT0X, SAOUT is SAOUT0, and SAOUTX is SAOUT0X.

  In FIG. 7, 1 is a 2-transistor / 2-capacitor type memory cell, 14 and 15 are 1-transistor / 1-capacitor type memory cells, WL is a word line, PL is a plate line, BL0, BL0X, BL1, and BL2 are bit lines. 2, 3, 12, and 13 are pre-sense amplifiers, and 6 to 11 are sense amplifiers.

  The memory cell 1 includes ferroelectric capacitors F1 and F2 that form a storage medium, and access transistors N1 and N2 that are NMOS transistors, and is configured in the same manner as the memory cell 1 shown in FIG.

  That is, the access transistor N1 has a gate connected to the word line WL, a source connected to the bit line BL0, a drain connected to one end of the ferroelectric capacitor F1, and the ferroelectric capacitor F1 connected to the plate line at the other end. Connected to PL. The access transistor N2 has a gate connected to the word line WL, a source connected to the bit line BL0X, a drain connected to one end of the ferroelectric capacitor F2, and the other end connected to the plate line PL. Connected.

  The memory cell 14 includes a ferroelectric capacitor F3 that forms a storage medium, and an access transistor N12 that includes an NMOS transistor. The access transistor N12 has a gate connected to the word line WL, a source connected to the bit line BL1, a drain connected to one end of the ferroelectric capacitor F3, and the other end connected to the plate line PL. Connected.

  The memory cell 15 has a ferroelectric capacitor F4 as a storage medium and an access transistor N13 made up of an NMOS transistor. The access transistor N13 has a gate connected to the word line WL, a source connected to the bit line BL2, a drain connected to one end of the ferroelectric capacitor F4, and the ferroelectric capacitor F4 connected to the plate line PL. Connected.

  The pre-sense amplifiers 2, 3, 12, and 13 are configured in the same manner as the pre-sense amplifier 2 shown in FIG. The pre-sense amplifier 2 is provided corresponding to the bit line BL0, and the output voltage of the pre-sense amplifier 2 is supplied to the sense amplifiers 6 and 7 and also supplied as a reference voltage REF to the sense amplifiers 9 and 11. .

  The pre-sense amplifier 3 is provided corresponding to the bit line BL0X, and the output voltage of the pre-sense amplifier 3 is supplied to the sense amplifiers 6 and 7 and also supplied as the reference voltage REFX to the sense amplifiers 8 and 10. .

  The pre-sense amplifier 12 is provided corresponding to the bit line BL1, and the pre-sense amplifier 13 is provided corresponding to the bit line BL2. Note that OUT1 is an output terminal of the presense amplifier 12 corresponding to the output terminal OUT of the presense amplifier 2 shown in FIG. 5, and OUT2 is an output terminal of the presense amplifier 13 corresponding to the output terminal OUT of the presense amplifier 2 shown in FIG. is there.

  The sense amplifiers 6 to 11 are sense amplifiers having the same configuration. The sense amplifiers 6 and 7 detect data read out to the bit lines BL0 and BL0X by amplifying the potential difference between the output voltages of the pre-sense amplifiers 2 and 3.

  The sense amplifier 8 detects data read to the bit line BL1 by amplifying the potential difference between the output voltage of the pre-sense amplifier 12 and the reference voltage REFX. The sense amplifier 9 detects data read to the bit line BL1 by amplifying the potential difference between the output voltage of the pre-sense amplifier 12 and the reference voltage REF.

  The sense amplifier 10 detects data read to the bit line BL2 by amplifying the potential difference between the output voltage of the pre-sense amplifier 13 and the reference voltage REFX. The sense amplifier 11 detects data read to the bit line BL2 by amplifying the potential difference between the output voltage of the pre-sense amplifier 13 and the reference voltage REF.

  The sense amplifier 6 is a sense amplifier having the same configuration as that of the sense amplifier 6 shown in FIG. 5. In the sense amplifier 6, 6A is a positive phase input terminal connected to the transfer gate TG1, and 6AX is connected to the transfer gate TG2. The negative phase input terminal, 6B is a positive phase output terminal to which the output terminal of the inverter IB2 is connected, and 6BX is a negative phase output terminal to which the output terminal of the inverter IB3 is connected.

  In the sense amplifiers 7 to 11, 7A to 11A are positive phase input terminals corresponding to the positive phase input terminal 6A of the sense amplifier 6, 7AX to 11AX are negative phase input terminals corresponding to the negative phase input terminal 6AX of the sense amplifier 6, and 7B -11B is a positive phase output terminal corresponding to the positive phase output terminal 6B of the sense amplifier 6, and 7BX to 11BX are negative phase output terminals corresponding to the negative phase output terminal 6BX of the sense amplifier 6.

  In this example, the sense amplifier 6 has the positive phase input terminal 6A connected to the output terminal OUT0 of the pre-sense amplifier 2, the negative phase input terminal 6AX connected to the output terminal OUT0X of the pre-sense amplifier 3, and the positive phase output terminal 6B connected to the node. Connected to SAOUT0, the negative phase output terminal 6BX is connected to the node SAOUT0X.

  The sense amplifier 7 has the positive phase input terminal 7A connected to the output terminal OUT0 of the pre-sense amplifier 2, the negative phase input terminal 7AX connected to the output terminal OUT0X of the pre-sense amplifier 3, and the positive phase output terminal 7B connected to the node SAOUT0. The negative phase output terminal 7BX is connected to the node SAOUT0X. That is, the sense amplifier 6 and the sense amplifier 7 are symmetrical.

  The sense amplifier 8 has a positive phase input terminal 8A connected to the output terminal OUT1 of the pre-sense amplifier 12, a negative phase input terminal 8AX connected to the output terminal OUT0X of the pre-sense amplifier 3, and a positive phase output terminal 8B connected to the node SAOUT1. The negative phase output terminal 8BX is connected to the node SAOUT1X.

  The sense amplifier 9 has the positive phase input terminal 9A connected to the output terminal OUT1 of the pre-sense amplifier 12, the negative phase input terminal 9AX connected to the output terminal OUT0 of the pre-sense amplifier 2, and the positive phase output terminal 9B connected to the node SAOUT1. The negative phase output terminal 9BX is connected to the node NODE1, and the node NODE1 is opened.

  The sense amplifier 10 has a positive phase input terminal 10A connected to the output terminal OUT2 of the pre-sense amplifier 13, a negative phase input terminal 10AX connected to the output terminal OUT0X of the pre-sense amplifier 3, and a positive phase output terminal 10B connected to the node SAOUT2. The negative phase output terminal 10BX is connected to the node SAOUT2X.

  The sense amplifier 11 has a positive phase input terminal 11A connected to the output terminal OUT2 of the pre-sense amplifier 13, a negative phase input terminal 11AX connected to the output terminal OUT0 of the pre-sense amplifier 2, and a positive phase output terminal 11B connected to the node SAOUT2. The negative phase output terminal 11BX is connected to the node NODE2, and the node NODE2 is open.

  That is, in this example, the pre-sense amplifiers 2 and 3 and the sense amplifiers 6 and 7 constitute a read circuit for the memory cells such as the memory cell 1 connected to the bit lines BL0 and BL0X. Further, the pre-sense amplifier 12 and the sense amplifiers 8 and 9 constitute a read circuit for a memory cell connected to the bit line BL1, such as the memory cell. Further, the pre-sense amplifier 13 and the sense amplifiers 10 and 11 constitute a read circuit for a memory cell connected to the bit line BL2, such as the memory cell 15.

  Note that a large number of 2-transistor / 2-capacitor type memory cells such as the memory cell 1 are arranged in the vertical direction, but illustration of the 2-transistor / 2-capacitor type memory cells other than the memory cell 1 is omitted. A number of 1-transistor / 1-capacitor type memory cells such as the memory cells 14 and 15 are arranged vertically and horizontally, but the illustration of the 1-transistor / 1-capacitor type memory cells other than the memory cells 14 and 15 is omitted. ing.

  For bit lines, pre-sense amplifiers, and sense amplifiers provided corresponding to 1-transistor / 1-capacitor type memory cells, only bit lines BL1, BL2, pre-sense amplifiers 12, 13, and sense amplifiers 8-11 are shown. The other bit lines, pre-sense amplifiers and sense amplifiers are not shown.

  Further, the threshold value generation circuit 4 and the negative voltage generation circuit 5 shown in FIG. 5 are provided as the threshold value generation circuit and the negative voltage generation circuit, and the threshold value VTHP and the negative voltage generation circuit 5 output by the threshold value generation circuit 4 output. The negative voltage VMINUS is configured to be supplied to pre-sense amplifiers such as the pre-sense amplifiers 2, 3, 12, and 13, but the threshold value generating circuit 5 and the negative voltage generating circuit 6 are not shown.

  Also in this example, as in the case of the conventional ferroelectric memory shown in FIG. 5, the latch activation signal SAPOWER and the inverter IB1 that inverts the latch activation signal SAPOWER are required, and the outputs of the latch activation signal SAPOWER and the inverter IB1 are required. Are supplied to the sense amplifiers 6 to 11, but the latch activation signal SAPOWER and the inverter IB1 are not shown.

  FIG. 8 is a waveform diagram showing an operation example at the time of data reading of the conventional ferroelectric memory shown in FIG. 7, and word lines WL, plate lines PL, latch activation signals SAPOWER, bit lines BL0 and BL0X, nodes MINUS0 and MINUS0X. , MINUS1, MINUS2, output terminals OUT0, OUT0X, OUT1, OUT2, and nodes SAOUT0X, SAOUT0X, SAOUT1, SAOUT1X, SAOUT2, and SAOUT2X of the pre-sense amplifiers 2, 3, 12, 13 are shown as ferroelectric capacitors F1. In this example, data “1” is written in the ferroelectric capacitor F2, data “0” is written in the ferroelectric capacitor F3, data “0” is written in the ferroelectric capacitor F3, and data “1” is written in the ferroelectric capacitor F4. It is said.

  Although the nodes MINUS0, MINUS0X, MINUS1, and MINUS2 are not shown in FIG. 7, the node MINUS0 is a node in the pre-sense amplifier 2 shown in FIG. 7 corresponding to the node MINUS shown in FIG. 5, and the node MINUS0X is shown in FIG. A node in the pre-sense amplifier 3 corresponding to the node MINUSX shown in FIG. 5, a node MINUS1 is a node in the pre-sense amplifier 12 corresponding to the node MINUS shown in FIG. 5, and a node MINUS2 corresponds to the node MINUS shown in FIG. This is a node in the pre-sense amplifier 13.

  In this example, data “1” is written in the ferroelectric capacitor F1, and data “0” is written in the ferroelectric capacitor F2. Therefore, when data is read from the memory cell 1, the conventional strong capacitor shown in FIG. As in the case of the dielectric memory, as shown in FIG. 8E, a relatively high voltage waveform appears at the node MINUS0 and a relatively low voltage waveform appears at the node MINUS0X. As a result, as shown in FIG. 8H, a relatively high voltage waveform appears at the output terminal OUT0 of the pre-sense amplifier 2, and a relatively low voltage waveform appears at the output terminal OUT0X of the pre-sense amplifier 3. .

  Therefore, when the latch activation signal SAPOWER rises to the VDD potential at time TLATCH, the sense amplifiers 6 and 7 amplify the potential difference between the nodes SAOUT0 and SAOUT0X so that the potential of the node SAOUT0 = VDD potential and the potential of the node SAOUT0X = GND potential. Data read from the memory cell 1 is latched. The sense amplifier 7 may be omitted, but is provided in order to make the layout and the load capacitance equivalent to the twin sense amplifiers such as the sense amplifiers 8 and 9 and the sense amplifiers 10 and 11.

  In addition, since data “0” is written in the ferroelectric capacitor F3 of the memory cell 14, when data is read from the memory cell 14, a waveform of a low voltage almost the same as that of the node MINUS0X is generated at the node MINUS1. At the output terminal OUT1 of the pre-sense amplifier 12, a waveform having a voltage that is substantially the same as that of the output terminal OUT0X of the pre-sense amplifier 3 is generated.

  Therefore, when the latch activation signal SAPOWER rises to the VDD potential at time TLATCH, the sense amplifiers 8 and 9 detect the potential of the output terminal OUT1 of the pre-sense amplifier 12 and the reference voltages REF and REFX (the output terminals OUT0 and OUT0X of the pre-sense amplifiers 2 and 3). And the potential of the node SAOUT1 = GND potential, the potential of the node SAOUT1X = VDD potential, and the data “0” read from the ferroelectric capacitor F3 of the memory cell 14 is compared according to the principle of the twin sense method described later. Latch.

  In addition, since data “1” is written in the ferroelectric capacitor F4 of the memory cell 15, when data is read from the memory cell 15, a waveform of a high voltage almost the same as that of the node MINUS0 is generated at the node MINUS2. At the output terminal OUT2 of the pre-sense amplifier 13, a waveform having a high voltage that is almost the same as that of the output terminal OUT0 of the pre-sense amplifier 2 is generated.

  Therefore, when the latch activation signal SAPOWER rises to the VDD potential at time TLATCH, the sense amplifiers 10 and 11 detect the potential of the output terminal OUT2 of the pre-sense amplifier 13 and the reference voltages REF and REFX (the output terminals OUT0 and OUT0X of the pre-sense amplifiers 2 and 3). And the potential of the node SAOUT2 = VDD potential and the potential of the node SAOUT2X = GND potential, and the data “1” read from the ferroelectric capacitor F4 of the memory cell 15 is determined according to the principle of the twin sense method described later. Latch.

  FIG. 9 shows the twin sense of the sense amplifiers 8 and 9 when data “1” is written in the ferroelectric capacitor F1, data “0” is written in the ferroelectric capacitor F2, and data “0” is written in the ferroelectric capacitor F3. It is a wave form diagram for demonstrating operation | movement. FIG. 9A shows the potential change of the latch activation signal SAPPOWER. FIG. 9B shows the operation of the sense amplifier 8 and shows potential changes at the nodes SAOUT1 and SAOUT1X. FIG. 9C shows the operation of the sense amplifier 9 and shows potential changes at the nodes SAOUT1 and NODE1.

  In this example, data “1” is written in the ferroelectric capacitor F1, data “0” is written in the ferroelectric capacitor F2, and data “0” is written in the ferroelectric capacitor F3. Therefore, immediately before the time TLATCH. Then, the potential of the output terminal OUT0 of the pre-sense amplifier 2 (reference voltage REF) is relatively high, the potential of the output terminal OUT0X of the pre-sense amplifier 3 (reference voltage REFX) is relatively low, and the output terminal of the pre-sense amplifier 12 The potential of OUT1 is relatively low.

  Here, in the sense amplifier 9, until the time TLATCH, the potential of the node SAOUT1 = the potential of the output terminal OUT1 of the pre-sense amplifier 12, the potential of the node NODE1 = the potential of the output terminal OUT0 of the pre-sense amplifier 2 = the reference voltage REF. Therefore, immediately before the time TLATCH, the potential of the node SAOUT1 is relatively low, and the potential of the node NODE1 is relatively high.

  That is, (the potential of the node NODE1−the potential of the node SAOUT1) = ΔVb is positive, and the voltage between the nodes NODE1 and SAOUT1 is such that the potential of the node NODE1 = VDD potential and the potential of the node SAOUT1 = GND potential. A voltage in a direction of latching data “0” read from the ferroelectric capacitor F3 of the memory cell 14 is applied.

  As a result, when the latch activation signal SAPOWER rises to the VDD potential at time TLATCH, the sense amplifier 9 amplifies the potential difference ΔVb between the nodes NODE1 and SAOUT1, and sets the potential of the node NODE1 = VDD potential and the potential of the node SAOUT1 = GND potential. The data “0” read from the ferroelectric capacitor F3 of the memory cell 14 is latched.

  On the other hand, in the sense amplifier 8, until the time TLATCH, the potential of the node SAOUT1 = the potential of the output terminal OUT1 of the pre-sense amplifier 12, the potential of the node SAOUT1X = the potential of the output terminal OUT0X of the pre-sense amplifier 3 = the reference voltage REFX. , (Potential of the node SAOUT1−potential of the node SAOUT1X) = ΔVa is almost zero.

  Therefore, even if the latch activation signal SAPOWER rises to the VDD potential at time TLATCH, there is no potential difference between the nodes SAOUT1 and SAOUT1X, so that the sense amplifier 8 enters the metastable state and does not move immediately.

  However, since the node SAOUT1 is shared by the sense amplifiers 8 and 9, the potential of the node SAOUT1 eventually falls and becomes the GND potential by the sense amplifier 9, so that the sense amplifier 8 is released from the metastable state. Then, the potential of the node SAOUT1X is set to the VDD potential, and the data “0” read from the ferroelectric capacitor F3 of the memory cell 14 is latched.

  FIG. 10 shows the twin sense of the sense amplifiers 10 and 11 when data “1” is written in the ferroelectric capacitor F1, data “0” is written in the ferroelectric capacitor F2, and data “1” is written in the ferroelectric capacitor F4. It is a wave form diagram for demonstrating operation | movement. FIG. 10A shows the potential change of the latch activation signal SAPPOWER. FIG. 10B shows the operation of the sense amplifier 10 and shows potential changes at the nodes SAOUT2 and SAOUT2X. FIG. 10C shows the operation of the sense amplifier 11 and shows potential changes at the nodes SAOUT2 and NODE2.

  In this example, data “1” is written in the ferroelectric capacitor F1, data “0” is written in the ferroelectric capacitor F2, and data “1” is written in the ferroelectric capacitor F4. The potential of the output terminal OUT0 of the amplifier 2 (reference voltage REF) is relatively high, the potential of the output terminal OUT0X of the pre-sense amplifier 3 (reference voltage REFX) is relatively low, and the potential of the output terminal OUT2 of the pre-sense amplifier 13. Becomes a relatively high potential.

  Here, in the sense amplifier 10, until the time TLATCH, the potential of the node SAOUT2 = the potential of the output terminal OUT2 of the pre-sense amplifier 13, and the potential of the node SAOUT2X = the potential of the output terminal OUT0X of the pre-sense amplifier 3 (reference voltage REFX). Therefore, immediately before the time TLATCH, the node SAOUT2 has a relatively high potential and the node SAOUT2X has a relatively low potential.

  That is, (potential of the node SAOUT2−potential of the node SAOUT2X) = ΔVc is positive, and the voltage between the nodes SAOUT2 and SAOUT2X is such that the potential of the node SAOUT2 = VDD potential and the potential of the node SAOUT2X = GND potential ( Data “1” read from the ferroelectric capacitor F4 of the memory cell 15 is applied).

  As a result, when the latch activation signal SAPOWER rises to the VDD potential at time TLATCH, the sense amplifier 10 amplifies the potential difference ΔVc between the nodes SAOUT2 and SAOUT2X so that the potential of the node SAOUT2 = VDD potential and the potential of the node SAOUT2X = GND potential. The data “1” read from the ferroelectric capacitor F4 of the memory cell 15 is latched.

  On the other hand, in the sense amplifier 11, until the time TLATCH, the potential of the node SAOUT2 = the potential of the output terminal OUT2 of the pre-sense amplifier 13, and the potential of the node NODE2 = the potential of the output terminal OUT0 of the pre-sense amplifier 2 (reference voltage REF). Therefore, (the potential at the node SAOUT2−the potential at the node NODE2) = ΔVd is almost zero.

  Therefore, even if the latch activation signal SAPOWER rises to the VDD potential at time TLATCH, there is no potential difference between the nodes SAOUT2 and NODE2, so that the sense amplifier 11 enters the metastable state and does not move immediately.

  However, since the node SAOUT2 is shared by the sense amplifiers 10 and 11, the potential of the node SAOUT2 eventually rises to the VDD potential by the sense amplifier 10, so that the sense amplifier 11 escapes from the metastable state, The potential of the node NODE2 is set to the GND potential, and the data “1” read from the ferroelectric capacitor F4 of the memory cell 15 is latched.

  In this example, data “1” is written in the ferroelectric capacitor F1, and data “0” is written in the ferroelectric capacitor F2, and the potential (reference voltage REF) of the output terminal OUT0 of the pre-sense amplifier 2 is relatively high. The potential (reference voltage REFX) of the output terminal OUT0X of the pre-sense amplifier 3 is relatively low, but the same can be said in the opposite case.

  As described above, in a twin-sense read circuit, a reference voltage REF that is relatively high and relatively low or vice versa without using a reference voltage that is an intermediate potential between the VDD potential and the GND potential. By using REFX, data read from the ferroelectric capacitor of the memory cell is latched.

Patent Document 1, Patent Document 2, and Non-Patent Document 1 disclose conventional data reading methods for ferroelectric memories.
JP 2002-133857 A JP 2002-157876 A S. Kawashima, et. al. , IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 5, MAY 2002, p592-598

  FIG. 11 is a waveform diagram showing a variation range of potentials of the output terminals OUT0, OUT0X, OUT1, and OUT2 of the pre-sense amplifiers 2, 3, 12, and 13 in the conventional ferroelectric memory shown in FIG. The range of potential variation of the output terminals OUT0, OUT0X, OUT1, and OUT2 when the expected logical values of the output terminals OUT0, OUT0X, OUT1, and OUT2 are “1” is shown. The hatched portion 22 indicates the output terminals OUT0, OUT0X, OUT1, and The range of potential variation of the output terminals OUT0, OUT0X, OUT1, and OUT2 when the expected logical value of OUT2 is “0” is shown.

  In general, in a ferroelectric memory, the amount of charge inversion between the ferroelectric capacitor and the ferroelectric capacitor varies greatly. In the case of the conventional ferroelectric memory shown in FIG. 7, after the time TWLPL, before the time TLATCH. The potentials of the output terminals OUT0, OUT0X, OUT1, and OUT2 of the pre-sense amplifiers 2, 3, 12, and 13 in FIG. 11 even when the expected logical value is “1” as indicated by the hatched portions 21 and 22 in FIG. Even in the case of “0”, both vary greatly.

  FIG. 12 shows a pre-sense amplifier for the sense amplifiers 8 and 9 when data “1” is written in the ferroelectric capacitor F1, data “0” is written in the ferroelectric capacitor F2, and data “0” is written in the ferroelectric capacitor F3. 6 is a waveform diagram for explaining a twin sense operation of the sense amplifiers 8 and 9 when the variation in potential of the output terminals OUT0, OUT0X, and OUT1 of 2, 3, and 12 is worst. FIG.

  In this example, after time TWLPL and before time TLATCH, the potential of the output terminal OUT0 of the pre-sense amplifier 2 (reference voltage REF) is relatively high, and the potential of the output terminal OUT0X of the pre-sense amplifier 3 (reference voltage REFX) is The output terminal OUT1 of the pre-sense amplifier 12 has a relatively low potential and a relatively low potential.

  In this case, the worst variation occurs when the potential at the output terminal OUT1 of the pre-sense amplifier 12 is the maximum value of the variation range when the potential of the expected logical value is “0” (the potential at the upper end of the hatched portion 22). When the potential (reference voltage REF) is the expected logical value “1”, the minimum value of the variation range (potential at the lower end of the shaded portion 21), and the potential (reference voltage REFX) of the output terminal OUT0X of the pre-sense amplifier 3 is the expected logical value “ In this case, the minimum value of the variation range in the case of 0 ″ (the potential at the lower end of the hatched portion 22) is obtained.

  Here, in the sense amplifier 9, until the time TLATCH, the potential of the node SAOUT1 = the potential of the output terminal OUT1 of the pre-sense amplifier 12, the potential of the node NODE1 = the potential of the output terminal OUT0 of the pre-sense amplifier 2 (reference voltage REF). Therefore, between the nodes SAOUT1 and NODE1, the potential of the node SAOUT1 is relatively low, the potential of the node NODE1 is relatively high, and (potential of the node NODE1−potential of the node SAOUT1) = ΔVf is positive. .

  In this example, the maximum value of the variation range when the potential of the output terminal OUT1 of the pre-sense amplifier 12 is the expected logical value “0” (the potential at the upper end of the hatched portion 22), the potential of the output terminal OUT0 of the pre-sense amplifier 2 (reference voltage) REF) is the minimum value of the variation range when the expected logical value is “1” (the potential at the lower end of the shaded portion 21), so ΔVf is smaller than ΔVb shown in FIG. 9, but between the nodes NODE1 and SAOUT1. Is applied with a potential in a direction such that the potential of the node NODE1 = VDD potential and the potential of the node SAOUT1 = GND potential (potential in the direction of latching the data “0” read from the ferroelectric capacitor F3 of the memory cell 14). .

  Therefore, when the latch activation signal SAPOWER rises to the VDD potential at time TLATCH, the sense amplifier 9 amplifies the potential difference ΔVf between the nodes NODE1 and SAOUT1, and sets the potential of the node NODE1 = VDD potential, the potential of the node SAOUT1 = GND potential, The data “0” read from the ferroelectric capacitor F3 of the memory cell 14 is correctly latched.

  On the other hand, in the sense amplifier 8, until the time TLATCH, the potential of the node SAOUT1X = the potential of the output terminal OUT0X of the pre-sense amplifier 3 (reference voltage REFX), and the potential of the node SAOUT1 = the potential of the output terminal OUT1 of the pre-sense amplifier 12. The potentials of the node SAOUT1X and the node SAOUT1 are both low.

  However, in this example, when the potential at the output terminal OUT1 of the pre-sense amplifier 12 is the expected logical value “0”, the maximum value of the variation range (the potential at the upper end of the hatched portion 22), the potential at the output terminal OUT0X of the pre-sense amplifier 3 ( Since the reference voltage REFX) is the minimum value of the variation range when the expected logical value is “0” (the potential at the lower end of the shaded portion 22), (the potential at the node SAOUT1X−the potential at the node SAOUT1) = ΔVe is negative. Become.

  That is, the voltage between the nodes SAOUT1 and SAOUT1X is such that the potential of the node SAOUT1 = VDD potential and the potential of the node SAOUT1X = GND potential (the data “0” read from the ferroelectric capacitor F3 of the memory cell 14). Is a voltage in the direction of latching the opposite “1”). As a result, when the latch activation signal SAPOWER rises to the VDD potential at time TLATCH, the sense amplifier 8 tries to set the potential of the node SAOUT1 = VDD potential and the potential of the node SAOUT1X = GND potential.

  However, in this example, since | ΔVf |> | ΔVe |, the potential of the node SAOUT1 is eventually lowered to the GND potential by the sense amplifier 9, and as a result, the sense amplifier 8 is in a reverse state. Then, the potential of the node SAOUT1X is set to the VDD potential, and the data “0” read from the ferroelectric capacitor F3 of the memory cell 14 is latched.

  As described above, in the conventional ferroelectric memory shown in FIG. 7, the sense amplifiers from the time TLATCH to the time TOUT1 are caused by variations in the potentials of the output terminals OUT0, OUT0X, and OUT1 of the pre-sense amplifiers 2, 3, and 12. 8 and 9, there is a problem in that the operation is inconsistent and the latch is not settled. As a result, the output time is delayed, and the latch result cannot be output to the outside until time TOUT2. If the variation is even larger, | ΔVf | <| ΔVe |, and there is a problem that the sense amplifier 8 can win and erroneous latching can occur.

  FIG. 13 shows a pre-sense amplifier for the sense amplifiers 10 and 11 when data “1” is written in the ferroelectric capacitor F1, data “0” is written in the ferroelectric capacitor F2, and data “1” is written in the ferroelectric capacitor F4. 6 is a waveform diagram for explaining a twin sense operation of the sense amplifiers 10 and 11 when the variation in potential of the output terminals OUT0, OUT0X, and OUT2 of 2, 3, and 13 is worst. FIG.

  In this example, after time TWLPL and before time TLATCH, the potential of the output terminal OUT0 of the pre-sense amplifier 2 (reference voltage REF) is relatively high, and the potential of the output terminal OUT0X of the pre-sense amplifier 3 (reference voltage REFX) is The output terminal OUT2 of the pre-sense amplifier 13 has a relatively low potential and a relatively high potential.

  In this case, the worst variation occurs when the potential of the output terminal OUT2 of the pre-sense amplifier 13 is the minimum value of the variation range when the potential of the expected logical value “1” (the potential at the lower end of the hatched portion 21), and the output terminal OUT0X of the pre-sense amplifier 3 When the potential (reference voltage REFX) is the expected logical value “0”, the maximum value of the variation range (the potential at the upper end of the hatched portion 22), the potential at the output terminal OUT0 of the pre-sense amplifier 2 (reference voltage REF) is the expected logical value “ In this case, the maximum value of the variation range in the case of 1 ″ (the potential at the upper end of the hatched portion 21) is obtained.

  Here, in the sense amplifier 10, until the time TLATCH, the potential at the node SAOUT2 = the potential at the output terminal OUT2 of the pre-sense amplifier 13 and the potential at the node SAOUT2X = the potential at the node OUT0X (reference voltage REFX). And SAOUT2X, the potential of the node SAOUT2 is high, the potential of the node SAOUT2X is low, and (potential of the node SAOUT2−potential of the node SAOUT2X) = ΔVg is positive.

  In this example, the minimum value of the variation range when the potential at the output terminal OUT2 of the pre-sense amplifier 13 is the expected logical value “1” (the potential at the lower end of the hatched portion 21), the potential at the output terminal OUT0X of the pre-sense amplifier 3 (reference voltage) Since REFX) is the maximum value of the variation range when the expected logical value is “0” (the potential at the upper end of the shaded portion 22), ΔVg is smaller than ΔVc shown in FIG. 10, but between the nodes SAOUT2 and SAOUT2X. Is applied with a potential in such a direction that the potential of the node SAOUT2 = VDD potential and the potential of the node SAOUT2X = GND potential (potential in the direction of latching the data “1” read from the ferroelectric capacitor F4 of the memory cell 15). .

  Therefore, when the latch activation signal SAPOWER rises to the VDD potential at time TLATCH, the sense amplifier 10 amplifies the potential difference ΔVg between the nodes SAOUT2 and SAOUT2X, and sets the potential of the node SAOUT2 = VDD potential and the potential of the node SAOUT2X = GND potential. The data “1” read from the ferroelectric capacitor F4 of the memory cell 15 is to be latched correctly.

  On the other hand, in the sense amplifier 11, until the time TLATCH, the potential of the node SAOUT2 = the potential of the output terminal OUT2 of the pre-sense amplifier 12, and the potential of the node NODE2 = the potential of the output terminal OUT0 of the pre-sense amplifier 2 (reference voltage REF). The potentials of the node SAOUT2 and the node NODE2 are both high.

  However, in this example, when the potential at the output terminal OUT2 of the pre-sense amplifier 13 is the expected logical value “1”, the minimum value of the variation range (the potential at the lower end of the hatched portion 21), the potential at the output terminal OUT0 of the pre-sense amplifier 2 ( Since the reference voltage REF) is the maximum value of the variation range when the expected logical value is “1” (the potential at the upper end of the shaded portion 21), (the potential at the node SAOUT2−the potential at the node NODE2) = ΔVh is negative. Become.

  That is, the voltage between the nodes SAOUT2 and NODE2 is such that the potential of the node SAOUT2 = GND potential and the potential of the node NODE2 = VDD potential (data “1 read from the ferroelectric capacitor F4 of the memory cell 15). The voltage in the direction of latching “0” opposite to “is applied”. As a result, when the latch activation signal SAPOWER rises to the VDD potential at time TLATCH, the sense amplifier 11 tries to set the potential of the node SAOUT2 = GND potential and the potential of the node NODE2 = VDD potential.

  However, in this example, since | ΔVg |> | ΔVh |, the potential of the node SAOUT2 is eventually increased to the VDD potential by the sense amplifier 10, and as a result, the sense amplifier 11 is in the reverse rotation state. Then, the potential of the node NODE2 is set to the GND potential, and the data “1” read from the ferroelectric capacitor F4 of the memory cell 15 is latched.

  As described above, in the conventional ferroelectric memory shown in FIG. 7, the sense amplifiers from the time TLATCH to the time TOUT1 are caused by variations in the potentials of the output terminals OUT0, OUT0X, and OUT2 of the pre-sense amplifiers 2, 3, and 13. 10 and 11, there is a problem in that the operation is inconsistent and the latch is not settled. As a result, the output time is delayed and the latch result cannot be output to the outside until time TOUT2. If the variation is even larger, | ΔVg | <| ΔVh |, and there is a problem that the sense amplifier 11 can win and erroneous latching can occur.

  SUMMARY OF THE INVENTION In view of the above, the present invention has an object to provide a ferroelectric memory that prevents erroneous reading even when the ferroelectric capacitor constituting the storage medium or the inversion charge amount of the ferroelectric capacitor varies. To do.

  The ferroelectric memory of the present invention includes first and second memory cells, first, second, and third pre-sense amplifiers, first and second sense amplifiers, and a reference voltage generation circuit. Yes.

  The first memory cell has first and second ferroelectric capacitors in which complementary data is stored. The second memory cell has a third ferroelectric capacitor.

  The first pre-sense amplifier first detects data read from the first ferroelectric capacitor of the first memory cell. The second pre-sense amplifier first detects data read from the second ferroelectric capacitor of the first memory cell. The third pre-sense amplifier first detects data read from the third ferroelectric capacitor of the second memory cell.

  The first sense amplifier detects the data read from the third ferroelectric capacitor by amplifying the potential difference between the output voltage of the third pre-sense amplifier and the first reference voltage. The second sense amplifier connects the positive phase output terminal to the positive phase output terminal of the first sense amplifier, amplifies the potential difference between the output voltage of the third pre-sense amplifier and the second reference voltage, and outputs the third sense amplifier. Data read from the ferroelectric capacitor is detected.

  The reference voltage generation circuit receives the output voltages of the first and second pre-sense amplifiers, and has a variation range that can be taken when the output voltages of the first, second, and third pre-sense amplifiers are the expected logical value “1”. The first and second reference voltages take a voltage value between the first, second, and third pre-sense amplifiers that can be taken when the output voltage of the first sense amplifier is the expected logical value “0”. The second reference voltage is generated.

  According to the present invention, the voltage values of the first and second reference voltages are the variation range that can be taken when the output voltages of the first, second, and third pre-sense amplifiers are the expected logical value “1”, and the first and second reference voltages. , The output voltage of the second and third pre-sense amplifiers is a voltage value between a variation range that can be taken when the expected logical value is “0”, so that the first, second, and third ferroelectric capacitors Even if the inversion charge amounts of the first, second, and third ferroelectric capacitors vary, correct reading can be performed without causing erroneous reading.

  FIG. 1 is a circuit diagram of a part of an embodiment of the present invention. In one embodiment of the present invention, a reference voltage generation circuit 25 is provided after the pre-sense amplifiers 2 and 3, and the reference voltage REF shown in FIG. , The signal is supplied to the sense amplifiers such as the sense amplifiers 6 to 11 instead of REFX, and the others are configured in the same manner as the conventional ferroelectric memory shown in FIG.

  The reference voltage generation circuit 25 includes resistors R1, R2, and R3. One end of the resistor R1 is connected to the output terminal OUT0 of the pre-sense amplifier 2, and one end of the resistor R2 is connected to the output terminal OUT0X of the pre-sense amplifier 3. R3 is connected between the other ends of the resistors R1 and R2, a connection point between the resistors R1 and R3 is connected to the node 26 as an output end of the reference voltage REF, and a connection point of the resistors R2 and R3 is set as an output end of the reference voltage REFX. Connected to node 27.

  Therefore, when data “1” is written in the ferroelectric capacitor F1 and data “0” is written in the ferroelectric capacitor F2, when data is read from the ferroelectric capacitors F1 and F2, the output terminal of the pre-sense amplifier 2 is read. The potential of OUT0> the reference voltage REF> the reference voltage REFX> the potential of the output terminal OUT0X of the pre-sense amplifier 3.

  On the other hand, when data “0” is written in the ferroelectric capacitor F1 and data “1” is written in the ferroelectric capacitor F2, when the data is read from the ferroelectric capacitors F1 and F2, the pre-sense amplifier 3 is read. Potential of the output terminal OUT0X> reference voltage REFX> reference voltage REF> potential of the output terminal OUT0 of the pre-sense amplifier 2.

  Therefore, in one embodiment of the present invention, the voltage values of the reference voltages REF and REFX are the same as the potentials of the output terminals OUT0, OUT0X, OUT1 and OUT2 of the pre-sense amplifiers 2, 3, 12, and 13. Resistance value so that the voltage value is between the variation range in this case and the variation range when the potentials of the output terminals OUT0, OUT0X, OUT1, and OUT2 of the pre-sense amplifiers 2, 3, 12, and 13 are the expected logical value “0”. The resistance values of R1, R2, and R3 are determined.

  FIG. 2 is a waveform diagram for explaining the relationship between the potential variation ranges of the output terminals OUT0, OUT0X, OUT1, and OUT2 of the pre-sense amplifiers 2, 3, 12, and 13 and the reference voltages REF and REFX in the embodiment of the present invention. It is.

  In FIG. 2, the shaded portion 21 indicates the pre-sense amplifiers 2, 3, when the expected logical values of the output terminals OUT0, OUT0X, OUT1, OUT2 of the pre-sense amplifiers 2, 3, 12, 13 are “1” as described above. 12 shows a variation range of potentials of the output terminals OUT0, OUT0X, OUT1, and OUT2 of 12 and 13.

  Further, as described above, the hatched portion 22 indicates the pre-sense amplifiers 2, 3, 12, when the expected logical values of the output terminals OUT0, OUT0X, OUT1, OUT2 of the pre-sense amplifiers 2, 3, 12, 13 are “0”. 13 shows a variation range of potentials of the output terminals OUT0, OUT0X, OUT1, and OUT2.

  Further, the curve 26 shows the maximum value of the variation range when the potential at the output terminal OUT0 of the pre-sense amplifier 2 is the expected logical value “1” (the potential at the upper end of the shaded area 21), and the potential at the output terminal OUT0X of the pre-sense amplifier 3 In the case of the maximum value of the variation range in the case of the expected logical value “0” (the potential at the upper end of the hatched portion 22), the potential change that the reference voltage REF should take is indicated.

  That is, the maximum value of the variation range when the potential at the output terminal OUT0 of the pre-sense amplifier 2 is the expected logical value “1” (the potential at the upper end of the hatched portion 21), and the potential at the output terminal OUT0X of the pre-sense amplifier 3 is the expected logical value “ In the case of the maximum value of the variation range in the case of 0 ″ (the potential at the upper end of the shaded portion 22), the voltage value of the reference voltage REF is the expected logic value of the potentials at the output terminals OUT1 and OUT2 of the pre-sense amplifiers 12 and 13. It is set to be lower than the minimum value of the variation range in the case of “1” (the potential at the lower end of the hatched portion 21).

  The curve 27 shows the minimum value of the variation range of the potential OUT1 of the pre-sense amplifier 2 in the expected logical value “1” (the potential at the lower end of the shaded portion 21), and the potential of the output terminal OUT0X of the pre-sense amplifier 3 is the expected logic. In the case of the minimum value of the variation range in the case of the value “0” (the potential at the lower end of the shaded portion 22), the potential change that the reference voltage REFX should take is indicated.

  That is, the minimum value of the variation range when the potential of the output terminal OUT0 of the pre-sense amplifier 2 is the expected logical value “1” (the potential at the lower end of the hatched portion 21), and the potential of the output terminal OUT0X of the pre-sense amplifier 3 is the expected logical value “ In the case of the minimum value of the variation range in the case of 0 ″ (the potential at the lower end of the shaded portion 22), the voltage value of the reference voltage REFX is the expected logic value of the potentials at the output terminals OUT1 and OUT2 of the pre-sense amplifiers 12 and 13. It is set to be higher than the maximum value of the variation range in the case of “0” (the potential at the upper end of the hatched portion 22).

  Although not shown, the minimum value of the variation range when the potential at the output terminal OUT0 of the pre-sense amplifier 2 is the expected logical value “1” (the potential at the lower end of the hatched portion 21), the output terminal OUT0X of the pre-sense amplifier 3 When the potential is the minimum value of the variation range when the expected logical value is “0” (the potential at the lower end of the hatched portion 22), the voltage value of the reference voltage REF is lower than that of the curve 26. Although the voltage value of the reference voltage REFX is even lower, the maximum value of the variation range when the potentials of the output terminals OUT1 and OUT2 of the pre-sense amplifiers 12 and 13 are the expected logical value “0” (the upper end of the hatched portion 22) Higher potential).

  Although not shown, the maximum value of the variation range when the potential of the output terminal OUT0 of the pre-sense amplifier 2 is the expected logical value “1” (the potential at the upper end of the hatched portion 21), the output terminal OUT0X of the pre-sense amplifier 3 When the potential is the maximum value of the variation range when the potential is the expected logical value “0” (the potential at the upper end of the shaded portion 22), the voltage value of the reference voltage REFX is higher than the curve 27. Although the voltage value of the reference voltage REF is higher, in this case as well, the minimum value of the variation range when the potentials of the output terminals OUT1 and OUT2 of the pre-sense amplifiers 12 and 13 are the expected logic value “1” (the lower end of the hatched portion 21) The potential is lower than the first potential.

  FIG. 3 shows a case where data “1” is written in the ferroelectric capacitor F1, data “0” is written in the ferroelectric capacitor F2, and data “0” is written in the ferroelectric capacitor F3 in the embodiment of the present invention. 10 is a waveform diagram for explaining the twin sense operation of the sense amplifiers 8 and 9 when the variation in potential of the nodes OUT0, OUT0X and OUT1 with respect to the sense amplifiers 8 and 9 is worst. FIG.

  In this example, after time TWLPL and before time TLATCH, the potential of the output terminal OUT0 of the pre-sense amplifier 2 is relatively high, the potential of the output terminal OUT0X of the pre-sense amplifier 3 is relatively low, The output terminal OUT1 has a relatively low potential.

  In this case, the worst variation occurs when the potential at the output terminal OUT1 of the pre-sense amplifier 12 is the maximum value of the variation range when the potential of the expected logical value is “0” (the potential at the upper end of the hatched portion 22). The minimum value of the variation range when the potential is the expected logical value “1” (the potential at the lower end of the shaded portion 21), and the minimum value of the variation range when the potential of the output terminal OUT0X of the pre-sense amplifier 3 is the expected logical value “0” (Potential at the lower end of the shaded portion 22).

  Here, in the sense amplifier 9, until the time TLATCH, the potential at the node SAOUT1 = the potential at the output terminal OUT1 of the pre-sense amplifier 12, and the node NODE1 = the reference voltage REF. Therefore, between the nodes SAOUT1 and NODE1, the node SAOUT1 The potential is low, and the potential of the node NODE1 is high.

  That is, the potential of the output terminal OUT0 of the pre-sense amplifier 2 is the minimum value of the variation range when the expected logical value is “1”, and further, the reference voltage REF is output from the output terminal OUT0 of the pre-sense amplifier 2 by the reference voltage generation circuit 25. The reference voltage REF is set to be higher than the maximum value of the variation range when the potential of the output terminal OUT1 of the pre-sense amplifier 12 is the expected logical value “0”. Therefore, (potential of node NODE1−potential of node SAOUT1) = ΔVj is positive.

  As described above, between the nodes NODE1 and SAOUT1, the potential in the direction in which the potential of the node NODE1 = VDD potential and the potential of the node SAOUT1 = GND potential (data “0 read from the ferroelectric capacitor F3 of the memory cell 14). "Potential in the direction of latching".

  Therefore, when the latch activation signal SAPOWER rises to the VDD potential at time TLATCH, the sense amplifier 9 amplifies the potential difference ΔVj between the nodes NODE1 and SAOUT1, and sets the potential of the node NODE1 = VDD potential and the potential of the node SAOUT1 = GND potential, The data “0” read from the ferroelectric capacitor F3 of the memory cell 14 is correctly latched.

  On the other hand, in the sense amplifier 8, until the time TLATCH, the potential of the node SAOUT1X = the reference voltage REFX and the potential of the node SAOUT1 = the potential of the output terminal OUT1 of the pre-sense amplifier 12, so that the nodes SAOUT1X and SAOUT1 are both at a low potential. Become.

  Here, even if the potential of the output terminal OUT0X of the pre-sense amplifier 3 is the minimum value of the variation range when the expected logical value is “0”, the reference voltage REFX is output from the pre-sense amplifier 3 by the reference voltage generation circuit 25. The potential of the output terminal OUT1 of the pre-sense amplifier 12 is raised from the potential of the terminal OUT0X, and is higher than the maximum value of the variation range when the expected logical value is “0”.

  As a result, (potential of node SAOUT1X−potential of node SAOUT1) = ΔVi is slightly positive. Therefore, when the latch activation signal SAPOWER rises to the VDD potential at time TLATCH, the sense amplifier 8 slowly tries to set the potential of the node SAOUT1 = GND potential and the potential of the node SAOUT1X = VDD potential.

  Here, since the node SAOUT1 is commonly connected by the sense amplifiers 8 and 9, the potential of the node SAOUT1 eventually falls and becomes the GND potential by the sense amplifier 9, so that the sense amplifier 8 also has the potential of the node SAOUT1X = VDD potential. To.

  Thus, the node for the sense amplifiers 8 and 9 when data “1” is written in the ferroelectric capacitor F1, data “0” is written in the ferroelectric capacitor F2, and data “0” is written in the ferroelectric capacitor F3. Even when the variation in potential of OUT0, OUT0X, and OUT1 is worst, (potential of node SAOUT1X−potential of node SAOUT1) = ΔVi> 0, (potential of node NODE1−potential of node SAOUT1 = ΔVj> 0, At time TOUT1, latching of the data “0” read from the ferroelectric capacitor F3 has been completed, and the result can be output to the outside, and there is no possibility of erroneous latching.

  FIG. 4 shows a case where data “1” is written in the ferroelectric capacitor F1, data “0” is written in the ferroelectric capacitor F2, and data “1” is written in the ferroelectric capacitor F4 in the embodiment of the present invention. 6 is a waveform diagram for explaining the twin sense operation of the sense amplifiers 10 and 11 when the variation in potential of the nodes OUT0, OUT0X and OUT2 with respect to the sense amplifiers 10 and 11 is worst.

  In this example, after time TWLPL and before time TLATCH, the potential of the output terminal OUT0 of the pre-sense amplifier 2 is relatively high, the potential of the output terminal OUT0X of the pre-sense amplifier 3 is relatively low, The output terminal OUT2 has a relatively high potential.

  In this case, the worst variation occurs when the potential at the output terminal OUT2 of the pre-sense amplifier 13 is the minimum value (potential at the lower end of the shaded portion 21) when the potential is the expected logic value “1”. The maximum value of the variation range when the potential is the expected logical value “1” (the potential at the upper end of the shaded portion 21), and the maximum value of the variation range when the potential of the output terminal OUT0X of the pre-sense amplifier 3 is the expected logical value “0” (Potential at the upper end of the hatched portion 22).

  Here, in the sense amplifier 10, since the potential at the node SAOUT2 = the potential at the output terminal OUT2 of the pre-sense amplifier 13 and the potential at the node SAOUT2X = the reference voltage REFX until just before the time TLATCH, between the nodes SAOUT2 and SAOUT2X, The potential of SAOUT2 is high, and the potential of node SAOUT2X is low.

  That is, the potential of the output terminal OUT0X of the pre-sense amplifier 3 is the maximum value of the variation range when the expected logical value is “0”, and the reference voltage REFX is output from the pre-sense amplifier 3 by the reference voltage generation circuit 25. Although the potential at the terminal OUT0X is raised, the potential at the output terminal OUT2 of the pre-sense amplifier 13 is set lower than the minimum value of the variation range when the expected logical value is “1”. The potential of the node SAOUT2−the potential of the node SAOUT2X) = ΔVk is positive.

  As described above, between the nodes SAOUT2 and SAOUT2X, the potential in the direction in which the potential of the node SAOUT2 = VDD potential and the potential of the node SAOUT2X = GND potential (data “1 read from the ferroelectric capacitor F4 of the memory cell 15). "Potential in the direction of latching".

  Therefore, when the latch activation signal SAPOWER rises to the VDD potential at time TLATCH, the sense amplifier 10 amplifies the potential difference ΔVk between the nodes SAOUT2 and SAOUT2X, and the potential of the node SAOUT2 = VDD potential, the potential of the node SAOUT2X = GND potential, The data “1” read from the ferroelectric capacitor F4 of the memory cell 15 is to be latched correctly.

  On the other hand, in the sense amplifier 11, until the time TLATCH, the potential of the node SAOUT2 = the potential of the output terminal OUT2 of the pre-sense amplifier 13 and the potential of the node NODE2 = the potential of the reference voltage REF, so both the nodes SAOUT2 and NODE2 are high. It becomes a potential.

  Here, even if the potential of the output terminal OUT0 of the pre-sense amplifier 2 is the maximum value of the variation range when the expected logical value is “1”, the reference voltage REF is output from the pre-sense amplifier 2 by the reference voltage generation circuit 25. The potential of the output terminal OUT2 of the pre-sense amplifier 13 is lower than the minimum value of the variation range when the potential of the output terminal OUT2 of the pre-sense amplifier 13 is the expected logical value “1”.

  As a result, (potential of node SAOUT2−potential of node NODE2) = ΔVm is slightly positive. Therefore, when the latch activation signal rises to the VDD potential at time TLATCH, the sense amplifier 11 slowly tries to set the potential of the node SAOUT2 = VDD potential and the potential of the node NODE2 = GND potential.

  Here, since the node SAOUT2 is commonly connected by the sense amplifiers 10 and 11, the potential of the node SAOUT2 eventually rises to the VDD potential by the sense amplifier 10, so that the sense amplifier 11 also has the potential of the node NODE2 = GND potential. To do.

  Thus, the node for the sense amplifiers 10 and 11 when data “1” is written in the ferroelectric capacitor F1, data “0” is written in the ferroelectric capacitor F2, and data “1” is written in the ferroelectric capacitor F4. Even when the variation in potential of OUT0, OUTX, and OUT2 is worst, (potential of node SAOUT2−potential of node SAOUT2X) = ΔVk> 0, (potential of node SAOUT2−potential of node NODE2 = ΔVm> 0, At time TOUT1, the latching of the data “1” read from the ferroelectric capacitor F4 has been completed, the result can be output to the outside, and there is no possibility of erroneous latching.

  The node OUT0 for the sense amplifiers 8 and 9 when the data “1” is written in the ferroelectric capacitor F1, the data “0” is written in the ferroelectric capacitor F2, and the data “1” is written in the ferroelectric capacitor F3. When the variation in the potentials of OUT0X and OUT1 is worst, (potential of node SAOUT1−potential of node SAOUT1X)> 0 and (potential of node SAOUT1−potential of node NODE1)> 0, so at time TOUT1. The latching of the data “1” read from the ferroelectric capacitor F3 of the memory cell 14 by the sense amplifiers 8 and 9 has been completed, the result can be output to the outside, and there is no possibility of erroneous latching.

  The node OUT0 for the sense amplifiers 10 and 11 when data “1” is written in the ferroelectric capacitor F1, data “0” is written in the ferroelectric capacitor F2, and data “0” is written in the ferroelectric capacitor F4, When the variation in the potentials of OUT0X and OUT2 is the worst, (potential of node SAOUT2X−potential of node SAOUT2)> 0 and (potential of node NODE2−potential of node SAOUT2)> 0, so at time TOUT1. The sense amplifiers 10 and 11 have finished latching the data “0” read from the ferroelectric capacitor F4 of the memory cell 15, so that the result can be output to the outside and there is no possibility of erroneous latching.

  As described above, according to the embodiment of the present invention, the reference voltage generation circuit 25 changes the voltage values of the reference voltages REF and REFX to the output terminals OUT0, OUT0X, OUT1, and the like of the pre-sense amplifiers 2, 3, 12, and 13, respectively. The variation range when the potential of OUT2 is the expected logical value “1” and the variation range when the potentials of the output terminals OUT0, OUT0X, OUT1, and OUT2 of the pre-sense amplifiers 2, 3, 12, and 13 are the expected logical value “0” Therefore, even if the inversion charge amount of the ferroelectric capacitors F1, F2, F3, and F4 and the ferroelectric capacitors F1, F2, F3, and F4 varies, erroneous reading does not occur. The effect that can be obtained.

FIG. 3 is a circuit diagram of a part of an embodiment of the present invention. It is a wave form diagram for demonstrating the relationship between the variation range of the electric potential of the output terminal of the pre-sense amplifier in one Embodiment of this invention, and a reference voltage. FIG. 6 is a waveform diagram for explaining a twin sense operation of the sense amplifier when the variation in potential at a predetermined node is worst in an embodiment of the present invention. FIG. 6 is a waveform diagram for explaining a twin sense operation of the sense amplifier when the variation in potential at a predetermined node is worst in an embodiment of the present invention. It is a circuit diagram of a part of an example of a conventional ferroelectric memory. FIG. 6 is a waveform diagram showing an operation example at the time of data reading of the conventional ferroelectric memory shown in FIG. 5. It is a circuit diagram of a part of another example of a conventional ferroelectric memory. FIG. 8 is a waveform diagram showing an operation example at the time of data reading of the conventional ferroelectric memory shown in FIG. 7. FIG. 8 is a waveform diagram for explaining a twin sense operation of a sense amplifier included in the conventional ferroelectric memory shown in FIG. 7. FIG. 8 is a waveform diagram for explaining a twin sense operation of a sense amplifier included in the conventional ferroelectric memory shown in FIG. 7. FIG. 8 is a waveform diagram showing a variation range of the potential at the output terminal of the pre-sense amplifier in the conventional ferroelectric memory shown in FIG. 7. FIG. 8 is a waveform diagram for explaining a twin sense operation of the sense amplifier when the variation in potential at a predetermined node in the ferroelectric memory shown in FIG. 7 is worst. FIG. 8 is a waveform diagram for explaining a twin sense operation of the sense amplifier when the variation in potential at a predetermined node in the ferroelectric memory shown in FIG. 7 is worst.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... 2 transistor / 2 capacitor type memory cell 2, 3 ... Pre-sense amplifier 4 ... Threshold generation circuit 5 ... Negative voltage generation circuit 6-11 ... Sense amplifier 12, 13 ... Pre-sense amplifier 14, 15 ... 1 transistor / 1 capacitor type Memory cell 25 ... reference voltage generation circuit WL ... word line PL ... plate line BL, BLX, BL0, BL0X, BL1, BL2 ... bit lines P1-P7 ... PMOS transistors N1-N7, N12, N13 ... NMOS transistors F1, F2 F3, F4, ferroelectric capacitors S1 to S6, switches C1 to C4, capacitors IB1 to IB3, inverters TG1, TG2, transfer gates

Claims (2)

A first memory cell having first and second ferroelectric capacitors in which complementary data is stored;
A second memory cell having a third ferroelectric capacitor;
A first pre-sense amplifier for pre-detecting data read from the first ferroelectric capacitor;
A second pre-sense amplifier that pre-detects data read from the second ferroelectric capacitor;
A third pre-sense amplifier that first detects data read from the third ferroelectric capacitor;
A first sense amplifier for amplifying a potential difference between an output voltage of the third pre-sense amplifier and a first reference voltage to detect data read from the third ferroelectric capacitor;
A positive phase output terminal is connected to a positive phase output terminal of the first sense amplifier, and a potential difference between an output voltage of the third pre-sense amplifier and a second reference voltage is amplified, and the third ferroelectric capacitor is amplified. A second sense amplifier for detecting data read from
When the output voltages of the first and second pre-sense amplifiers are input, and the output voltage of the first, second and third pre-sense amplifiers is an expected logical value “1”, The first and second reference voltages take a voltage value between a variation range that can be taken when the output voltage of the second and third pre-sense amplifiers is an expected logical value “0”. A ferroelectric memory comprising a reference voltage generation circuit for generating two reference voltages. The reference voltage generation circuit includes:
A first resistor having one end connected to the output end of the first pre-sense amplifier;
A second resistor having one end connected to the output end of the second pre-sense amplifier;
A third resistor connected between the other end of the first resistor and the other end of the second resistor;
The connection point of the second and third resistors is the output terminal of the first reference voltage,
The ferroelectric memory according to claim 1, wherein a connection point of the first and third resistors is used as an output terminal of the second reference voltage.

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