JP4807191B2 - Ferroelectric memory device and electronic device - Google Patents

Description

  The present invention relates to a ferroelectric memory device, and more particularly to a sense amplifier circuit, an equalize circuit, a positive potential conversion circuit, and the like related to reading of a ferroelectric memory device.

  For reading from a ferroelectric memory device (FeRAM: Ferroelectric Random Access Memory), a method using a latch-type sense amplifier circuit is generally used (for example, see Patent Document 1 below).

  However, in this case, the voltage applied to the plate line is divided into the ferroelectric capacitor capacitance (Cs) and the bit line capacitance (Cbl). Accordingly, a sufficient potential is not applied to the ferroelectric capacitor due to the bit line capacitance (Cbl). In addition, since the difference between the bit line voltages is amplified and read by the sense amplifier, the bit line voltage decreases and the sense margin decreases as the bit line capacitance (Cbl) increases.

Therefore, a read circuit that can virtually fix the bit line to the ground potential has been studied (see, for example, Patent Document 2 and Non-Patent Document 1 below).
JP 2000-187990 A (US6233170 (B1)) JP 2002-133857 A (US 6487103 (B2)) IEEE JOURNAL OF SOLID STATE CIRCUITS VOL.37.No.5, MAY 2003 "Bitline GND SensingTechnique for Low-Voltage Operation FeRAM"

  (1) However, even when the circuit described in the above-mentioned Patent Document 2 is used, as will be described in detail later, (a) fine fitting of each element constituting the circuit is required according to the ferroelectric characteristics. There are some problems such as (b) the timing at which the sense margin becomes maximum may fluctuate, (c) a through current flows in the inverter during a read operation, and (d) a large area.

  (2) In the circuit described in Patent Document 2, the read operation is performed by transferring the charge read from the memory cell to a capacitor charged to a negative potential. Therefore, a negative potential node [for example, VMN or VTH in FIG. 3] is generated. However, since these nodes are in a floating state during standby, the initial potential becomes unstable. When the initial potential changes, the output potential at the time of reading also changes, and the sense margin decreases.

  (3) Further, in the circuit described in Patent Document 2, reading is performed by amplifying a potential difference between the node VMN when the charge read from the memory cell is “0” data and the node VMN when the charge is “1” data. To do. However, in order to amplify the potential difference with the sense amplifier, it is necessary to amplify after converting the negative potential to the positive potential. For this reason, in the circuit described in Patent Document 2, after the negative potential is converted into the positive potential by using the voltage shift circuit [7], reading is performed by the sense amplifier [5]. However, the voltage shift circuit [7] described in Patent Document 2 has a problem that the conversion loss is large and the potential difference of the node VMN becomes small after the conversion. [] Parentheses are the codes in the literature.

  Therefore, an object of the present invention is to provide a ferroelectric memory device that can solve the above-described problems. More specifically, an object of the present invention is to provide various circuits (for example, a sense amplifier circuit, an equalize circuit, or a positive potential conversion circuit) necessary for reading data of a ferroelectric memory device that can solve the above-described problems. To do.

(1) A ferroelectric memory device of the present invention is connected between a first node and a second node connected to a second bit line connected to the first bit line, the ground potential the base plate potential And a first negative voltage generating circuit having a ferroelectric capacitor connected between a control signal line and a gate terminal of the first p-channel type MISFET .

According to such a configuration, the first and second nodes can be set to the same potential (can be equalized). Therefore, the reading accuracy of the ferroelectric memory device can be improved. Even when the first and second nodes have negative potentials, if the substrate potential is set higher than the potentials of these nodes (for example, the ground potential), the first and second substrate potentials only rise, It is possible to prevent the potential of the node from rising from the above potential. That is, the potential of the first and second nodes is not adversely affected by the equalization path. Further, according to such a configuration, a negative potential can be easily generated by a large-capacity capacitor even in a small area.

  For example, the ferroelectric memory device is further connected between the first node and a ground potential, its gate terminal is connected to the first negative potential generating circuit, and its substrate potential is the ground potential. A 2p channel type MISFET, a third p channel type MISFET connected between the second node and the ground potential, a gate terminal thereof connected to the first negative potential generation circuit, and a substrate potential thereof being a ground potential; Have According to this configuration, the first and second nodes can be equalized to the ground potential.

  For example, a clamp circuit is connected to the output of the first negative potential generating circuit. According to such a configuration, the potential of the output node can be fixed within a certain range.

  For example, the clamp circuit is a resistor connected between the output and a ground potential. According to such a configuration, a clamp circuit having a relatively simple configuration can be obtained.

  For example, the ferroelectric memory device further includes a fourth p-channel type MISFET connected between the first node and the first bit line, and between the second node and the second bit line. A fifth p-channel MISFET connected; a second negative potential generating circuit connected to the first node; and a third negative potential generating circuit connected to the second node. According to this configuration, a negative potential can be transferred to the bit line via the fourth and fifth p-channel type MISFETs, so that an increase in the potential of the bit line during reading can be suppressed. Therefore, the voltage applied to the ferroelectric capacitor constituting the memory cell can be increased. The read characteristics of the ferroelectric memory device can be improved.

  For example, a ferroelectric memory is connected to each of the first bit line and the second bit line. With this configuration, the present invention can be applied to so-called 2T2C ferroelectric memory cells.

  For example, a ferroelectric memory is connected to the first bit line, and a reference potential is applied to the second bit line. With this configuration, the present invention can be applied to so-called 1T1C ferroelectric memory cells.

  (2) An electronic apparatus of the present invention has the above ferroelectric memory device. The electronic device generally refers to a device having a certain function provided with the ferroelectric memory device according to the present invention, and its configuration is not particularly limited. For example, a computer device generally including the ferroelectric memory device is generally described. Any device that requires a storage device, such as a mobile phone, PHS, PDA, electronic notebook, and IC card, is included.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same or related code | symbol is attached | subjected to what has the same function, and the repeated description is abbreviate | omitted.

  FIG. 1 is a block diagram showing a configuration of a ferroelectric memory device. As shown in the figure, the ferroelectric memory device 100 includes a memory cell array 110 and peripheral circuit units (120, 130, 140, etc.). The memory cell array 110 is composed of a plurality of memory cells arranged in an array, and each memory cell is arranged at the intersection of the word line WL and the bit lines BL-L and BL-R. Here, a 2T2C cell will be described as an example. Therefore, one data is stored by two transistors and two ferroelectric capacitors respectively connected to the bit lines BL-L and BL-R. Further, the word line control unit 120 and the plate line control unit 130 configuring the peripheral circuit control voltages of the plurality of word lines WL and the plurality of plate lines PL. By these controls, data stored in the memory cell MC is read to the plurality of bit lines BL, and data supplied from the outside is written to the memory cell MC via the bit line BL. Such reading and writing are performed by the bit line control unit 140.

Hereinafter, embodiments of the present invention will be described in the order of a sense amplifier circuit, an equalize circuit, and a positive potential conversion circuit.
1) Sense amplifier circuit (first sense amplifier circuit)
FIG. 2 is a circuit diagram showing a configuration of a first sense amplifier circuit according to an embodiment of the present invention. As shown in the figure, the bit lines BL-L and BL-R are connected to the first node ML-L and the second node ML-R via p-channel type MISFETs P1-L and P1-R, respectively. On the other hand, the gate terminal of the p-channel type MISFET P1-L is connected to the second node ML-R, and the gate terminal of the p-channel type MISFET P1-R is connected to the first node ML-L. Thus, one end of the two p-channel type MISFETs P1-L and P1-R and the gate terminal are cross-connected. The substrate potential (back gate potential) of the p-channel type MISFETs P1-L and P1-R is set to the ground potential. More preferably, it has the same potential as the terminal (first end) on the bit line side. This is because the higher the substrate potential, the easier it is to turn on. In the present specification, the source and drain regions of the MISFET may be referred to as the first end, the second end or one end, and the other end of the MISFET.

  A negative potential generating circuit MG is connected to the first node ML-L and the second node. The negative potential generating circuit MG includes a ferroelectric capacitor Ct-L connected to the first node ML-L and a ferroelectric capacitor Ct-R connected to the second node ML-R. Are commonly connected to the MGEN signal line. Hereinafter, a signal and a signal line may be denoted by the same reference numeral.

  A sense amplifier SA is composed of two p-channel MISFETs P1-L and P1-R cross-connected to the negative potential generating circuit MG (see FIG. 5).

  A charge transfer circuit (charge supply circuit) CT is connected between the first node ML-L and the second node ML-R. The circuit includes p-channel MISFETs P2-L and P2-R connected in series between the first node ML-L and the second node ML-R. The connection node of the p-channel type MISFETs P2-L and P2-R is connected to the ground potential (ground, GND), and the gate terminal of the p-channel type MISFET P2-L is connected to the second node ML-R, and the p-channel type The gate terminal of the MISFET P2-R is connected to the first node ML-L. The substrate potential (back gate potential) of the p-channel type MISFETs P2-L and P2-R is set to the ground potential. More preferably, it is set to the same potential as the terminal (first end) on the bit line side of the p-channel type MISFETs P1-L and P1-R. This is because the higher the substrate potential, the easier it is to turn on.

  A circuit for discharging each bit line to the ground potential is connected to the bit lines BL-L and BL-R. This circuit is connected between the n-channel MISFET N1-L connected between the bit line BL-L and the ground potential (first potential), and between the bit line BL-R and the ground potential (first potential). N-channel type MISFET N1-R. These gate terminals are connected to the BLGND line.

  Further, switching transistors (N2-L, N2-R) are connected between the bit lines BL-L, BL-R and the sense amplifier circuit SA. That is, the switching transistor N2-L is connected between the bit line BL-L and the p-channel type MISFET P1-L, and the switching transistor N2-R is connected between the bit line BL-R and the p-channel type MISFET P1-R. Is connected. The gate terminals of these switching transistors are connected to the BLSW line. These switching transistors are n-channel MISFETs.

  Further, an equalize circuit EQ1 is connected between the first node ML-L and the second node ML-R. The equalize circuit EQ1 is a circuit that sets the potentials of the first node ML-L and the second node ML-R, which are negative potential nodes, to the same potential (for example, ground potential). The equalize circuit EQ1 is connected to the MEQ line and controlled by the MEQ signal. The detailed description of the equalizing circuit will be described in detail in the column “2) Equalizing circuit”.

  A positive potential conversion circuit TP is connected to the first node ML-L and the second node ML-R. The input part of the positive potential conversion circuit TP is connected to the first and second nodes ML-L and ML-R, respectively, and outputs an output corresponding to the potential difference between the first and second nodes from the output part OUT. For example, a positive potential output corresponding to the potential difference between the first and second nodes, which are negative potential nodes, is output from the output units OUT-R and OUT-L (see FIGS. 4 and 14). The positive potential conversion circuit TP is connected to the MTP line and controlled by the MTP signal. A detailed description of this positive potential conversion circuit will be described in detail in the section “3) Positive Potential Conversion Circuit”.

  FIG. 3 is a timing chart at the time of reading from the ferroelectric memory device. As shown in the figure, the BLSW line is set to the H level, and the sense amplifier circuit SA and the bit lines BL-L and BL-R are connected (FIG. 3D). Next, the word line WL is set to the H level (FIG. 3A). Next, the BLGND line is set to the L level, and the bit lines BL-L and BL-R that have been discharged to the ground potential are brought into a floating state (FIG. 3C). Next, the MEQ line is set to L level, and the equalizing circuit is turned off (FIG. 3F).

  Next, the plate line PL is set to the H level (FIG. 3B), and charges are transferred from the memory cells to the bit lines BL-L and BL-R. Next, the MGEN line (first line) is changed from the H level to the L level, and the negative potential generating circuit MG is operated (FIG. 3E).

  FIG. 4 shows the simulation results of the potentials of the bit lines BL-L, BL-R and the first and second nodes ML-L, MLR and the like at the time of reading. As shown in FIG. 4A, the potentials of the bit lines BL-L and BL-R gradually rise due to charge transfer from the memory cell (ferroelectric capacitor). At this time, the potential of the bit line on the “1” data side (BL-L in FIG. 4) rises faster. On the other hand, due to the change of the MGEN line to the L level, the potentials of the first and second nodes ML-L and ML-R suddenly drop, and the threshold value Vth (here, -0.8 V) of the p-channel type MISFET is below. Negative potential. As a result, the p-channel MISFETs P1-L and P1-R are turned on. Thereafter, the potentials of the first and second nodes ML-L and ML-R rise due to charge transfer from the bit line. At this time, the potential of the node (ML-L in FIG. 4) connected to the bit line on the “1” data side (BL-L in FIG. 4) rises earlier. Therefore, when the potential of the node (ML-L) becomes equal to or higher than the threshold value Vth, the p-channel MISFET P1-R is turned off and the increase in the potential of the other node (ML-R) is stopped. Therefore, the read data is determined at this point.

  Next, as shown in FIG. 4B, the MTP line is changed from L level to H level, and the positive potential conversion circuit TP is turned on. As a result, as shown in FIG. 4C, the potential difference between the first and second nodes ML-L and ML-R can be extracted as output data OUT-L and OUT-R. In FIG. 4, the output data OUT-L is “1”, and OUT-R is “0”.

  Thus, according to the first sense amplifier circuit, the gate terminals of the p-channel type MISFETs P1-L, P1-R connected to the negative potential nodes (ML-L, ML-R) are cross-connected. Of these, the rise in potential from the node on the “1” data side can be used to turn off the p-channel MISFET connected to the node on the “0” data side (see FIG. 5). Therefore, the potential difference of the negative potential node at this time or thereafter can be taken out as output data. FIG. 5 is a circuit diagram showing a configuration of a main part of the first sense amplifier circuit. The same parts as those in FIG. 2 are denoted by the same reference numerals.

  In particular, according to the configuration of the first sense amplifier circuit and its driving method (data reading method), there are the following advantages (1) to (5).

  (1) For example, the potential applied to the ferroelectric capacitor is increased because the potentials of the bit lines BL-L and BL-R are lowered to near the ground potential as compared with the circuit described in Patent Document 1 described above. Can do. Therefore, it is possible to read more charges stored in the ferroelectric capacitor. In addition, the reading speed can be improved.

  (2) Since the influence of the bit line capacity can be reduced, the capacity of the memory can be increased. In other words, the read accuracy can be maintained even when the number of memories increases and the bit line becomes longer.

  (3) Since one of the potentials of the first and second nodes (ML-L, ML-R) is fixed above the threshold value Vth and the other is below the threshold value Vth, a subsequent circuit (for example, , Positive potential conversion circuit) can be easily designed.

  (4) Moreover, compared with the circuit shown in FIG. 6, since the inverter is not used, the through current can be reduced. Further, the number of elements constituting the circuit is reduced, and according to the study of the present inventors, the layout area can be reduced to about 30%. In addition, the first sense amplifier circuit facilitates circuit fitting. For example, in the circuit of FIG. 6, it is necessary to finely set the characteristics (for example, threshold value and capacitance) of each constituent element, which makes it difficult to form. On the other hand, the first sense amplifier circuit requires less setting. FIG. 6 is a comparison circuit for explaining the effect of the first sense amplifier circuit. FBA and FBB are feedback circuits, PTA and PTB are p-channel MISFETs, C1A and C1B are capacitors, NA and NB are nodes, C2A and C2B are capacitors, and GSA is a general sense amplifier circuit. .

(5) Further, the charge transfer circuit CT promotes the rise of the potentials of the first and second nodes ML-L and ML-R, and the time until one of the nodes exceeds the threshold value Vth is shortened. Therefore, the reading speed can be improved. In addition, since the initial potentials of the first and second nodes ML-L and ML-R are fixed by the equalizer circuit EQ1, the read operation can be stabilized. In particular, it is possible to reduce a phenomenon in which the potentials of the first and second nodes ML-L and ML-R are only lowered to a potential that is higher than the threshold value Vth. Further, the positive potential conversion circuit TP can efficiently extract the potential difference between the first and second nodes, which are negative potential nodes, as positive potential outputs OUT-L and OUT-R.
(Second sense amplifier circuit)
FIG. 7 is a circuit diagram showing a configuration of a second sense amplifier circuit according to an embodiment of the present invention. The difference from the first sense amplifier circuit is that a potential transfer circuit composed of a ferroelectric capacitor Ct2-L is connected between the gate terminal (node PG-R) of the p-channel type MISFET P2-R and the first node ML-L. In addition, a potential transfer circuit including a ferroelectric capacitor Ct2-R is connected between the gate terminal (node PG-L) of the p-channel type MISFET P2-L and the second node ML-R. Further, an equalize circuit EQ2 is connected between the gate terminals (node PG-L) of the p-channel type MISFETs P1-L and P2-L and the gate terminals (node PG-R) of the p-channel type MISFETs P1-R and P2-R. It is in the point. This equalize circuit EQ2 is also connected to the MEQ line and controlled by the MEQ signal.

  According to such a configuration, a change in potential of the first or second node can be immediately transferred to the gate terminal of the p-channel MISFET, and the node on the “0” data side (ML-R in FIG. 8) can be transferred. The connected p-channel type MISFET (P2-R) can be quickly turned off, and the rise in potential of the node (ML-R) on the “0” data side can be stopped earlier.

  The timing chart at the time of reading of the second sense amplifier circuit is the same as that in FIG. FIG. 8 shows a simulation result of potentials of the nodes PG-L, PG-R, etc. at the time of reading. Changes in the potentials of the bit lines BL-L and BL-R and the first and second nodes ML-L and ML-R are the same as those in FIG. As shown in FIG. 8 (A), the potentials of the first and second nodes ML-L and ML-R rapidly drop due to the change of the MGEN line to the L level, and then the p-channel type MISFETs P2-L and P2 Since -R is turned on, charges are injected from the ground potential to the first and second nodes ML-L and ML-R via these MISFETs. Therefore, the potential increase of these nodes is promoted. Here, the potential of the node PG-R on the “0” data side rises earlier than the first node ML-L. As a result, as described above, the p-channel MISFET connected to the bit line on the “0” data side (BL-R in FIG. 8) is quickly turned off, and the node on the “0” data side (ML-R) The increase in potential can be stopped more quickly. As described above, the second sense amplifier circuit has the above-described effects in addition to the effects of the first sense amplifier circuit.

  Here, since the nodes PG-L and PG-R also have negative potentials, the read operation can be stabilized by providing an equalize circuit EQ2 between these nodes and fixing the initial potential. As the equalize circuit EQ2, a first, second or third equalize circuit which will be described later can be used.

  In the first and second sense amplifier circuits, a ferroelectric capacitor is used as the negative potential generating circuit, but a paraelectric capacitor, a gate capacitor, or the like may be used. Further, a negative potential may be applied to the first and second nodes ML-L and ML-R by completely different circuit systems.

  In the second sense amplifier circuit, the ferroelectric capacitor is used as the potential transfer circuit, but a paraelectric capacitor, a gate capacitor, or the like may be used.

The sense amplifier circuit of the present invention is applicable not only to a 2T2C ferroelectric memory but also to a 1T1C ferroelectric memory in which a reference potential is applied to one bit line.
2) Equalize Circuit Next, the configuration of the equalize circuit used in the first and second sense amplifier circuits will be described in detail.
(First equalize circuit)
FIG. 9 is a circuit diagram showing a configuration of a first equalize circuit according to an embodiment of the present invention. As shown in the figure, a p-channel MISFET P4 is connected between the first and second nodes ML-L and ML-R. A p-channel type MISFET P3-L is connected between the first node ML-L and the ground potential, and a p-channel type MISFET P3-R is connected between the second node ML-R and the ground potential. Has been. The gate terminals of these p-channel type MISFETs are connected to one end of a ferroelectric capacitor C1 (negative potential generation circuit), and the substrate potential is the ground potential. The negative potential generating circuit includes a ferroelectric capacitor C1 connected between the MEQ line and the node vrst. A safety device (clamp circuit) S is connected to the node vrst. The safety device S controls the potential of the node vrst in the floating state to be in a predetermined potential range when the first equalizing circuit is on standby. A bit line is connected to the first node ML-L and the second node ML-R through the above-described sense amplifier circuit SA and the like.

  FIG. 10 shows a timing chart during operation of the first equalize circuit. As shown in FIG. 10A, the MEQ line changes from the H level to the L level, and the equalizing operation starts. Therefore, as shown in FIG. 10C, the first node ML-L and the second node ML-R, which have been different potentials so far, are equalized to the ground potential. Thereafter, when the MEQ line becomes H level, the first equalize circuit is turned off. Further, when the MGENb line changes from the H level to the L level, the potentials of the first and second nodes ML-L and ML-R rapidly decrease, and thereafter increase due to the increase in the bit line potential. . These changes are as described in the section “1) Sense amplifier circuit” with reference to FIG. MGENb indicates an inverted signal (signal line) of MGEN. In the drawing, the potential change of the node vrst is also shown.

  As described above, since the equalize circuit uses the p-channel type MISFET, even if the first and second nodes ML-L and ML-R become negative potential nodes, these nodes have the same potential. Can do. For example, when an n-channel MISFET is used, the potential of the first and second nodes increases because the potential of the source and drain regions increases due to the PN junction current. Further, since the substrate potential of the p-channel MISFET is set to the ground potential, the equalizing circuit can be turned off only by setting the gate potential to the ground potential.

  Thus, in the equalizing circuit, the negative potential node can be equalized with a simple configuration.

Note that the equalize circuit may be configured with only the p-channel type MISFET P4. However, each node can be equalized to the ground potential by using the p-channel type MISFETs P3-L and P3-R. Therefore, it is possible to stabilize the subsequent circuit operation, for example, the sense amplifier circuit operation.
(Second equalize circuit)
FIG. 11 is a circuit diagram showing a configuration of a second equalize circuit according to an embodiment of the present invention. The difference from the first equalize circuit is that the p-channel type MISFET P4 is omitted. Also in this case, the first and second nodes ML-L and ML-R can be equalized to the ground potential. The timing chart during the operation of the second equalize circuit is the same as that in FIG.
(Third equalize circuit)
FIG. 12 is a circuit diagram showing a configuration of a third equalize circuit according to an embodiment of the present invention. As shown, a resistor R may be used as the safety device S. As the resistor R, a well resistor, a polycrystalline silicon resistor (Poly resistor), a transistor resistor, or the like can be used.

  A timing chart during the operation of the third equalize circuit is shown in FIG. As shown in FIG. 13A, the MEQ line changes from the H level to the L level, and the equalizing operation starts. Therefore, as shown in FIG. 13C, the first and second nodes ML-L and ML-R, which have been different potentials so far, are equalized to the ground potential. Further, when the MGENb line changes from the H level to the L level, the potentials of the first and second nodes ML-L and ML-R rapidly decrease, and then increase due to the increase in the bit line potential. These changes are as described in the section “1) Sense amplifier circuit” with reference to FIG. Note that the potential change of the node vrst is also shown in the figure. In this case, when a predetermined time elapses from the change of the MEQ line, the node vrst becomes the ground potential and becomes stable. Therefore, it is not necessary to change the MEQ line from the L level to the H level.

  As described in detail above, in the first to third equalize circuits, the negative potential node can be equalized with a simple configuration. Therefore, the initial potentials of the first and second nodes can be stabilized, and subsequent circuit operation, for example, sense amplifier circuit operation can be stabilized. In particular, when the equalizing circuit of the present invention is applied to the first and second sense amplifier circuits described above, it is more effective. That is, in the first and second sense amplifier circuits, it is necessary that one of the potentials of the first and second nodes changes beyond the threshold value Vth. Therefore, by stabilizing the initial potential of the first and second nodes, the change in the potential of the node can be ensured.

  In the first and second equalizing circuits, the period in which the MEQ line is at the L level is the equalizing period, and the equalizing period can be accurately ensured by the input pulse (change in the MEQ signal). On the other hand, the third equalizer circuit can perform equalization with a simple circuit configuration and simple input (only the MEQ line is set to L level).

  The equalize circuit of the present invention can be applied not only to the first and second sense amplifier circuits but also to the circuit shown in FIG. 6 and FIG. 23 described later. That is, by connecting the equalizing circuit of the present invention between the nodes NA and NB, even if these nodes become negative potential nodes, these nodes can be set to the same potential.

  The equalize circuit of the present invention is applicable not only to a 2T2C ferroelectric memory but also to a 1T1C ferroelectric memory in which a reference potential is applied to one bit line.

In the first to third equalizing circuits, the ferroelectric capacitor is used as the negative potential generating circuit, but a paraelectric capacitor, a gate capacitor, or the like may be used. Further, a negative potential may be applied to the node vrst by a completely different circuit system.
3) Positive Potential Conversion Circuit Next, the configuration of the positive potential conversion circuit used in the first and second sense amplifier circuits will be described in detail.
(First positive potential conversion circuit 1)
FIG. 14 is a circuit diagram showing a configuration of a first positive potential converter circuit according to an embodiment of the present invention. As shown in the figure, the potential difference between the first and second nodes is taken out as the output of the cross-connected inverter. Specifically, the circuit is connected between the power supply potential and the node NL, and the inverter IN1 including the p-channel MISFET P12-L and the n-channel MISFET N12-L connected between the power supply potential and the node NL. And an inverter IN2 composed of an n-channel MISFET N12-R. A connection node between the p-channel type MISFET P12-L and the n-channel type MISFET N12-L is an output unit OUT-L. The output unit OUT-L is a gate terminal of the p-channel type MISFET P12-R and a gate terminal of the n-channel type MISFET N12-R. It is connected to the. The connection node between the p-channel type MISFET P12-R and the n-channel type MISFET N12-R serves as an output unit OUT-R. The output unit OUT-R includes the gate terminal of the p-channel type MISFET P12-L and the gate of the n-channel type MISFET N12-L. Connected to the terminal.

  A p-channel MISFET P11-L is connected between the node NL and the ground potential, and its gate terminal is connected to the first node ML-L. A p-channel MISFET P11-R is connected between the node NR and the ground potential, and its gate terminal is connected to the second node ML-R. The substrate potential of the p-channel type MISFETs P11-L and 11-R is the ground potential.

  Here, after the potentials of the first and second nodes are determined, the switching transistor N11-L is connected between the first end of the n-channel MISFET N12-L and the node NL to turn on the positive potential conversion circuit. The switching transistor N11-R is connected between the first end of the n-channel type MISFET N12-R and the node NR. These switching transistors are made of n-channel MISFE, and the gate terminals of these switching transistors are connected to the MTP line.

  Further, in order to fix the output unit at a predetermined potential in advance, a switching transistor P13-L is connected between the power supply potential and the output unit OUT-L, and the switching transistor P13- is connected between the power supply potential and the output unit OUT-R. R is connected. These switching transistors are made of p-channel type MISFE, and the gate terminals of these switching transistors are connected to the MTP line.

  FIG. 15 shows a timing chart during operation of the first positive potential converter circuit. As shown in FIG. 15A, while the MTP line is at the L level, the output units OUT-L and OUT-R are precharged to the power supply potential (H level). Thus, by performing precharge during standby, undesired operations of the inverters IN1 and IN2 can be prevented. Thereafter, when the MGENb line shown in FIG. 15B changes from the H level to the L level, the potentials of the first and second nodes ML-L and ML-R rapidly decrease, and then the bit line potential increases. As shown in FIG. 15 (C). These changes are as described in the section “1) Sense amplifier circuit” with reference to FIG. At this time, one potential is equal to or higher than the threshold value Vth, and the other potential is equal to or lower than the threshold value Vth. Next, when the MTP line becomes H level, the positive potential conversion circuit operates. That is, since the node on the “1” data side (ML-L in FIG. 15) is equal to or higher than the threshold Vth, the p-channel MISFET P11-R is turned on. Therefore, the output part OUT-R becomes L level (ground potential). On the other hand, the output portion OUT-L maintains the H level (power supply potential) (FIG. 15C).

Thus, in the first positive potential conversion circuit, the output corresponding to the potential difference between the first and second nodes, which are negative potential nodes, can be taken out as H level and L level, which are positive potential nodes. Here, a negative potential refers to a potential of 0 or less, and a positive potential refers to a potential of 0 or more. Further, depending on the operation timing, the potential of the first or second node may slightly exceed 0.
(Second positive potential conversion circuit)
FIG. 16 is a circuit diagram showing a configuration of a second positive potential converter circuit according to an embodiment of the present invention. Also in this case, the potential difference between the first and second nodes is taken out as the output of the cross-connected inverter. Specifically, the circuit is connected between an inverter IN1 including a p-channel MISFET P12-L and an n-channel MISFET N12-L connected between the node NC and the node NL, and between the node NC and the node NL. And an inverter IN2 composed of an n-channel MISFET N12-R. A connection node between the p-channel type MISFET P12-L and the n-channel type MISFET N12-L serves as an output unit OUT-L. The output unit OUT-L includes the gate terminal of the p-channel type MISFET P12-R and the gate of the n-channel type MISFET N12-R. Connected to the terminal. The connection node between the p-channel type MISFET P12-R and the n-channel type MISFET N12-R serves as an output unit OUT-R. The output unit OUT-R includes the gate terminal of the p-channel type MISFET P12-L and the gate of the n-channel type MISFET N12-L. Connected to the terminal.

  A p-channel MISFET P11-L is connected between the node NL and the ground potential, and its gate terminal is connected to the first node ML-L. A p-channel MISFET P11-R is connected between the node NR and the ground potential, and its gate terminal is connected to the second node ML-R. The substrate potential of the p-channel type MISFETs P11-L and 11-R is the ground potential.

  Here, after the potentials of the first and second nodes are determined, a switching transistor P15 is connected between the power supply potential and the node NC in order to turn on the positive potential conversion circuit. The switching transistor P15 is made of a p-channel type MISFE, and the gate terminal of the switching transistor P15 is connected to the MTPb line. MTPb represents an inverted signal (signal line) of MTP.

  Further, in order to fix the output unit at a predetermined potential in advance, a switching transistor N12-L is connected between the ground potential and the output unit OUT-L, and the switching transistor N12- is connected between the ground potential and the output unit OUT-R. R is connected. These switching transistors are made of n-channel type MISFE, and the gate terminals of these switching transistors are connected to the MTPb line.

  FIG. 17 shows a timing chart during the operation of the second positive potential conversion circuit. As shown in FIG. 17A, while the MTPb line is at the H level, the output units OUT-L and OUT-R are discharged to the ground potential (L level). In this way, by performing discharge during standby, undesired operations of the inverters IN1 and IN2 can be prevented. Thereafter, when the MGENb line shown in FIG. 17B changes from the H level to the L level, the potentials of the first and second nodes ML-L and ML-R rapidly decrease, and then the bit line potential increases. As shown in FIG. These changes are as described in the section “1) Sense amplifier circuit” with reference to FIG. At this time, one potential is equal to or higher than the threshold value Vth, and the other potential is equal to or lower than the threshold value Vth. Next, when the MTPb line becomes L level, the positive potential conversion circuit operates. That is, since the node on the “1” data side (ML-L in FIG. 17) is equal to or higher than the threshold value Vth, the p-channel MISFET P11-R is turned on. Therefore, the output part OUT-R becomes L level (ground potential). On the other hand, when the output part OUT-R becomes L level, the p-channel MISFET P12-L is turned on, so that the output part OUT-L becomes H level (power supply potential) (FIG. 17C).

Thus, also in the second positive potential conversion circuit, the output corresponding to the potential difference between the first and second nodes, which are negative potential nodes, can be taken out as H level and L level.
(Third positive potential conversion circuit)
FIG. 18 is a circuit diagram showing a configuration of a third positive potential converter circuit according to an embodiment of the present invention. As illustrated, the circuit includes an n-channel MISFET N12-L having a first terminal connected to a node NL and an n-channel MISFET N12-R having a first terminal connected to a node NR. The second terminal of the n-channel type MISFET N12-L serves as an output unit OUT-L, and is connected to the gate terminal of the n-channel type MISFET N12-R. The second terminal of the n-channel type MISFET N12-R serves as an output unit OUT-R, and is connected to the gate terminal of the n-channel type MISFET N12-L.

  A p-channel MISFET P11-L is connected between the node NL and the ground potential, and its gate terminal is connected to the first node ML-L. A p-channel MISFET P11-R is connected between the node NR and the ground potential, and its gate terminal is connected to the second node ML-R. The substrate potential of the p-channel type MISFETs P11-L and 11-R is the ground potential.

  Here, after the potentials of the first and second nodes are determined, the switching transistor N11-L is connected between the n-channel MISFET N12-L and the node NL to turn on the positive potential conversion circuit, and the n-channel A switching transistor N11-R is connected between the type MISFET N12-R and the node NR. These switching transistors are made of n-channel MISFE, and the gate terminals of these switching transistors are connected to the MTP line.

  Further, in order to fix the output unit at a predetermined potential in advance, a switching transistor P13-L is connected between the power supply potential and the output unit OUT-L, and the switching transistor P13- is connected between the power supply potential and the output unit OUT-R. R is connected. These switching transistors are made of p-channel type MISFE, and the gate terminals of these switching transistors are connected to the MTP line.

  FIG. 19 shows a timing chart during operation of the third positive potential converter circuit. As shown in FIG. 19B, while the MTP line is at the L level, the output sections OUT-L and OUT-R are precharged to the power supply potential (H level). Thereafter, when the MGENb line shown in FIG. 19C changes from the H level to the L level, the potentials of the first and second nodes ML-L and ML-R rapidly decrease, and then the bit line potential increases. As shown in FIG. 19 (D). These changes are as described in the section “1) Sense amplifier circuit” with reference to FIG. Next, when the MTP line shown in FIG. 19B becomes H level, the third positive potential converter circuit operates.

  In FIG. 19, since the potentials of the first and second nodes ML-L and ML-R are equal to or lower than the threshold Vth due to the decrease in the potential, the p-channel MISFETs P11-L and P11-R are turned on. . Therefore, the potentials of the output units OUT-L and OUT-R are lowered. On the other hand, when any potential (ML-L in FIG. 19) exceeds the threshold value Vth due to the rise of the potentials of the first and second nodes ML-L and ML-R, the p-channel transistor P11-R is turned off. It becomes. Therefore, the output unit OUT-L maintains the potential at that time. On the other hand, the output part OUT-R drops to the ground potential. Therefore, after that, the SAE signal shown in FIG. 19A is changed from the L level to the H level, and the potential difference between the output units OUT-L and OUT-R is amplified by a general sense amplifier, whereby the H level LAT -L signal and L level LAT-R signal can be taken out as output signals (FIG. 19D).

  In FIG. 19D, the n-channel MISFET N12-R is turned off when the potential of the output section OUT-L becomes equal to or lower than the threshold Vthn of the n-channel MISFET N, and the potential of the output section OUT-L The decline has stopped. Either the n-channel MISFET N (12-L, N12-R) is turned off or the p-channel MISFET (P11-L, P11-R) is turned on earlier. In any case, more reliable reading can be performed by activating the SAE line after the potential of one of the first and second nodes ML-L and ML-R exceeds the threshold value Vth.

  Further, by adjusting L (length) and W (width) of a gate of n-channel type MISFET N (12-L, N12-R) or the like, or adjusting the threshold potential thereby, the output unit OUT-L , A large potential difference between OUT-R can be secured.

Thus, also in the third positive potential conversion circuit, an output corresponding to the potential difference between the first and second nodes, which are negative potential nodes, can be taken out as positive potential outputs (OUT-L, OUT-R). However, in this case, unlike the first and second positive potential conversion circuits, it is necessary to further sense the signals of the output units OUT-L and OUT-R.
(Fourth positive potential converter)
FIG. 20 is a circuit diagram showing a configuration of a fourth positive potential converter circuit according to an embodiment of the present invention. The circuit is characterized in that ferroelectric capacitors C3-L and C3-R are further added to the third positive potential converter circuit (FIG. 18). As shown in the figure, a ferroelectric capacitor C3-L is connected between the first node ML-L and the output part OUT-L, and the ferroelectric is connected between the first node ML-L and the output part OUT-L. A body capacitor C3-L is connected. Other configurations are the same as those of the third positive potential conversion circuit.

  In the third positive potential converter circuit, when the potentials of the first and second nodes ML-L and ML-R are both larger than the threshold value Vth, the p-channel type MIFETs P11-L and P11-R are not turned on, The circuit does not operate. Therefore, it is necessary to perform circuit design (circuit control) so that the first and second nodes ML-L and ML-R are lower than the threshold value Vth.

  On the other hand, in the fourth positive potential conversion circuit, the first and second nodes ML− are reduced by using the ferroelectric capacitors C3-L and C3-R to decrease the potentials of the output units OUT-L and OUT-R. L and ML-R can be transmitted. Therefore, the potentials of the first and second nodes ML-L and ML-R are lowered, and one of the nodes can be set to the threshold value Vth or less.

  FIG. 21 shows a timing chart during operation of the fourth positive potential converter circuit. As shown in FIG. 21B, while the MTP line is at the L level, the output sections OUT-L and OUT-R are precharged to the power supply potential (H level). Thereafter, when the MGENb line shown in FIG. 21C changes from the H level to the L level, the potentials of the first and second nodes ML-L and ML-R rapidly decrease, and thereafter, the charge from the bit line Receiving the injection, each rises (FIG. 21D). These changes are as described in the section “1) Sense amplifier circuit” with reference to FIG.

  Next, when the MTP line illustrated in FIG. 21B is at an H level, the positive potential conversion circuit operates. In FIG. 21, since the potentials of the first and second nodes ML-L and ML-R are initially equal to or higher than the threshold value Vth, the p-channel type MISFETs P11-L and P11-R are in the off state. However, since the substrate potentials of the p-channel type MISFETs P11-L and P11-R are the ground potential, the p-channel type MISFEP11-R from the output unit OUT-R through the n-channel type transistor N12-R and the switching transistor N11-R. Current flows into the substrate. Similarly, current flows from the output part OUT-L to the substrate of the p-channel type MISFEP11-L. Therefore, the potentials of the output units OUT-L and OUT-R are lowered.

The decrease in the potentials of the output parts OUT-L and OUT-R is transmitted through the ferroelectric capacitors C3-L and C3-R, and the potentials of the first and second nodes ML-L and ML-R are decreased. To do.
Here, when the potential of the node on the “0” data side (ML-R in FIG. 21) where the potential drops from a lower potential exceeds the threshold value Vth, the p-channel transistor P11-R is turned on. Therefore, the output part OUT-R is lowered to the ground potential. On the other hand, since the n-channel MISFET N12-L is turned off, the output part OUT-L maintains the potential at that time. Therefore, after that, the SAE signal shown in FIG. 21A is changed from the L level to the H level, and the potential difference between the output units OUT-L and OUT-R is amplified by a general sense amplifier, whereby the H level LAT -L signal and L level LAT-R signal can be taken out (FIG. 21D).

  Thus, also in the fourth positive potential conversion circuit, an output corresponding to the potential difference between the first and second nodes, which are negative potential nodes, can be extracted as positive potential outputs (OUT-L, OUT-R). However, in this case, unlike the first and second positive potential conversion circuits, it is necessary to further sense the signals of the output units OUT-L and OUT-R.

  As described in detail above, in the first to fourth positive potential conversion circuits, the potential difference at the negative potential node can be converted into the potential difference of the positive potential. Here, in the comparison circuit of FIG. 6, the negative potential nodes NA and NB are converted to positive potentials by the capacitors C2A and C2B, and this potential difference is amplified by a general sense amplifier GSA. However, the conversion by the capacitors C2A and C2B has a large loss. Therefore, even if a large potential difference is ensured at nodes NA and NB, the potential difference after conversion to a positive potential is reduced. On the other hand, in the first to fourth positive potential conversion circuits, conversion loss can be reduced. Therefore, a large potential difference (potential difference between the output units OUT-L and OUT-R) can be ensured even after conversion to a positive potential. In other words, the sense margin can be increased.

  Further, in the first and second positive potential conversion circuits, the potentials of the output units OUT-L and OUT-R can be taken out as H level and L level. Further, the potential can be latched (maintained).

  As shown in FIG. 22, p-channel type MISFETs P17-L are respectively provided between the first and second nodes ML-L and ML-R, which are inputs of the first to fourth positive potential conversion circuits, and the ground potential. And an optional circuit OP comprising P17-R may be provided. FIG. 21 is a circuit diagram showing a configuration of an optional circuit of the positive potential conversion circuit. TP denotes any one of the first to fourth positive potential conversion circuits.

  As illustrated, the gate terminal of the p-channel type MISFET P17-L is connected to the second node ML-R, and the gate terminal of the p-channel type MISFET P17-R is connected to the first node ML-L. The substrate potentials of these p-channel type MISFETs P17-L and P17-R are ground potentials.

  Providing such an optional circuit OP can prevent the potentials of both the first and second nodes from becoming lower than the threshold value Vth. Therefore, the first to fourth positive potential conversion circuits are likely to operate normally.

  In this case, of the first and second nodes ML-L and ML-R, the node on the “1” data side rises to the ground potential. As a result, the potential of the output unit on the “0” data side of the output units OUT-L and OUT-R falls to the ground potential. Therefore, the subsequent circuit design is facilitated.

  As described above in detail, in the positive potential conversion circuit of the present invention, the output corresponding to the potential difference between the first and second nodes, which are negative potential nodes, is output as a positive potential (OUT-L, OUT-R). Can be taken out as.

  Note that the equalize circuit of the present invention is applicable not only to the first and second sense amplifier circuits but also to the circuit shown in FIG. That is, as shown in FIG. 23, the positive potential conversion circuit TP is used instead of the capacitors C2A and C2B. FIG. 23 is a circuit diagram showing another application example of the positive potential conversion circuit.

  In this case, the nodes NA and NB are connected to the input unit, and the output corresponding to the potential difference between the nodes NA and NB, which are negative potential nodes, is taken out as positive potential outputs (OUT-L and OUT-R) by the above operation. Can do. However, in this case, it is more preferable to use the third and fourth positive potential conversion circuits for the TP portion. In this case, the potentials of the nodes NA and NB can be set regardless of the threshold value Vth. Therefore, the signals of the output units OUT-L and OUT-R are further sensed by a general sense amplifier circuit GSA, and the output signals LAT-L and LAT-R are taken out.

  Note that the first and second positive potential converter circuits can be used depending on the relationship between the potentials of the nodes NA and NB and the threshold value Vth. In other words, the general sense amplifier circuit GSA can be omitted. In addition, the first and second positive potential conversion circuits can be used by adding the above-described option circuit OP.

  The positive potential conversion circuit of the present invention can be applied not only to a 2T2C ferroelectric memory but also to a 1T1C ferroelectric memory in which a reference potential is applied to one bit line.

  In the third positive potential conversion circuit, a ferroelectric capacitor is used for potential transfer, but a paraelectric capacitor, a gate capacitor, or the like may be used.

  The examples and application examples described through the embodiments of the present invention can be used in combination as appropriate according to the application, or can be used with modifications or improvements, and the present invention is limited to the description of the above-described embodiments. It is not a thing. It is apparent from the description of the scope of claims that the embodiments added with such combinations or changes or improvements can be included in the technical scope of the present invention.

It is a block diagram which shows the structure of a ferroelectric memory device. 1 is a circuit diagram showing a configuration of a first sense amplifier circuit according to an embodiment of the present invention. FIG. 3 is a timing chart at the time of reading from a ferroelectric memory device. It is a figure which shows the simulation result of electric potentials, such as bit line BL-L and BL-R at the time of read, 1st, 2nd node ML-L, MLR. FIG. 3 is a circuit diagram illustrating a configuration of a main part of a first sense amplifier circuit. 3 is a comparison circuit for explaining the effect of the first sense amplifier circuit. It is a circuit diagram which shows the structure of the 2nd sense amplifier circuit which is one embodiment of this invention. It is a figure which shows the simulation result of the electric potential of nodes PG-L, PG-R, etc. at the time of reading. It is a circuit diagram which shows the structure of the 1st equalize circuit which is one embodiment of this invention. 6 is a timing chart during operation of the first equalize circuit. It is a circuit diagram which shows the structure of the 2nd equalize circuit which is one embodiment of this invention. It is a circuit diagram which shows the structure of the 3rd equalize circuit which is one embodiment of this invention. 12 is a timing chart during operation of the third equalize circuit. It is a circuit diagram which shows the structure of the 1st positive electric potential converter circuit which is one embodiment of this invention. 6 is a timing chart during operation of the first positive potential conversion circuit. It is a circuit diagram which shows the structure of the 2nd positive electric potential converter circuit which is one embodiment of this invention. It is a timing chart at the time of operation of the 2nd positive potential conversion circuit. It is a circuit diagram which shows the structure of the 3rd positive electric potential converter circuit which is one embodiment of this invention. It is a timing chart at the time of operation of the 3rd positive potential conversion circuit. It is a circuit diagram which shows the structure of the 4th positive electric potential converter circuit which is one embodiment of this invention. It is a timing chart at the time of operation of the 4th positive potential conversion circuit. It is a circuit diagram which shows the structure of the option circuit of a positive potential converter circuit. It is a circuit diagram which shows the other application example of a positive potential converter circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Ferroelectric memory device, 110 ... Memory cell array, 120 ... Word line control part, 130 ... Plate line control part, 140 ... Bit line control part, BL, BL-L, BL-R ... Bit line, Ct-L Ct-R, Ct2-L, Ct2-R ... Ferroelectric capacitor, C3-L, C3-R ... Ferroelectric capacitor, C1A, C1B, C2A, C2B ... Capacitor, C1 ... Ferroelectric capacitor, EQ1, EQ2 ... Equalize circuit, FBA, FBB ... Feedback circuit, GSA ... Sense amplifier circuit, ML-L, ML-R ... Node, N1-L, N1-R, N2-L, N2-R ... Switching transistor, N11-L , N11-R, N12-L, N12-R ... switching transistor, NL, NR, NA, NB ... node, OP ... optional circuit, OUT-L, UT-R: output unit, P1-L, P1-R, P2-L, P2-R ... p-channel type MISFET, P3-L, P3-R, P4 ... p-channel type MISFET, P11-L, P11-R P12-L, P12-R, P17-L, P17-R ... p-channel MISFET, P13-L, P13-R, P15 ... switching transistor, PG-R, PG-L ... node, PL ... plate line, PTA, PTB ... p channel type MISFET, R ... resistance, SA ... sense amplifier circuit, TP ... positive potential conversion circuit, vrst ... node, WL ... word line, BLGND, BLSW, MGEN, MGENb, MEQ, MTP, MTPb ... signal (Signal line)

Claims (8)

Is connected between the first node and a second node connected to a second bit line connected to the first bit line, a second 1p channel type MISFET its board potential and the ground potential,
A first negative voltage generating circuit having a ferroelectric capacitor connected between a control signal line and a gate terminal of the first p-channel type MISFET;
A ferroelectric memory device comprising: A second p-channel MISFET connected between the first node and a ground potential, having a gate terminal connected to the first negative potential generating circuit, and a substrate potential being a ground potential;
A third p-channel MISFET connected between the second node and the ground potential, having a gate terminal connected to the first negative potential generating circuit, and a substrate potential being the ground potential;
The ferroelectric memory device according to claim 1 , comprising : A clamp circuit is connected to the output of the first negative potential generating circuit ,
The ferroelectric memory device according to claim 1 or 2. The clamp circuit is a resistor connected between the output and a ground potential .
The ferroelectric memory device according to claim 3 . A fourth p-channel MISFET connected between the first node and the first bit line;
A fifth p-channel MISFET connected between the second node and the second bit line;
A second negative potential generating circuit connected to the first node;
A third negative potential generating circuit connected to the second node ;
Ferroelectric memory device of any one of claims 1 to 4. Wherein the first bit line and second bit line, each ferroelectric memory is connected, the ferroelectric memory device according to any one of claims 1 to 5. Wherein the first bit line, a ferroelectric memory is connected, wherein the second bit line, a reference potential is applied, the ferroelectric memory device according to any one of claims 1 to 5. Strong that having a dielectric storage device electronic device according to any one of claims 1 to 7.

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