JP4343011B2 - Digital amplifier - Google Patents

Description

  The present invention relates to a digital amplifier (class D amplifier) that performs switching amplification of a digital signal such as an audio signal using a pulse density modulation (PDM) signal or a pulse width modulation (PWM) signal.

  In the digital amplifier that performs the switching amplification, a high-speed switching element capable of reproducing the audio signal can be obtained relatively easily, and it is rapidly used because of its high power efficiency. It is coming.

  FIG. 6 is a block diagram showing an example of the electrical configuration of a switching amplifier 150 which is a typical prior art digital amplifier. In the switching amplifier 150, the ΔΣ modulation block 101 includes a ΔΣ conversion circuit (not shown), and a 1-bit positive signal that is a series of binary signals from an analog input signal, a multi-bit digital input signal, or a 1-bit input signal. Although an example in which the phase signal b is generated and output from the 1-bit positive phase output terminal 102 is shown, it goes without saying that the digital signal for driving the switching element may be a PWM signal.

  Between a high-potential-side power supply line connected to the power supply terminal 512 and the GND line, a series circuit including N-channel output transistors 501 and 503 and a series circuit including N-channel output transistors 502 and 504 are included. A full bridge circuit which is an H-type bridge circuit is connected. A positive-phase 1-bit signal output from the 1-bit positive-phase output terminal 102 of the ΔΣ modulation block 101 is applied to the gate of the output transistor 501 via the buffer 301 and also to the output transistor 504 via the buffer 303. Given to the gate. The buffer 301 is an upper buffer, and the buffer 303 is a lower buffer. Further, the voltage is supplied to the gate of the output transistor 502 through the inverter 302 and is supplied to the gate of the output transistor 503 through the inverter 304. The inverter 302 is an upper buffer, and the inverter 304 is a lower buffer. Thus, the output transistors 501 and 503 and the output transistors 502 and 504 perform switching by a reciprocal operation.

  The connection point of the output transistors 501 and 503 is an output terminal having a negative phase, and is connected to a negative phase output terminal 510 through a low-pass filter including a coil 506 and a capacitor 508. The connection point of the output transistors 502 and 504 is a positive phase. And is connected to the positive-phase output terminal 509 through a low-pass filter composed of a coil 505 and a capacitor 507. A load 511 such as a speaker is connected between the output terminals 509 and 510. Each circuit in the switching amplifier 150 such as the ΔΣ modulation block 101 and a power supply circuit (not shown) is controlled by the control microcomputer 201 via the control signal line 104.

  FIG. 7 is a waveform diagram for explaining the operation of the switching amplifier 150 configured as described above. The 1-bit positive phase signal b shown in A of FIG. 7 is delayed by a certain time in the buffers 301 and 303 so that the rising and falling timings thereof are slightly different as shown in B and C of FIG. This is applied to the gates of the output transistors 501 and 504. Similarly, the 1-bit positive phase signal b is delayed by a certain time in the inverters 302 and 304 so that the rising and falling timings thereof are slightly different as shown in FIGS.・ It is given to the gate of 503.

  Accordingly, the output transistors 501 and 503 perform switching operations indicated by F and I in FIG. 7, and the output transistors 502 and 504 perform switching operations indicated by H and G in FIG. The load 511 is push-pull driven by the normal phase output and the reverse phase output. When this switching amplifier 150 is used, a simple process of removing a high-frequency signal by a low-pass filter including coils 505 and 506 and capacitors 507 and 508 without performing digital / analog conversion when reproducing a 1-bit signal. The original analog signal can be reproduced.

However, in this switching amplifier 150, the signals for driving the output transistors 501 to 504 of the full bridge circuit depend only on the 1-bit positive phase signal b, and the rising and falling timings as described with reference to B to E in FIG. If the 1-bit signal slightly fluctuates in time due to the shift of
1) Audio performance such as S / N ratio, distortion, separation, and frequency characteristics, that is, signal quality also fluctuates.
2) Since the switch timing of the high-side output transistors 501 and 502 and the low-side output transistors 503 and 504 that are connected in series between the power supply lines also fluctuate, a through current that short-circuits between the power supply lines flows, and power consumption is reduced. There is a problem of large and fluctuating.

Therefore, another conventional technique for solving such a problem is shown by a switching amplifier 250 in FIG. The switching amplifier 250 is similar to the switching amplifier 150 described above, and corresponding portions are denoted by the same reference numerals, and description thereof is omitted. It should be noted that in this switching amplifier 250, the ΔΣ modulation block 101 is provided with a clock output terminal 103 and provided with D flip-flop circuits 305 and 306 that use a clock signal output therefrom. The D flip-flop circuit has a D (delay) terminal, a CK (clock input) terminal, a Q (positive phase output) terminal, and a QB (reverse phase output) terminal, and a signal at the D (data input) terminal at the rising edge of the clock signal. The Q (normal phase output) terminal outputs normal output, and the QB (reverse phase output) terminal outputs inverted. This makes the switch timing more accurate.
JP 2002-246852 A (publication date: published on August 30, 2002)

  However, in the prior art of FIG. 8 for solving the above-described problems, the clock signal for operating the D flip-flop circuit is required. When a clock signal is generated in a portable device that requires low power consumption, there is a problem that power consumption increases due to an increase in through current in the circuit itself.

  The object of the present invention has been made in view of the above-described conventional problems, and the object thereof is a digital amplifier capable of setting optimum fidelity and power consumption in accordance with required signal quality and power consumption. Is to realize.

  In order to solve the above problems, a digital amplifier according to the present invention includes a binary signal output unit that outputs a binary signal that expresses a signal in binary, a switching amplification unit that switches and amplifies the binary signal, and the switching For each push-pull operation circuit of the amplifying means, the binary signal output from the binary signal output means and input to the high-potential side or low-potential side switching element is used as a positive phase signal, and the positive phase A digital amplifier comprising: a switching element to which a signal is input; and a positive-phase signal and a negative-phase signal generating means for inputting the binary signal input to the switching element on the opposite polarity potential side to the switching amplification means as a negative-phase signal The positive phase signal / negative phase signal generation means includes at least a first positive phase signal / negative phase signal generation means and a second positive phase signal / negative phase signal generation means. The binary signal is input to the switching amplification means as the normal phase signal or the negative phase signal by the first positive phase signal negative phase signal generation means, or the second positive phase signal negative phase signal generation is performed. Switching means for switching whether to input the positive phase signal or the negative phase signal to the switching amplification means, and the first positive phase signal negative phase signal generation means is output from the binary signal output means. A D flip-flop circuit that receives the binary signal as an input signal, and the second positive-phase signal / negative-phase signal generation means uses the binary signal output from the binary signal output means as an input signal. It includes a pair of a buffer and an inverter.

  According to the above invention, the positive phase signal / negative phase signal generation means includes the first positive phase signal / negative phase signal generation means and the second positive phase signal / negative phase signal generation means. Depending on the power consumption, the first positive-phase signal / negative-phase signal generation means is selected and the D flip-flop circuit is used to drive the switching amplification means, or the second positive-phase signal / negative-phase signal generation is performed. By selecting the means and using the buffer and the inverter, the switching amplification means is switched to be driven.

  When high signal quality is required, the first positive phase signal / negative phase signal generation means is selected, and the clock signal is input to the D flip-flop circuit. Although power consumption increases in order to generate a clock signal, the switching timing of each switching element is exactly matched, and amplitude amplification with high fidelity is performed.

  On the other hand, when suppression of power consumption is required, the second positive phase signal / negative phase signal generation means is selected, and the operation of inputting the clock signal to the D flip-flop circuit is stopped. As a result, power consumption is reduced, and amplitude amplification is performed to reduce power consumption at the expense of some strictness with respect to matching of switching timings of the switching elements.

  As described above, it is possible to realize a digital amplifier capable of setting optimum fidelity and power consumption corresponding to required signal quality and power consumption.

  In order to solve the above-described problems, the digital amplifier according to the present invention is characterized in that the switching amplification means includes a full bridge circuit that performs switching amplification of the binary signal and performs balanced output.

  According to the above invention, in a digital amplifier that applies a voltage of a difference between the potential of the positive phase output terminal and the potential of the negative phase output terminal to the load, an optimum fidelity corresponding to the required signal quality and power consumption is achieved. There is an effect that the power and the power consumption can be set.

  In the digital amplifier of the present invention, in order to solve the above-described problem, the switching unit outputs the first positive phase signal / negative phase signal generation unit with respect to the input of each switching element of the switching unit. It includes a multiplexer that selects and outputs either a binary signal or the binary signal output from the second positive phase signal / negative phase signal generation means according to a control signal.

  According to the above invention, by providing the multiplexer with respect to the input of each switching element, the binary is obtained by either the first positive phase signal / negative phase signal generation means or the second positive phase signal / negative phase signal generation means. There is an effect that it is possible to easily switch whether a signal is input to each switching element.

  In the digital amplifier of the present invention, as described above, the positive phase signal / negative phase signal generation means includes at least a first positive phase signal / negative phase signal generation means and a second positive phase signal / negative phase signal generation means, A binary signal is input to the switching amplification unit as the normal phase signal or the negative phase signal by the first positive phase signal / negative phase signal generation unit, or by the second positive phase signal / negative phase signal generation unit. Switching means for switching whether to input the positive phase signal or the negative phase signal to the switching amplification means, and the first positive phase signal / negative phase signal generation means outputs the 2 signal output from the binary signal output means. A D flip-flop circuit having a value signal as an input signal, wherein the second positive-phase signal / negative-phase signal generation means is a buffer having the binary signal output from the binary signal output means as an input signal; Including a pair of micro-inverter.

  Therefore, it is possible to realize a digital amplifier capable of setting optimum fidelity and power consumption corresponding to required signal quality and power consumption.

  An embodiment of the present invention will be described below with reference to FIGS.

  FIG. 1 is a block diagram showing an example of an electrical configuration of a switching amplifier 1 which is a digital amplifier according to an embodiment of the present invention.

  The switching amplifier 1 includes a ΔΣ modulation block 11, a microcomputer 21, buffers 31 and 33, inverters 32 and 34, D flip-flop circuits 35 and 36, multiplexers 41, 42, 43, and 44, output transistors 51, 52, 53, and 54, Coils 55 and 56, capacitors 57 and 58, a normal phase output terminal 59, a negative phase output terminal 60, and a power supply terminal 61 are provided.

  The ΔΣ modulation block (binary signal output means) 11 includes a ΔΣ conversion circuit (not shown) and expresses a signal in binary from an analog input signal, a multi-bit digital input signal, or a 1-bit input signal as an audio signal. A 1-bit positive phase signal b, which is a series of binary signals, is generated and output from the 1-bit positive phase output terminal 12. The 1-bit positive phase signal b is a digital signal for driving the output transistors 51 to 54. The ΔΣ modulation block 11 outputs a clock signal c from the 1-bit latch clock signal output terminal 13. Needless to say, the digital signal for driving the output transistors 51 to 54 may be a PWM signal.

  The microcomputer 21 controls each circuit in the switching amplifier 1 such as the ΔΣ modulation block 11 and a power supply circuit (not shown) via the control signal line 14. As one of them, switching control for outputting the clock signal c from the 1-bit latch clock signal output terminal 13 of the ΔΣ modulation block 11 or stopping the output is performed. In addition, the microcomputer 21 outputs a synchronous / asynchronous switching signal e serving as a control signal for the multiplexers 41 to 44 from the synchronous / asynchronous switching terminal 22.

  The buffers 31 and 33 receive the 1-bit positive phase signal b as an input signal, and output a positive phase signal that is logically a non-inverted signal. The buffer 31 is an upper buffer, and the buffer 33 is a lower buffer. The inverters 32 and 34 receive the 1-bit positive phase signal b as an input signal, and output a negative phase signal that is logically an inverted signal thereof. The inverter 32 is an upper inverter, and the inverter 34 is a lower inverter. The buffer 31 and the inverter 34 form a pair and are provided for the output transistors 51 and 53 that perform the push-pull operation. The buffer 33 and the inverter 32 form a pair and are provided for the output transistors 52 and 54 that perform a push-pull operation.

  The D flip-flop circuits 35 and 36 have a 1-bit positive phase signal b as an input signal, a positive phase signal that is logically non-inverted from the Q terminal, and a negative phase that is logically inverted from the QB terminal. Each signal is output. The clock signal c output from the 1-bit latch clock signal output terminal 13 of the ΔΣ modulation block 11 is input to the clock terminals of the D flip-flop circuits 35 and 36.

  The buffers 31 and 33, the inverters 32 and 34, and the D flip-flop circuits 35 and 36 constitute a positive phase signal / negative phase signal generation means. The D flip-flop circuits 35 and 36 constitute first positive phase signal / negative phase signal generating means, and the buffers 31 and 33 and the inverters 32 and 34 constitute second positive phase signal / negative phase signal generating means, respectively. Yes.

  The multiplexers 41 to 44 are two-input multiplexers having input terminals A and B, an output terminal Y, and a control terminal S. A synchronous / asynchronous switching signal e that is a control signal output from the synchronous / asynchronous switching terminal 22 of the microcomputer 21 is input to the control terminals S of the multiplexers 41 to 44. The multiplexers 41 to 44 select signals to be output in accordance with the synchronous / asynchronous switching signal e. When the synchronous / asynchronous switching signal e is L, the signal input to the input terminal A is selected and output from the output terminal Y. When the synchronous / asynchronous switching signal e is H, the signal input to the input terminal B is selected. Select and output from output terminal Y.

  The multiplexer 41 is provided for the output transistor 51, and the output signal of the buffer 31 is input to the input terminal A, and the Q output of the D flip-flop circuit 35 is input to the input terminal B. The multiplexer 42 is provided for the output transistor 52, and the output signal of the inverter 32 is input to the input terminal A, and the QB output of the D flip-flop circuit 35 is input to the input terminal B. The multiplexer 43 is provided for the output transistor 54, and the output signal of the buffer 33 is input to the input terminal A, and the Q output of the D flip-flop circuit 36 is input to the input terminal B. The multiplexer 44 is provided for the output transistor 53, and the output signal of the inverter 34 is input to the input terminal A, and the QB output of the D flip-flop circuit 36 is input to the input terminal B.

  Accordingly, when the synchronous / asynchronous switching signal e is L, a binary signal is input to the output transistors 51 to 54 by the buffers 31 and 33 and the inverters 32 and 34, and when the synchronous / asynchronous switching signal e is H, 2 signals are input. The input path is switched so that the value signal is input to the output transistors 51 to 54 by the D flip-flop circuits 35 and 36. Thus, the microcomputer 21 and the multiplexers 41 to 44 constitute a switching unit. In addition, the timing of outputting the clock signal c from the 1-bit latch clock signal output terminal 13 of the ΔΣ modulation block 11 controlled by the microcomputer 21 is synchronized with the synchronous / asynchronous switching signal e of H, and the output of the clock signal c is stopped. The timing is adjusted to the L synchronous / asynchronous switching signal e.

  The four output transistors (switching elements) 51 to 54 are all N-channel MOSFETs. The output transistor 51 and the output transistor 53 are connected in series so that the output transistor 51 is on the high potential side and the output transistor 53 is on the low potential side to form a push-pull operation circuit. The output transistor 52 and the output transistor 54 are connected in series so that the output transistor 52 is on the high potential side and the output transistor 54 is on the low potential side to form a push-pull operation circuit.

  The output signal of the multiplexer 41 is input to the gate of the output transistor 51, the output signal of the multiplexer 42 is input to the gate of the output transistor 52, the output signal of the multiplexer 44 is input to the gate of the output transistor 53, and the output transistor The output signal of the multiplexer 43 is input to the gate 54. The output signals of the multiplexers 41 to 44 are drive signals for the output transistors 51 to 54, and are signals to be subjected to switching amplification. The positive phase signal is input to the gates of the output transistors 51 and 54, and the negative phase signal is input to the gates of the output transistors 53 and 52 on the opposite polarity potential side. Thus, by providing a multiplexer for the input of each output transistor, which of the D flip-flop circuits 35 and 36, the buffers 31 and 33, and the inverters 32 and 34 is used to input a binary signal to each output transistor Can be easily switched.

  The push-pull operation circuit composed of the output transistor 51 and the output transistor 53 and the push-pull operation circuit composed of the output transistor 52 and the output transistor 54 constitute a full bridge circuit that is an H-type bridge circuit. Yes. The high potential side of the full bridge circuit is connected to the power supply terminal 61, and the low potential side is connected to GND. Reciprocal operations are performed so that the ON / OFF states of the output transistor 51 and the output transistor 52 are reversed, and the ON / OFF states of the output transistor 53 and the output transistor 54 are reversed. Then, balanced output is performed from a connection point M between the output transistor 52 and the output transistor 54 and a connection point N between the output transistor 51 and the output transistor 53. From the connection point M, a positive phase output signal consisting of the potential of the power supply terminal 61 and the potential of GND is outputted from the connection point N, and a negative phase output signal consisting of the potential of the power supply terminal 61 and the potential of GND is outputted. . Each output signal is a signal obtained by switching amplification of the signal input to the gates of the output transistors 51 to 54 using the potential of the power supply terminal 61 and the potential of GND. Thus, the output transistors 51 to 54 constitute a switching amplification means.

  The coil 55 and the capacitor 57 constitute a low-pass filter, and convert the positive phase output signal output from the connection point M into an analog signal. One end of the coil 55 is connected to the connection point M, and the other end is connected to the positive phase output terminal 59. One end of the capacitor 57 is connected to the other end of the coil 55, and the other end is connected to GND. The coil 56 and the capacitor 58 constitute a low-pass filter, and convert a negative phase output signal output from the connection point N into an analog signal. One end of the coil 56 is connected to the connection point N, and the other end is connected to the reverse phase output terminal 60. One end of the capacitor 58 is connected to the other end of the coil 56, and the other end is connected to GND.

  A load 71 composed of an electroacoustic transducer such as a speaker or a headphone is connected between the normal phase output terminal 59 and the reverse phase output terminal 60. The voltage of the difference between the potential of the normal phase output terminal 59 and the potential of the negative phase output terminal 60 is applied to the load 71, and a current flows through the load 71, so that the audio signal is reproduced. In this way, the load 71 is push-pull driven by positive and negative polarity signals output from the positive phase output terminal 59 and the negative phase output terminal 60.

  In the switching amplifier 1 having the above configuration, the operation when the synchronous / asynchronous switching signal e is L will be described first. At this time, the input to the control terminal S of the multiplexers 41 to 44 is L, and each multiplexer selects the signal input to the input terminal A and outputs it to the output terminal Y. FIG. 2 is a circuit diagram in which only the circuit on the side selected at this time is extracted, and FIG. 3 is a timing chart showing the state of each part at this time. That is, the 1-bit positive phase signal b is input to the buffers 31 and 33 and the inverters 32 and 34, and the respective outputs are output to the gates of the transistors 51 to 54. At this time, the clock signal c is unnecessary, and is stopped by a control signal from the microcomputer 21. For this reason, although the switching timing of the output transistors 51 to 54 varies somewhat due to a slight difference in the propagation delay time of each buffer and inverter, since the clock signal c is not necessary, an operation such as a through current is generated in a circuit that generates the clock signal c. The power consumed for the current becomes unnecessary. Therefore, the operation of at least the 1-bit latch clock signal output terminal 13 is stopped.

  Next, an operation when the synchronous / asynchronous switching signal e is H will be described. At this time, the input to the control terminal S of the multiplexers 41 to 44 is H, and each multiplexer selects the signal input to the input terminal B and outputs it to the output terminal Y. FIG. 4 is a circuit diagram in which only the circuit on the side selected at this time is extracted, and FIG. 5 is a timing chart showing the state of each part at this time. That is, the 1-bit positive phase signal b is input to the D terminals of the D flip-flop circuits 35 and 36, and the respective outputs are output to the gates of the transistors 51 to 54. At this time, since the clock signal c is necessary, the microcomputer 21 causes the 1-bit latch clock signal output terminal 13 to output the clock signal c by the control signal. Therefore, signals are output from the Q terminals and QB terminals of the D flip-flop circuits 35 and 36 at an accurate timing in synchronization with the clock signal c, and the switching timings of the output transistors 51 to 54 are exactly the same. Since the clock signal c is output to the 1-bit latch clock signal output terminal 13, some power is required for the operation current such as a through current in the circuit for generating the clock signal c.

  Based on such an operation, the switching amplifier 1 drives the full bridge circuit by selecting and using the D flip-flop circuits 35 and 36 corresponding to the desired signal quality and power consumption, or the buffer 31. -Select whether to drive the full bridge circuit by selecting and using 33 and inverters 32, 34. Specifically, when high signal quality is required, the D flip-flop circuits 35 and 36 are selected, and the clock signal c is output from the 1-bit latch clock signal output terminal 13. Although the power consumption increases in order to generate the clock signal c, the switching timings of the output transistors 51 to 54 are strictly matched to perform amplitude amplification with high fidelity.

  On the other hand, when suppression of power consumption is required, the buffers 31 and 33 and the inverters 32 and 34 are selected and used to stop the operation of the 1-bit latch clock signal output terminal 13. As a result, amplitude amplification that reduces power consumption is performed at the expense of some strictness with respect to matching of the switching timings of the output transistors 51 to 54.

  Thus, the optimum fidelity and power consumption can be set in accordance with the required signal quality and power consumption. This switching amplifier 1 is assumed to be used in, for example, a portable mini-disc player. Therefore, the microcomputer 21 corresponds to the user setting in the high sound quality mode and the low power consumption mode, that is, depending on whether the user desires high sound quality or extends the life of the battery or the secondary battery. The multiplexers 41 to 44 may be switched. Alternatively, the high sound quality mode may be selected when used with a commercial power supply, and the low power consumption mode may be automatically selected when the battery is driven. Also, in response to the degree of compression of the digital signal, for example, when the compression is in the shallow standard mode, the high sound quality mode in which the variation in switching timing is zero, and in the deep long time mode, the switching timing of a certain degree Automatic setting may be performed such as switching to a low power consumption mode that allows variation.

  In this way, by switching the multiplexers 41 to 44 according to the desired sound quality and power consumption, it is possible to cope with the required sound quality and power consumption.

  In the present embodiment, the switching amplification means is configured by a full bridge circuit. However, the present invention is not limited to this, and can also be configured by a half bridge circuit.

  The present invention can be suitably applied to a portable audio signal reproducing device and the like.

1 is a circuit block diagram illustrating a configuration of a digital amplifier according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a portion that becomes effective when a buffer and an inverter are selected in the digital amplifier shown in FIG. 1. 2 is a timing chart for explaining the operation of the digital amplifier shown in FIG. 1 in a low power consumption mode. FIG. 2 is a circuit diagram of a portion that becomes effective when a D flip-flop circuit is selected in the digital amplifier shown in FIG. 1. 2 is a timing chart for explaining the operation of the digital amplifier shown in FIG. 1 in a high sound quality mode. It is a circuit block diagram which shows the 1st prior art and shows the structure of a digital amplifier. 7 is a timing chart for explaining the operation of the digital amplifier shown in FIG. 6. It is a circuit block diagram which shows the 2nd prior art and shows the structure of a digital amplifier.

Explanation of symbols

1 Switching amplifier (digital amplifier)
11 ΔΣ modulation block (binary signal output means)
12 1-bit positive phase output terminal 13 1-bit latch clock signal output terminal 21 Microcomputer 22 Synchronous / asynchronous switching output terminal 31, 33 Buffer 32, 34 Inverter 35, 36 D flip-flop circuit 41-44 Multiplexer 51-54 Output transistor ( Switching element)
55, 56 Coil 57, 58 Capacitor 59 Positive phase output terminal 60 Reverse phase output terminal 71 Load 61 Power supply terminal b 1-bit positive phase signal (binary signal)
c Clock signal e Synchronous / asynchronous switching signal (control signal)

Claims (3)

Binary signal output means for outputting a binary signal representing the signal by binary values;
Switching amplification means for switching and amplifying the binary signal;
For each push-pull operation circuit of the switching amplification means, the binary signal output from the binary signal output means and input to the high-potential side or low-potential side switching element as a positive phase signal, and A positive-phase signal / negative-phase signal generating means that inputs the binary signal input to the switching element on the opposite polarity potential side to the switching element to which the positive-phase signal is input as a negative-phase signal;
In a digital amplifier comprising
The positive-phase signal / negative-phase signal generation means includes a first positive-phase signal / negative-phase signal generation means including a D flip-flop circuit having the binary signal output from the binary signal output means as an input signal, and the 2 A second positive-phase signal / negative-phase signal generating means including a pair of a buffer and an inverter having the binary signal output from the value signal output means as an input signal ;
Switching means for switching between a high quality mode for matching the switching timing of each switching element in the switching amplification means and a low power consumption mode for suppressing power consumption required for switching of each switching element, When operating, the binary signal output from the first positive phase signal / negative phase signal generation means is input to the switching amplification means as the positive phase signal or the negative phase signal, and the low power consumption When operating in the mode, switching means for inputting the binary signal output from the second positive phase signal / negative phase signal generating means to the switching amplification means as the positive phase signal or the negative phase signal. digital amplifier characterized in that it comprises.   The digital amplifier according to claim 1, wherein the switching amplification unit includes a full bridge circuit that performs switching amplification of the binary signal and performs balanced output. The switching means has the binary signal output from the first positive phase signal negative phase signal generation means and the second positive phase signal negative phase with respect to the input of each switching element of the switching amplification means. 3. The digital amplifier according to claim 1, further comprising a multiplexer that selects and outputs any one of the binary signals output from the signal generating means according to a control signal.

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