JP4040378B2 - Balanced output circuit for 1-bit amplifier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is a class D amplifier that performs high-efficiency power amplification of an acoustic signal by using a PDM (pulse Density Modulation) signal or a PWM (pulse Width Modulation) signal, and in particular, prevents the generation of an impact sound when the power is turned on or off. The present invention relates to a balanced output circuit having a muting function.
[0002]
[Prior art]
Conventionally, as a high-efficiency power amplifier as described above, a configuration including a balanced output circuit using positive-phase and negative-phase outputs has been put into practical use. This balanced output circuit will be described below.
[0003]
In an amplifier that drives a load with a single-phase output, the drive output of the load changes around a certain DC level with reference to the ground level. On the other hand, loads such as headphones and speakers are designed to vibrate based on a state in which no voltage is applied. For this reason, by passing a signal that changes around a certain DC level through the capacitor, only the AC component is extracted from the signal and applied to the load. At this time, since a low-pass filter is formed by a capacitor and a load (such as headphones) or a coil, in order to prevent the bass signal from being attenuated by setting the cutoff frequency of the low-pass filter sufficiently low, the capacitance of the capacitor Must be several thousand to several tens of thousands of μF. This not only increases the cost of the apparatus, but also makes it impossible to secure a space for arranging the capacitor in the portable device. Also, if the performance of the capacitor is poor, audio performance may be degraded even if the capacity is sufficient.
[0004]
For this reason, when the load is driven by obtaining normal-phase and reverse-phase outputs, the load does not change with a certain DC level centered on the ground level. Since it is connected to the negative phase output but not to the ground level, a signal that changes around 0 V as viewed from the load is input. For this reason, a capacitor required when a load is driven with a single-phase output becomes unnecessary, and cost reduction, sound quality degradation, and the like can be avoided.
[0005]
A conventional high-efficiency power amplifier including a balanced output circuit as described above has been put to practical use, for example, as an audio power amplifier disclosed in the March 2001 issue of transistor technology, p232. Hereinafter, such a high efficiency power amplifier will be described. 4 and 5 show a configuration example of a conventional high-efficiency power amplifier having a muting function.
[0006]
In the high-efficiency power amplifier shown in FIG. 4, for example, PWM signals are output from the 1-bit output terminals 102 and 103 of the ΔΣ block 101 as two 1-bit signals B1 and B2, respectively. The 1-bit signals B1 and B2 are the same positive phase output.
[0007]
The 1-bit signal B1 is input to EX (Exclusive) -OR gates 304 and 305 through a level shifter including a capacitor 301 and resistors 302 and 303, respectively. The EX-OR gates 304 and 305 are supplied with the power supply voltage V1 from the power supply terminal 306. The EX-OR 304 receives the power supply voltage V1 as the other input signal. The EX-OR 305 has the other input connected to the ground. It is connected.
[0008]
On the other hand, the 1-bit signal B2 is input to EX (Exclusive) -OR gates 401 and 402, respectively. The EX-OR gates 401 and 402 are supplied with the power supply voltage V2 from the power supply terminal 403 and the power supply voltage V2 is input as the other input signal.
[0009]
The EX-OR 304 outputs a signal having a phase opposite to that of the 1-bit signal B1, and the EX-OR 305 outputs a signal having the same phase as that of the 1-bit signal B1. The outputs of EX-ORs 304 and 305 are input to the gates of output transistors 501 and 502 which are N-channel MOS transistors, respectively. The output transistors 501 and 502 are supplied with the power supply voltage V3 from the power supply terminal 512 at their sources. On the other hand, the EX-OR 401 outputs a signal in phase opposite to the 1-bit signal B2, and the EX-OR 401 outputs a signal in phase with the 1-bit signal B2. The outputs of EX-ORs 402 and 401 are input to the gates of output transistors 503 and 504 that are N-channel MOS transistors, respectively.
[0010]
As a result, the output transistors 501 and 503 are alternately turned on and off alternately, while the output transistors 502 and 504 are alternately turned on and off at the opposite timing.
[0011]
The output taken out from the connection point of the output transistors 502 and 504 passes through the muting transistor 601 and is output as a positive phase output from the output terminal 509 through a low-pass filter including a coil 505 and a capacitor 507. On the other hand, the output taken out from the connection point of the output transistors 501 and 503 is output as a reverse phase output from the output terminal 510 through the muting transistor 602 and the low-pass filter including the coil 506 and the capacitor 508.
[0012]
The load resistor 511 is driven when one end is given a normal phase output from the output terminal 509 and the other end is given a negative phase output from the output terminal 510.
[0013]
In the above high-efficiency power amplifier, when the power is turned on or off, in particular, the output of the PWM signal from the 1-bit output terminals 102 and 103 by the ΔΣ block 101 is started simultaneously, or the outputs of both PWM signals are stopped simultaneously. When hitting, an impact sound such as “spot” is generated. In order to avoid the generation of such an impact sound, a so-called muting circuit by the following method has been used.
(1) Method of providing a muting transistor in parallel with the output transistor
(2) Method of providing a muting relay in parallel with the output transistor
In the method (2), a method is conceivable in which the output terminal is grounded for a certain period of time immediately after power-on or power-off.
[0014]
FIG. 4 shows an example of a muting circuit by the method (1).
[0015]
In this circuit, a muting control signal MUTE output from a mute output terminal 202 of a microcomputer (hereinafter referred to as a microcomputer) 201 is applied to the gates of muting transistors 601 and 602. The muting transistors 601 and 602 are turned on when the “H” (high level) muting control signal MUTE is applied, and the signals from the output transistors 502 and 503 are transmitted to the muting transistors 601 and 602 and subsequent ones. Disappear.
[0016]
FIG. 5 shows an example of the method (2). In this circuit, muting relays 603 and 604 are provided instead of the muting transistors 601 and 602, and the muting output terminal 202 of the microcomputer 201 is set to “H” at the time of muting. As a result, the coils of the muting relays 603 and 604 are excited and the muting relays 603 and 604 are turned on. As a result, signals are not transmitted from the output transistors 502 and 503 to the muting relays 603 and 604 and thereafter.
[0017]
As described above, in the circuits of FIGS. 4 and 5, by using a muting transistor or relay, signal transmission is interrupted to prevent the generation of an impact sound.
[0018]
[Problems to be solved by the invention]
However, in recent years, when the demand for miniaturization of equipment increases, the following problems occur in the muting circuits of FIGS. 4 and 5 that employ the methods (1) and (2), respectively.
[0019]
In the circuit of FIG. 4, the board on which the balanced output circuit is mounted is miniaturized as the equipment becomes portable. However, if the area of the muting transistors 601 and 602 on the board becomes too large to be ignored, The transistors 601 and 602 are not only one of the elements that increase the distortion, but also increase the cost.
[0020]
On the other hand, in the circuit of FIG. 5, the miniaturization of the muting relays 603 and 604 is also required with the miniaturization of the board on which the balanced output circuit is mounted. If the board is miniaturized so that the area occupied by the relay is not negligible, considering the mechanical reliability of the relay, other more reliable parts for disconnection will be required, which is also a factor in increasing costs. It was also.
[0021]
The present invention solves the above-described conventional problems, can reliably avoid the generation of impact noise when power is turned on and off without affecting the performance of the amplifier, and the substrate An object of the present invention is to provide a balanced output circuit that does not increase the area and cost.
[0022]
[Means for Solving the Problems]
The balanced output circuit for a 1-bit amplifier according to the present invention comprises two-sequence means for converting one sequence of binary signals into in-phase two-sequence signals; High Potential side output transistor pair A first high-potential side transistor and a second high-potential side transistor constituting Low potential side output transistor pair The first low potential side transistor and the second low potential side transistor, the first high potential side transistor and the first low potential side transistor are connected in series, and the second high potential side transistor and the A second low potential side transistor is connected in series, the first high potential side transistor and the second low potential side transistor are turned on, and the second high potential side transistor and the first low potential side transistor are turned on. To turn off the first high potential side transistor and the second low potential side transistor, and turn off the second high potential side transistor and the first low potential side transistor. To output a positive-phase signal. Output means having an H bridge circuit, high potential side output transistor driving means for driving the high potential side output transistor pair based on one of the two series signals, and the low potential based on the other of the two series signals 1-bit amplifier balanced output circuit having a low-potential-side output transistor driving means for driving a pair of side-side output transistors, when the 1-bit amplifier is turned on and off The command for stopping the output of the signal from the H bridge circuit is: By direct input only to the low potential side output transistor driving means, the low potential side output transistor driving means causes the low potential side output transistor pair to be connected based on a given command. on By doing so, regardless of one input / output state of the two series signals in the high potential side output transistor driving means, the driving means H bridge circuit The output of the signal from is stopped.
[0023]
In the above configuration, when a command is given to the driving unit, the driving unit stops signal output of the high-potential side and low-potential side output transistor pairs. Thereby, when the above-mentioned command is given to the driving means when the power is turned on and when the power is shut off, it is possible to avoid the generation of the impact sound at that time. Further, by shutting down the output operation of the high-potential side and low-potential side output transistor pair, a blocking component that prevents the signals output from the high-potential side and low-potential side output transistor pair from being transmitted to the subsequent circuit ( Transistors and relays are not required.
[0024]
In the above-described balanced output circuit, it is desirable that the driving unit turns off the low potential side output transistor pair based on the command.
[0025]
In the balanced output circuit, the H-bridge circuit includes a high-potential side output transistor pair (output transistors 501 and 502 in FIG. 1) and a low-potential side output transistor pair (output transistors 503 and 504 in FIG. 1). Therefore, by turning off the low-potential side output transistor pair as described above, the signal output of the high-potential side and low-potential side output transistor pair can be stopped regardless of the output state of the high-potential side output transistor pair. it can.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
One embodiment of the present invention will be described with reference to FIGS. 1 to 3 as follows. In the present embodiment, components having functions equivalent to those of the conventional amplifier shown in FIGS. 4 and 5 are denoted by the same reference numerals.
[0027]
FIG. 1 shows a configuration of a high-efficiency power amplifier including a balanced output circuit according to this embodiment.
[0028]
This balanced output circuit is mounted on, for example, a 1-bit amplifier, and includes a ΔΣ block 101, a microcomputer 201, a capacitor 301, resistors 302 and 303, EX-OR gates 304 and 305, a power supply terminal 306, an EX-OR gate, EX -OR gate 401, 402, power supply terminal 403, output transistors 501-504, N coils 505, 506, capacitors 507, 508, positive phase output terminal 509, negative phase output terminal 510, load resistor 511 and power supply terminal 512 are included. Yes. The power supply terminals 306, 403, and 512 are supplied with power supply voltages V1, V2, and V3, respectively.
[0029]
The ΔΣ block 101 includes a ΔΣ conversion circuit (not shown), and generates a PDM signal or a PWM signal as a series of binary signals from an input 16-bit digital signal. Further, the ΔΣ block 101 generates two series of 1-bit signals B1 and B2 (2 series signals) based on the generated binary signal, and outputs them from the 1-bit output terminals 102 and 103, respectively. The ΔΣ block 101 includes a D flip-flop 1011 and AND gates 1012 and 1013 in order to generate 1-bit signals B1 and B2.
[0030]
The D flip-flop 1011 outputs a 1-bit signal from the output terminal Q by sampling one series of binary signals input to the input terminal D with a clock input to the clock input terminal CK from the outside. The period of the clock is set to be sufficiently shorter than the pulse width of the binary signal for sampling.
[0031]
The AND gate 1012 outputs a logical product of the output from the output terminal Q of the D flip-flop 1011 and the output control signal S 1 from the microcomputer 201. The AND gate 1013 outputs a logical product of the output from the output terminal Q of the D flip-flop 1011 and the output control signal S 2 from the microcomputer 201. By setting the output control signal S1 to “H”, the 1-bit signal B1 is output via the AND gate 1012. By setting the output control signal S2 to “H”, the 1-bit signal B2 is output via the AND gate 1013. Is output. On the other hand, by setting the output control signals S1 and S2 to “L”, the output of the 1-bit signal from the output terminal Q is stopped, and the output terminals 102 and 103 are fixed to “L”.
[0032]
The microcomputer 202 is provided to control the operation of a device such as a 1-bit amplifier on which the balanced output circuit is mounted. The balanced output circuit is used during the muting operation period when the device is turned on and off. The “H” muting control signal MUTE is output as a command for causing the muting operation to be performed. Further, the microcomputer 202 outputs an “L” muting control signal MUTE when the balanced output circuit is normally operated.
[0033]
The microcomputer 202 outputs the 1-bit signal B2 after a sufficiently long time has elapsed from the output of the 1-bit signal B1 to the transient response time determined by a circuit described later including the capacitor 301 and resistors 302 and 303 that operate as a level shifter. Is output (in order to delay the output start of the 1-bit signal B2 from the output start of the 1-bit signal B1), the above-described output delay control signal DL is supplied to the ΔΣ block 101. Further, the microcomputer 202 controls the ΔΣ block 101 so that the 1-bit signals B1 and B2 of the ΔΣ block 101 are fixed to “L” as an initial setting (first step described later) when the power is turned on.
[0034]
The 1-bit signal B1 output from the 1-bit output terminal 102 is input to one input terminal of each of the EX-OR gates 304 and 305 via the capacitor 301. The other input terminal of the EX-OR gate 304 is connected to the power supply terminal 306, and the other input terminal of the EX-OR gate 305 is connected to the ground. Resistors 302 and 303 are connected in series between the power supply terminal 306 and the ground. The connection point of these resistors 302 and 303 is connected to the input terminal to which the 1-bit signal B1 of the EX-OR gates 304 and 305 is input. The EX-OR gates 304 and 305 are supplied with the power supply voltage V 1 from the power supply terminal 306.
[0035]
In order to turn on the upper (high potential side) transistor by stacking the Nch transistors in the vertical direction, a voltage higher than the voltage for turning on the lower (low potential side) transistor is required. Therefore, in order to drive the output transistors 501 and 502, a voltage higher than the power supply voltage V2 is necessary. For example, the power supply voltage V3 is 2V, and the voltage for turning on the output transistors 501 and 502 (the gate-source voltage V _GS ) Is 1V, the gate voltage needs to be 3V (= 2V + 1V). Therefore, it is necessary to set the output voltage of the EX-OR gates 304 and 305 to 3 V or more, and the threshold value for determining whether the EX-OR gates 304 and 305 are “H” or “L” of the input voltage accordingly. Is set high. However, the amplitude of the 1-bit signal B1 is only the same as the power supply voltage V3. For this reason, the EX-OR gates 304 and 305 do not operate normally as follows.
[0036]
As shown in FIG. 2A, when the power supply voltage V2 is 2.5V, the EX-OR gates 401 and 402 determine that the input voltage of 2V or higher is "H" and input of 0.5V or lower. The voltage is determined to be “L”. Since the output voltage from the ΔΣ block 101, which is the input voltage to the EX-OR gates 401 and 402, is a binary value of 0V and 2.5V, the EX-OR gates 401 and 402 have 2V with respect to these voltages. “H” can be determined with a threshold value of “L”, and “L” can be determined with a threshold value of 0.5V.
[0037]
On the other hand, as shown in FIG. 2B, if the power supply voltage V1 is 4V higher than the above 3V, the EX-OR gates 304 and 305 determine that the input voltage of 3V or more is “H”. An input voltage of 0.8 V or less is determined as “L”. However, since the output voltage from the ΔΣ block 101, which is the input voltage to the EX-OR gates 304 and 305, is a binary value of 0V and 2.5V as described above, the EX-OR gates 304 and 305 are 0V. “L” can be determined with a threshold of 0.8 V with respect to the input voltage of 2.5 V, but “H” cannot be determined because the input voltage of 2.5 V is lower than the threshold of 3 V.
[0038]
Therefore, by operating the capacitor 301 and the resistors 302 and 303 as a level shifter, the intermediate potential (2V) is set by setting the resistance value of the resistor 302 and the resistance value of the resistor 303 to the same value. When only an AC component having an amplitude of 2.5 V is applied to the intermediate potential via the above, as shown in FIG. 2B, the level of the 1-bit signal B1 is shifted without changing the amplitude of the 1-bit signal B1. Can do.
[0039]
Thereby, the input voltage to the EX-OR gates 304 and 305 is 3.25 V (= 2 + 2.5 / 2) on the high potential side around V1 / 2 (2 V), and 0.75 V (= The level is shifted to 2-2.5 / 2). Therefore, the EX-OR gates 304 and 305 can determine “H” for an input voltage equal to or higher than the threshold voltage of 3V and can determine “L” for an input voltage equal to or lower than the threshold voltage of 0.8V. Works correctly.
[0040]
The 1-bit signal B 2 output from the 1-bit output terminal 103 is input to one input terminal of each of the EX-OR gates 401 and 402. The other input terminals of the EX-OR gates 401 and 402 are connected to the power supply terminal 403. The EX-OR gates 401 and 402 are supplied with the power supply voltage V2 from the power supply terminal 403.
[0041]
The EX-OR gates 304 and 305 and the EX-OR gates 401 and 402 constitute a drive unit 300 as drive means for driving output transistors 501 to 504 described later.
[0042]
The sources of the output transistors 501 and 502 which are N channel MOS transistors are connected to the power supply terminal 512. The gate of the output transistor 501 is connected to the output terminal of the EX-OR gate 304, and the gate of the output transistor 502 is connected to the output terminal of the EX-OR gate 305. The output transistors 501 and 502 constitute a high potential side output transistor pair.
[0043]
The sources of the output transistors 503 and 504, which are N-channel MOS transistors, are connected to the drains of the output transistors 503 and 504, respectively, and the drains of the output transistors 503 and 504 are connected to the ground. The output transistors 503 and 504 constitute a low potential side output transistor pair.
[0044]
The configuration in which the output transistors 501 to 504 are connected as described above is an H bridge circuit. Further, the portion including the H bridge circuit and the power supply terminal 512 constitutes an output unit 500 as output means.
[0045]
The positive side end of the coil 505 is connected to the connection point of the output transistors 502 and 504, and the negative side end of the coil 505 is connected to the positive phase output terminal 509. On the other hand, the negative side end of the coil 506 is connected to the connection point of the output transistors 501 and 503, and the positive side end of the coil 506 is connected to the reverse phase output terminal 510. A capacitor 507 is connected between the negative side end of the coil 505 and the ground, and a capacitor 508 is connected between the positive side end of the coil 506 and the ground.
[0046]
The coil 505 and the capacitor 507 constitute a low pass filter. Similarly, the coil 506 and the capacitor 508 constitute a low pass filter.
[0047]
Further, a load resistor 511 is connected between the positive phase output terminal 509 and the negative phase output terminal 510. The load resistor 511 is generally configured by an electroacoustic transducer such as a speaker or headphones.
[0048]
The operation of the muting circuit configured as described above 3 This will be described with reference to the timing chart. Note that third to sixth steps described later proceed simultaneously.
[0049]
(1) First step
First, the microcomputer 201 outputs a muting control signal MUTE of “H” from the mute output terminal 202 by the initial setting. Further, the ΔΣ block 101 receives “L” 1 from the 1-bit output terminals 102 and 103 when the “L” output control signals S 1 and S 2 are given to the AND gates 1012 and 1013 by the initial setting of the microcomputer 201. Bit signals B1 and B2 are output. Therefore, the outputs EXOR3, 4 of the EX-OR gates 401, 402 are “H”. Therefore, the gates of the output transistors 503 and 504 are set to “H”, and the respective output transistors 503 and 504 are turned on. Therefore, regardless of the state of the outputs EXOR1, 2 of the EX-OR gates 304, 305, the transistor side of the coils 505, 506 is “L”, and no potential difference occurs between both ends of the load resistor 511 connected to the output. .
[0050]
(2) Second step
Next, when the “H” output control signal S1 is supplied to the AND gate 1012, a PWM signal, for example, is output from the 1-bit output terminal 102 as the 1-bit signal B1. At the start of output of the PWM signal, the outputs EXOR1 and EXOR2 from the EX-OR gates 304 and 305 are the correct positive phase signal and negative phase signal with a transient response determined by the circuit composed of the capacitor 301 and the resistors 302 and 303 operating as a level shifter. Don't be.
[0051]
However, during this time, the mute output terminal 202 continues to output the “H” muting control signal MUTE, and the output control signal S2 is maintained at “L”, so that the 1-bit output terminal 103 also outputs “L”. "1 bit signal B2" is output. As a result, the output transistors 503 and 504 are turned on when the gates become “H”. Accordingly, since “L” is maintained on the transistor side of the coils 505 and 506, no potential difference occurs between both ends of the load resistor 511 between the positive phase output terminal 509 and the negative phase output terminal 510.
[0052]
(3) Third step
Next, after a predetermined time from the start of output of the PWM signal from the 1-bit output terminal 102 (a time sufficiently longer than the transient response time in the second step (2)), the output control signal S2 is “ As a result, the PWM signal is output from the 1-bit output terminal 103 as the 1-bit signal B2. At the same time, an “L” muting control signal MUTE is output from the mute output terminal 202. As a result, the output EXOR3 from the EX-OR gate 401 becomes a signal having a phase opposite to that of the 1-bit signal B2 from the 1-bit output terminal 102.
[0053]
(4) Fourth step
The output EXOR4 of the EX-OR gate 402 is a positive-phase signal in phase with the 1-bit signal B1 from the 1-bit output terminal 102 by the PWM signal from the 1-bit output terminal 103 and the "L" muting control signal MUTE. Become.
[0054]
(5) 5th step
The output EXOR1 of the EX-OR gate 304 becomes a signal having a phase opposite to that of the PWM signal from the 1-bit output terminal 102 by the PWM signal from the 1-bit output terminal 102 and the power supply voltage of “H”. At this time, since a sufficiently long time has elapsed compared to the transient response time in the second step (2), a correct reverse phase signal is output.
[0055]
(6) Sixth step
The output EXOR2 from the EX-OR gate 305 becomes a positive-phase signal in phase with the PWM signal from the 1-bit output terminal 102 by the PWM signal from the 1-bit output terminal 102 and the “L” ground potential. At this time, since a sufficiently long time has elapsed compared to the transient response time in the second step, a correct positive phase signal is output.
[0056]
While the output transistors 501 and 503 are alternately turned on and off from the outputs EXOR1 to EXOR1 to the output transistors 501 to 504 from the EX-OR gates 304, 305, 401, and 402, they are output at the opposite timing. The transistors 502 and 504 are alternately turned on and off. A signal output from a connection point between the output transistors 502 and 504 passes through a low-pass filter including a coil 505 and a capacitor 507. On the other hand, a signal output from a connection point between the output transistors 501 and 503 passes through a low-pass filter including a coil 506 and a capacitor 508. The signals that have passed through the respective low-pass filters are given to the load resistor 511 via the positive phase output terminal 509 and the negative phase output terminal 510. As a result, the audio signal is output as sound by the load resistor 511.
[0057]
Further, by operating in the reverse order, it is possible to avoid the impact sound when the power is shut off.
[0058]
Specifically, when the 1-bit signal B2 is fixed to “L” and the muting control signal MUTE changes to “H”, the output transistors 503 and 504 have the gates of “H” as in the second step. Turn on by becoming "". Accordingly, since “L” is maintained on the transistor side of the coils 505 and 506, no potential difference occurs between both ends of the load resistor 511 between the positive phase output terminal 509 and the negative phase output terminal 510. When the 1-bit signal B1 is fixed to “L” after a sufficiently long time compared to the transient response time in the second step, and the muting control signal MUTE maintains “H”, the output transistor 503 , 504 also remain on, and the transistor side of the coils 505, 506 is maintained at "L", that is, the muting state (corresponding to the first step here).
[0059]
As described above, the balanced output circuit according to the present embodiment can avoid the impact sound when the power is turned on by directly inputting the muting control signal MUTE to the EX-OR gate 402. Further, since it is unnecessary to interpose components such as a muting transistor and a relay between the output transistors 501 to 504 and the coils 505 and 506, the cost of the balanced output circuit can be avoided and the balanced output can be avoided. Increasing the area of the board on which the circuit is mounted for mounting such components can be avoided.
[0060]
【The invention's effect】
As described above, the balanced output circuit for a 1-bit amplifier according to the present invention has two-sequence means for converting one sequence of binary signals into in-phase two-sequence signals. High Potential side output transistor pair A first high-potential side transistor and a second high-potential side transistor constituting Low potential side output transistor pair The first low potential side transistor and the second low potential side transistor, the first high potential side transistor and the first low potential side transistor are connected in series, and the second high potential side transistor and the A second low potential side transistor is connected in series, the first high potential side transistor and the second low potential side transistor are turned on, and the second high potential side transistor and the first low potential side transistor are turned on. To turn off the first high potential side transistor and the second low potential side transistor, and turn off the second high potential side transistor and the first low potential side transistor. To output a positive-phase signal. Output means having an H bridge circuit, high potential side output transistor driving means for driving the high potential side output transistor pair based on one of the two series signals, and the low potential based on the other of the two series signals Driving means having low potential side output transistor driving means for driving the pair of side output transistors, and at the time of turning on and turning off the power of the 1-bit amplifier The command for stopping the output of the signal from the H bridge circuit is: By direct input only to the low potential side output transistor driving means, the low potential side output transistor driving means causes the low potential side output transistor pair to be connected based on a given command. on By doing so, regardless of one input / output state of the two series signals in the high potential side output transistor driving means, the driving means H bridge circuit The output of the signal from is stopped.
[0061]
Thereby, it is possible to avoid an impact sound when the power is turned on and when the power is turned off without affecting the transmission path of the audio signal represented by the binary signal. Also, by stopping the output operation of the high-potential side and low-potential side output transistor pair, a blocking circuit (transistor or Relay) becomes unnecessary. Therefore, it is not necessary to secure such a part for a circuit breaker and an area for mounting the part on the substrate, and the balanced output circuit can be easily reduced in size and cost. In addition, since mechanical parts such as relays are not required, operational reliability can be improved.
[0062]
In the above balanced output circuit, the driving means turns off the low potential side output transistor pair based on the command, so that the high potential side output and the low potential side output are output regardless of the output state of the high potential side output transistor pair. The signal output of the transistor pair can be stopped. Therefore, there is an effect that it is possible to more easily avoid the generation of impact sound.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a balanced output circuit according to an embodiment of the present invention.
FIGS. 2A and 2B are timing charts showing the operation of the EX-OR gate in the balanced output circuit.
FIG. 3 is a timing chart showing the operation of the balanced output circuit.
FIG. 4 is a circuit diagram showing a configuration of a conventional balanced output circuit.
FIG. 5 is a circuit diagram showing a configuration of another conventional balanced output circuit.
[Explanation of symbols]
101 ΔΣ block (two series means)
202 Microcomputer
300 Drive unit (drive means)
500 Output unit (output means)
501,502 Output transistor (high potential side output transistor pair)
503, 504 Output transistor (low potential side output transistor pair)
MUTE Muting control signal (command)

Claims (1)

Two-sequence means for converting one sequence of binary signals into in-phase two-sequence signals;
A first high potential side transistor and a second high potential side transistor constituting a high potential side output transistor pair, and a first low potential side transistor and a second low potential side transistor constituting a low potential side output transistor pair, The first high potential side transistor and the first low potential side transistor are connected in series, the second high potential side transistor and the second low potential side transistor are connected in series, and the first high potential side transistor is connected to the first high potential side transistor. By turning on the potential side transistor and the second low potential side transistor and turning off the second high potential side transistor and the first low potential side transistor, a signal having a reverse phase is output, and the first high potential side transistor is output. A transistor and the second low potential side transistor are turned off; and the second high potential side transistor and the first low potential side An output means having an H-bridge circuit for outputting a signal of a positive phase by turning on the transistor,
High potential side output transistor driving means for driving the high potential side output transistor pair based on one of the two series signals, and a low potential for driving the low potential side output transistor pair based on the other of the two series signals In a balanced output circuit for a 1-bit amplifier comprising a driving means having a side output transistor driving means,
Control means for outputting a binary control signal for controlling the output of the signal from the H-bridge circuit;
The low-potential-side output transistor drive means uses the other of the two series signals and the power supply voltage as input signals, and outputs a signal after exclusive-OR operation to the second low-potential side transistor. A second exclusive OR that outputs the signal after the exclusive OR operation to the first low-potential side transistor, using the other of the two series signals and the control signal directly input from the control means as an input signal. Consisting of a gate,
When the 1-bit amplifier is turned on and off, the two-sequence means outputs the other of the two-sequence signals at a low level, and the control means outputs the control signal at a high level. the low potential side output transistor driving means, by turning on the pre-Symbol low potential side output transistor pair, irrespective of the one of the input and output states of the two series of signals in the high-potential-side output transistor drive means, said drive means A balanced output circuit for a 1-bit amplifier, wherein output of a signal from the H bridge circuit is stopped.

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