JP4330200B2 - Navigation device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  This inventionIs naConcerning vigation devices, especially devices that transfer data from a disk-shaped storage medium to a memory, and are suitable for in-vehicle devices that have severe operating environment conditionsNaThe present invention relates to a navigation device.
[0002]
[Prior art]
Conventionally, a direct memory access (DMA) system is known as a system for transferring data from a disk-shaped storage medium (for example, CD-ROM, DVD, etc.) to a memory. This is because the central processing unit (hereinafter referred to as “CPU”) designates the start address for storing data in the memory and the transfer size of the data to the DMA processing unit, and thereafter the data sent from the storage medium in order. Is a system in which the DMA processing unit transfers data continuously from a specified memory address without depending on the processing of the CPU.
[0003]
FIG. 11 is a block diagram showing a configuration of a conventional data transfer management device. Referring to the figure, the data transfer management device includes a CPU 101, a DMA processing unit 103, a memory 105, a disk reading device 107, and a disk 109.
[0004]
Based on a request from the CPU 101, data in a desired area of the disk 109 is transferred to a desired address in the memory 105 by the DMA processing unit 103.
[0005]
The CPU 101 requests the disk reader 107 to transfer data in a desired area of the disk 109 (data transfer request control). The disk reader 107 makes a data transfer request to the DMA processing unit 103. The DMA processing unit 103 permits data transfer to the disk reading device 107.
[0006]
The CPU 101 controls the DMA processing unit 103 and permits use of the bus. The DMA processing unit 103 outputs a transfer end notification and a bus use request to the CPU 101.
[0007]
The disk 109 is divided into a plurality of areas (for example, areas A to C), and data is stored in units of each area.
[0008]
Here, the data in the areas A1 and A2 which are part of the area A of the disk 109 are read, stored in the areas of the addresses WWW to WWW + L1 and the addresses XXXX to XXXX + L2 of the memory 105, respectively, and the data from the area C is stored. It is assumed that data is read and stored in the area of the address ZZZZ to ZZZZZ + N in the memory 105.
[0009]
That is, the data in the area B of the disk 109 is unnecessary data here.
[0010]
FIG. 12 is a diagram for explaining data exchange among the CPU 101, the memory 105, the DMA processing unit 103, and the disk reading device 107.
[0011]
First, in step (I), the CPU 101 sets a start address WWWW for storing data in the memory 105 and a transfer byte number L1 for the DMA processing unit 103. The CPU 101 requests the disk reader 107 to output L1 size (L1 byte) data from the beginning of the area A of the disk.
[0012]
In response to this request, the disk reader 107 shifts from the stopped state to the driven state. The head of the disk reader 107 moves immediately before the beginning of the area A and prepares for data reading. Thereafter, when the disk reading device 107 finishes reading the first sector at the beginning of the area A, data transfer is started.
[0013]
In step (II), the disk reader 107 requests the DMA processing unit 103 to transfer the first byte data. In response to this, the DMA processing unit 103 outputs a CPU bus use request to the CPU 101. The CPU 101 outputs a CPU bus use permission to the DMA processing unit 103.
[0014]
After that, the DMA processing unit 103 notifies the transfer destination address WWWW to the memory 105, while permitting data transfer to the disk reader 107. Thereafter, the first byte data is written into the memory 105 via the DMA processing unit 103 from the disk reader.
[0015]
At this time, the DMA processing unit 103 increments the transfer destination address by 1 and decrements the transfer byte count by 1. Thereafter, the process indicated by (1) in FIG. 12 is repeated. If the disk reading device 107 has finished reading L1 bytes of data, the rotation of the disk 109 is stopped.
[0016]
In step (III), a data transfer request for the L1 byte is sent from the disk reader 107 to the DMA processing unit 103, the DMA processing unit 103 outputs a CPU bus use request to the CPU 101, and the CPU 101 performs DMA processing. If the CPU bus use permission is output to the unit 103, the DMA processing unit 103 designates the address WWW + L 1 for the memory 105 and gives the data transfer permission to the disk reading device 107.
[0017]
Thereafter, the L1 byte data is written from the disk reader 107 to the memory 105 via the DMA processing unit 103. At this time, similarly to the portion indicated by (1), the transfer destination address is incremented by 1, and the transfer byte count is decremented by 1. When the transfer byte count is decremented by 1, it becomes “0”, so that the DMA processing unit detects that the data transfer is completed. In accordance with the detection result, the DMA processing unit 103 performs an interrupt process for completing the transfer to the CPU 101.
[0018]
The operations of steps (I) to (III) indicated by (2) in FIG. 12 are similarly performed on the start address XXXX and the start address ZZZ.
[0019]
That is, the CPU 101 sets the start address XXXX and the transfer byte number L2 to the DMA processing unit 103, and requests the disk reading device for L2 byte data from the position of the beginning of the area A + L1. Thereafter, the CPU 101 sets the start address ZZZ and the transfer byte number N to the DMA processing unit 103, and requests the disk reader to output data of N bytes from the head of the area C.
[0020]
By this operation, the data in the areas A1 and A2 of the disk 109 are stored in the areas of the addresses WWW to WWW + L1 and the addresses XXXX to XXXX + L2 of the memory 105. Further, the data in the area C is stored in the areas of the addresses ZZZZZ to ZZZZZ + N in the memory 105.
[0021]
[Problems to be solved by the invention]
However, the conventional data transfer management device has the following problems.
[0022]
[Problem 1]
In the conventional data transfer management device, since it is necessary to transfer the discontinuous data area of the disk-shaped storage medium to the discontinuous memory area, the data transfer request to the disk and the control frequency of the DMA processing unit are high. CPU overhead is high.
[0023]
In particular, map data used in a navigation device or the like is stored in the concept of mesh, and map data required by the CPU is often stored in a disc-like and discrete state. Therefore, in order to request only necessary data from the storage medium, it is necessary to make a plurality of data transfer requests.
[0024]
On the other hand, since data calculation is also performed on the CPU side based on the concept of mesh, unnecessary data is discretely generated when the map display is moved on the screen. In other words, since the memory usage efficiency deteriorates, only the necessary data is collected in a continuous area as appropriate, and a large memory continuous space is secured to enable the next data transfer. There is a need.
[0025]
However, when garbage collection is performed, CPU processing time is used for data reduction. On the other hand, the use of a memory management unit (MMU) that performs conversion between logical addresses and physical addresses eliminates such time for data reduction. However, when MMU is used, the free space of the memory is divided into discrete pieces. Therefore, there is a demerit that the control frequency of the DMA processing unit is increased.
[0026]
[Problem 2]
When data is read while repeatedly moving the pickup at a short distance in a disk shape, more time is required than when data is read all at once including unnecessary portions.
[0027]
When the moving distance of the pickup is short, the time until the focus is adjusted and the data reading at the designated place becomes possible is longer than the time for moving the pickup to the required place. Therefore, if data reading of only a necessary part is performed while performing a short distance movement a plurality of times, a longer time is required than when data reading is continuously performed in a lump including unnecessary parts.
[0028]
However, reading data collectively including unnecessary data means that the memory use efficiency deteriorates. Further, when using the MMU, it is often impossible to secure such a continuous physical address area on the memory.
[0029]
[Problem 3]
In the navigation device, the stress applied to the motor of the data reading device is greater than that of a personal computer or the like.
[0030]
In a navigation device, map data divided in a mesh shape is read and data processing is performed. Therefore, there are few cases of reading a large amount of continuous data from a disk-shaped storage medium. That is, data that is close to each other is often read discontinuously from a disk-shaped storage medium. For this reason, the motor that controls the position of the pickup in data reading repeats start-up, high-speed rotation, low-speed rotation during read-out, and stop, and the frequency of start-up and stop that causes stress on the motor increases.
[0031]
Therefore, the motor in the navigation apparatus is likely to be worn and broken among the components used. In particular, when a navigation device is mounted on a vehicle, the conditions of the operating environment such as temperature and vibration are poor, and it is necessary to consider that the motor is not stressed as much as possible.
[0032]
[Problem 4]
The conventional data transfer management device has a problem that the CPU bus utilization efficiency is low because the data bus width of the memory is wider than the data bus width of the data transferred from the storage medium.
[0033]
That is, the bit width of data transferred from the disk reader is 8 bits or 16 bits, but recently, 32-bit CPUs are often used as navigation devices become more sophisticated. That is, the data width of the memory is 32 bits. Therefore, when the data bus width of the storage medium is 8 bits, the effective portion in one DMA transfer is 1/4 of the CPU data bus, which is wasteful.
[0034]
  Accordingly, an object of the present invention is to perform efficient data transfer.NaIt is to provide a vigination device.
[0035]
  Another object of the present invention is to increase the processing speed.InnaIt is to provide a vigination device.
[0036]
  Still another object of the present invention is to reduce the stress applied to the apparatus.NaIt is to provide a vigination device.
[0037]
  Still another object of the present invention is to enable effective data transfer.NaIt is to provide a vigination device.
[0038]
[Means for Solving the Problems]
  In order to achieve the above object, according to one aspect of the present invention,navigationThe device
  A navigation device that can be mounted on a vehicle,
  Data from disk-shaped storage mediaofReadDisk readerWhen,
  SaidDisc readerReaddiddataThe casePayMemory,
  A DMA processor connected to and controlling each of the disk reader and the memory;
  A central control device connected to each of the disk reading device, the memory and the DMA processing unit for controlling the entire device;
  Storage means for storing at least one command including a transfer address of data, a size of data to be transferred, and a flag for controlling transfer;
  The memory is connected to the disk reading device via the DMA processing unit separately from a route connected to the disk reading device via the central control unit, and from the disk reading device via the DMA processing unit. Writing data to the memory can be performed independently of the operation of the central control unit,
  The storage means stores at least one of the transfer address of the data and the size of the data to be transferred in a simplified manner, and the command stored in a simplified manner can be read by one read operation. Yes,
  The disk reader reads continuous data including unnecessary data from the disk-shaped storage medium,
  The DMA processing unit
    A register that temporarily latches data from the disk reader;
    Of the data read by the disk reader based on the command stored in the storage means, store the data in the memory excluding the unnecessary data,
    When the register latches data corresponding to the data bus width of the central controller, the latched data is transferred.The
[0039]
  According to the present invention, from a disk-shaped storage mediumtransferContinuous data reading including unnecessary data is performed,transferSince data excluding unnecessary data is stored in the memory, efficient data transfer is possible.KiThe processing speed is fast and the stress on the device can be reduced.navigationAn apparatus can be provided.
[0041]
  TheIn additionWhen the register latches data for the data bus width of the central control unit, in order to transfer the latched data,Data can be transferred effectivelyRu.
  Further, since one command can be read by one reading operation, more efficient processing can be performed.
[0042]
Preferably, the central processing unit outputs endian control information, and the storage order of data in the register is changed based on the endian control information.
[0043]
According to the present invention, in addition to the above effects, data can be easily transferred even when the endian is different.
[0048]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
FIG. 1 is a block diagram showing a configuration of a navigation device provided with a data transfer management device according to the first embodiment of the present invention.
[0049]
Referring to the figure, the navigation device is composed of a CPU 101 that controls the entire device, a ROM 109 that stores a program executed when the device is activated, a GPS, a vehicle speed detection unit, a gyro sensor, and the like. A position detection unit 111 that detects the current position of the vehicle, a display 113 that displays a map of the vicinity of the vehicle superimposed on the current position of the vehicle, an input device 115 that inputs the destination of the vehicle, and a disk-shaped storage A memory 105 for storing data from the medium and a transfer command data string to be described later, a DMA processing unit 103 for controlling direct memory access to the disk-shaped storage medium and the memory 105, and reading data from the disk-shaped processing medium , And an output disk reading device 107.
[0050]
Since the memory 105 and the DMA processing unit 103 are connected to each other, and the DMA processing unit 103 and the disk reading device 107 are connected to each other, data writing from the disk reading device 107 to the memory 105 via the DMA processing unit 103 is performed by the operation of the CPU 101. Can be done independently.
[0051]
FIG. 2 is a block diagram showing a configuration of a data transfer management device included in the navigation device of FIG. The data transfer management device according to the present embodiment is characterized in that the memory 105 includes a transfer command data string storage unit 105a (FIG. 3) as compared with the conventional device shown in FIG.
[0052]
The transfer command data string includes at least one transfer command data. One transfer command data includes transfer byte number information, transfer destination address information, and a transfer control flag.
[0053]
Here, the transfer byte number information is information indicating the size of data to be transferred, and the transfer destination address information is information regarding an address in the memory 105 in which the data is stored.
[0054]
The transfer control flag is a flag for controlling the transfer state. When it is “00”, the data read from the disk 109 is stored in the memory 105 as it is.
[0055]
When the transfer control flag is “10”, the data read from the disk 109 is not stored in the memory 105.
[0056]
When the transfer control flag is “01”, the data read from the disk 109 is stored in the memory 105 as it is. At this time, all processing is completed when reading and storage are completed.
[0057]
Transfer byte number information (for example, l1) and transfer destination address information (for example, www) in the transfer command data string are converted into an actual transfer byte number (for example, L1) and a physical address (for example, WWWW) by the DMA processing unit 103, respectively. .
[0058]
FIG. 3 is a diagram for explaining a conversion method between transfer byte number information and transfer destination address information.
[0059]
In this embodiment, the data of the transfer destination address and the number of transfer bytes are simplified to the transfer destination address information and the transfer byte number information and stored in the memory. As a result, the amount of memory used for storing the command string can be reduced, and the DMA processing unit 103 can acquire all the information necessary for the data transfer process in one memory access.
[0060]
For example, when processing information such as map data, the data is generally managed in a specific unit. Therefore, the data amount cannot take any value.
[0061]
For example, data is managed in units of 2 to the power of 2 such as 256 bytes, 512 bytes, and 1024 bytes. Accordingly, the transfer destination address and the number of transfer bytes are also set as a multiple of such a unit. That is, all the lower bits of the set value are “0”.
[0062]
Even in a CPU with an address bus of 32 bits (4 Gbyte space), the memory area actually used for data transfer is only in the range of 8 Mbytes and 16 Mbytes. For this reason, the upper bits of the transfer destination memory address are fixed values. Therefore, this fixed value may be stored in the DMA processing unit 103.
[0063]
For the above reasons, when setting the transfer destination address, the upper bit and the lower bit are not required, and the lower bit is not required when setting the number of transfer bytes. Therefore, it is possible to edit the transfer command data string only in each necessary portion and acquire all information necessary for data transfer by reading the memory once.
[0064]
2 and 3, when the data management unit is 1024 bytes and the address space used for data transfer is 16 Mbytes, as shown in FIG. 4, transfer byte number information 11 and transfer destination address information wwww It is possible to convert the actual transfer byte number L1 to the transfer destination address (physical address) WWWW.
[0065]
On the other hand, the data management unit in the disk is also determined. For example, when a CD-ROM is used as a disk, one sector is 2048 bytes, and the data transfer amount from the disk reading device is a value of 2048 × n.
[0066]
Therefore, when the data management unit on the CPU side is 1024 bytes as in the above example, even if the necessary data is 1024 bytes, it is necessary to transfer 2048 bytes of data. This may cause unnecessary data to be stored in the memory. However, in this embodiment, even in such a case, by setting the transfer command data string so that the data is not stored in the memory, only necessary data below the management unit of the disk reading device can be transferred to the memory. And the memory can be used effectively.
[0067]
FIGS. 5 to 7 are diagrams showing a data flow among the CPU 101, the DMA processing unit 103, and the disk reader 107 when the transfer command data string shown in FIG. 2 is set.
[0068]
According to the transfer command data sequence shown in FIG. 2, of the continuous data areas A, B, and C in the disk, the data in the area A (data size L bytes) is an XXXX address corresponding to the L1 size from the physical address WWW address of the memory. To L2 size (here, L = L1 + L2) is transferred, and the data of area C (data size N bytes) is further transferred from memory area ZZZ for N size.
[0069]
Area B (data size M bytes) is unnecessary data.
Here, it is assumed that the CPU data bus is 32 bits, the local bus width is 8 bits, and the endian is little endian.
[0070]
5 to 7, in step (I), CPU 101 stores a command string from address AAAA in memory 105. The CPU 101 sets the head address of the command string in the DMA processing unit 103. The CPU 101 requests the disk reader 107 to output data for the L1 size from the beginning of the area A.
[0071]
In step (II), the DMA processing unit 103 transmits a CPU bus use request to the CPU 101. The CPU 101 outputs a CPU bus use permission to the DMA processing unit 103. The DMA processing unit 103 outputs an address AAAA to the memory 105 and reads data at the address from the memory 105.
[0072]
Based on the read data, the DMA processing unit 103 converts the transfer destination address information wwww to the physical address WWWW, and sets it as the transfer destination address. Also, the transfer byte number information l1 is converted into the actual transfer byte number L1 and set as the byte number. Further, the transfer control flag “00” is set inside based on the read data. Then, the command string address is set to AAAA + 4.
[0073]
At this time, the disk reader 107 finishes reading the first sector at the beginning of the area A and starts data transfer.
[0074]
In step (III), the disk reader 107 outputs a data transfer request for the first byte to the DMA processing unit 103. In response to this, the DMA processing unit 103 outputs a CPU bus use request to the CPU 101. The CPU 101 outputs a CPU bus use permission to the DMA processing unit 103.
[0075]
The DMA processing unit 103 outputs an address WWWW to the memory 105 and outputs a data transfer permission to the disk reading device 107. Then, the first byte of data is transferred from the disk reader 107 to the memory 105 via the DMA processing unit 103, and the data is written. Then, the DMA processing unit 103 increments the transfer destination address by 1, and decrements the transfer byte count by 1. Thereafter, the process indicated by (3) in FIG. 5 is repeated.
[0076]
The disk reader 107 continues to operate after reading L1 worth of data.
[0077]
In step (IV), the disk reader 107 outputs a data transfer request for the L1 byte to the DMA processing unit 103. The DMA processing unit 103 outputs a bus use request to the CPU, and the CPU 101 outputs a CPU bus use permission to the DMA processing unit 103.
[0078]
Thereafter, the DMA processing unit 103 outputs an address WWW + L1 to the memory 105, and grants data transfer permission to the disk reading device 107.
[0079]
The L1 byte data is transferred from the disk reader 107 to the memory 105 via the DMA processing unit 103, and data is written.
[0080]
Here, when the transfer byte count is decremented by 1 to “0”, the DMA processing unit 103 detects that the first command processing has been completed.
[0081]
Next, the DMA processing unit 103 converts the transfer destination address information xxx into the physical address XXXX based on the data read from the command string address AAAA + 4, and sets it as the transfer destination address. Also, the transfer byte number information 12 is converted into the actual transfer byte number L2 and set as the byte number. Also, the transfer control flag “00” is set inside. In this state, the process (4) in FIG. 5 is performed.
[0082]
Next, in step (V), the DMA processing unit 103 outputs a CPU bus use request to the CPU 101. The CPU 101 transmits a CPU bus use permission to the DMA processing unit 103.
[0083]
The DMA processing unit 103 outputs an address AAAA + 8 to the memory 105 and reads data from the memory 105. Based on the read data, the DMA processing unit 103 converts the transfer destination address information yyyy into a physical address YYYY and sets it as a transfer destination address. Also, the transfer byte count information m is converted into the actual transfer byte count M and set as the byte count. Further, the transfer control flag “10” is set inside. Further, the command string address is AAAA + 12.
[0084]
At this time, the disk reader continuously reads the data in the area B even after the data in the area A is read.
[0085]
In step (VI), the disk reading device 107 outputs a data transfer request for the first byte in area B to the DMA processing unit 103. In response to this, the DMA processing unit 103 transmits data transfer permission to the disk reading device 107. The disk reading device 107 transmits the first byte data to the DMA processing unit 103 based on the data transfer permission.
[0086]
However, since the transfer control flag is set to “10” in this process, the data transfer process to the memory 105 is not performed. As a result, data is read from the disk reader 107, but no data is stored in the memory 105.
[0087]
Each time one piece of data is transferred, the DMA processing unit 103 increments the transfer destination address by 1 and decrements the transfer byte count by 1.
[0088]
Then, the process shown in (5) of FIG. 6 is repeated. Even after the reading of the data in the area B is completed, the disk reading device 107 continuously reads the data in the area C.
[0089]
If the M byte data transfer request is transmitted from the disk reading device 107 to the DMA processing unit 103, the DMA processing unit 103 grants the data transfer permission to the disk reading device 107. Based on this, the disk reader 107 transfers the Mth byte data to the DMA processing unit 103.
[0090]
The DMA processing unit 103 detects that the third command processing has been completed by detecting that the result of decrementing the transfer byte count by 1 is “0”.
[0091]
Next, in step (VII), the DMA processing unit 103 outputs a CPU bus use request to the CPU 101. In response to this, the CPU 101 outputs a CPU bus use permission to the DMA processing unit 103.
[0092]
The DMA processing unit 103 reads the data by outputting the address AAAA + 12 to the memory 105. The DMA processing unit 103 converts the transfer destination address information zzzz into a physical address ZZZZ and sets it as a transfer destination address. Also, the transfer byte count information n is converted into the actual transfer byte count N and set as the byte count. Further, the transfer control information flag “01” is set inside. The command string address is AAAA + 16.
[0093]
In step (VIII), the disk reading device 107 outputs a transfer request for data of the first byte in area C to the DMA processing unit 103. In response to this, the DMA processing unit 103 outputs a CPU bus use request to the CPU 101.
[0094]
The CPU 101 outputs a CPU bus use permission to the DMA processing unit 103. In response to this, the DMA processing unit 103 outputs the address ZZZZ to the memory 105 and gives the disk reader 107 data transfer permission.
[0095]
When the first byte data is transferred from the disk reader 107 via the DMA processing unit 103, the data is written into the memory 105.
[0096]
The DMA processing unit 103 increments the transfer destination address by 1 and decrements the transfer byte count by 1.
[0097]
Thereafter, the process shown in (6) of FIG. 7 is repeated.
The disk reader 107 stops the rotation of the disk after reading the data in the area C. Thereafter, in step (IV), the disk reader 107 outputs a transfer request for the Nth byte data to the DMA processing unit 103. In response to this, the DMA processing unit 103 outputs a CPU bus use request to the CPU 101. The CPU 101 outputs a CPU bus use permission to the DMA processing unit 103.
[0098]
The DMA processing unit 103 transmits the address ZZZZZ + N to the memory 105 and gives permission to transfer data to the disk reading device 107.
[0099]
The disk reading device 107 transfers the Nth byte data to the memory 105 via the DMA processing unit 103. As a result, data is written to the memory 105.
[0100]
The DMA processing unit 103 detects that the fourth command processing has been completed based on the result of decrementing the transfer byte count by 1 being 0. Since the transfer control flag is “01”, the end of the command string is determined, and all the processes are ended. The end of all processes is notified to the CPU 101 by interruption.
[0101]
As described above, according to the present embodiment, the discontinuous memory area has a discontiguous area of the disc based on the issuance of a command to the DMA processor and a data request to the disc reader once. Data can be transferred.
[0102]
Here, it seems that the CPU control load is generated because the DMA control command sequence is prepared in advance. However, even in the conventional divided DMA transfer method, in any part of the memory, any disk-like area Information on whether to transfer the data is naturally stored in an arbitrary part of the memory. Therefore, in the creation of the command sequence this time, the form and order of writing the command sequence information are simply changed, and the processing load on the CPU does not increase as compared with the conventional technology.
[0103]
[Second Embodiment]
The second embodiment is characterized in that the DMA transfer processing unit temporarily takes data from the disk reading device into a data latch register. Data transfer is performed when data corresponding to the CPU bus width is stored in the data latch register.
[0104]
In the following, portions of the navigation device according to the second embodiment of the present invention that are different from those of the first embodiment will be described.
[0105]
FIG. 8 is a diagram illustrating an internal configuration of the DMA processing unit 103 according to the second embodiment of the present invention. Referring to the figure, a DMA processing unit 103 includes a command string address counter 103a that stores an address of a transfer command to be executed, a data transfer destination address counter 103b that records a transfer destination address, and transfer control that stores a transfer control flag. By latching the 8-bit data sent from the disk reader 107 four times, the flag register 103c, the bus control unit 103d, the data transfer number counter 103e for counting the number of transferred data bytes , A data latch register 103f that generates and outputs 32-bit data, and a selector 103g.
[0106]
FIG. 9 is a diagram for explaining the operation of the data latch register 103f and the selector 103g of the DMA processing unit 103.
[0107]
In the figure, the portion indicated by (7) corresponds to the operation of repeating the operation of (3) in FIG. 5 or (6) in FIG. 7 four times.
[0108]
That is, as shown in FIG. 9, in the present embodiment, the number of times data is written to the memory is ¼ compared to the first embodiment. Therefore, since the frequency of using the CPU data bus is reduced due to the data transfer, the CPU data bus can be used effectively accordingly.
[0109]
More specifically, with reference to FIG. 9, the disk reader 107 outputs a 4i byte data transfer request to the DMA processing unit 103. In response to this, the DMA processing unit 103 permits data transfer to the disk reading device 107. The disk reader 107 outputs the 4i-th byte data to the DMA processing unit processing unit 103.
[0110]
The DMA processing unit 103 stores the transferred data in bits 7 to 0 of the data latch register 103f composed of 32 bits. Then, the transfer destination address is incremented by 1, and the transfer byte count is decremented by 1.
[0111]
Next, the disk reader 107 outputs a 4i + 1 byte data transfer request to the DMA processing unit 103. When the DMA processing unit 103 outputs data transfer permission to the disk reading device 107, the disk reading device 107 transfers the 4i + 1 byte data to the DMA processing unit 103.
[0112]
Then, the DMA processing unit 103 stores data in bits 15 to 8 of the data latch register 103f. Thereafter, the transfer destination address is incremented by 1, and the transfer byte count is decremented by 1.
[0113]
Next, the disk reader 107 outputs a 4i + 2 byte data transfer request to the DMA processing unit 103. When data transfer permission is given from the DMA processing unit 103 to the disk reading device 107, the disk reading device 107 transfers the 4i + 2 byte data to the DMA processing unit 103.
[0114]
The DMA processing unit 103 stores data in bits 23 to 16 of the data latch register 103f. Thereafter, the transfer destination address is incremented by 1, and the transfer byte count is decremented by 1.
[0115]
Next, the disk reader 107 issues a 4i + 3 byte data transfer request to the DMA processing unit 103. When the transfer of data from the DMA processing unit 103 to the disk reading device 107 is permitted, the 4i + 3rd byte data is transferred from the disk reading device 107 to the DMA processing unit 103.
[0116]
The DMA processing unit 103 stores data in bits 31 to 24 of the data latch register 103f.
[0117]
Thereafter, the DMA processing unit 103 outputs a CPU bus use request to the CPU 101. When the CPU 101 permits the CPU processing unit 103 to use the bus of the CPU, the DMA processing unit 103 outputs the address JJJJ to the memory 105 and writes data. Thereafter, the DMA processing unit 103 increments the transfer destination address by 1 and decrements the transfer byte count by 1.
[0118]
In FIG. 9, the case where little endian is set is described. However, when big endian is set as endian information in the DMA processing unit, the order of data transfer and data storage in the data latch register are described. The positional relationship is changed. More details
4i byte data → bits 31-24 of data latch register
4i + 1 byte data → bits 23 to 16 of data latch register
4i + 2nd byte data → bit 15 to 8 of data latch register
4i + 3rd byte data → data latch register bits 7-0
It becomes. By storing data in this order, endian conversion can be easily performed.
[0119]
In this manner, the endian conversion processing by the CPU can be made unnecessary by outputting the endian information by the CPU and changing the data storage order in the register based on the output.
[0120]
[Modification]
The command sequence shown in FIG. 10 may be used as the transfer command data sequence.
[0121]
The command sequence shown in FIG.
(1) Transfer L1 bytes of data to the transfer destination physical address WWW,
(2) Transfer L2 bytes of data to the transfer destination physical address XXXX,
(3) Data having a transfer byte count of M bytes is transferred only from the disk reader to the DMA processing unit and is not stored in the memory (YYYY is set as a dummy transfer destination address. Any value)
(4) This is a command sequence for performing batch processing of transferring data of the number of transfer bytes of N bytes to the transfer destination physical address ZZZ.
[0122]
The operation of the DMA processor in this case is as follows:
(1) The command data amount (command information amount) is read from the address AAAA, and the extent on the memory is identified as the data representing the command string.
[0123]
(2) The data transfer destination physical address as the first command is read from the AAAA + 4 address and set in the internal transfer address counter.
[0124]
(3) The number of data transfer bytes of the first command is read from the AAAA + 8 address and set in the internal transfer byte number counter.
[0125]
(4) Read information on the necessity of writing transfer data from the disk reading device of the first command to the memory from AAAAA + 12 and set it in the internal flag register.
[0126]
(5) When the first command is completed, the data transfer destination physical address as the second command is read from the AAAA + 16 address and set in the internal transfer address counter.
[0127]
(6) The number of data transfer bytes as the second command is read from the address AAAA + 20 and set in the internal transfer byte number counter.
[0128]
(7) From the address AAAA + 24, information on the necessity of writing transfer data from the disk reading device of the second command to the memory is read and set in the internal flag register.
[0129]
Thereafter, the same operation is repeated, and when the processing of the command string data having the command information amount read first is finished, it is determined that all commands are finished.
[0130]
In this embodiment, a circuit for storing and calculating the command information amount in the DMA transfer processing unit is required. By adding 1 bit to the transfer control flag portion whether or not the data stored at the next address means a command string for the DMA transfer processing unit, the memory usage is reduced, and the DMA transfer processing unit It is also possible to easily determine the end of the command string.
[0131]
[Effects of the embodiment]
The above-described embodiment has the following effects.
[0132]
The CPU can transfer the data in the disc-like discontinuous area to the discontinuous memory area by performing control once for each of the DMA processing unit and the disc reader. Thereby, the effect of reducing the processing load on the CPU is great.
[0133]
Further, unnecessary data is not written in the memory, and transfer processing can be performed only by the local bus during transfer of unnecessary data, so that the use efficiency of the data bus of the CPU is not affected at all.
[0134]
In addition, in the case of data reading over a short distance of the disk, since there is no data reading overhead, the data transfer time can be shortened.
[0135]
Furthermore, since the motor for moving the pickup of the disk reader can be continuously operated at a stable speed, the wear of the motor is reduced and the life of the motor can be extended.
[0136]
In the second embodiment, the difference between the CPU data bus width and the disk reader data bus width can be absorbed by the data latch register. As a result, the use frequency of the CPU data bus can be reduced as compared with the conventional data transfer, and the use efficiency of the CPU data bus is improved.
[0137]
Further, when endian conversion processing is performed, the difference between the data stored in the storage medium and the endian of the CPU can be absorbed. Further, endian conversion processing by the CPU can be eliminated.
[0138]
In addition, the transfer start address, the number of transfer bytes, and transfer control information can be obtained by reading the command data from the memory once, and the DMA processing unit can also be configured easily.
[0139]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a navigation device according to a first embodiment of the present invention.
2 is a block diagram showing a configuration of a data transfer management device included in FIG. 1. FIG.
FIG. 3 is a diagram illustrating a specific example of a transfer command data string.
FIG. 4 is a diagram for explaining processing for converting transfer byte count information and transfer destination address information into transfer byte count and transfer destination address;
FIG. 5 is a diagram for explaining the operation of the data transfer management device;
FIG. 6 is a diagram following FIG. 5;
FIG. 7 is a diagram subsequent to FIG. 6;
FIG. 8 is a block diagram illustrating a configuration of a data transfer management device according to a second embodiment.
FIG. 9 is a diagram for explaining the operation of the data transfer management device according to the second embodiment;
FIG. 10 is a diagram for explaining a modification of the embodiment.
FIG. 11 is a block diagram showing a configuration of a conventional data transfer management device.
FIG. 12 is a diagram for explaining the operation of a conventional data transfer management device.
[Explanation of symbols]
101 CPU
103 DMA processor
105 memory
107 Disc reader
109 discs

Claims (2)

A navigation device that can be mounted on a vehicle,
A disk reader for reading data from a disk-shaped storage medium;
The data to which the disk reader is reading a memory which store,
A DMA processor connected to and controlling each of the disk reader and the memory;
A central control device connected to each of the disk reading device, the memory and the DMA processing unit for controlling the entire device;
Storage means for storing at least one command including a transfer address of data, a size of data to be transferred, and a flag for controlling transfer ;
The memory is connected to the disk reading device via the DMA processing unit separately from a route connected to the disk reading device via the central control unit, and from the disk reading device via the DMA processing unit. Writing data to the memory can be performed independently of the operation of the central control unit,
The storage means stores at least one of the transfer address of the data and the size of the data to be transferred in a simplified manner, and the command stored in a simplified manner can be read by one read operation. Yes,
The disk reader reads continuous data including unnecessary data from the disk-shaped storage medium,
The DMA processing unit
A register that temporarily latches data from the disk reader;
Of the data read by the disk reader based on the command stored in the storage means, store the data in the memory excluding the unnecessary data,
A navigation device that transfers the latched data when the register latches data for the data bus width of the central control device. The navigation device according to claim 1 , wherein the central processing unit outputs endian control information, and a storage order of data in the register changes based on the endian control information.

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