JP4327078B2 - Detection circuit - Google Patents

Description

The present invention relates to a detection circuit that inputs a high-frequency signal received by an antenna and detects a waveform corresponding to the amplitude.
In particular, in mobile communication devices such as ETC, RFID, DSRC, smart plate, etc., it is used for an activation signal output circuit (wake-up circuit) that outputs an activation signal for normal operation of a receiving circuit when a high frequency signal is received. It is valid.

  Conventionally, as shown in Patent Document 1 below, wake-up circuits in mobile communication such as ETC, RFID, DSRC, and smart plate are known. The main issue of the wake-up circuit is that the power consumption at the time of sleeping is low, and therefore it can be driven at a low voltage.

  In order to achieve this object, in Patent Document 1, as shown in FIG. 6 of the present application, a differential amplifier circuit having a pair of a transistor Tr83 and a transistor Tr84, and a transistor Tr80 for making the emitter current of this circuit constant. , Tr85 and a current mirror circuit. Then, a first series connection circuit including a diode Tr81 in which transistors are diode-connected, a detection diode Tr82 and a capacitor C81, and a second series connection circuit including diodes Tr91 and Tr92 and a capacitor C91 having the same characteristics as these. The high-voltage side terminals of the capacitors C81 and C91 are connected to the bases of the transistors Tr83 and Tr84. A high-frequency signal received by the antenna is input to the anode of the detection diode Tr82 via the matching circuit 50 including the series capacitor C100.

  This high frequency signal is rectified by the action of the detection diode Tr82 and the capacitor C81, and a voltage having a waveform corresponding to the amplitude of the high frequency signal appears in the capacitor C81. On the other hand, the terminal voltage of the capacitor C91 indicates a value when no high frequency signal is input. The terminal voltages of these capacitors C81 and C91 are differentially amplified by the pair of transistors Tr83 and Tr84, and a waveform corresponding to the amplitude of the high-frequency signal whose potential difference between the collectors of these transistors is to be detected is the next stage. It is output to the processing circuit.

Among the above-described conventional circuits, the series capacitor C100, the diode Tr81, the detection diode Tr82, and the parallel impedance R of the resistor R81 and the input impedance of the transistor Tr83 included in the matching circuit constitute an equivalent circuit as shown in FIG. However, the power supply voltage Vcc applied to the diode Tr81 is a power supply for applying a bias to each diode and the transistors Tr83 and Tr84, and is equivalent to ground for a high-frequency signal. In this circuit, when a high frequency signal is input, it is clearly a voltage doubler circuit for the high frequency signal. In an ideal state ignoring loss and leakage, the voltage across the capacitor C81 is the amplitude of the high frequency signal. Will be twice the value. That is, in the half cycle of the high frequency signal, the series capacitor C100 is charged to the peak value of the high frequency signal through the diode Tr81, and in the next half cycle, the capacitor C81 is connected to the voltage across the terminals of the series capacitor C100 through the detection diode Tr82. The battery is charged up to a value obtained by adding the peak value of the high-frequency signal. In this way, since the capacitor C81 can obtain a voltage twice the amplitude of the high-frequency signal, there is an advantage that the sensitivity of the detection circuit is improved.
JP 2004-194301 A

  However, in the circuit shown in FIG. 6, between the power supply Vcc and the chassis ground (hereinafter simply referred to as “earth”), a diode Tr81, a detection diode Tr82, a base-emitter of the transistor Tr83, and a first transistor Tr80. Are connected in series. At this time, the voltage drop of the pn junction through which current flows in the forward direction is about 0.7V, and when the power supply voltage is 2V, the base potential of the transistor Tr83 constituting the differential amplifier is 0.6V. However, the base-emitter voltage of the transistor Tr83 requires 0.7 V. However, considering the voltage drop between the collector and emitter of the transistor Tr80, a sufficient bias voltage is not applied to the transistor Tr83. As a result, there has been a problem that a sufficient amplification factor cannot be obtained in the differential amplifier circuit, and the sensitivity is not improved in low voltage driving.

  Therefore, an object of the present invention is made to solve this problem, and even if the configuration of a voltage doubler rectifier circuit is adopted, a sufficient amplification factor can be obtained in low voltage driving. It is to be.

According to a first aspect of the present invention, there is provided a reference transistor for controlling a current in a detection circuit that receives a predetermined high-frequency signal from an antenna and detects a value corresponding to the amplitude thereof. , A current mirror circuit comprising a plurality of subordinate transistors that pass the same amount of current as that flowing through the reference transistor, a pnp / p-channel first transistor, a pnp / p-channel second transistor, And a first subordinate transistor which is one of subordinate transistors disposed between the connection point and the power source, and a collector / source of the first and second transistors. A differential amplifier circuit comprising a load disposed between the drain and the ground; and a first diode disposed in the forward direction between the power source and the ground. And a first series connection circuit composed of a detection diode for inputting a high frequency signal arranged in the forward direction and a first capacitor, and a second diode arranged in the forward direction between the power source and the ground. a second series circuit comprising a third diode and a second capacitor disposed in a direction, is connected to the connection point between the first diode and the detector diode, and outputs a high frequency signal received from the antenna to the detection diode, A matching circuit including a third capacitor inserted in series in the transmission line; a second slave transistor that is one of slave transistors connected between a connection point between the detection diode and the first capacitor and the ground; And a third subordinate transistor that is one of subordinate transistors connected between the connection point of the three diodes and the second capacitor and the ground, and the connection point of the detection diode and the first capacitor is connected to the first transistor. The base / gate is connected, the connection point between the third diode and the second capacitor is connected to the base / gate of the second transistor, and the collector / drain of the first transistor and the collector / drain of the second transistor of the differential amplifier circuit The voltage difference between the two is output as a value corresponding to the detected amplitude.

  The current mirror circuit includes a reference transistor inserted in a circuit for controlling current, and a subordinate transistor that acts to flow the same amount of current as the load current of the reference transistor by inputting a bias voltage of the reference transistor. It is configured. The number of subordinate transistors is arbitrary, and by inserting the subordinate transistor into a circuit provided between the power source and the ground, the current flowing through the circuit can be controlled to a predetermined current value flowing through the reference transistor. The present invention has a function of controlling the sum of the emitter / source currents of the first transistor and the second transistor constituting the differential amplifier circuit to be constant.

  The circuit composed of the third capacitor, the first diode, the detection diode, and the first capacitor constitutes a voltage doubler rectifier circuit in which the voltage between the terminals of the first capacitor is a voltage that is twice the amplitude of the high frequency signal. Similarly, a circuit composed of the third capacitor, the second diode, the third diode, and the second capacitor constitutes a voltage doubler rectifier circuit. However, since no high frequency signal is input to the anode of the third diode, the terminal voltage of the second capacitor provides a background reference voltage in a state where no high frequency signal is input.

The present invention is characterized in that both the first transistor and the second transistor constituting the differential amplifier are pnp / p-channel transistors. With this configuration, as will be described later, even when the driving voltage is 2 V, a sufficient bias voltage can be applied to the first transistor and the second transistor.

  Note that as a transistor or a transistor forming a diode, a field effect transistor (FET) or the like can be used in addition to a bipolar transistor. In the above, emitter / source means an emitter for a bipolar transistor and a source for an FET. Similarly, collector / drain means collector for bipolar transistors and drain for FETs. Similarly, base / gate means base for bipolar transistors and gate for FETs. In any case, both are parts having the same function in the transistor action.

The present invention also provides a second subordinate transistor that is one of subordinate transistors connected between a connection point between the detection diode and the first capacitor and the ground, and a connection point between the third diode and the second capacitor. And a third dependent transistor which is one of the dependent transistors connected to ground .

  In other words, this configuration is characterized in that a predetermined current mirror current is supplied to the series connection circuit of the first diode and the detection diode, so that both diodes are operated with bias. Similarly, a predetermined current mirror current is supplied to a series connection circuit of the second diode and the third diode.

According to a second aspect of the present invention, the load includes a first load transistor connected between the collector / drain of the first transistor and the ground, and a second load connected between the collector / drain of the second transistor and the ground. An active load comprising a load transistor, wherein the base / gate of the first load transistor is connected to the base / gate of the second load transistor, and the collector / drain of the first load transistor or the second load transistor is connected to the base / gate. The detection circuit according to claim 1, wherein the detection circuit is a detection circuit.
With this configuration, the current flowing through both load transistors is the same amount.

  According to the first aspect of the present invention, by making the first transistor constituting the differential amplifier circuit pnp type, the series voltage drop of 1.4 V between the first diode and the detection diode is reduced to the base / gate of the first transistor. Bias voltage. That is, the true bias voltage between the base / gate and the emitter / source of the first transistor is obtained by subtracting the voltage drop between the emitter / source and the collector / drain of the first subordinate transistor from the series voltage drop of 1.4V. Voltage. This voltage drop is determined by the operating states of the load transistors Tr15 and Tr25, the first transistor Tr13, and the second transistor Tr23, and can take a sufficiently low value. Therefore, a voltage of 0.7 V can be applied between the base / gate and the emitter / source of the first transistor. As a result, the first transistor can ensure a sufficient amplification factor. The same applies to the second transistor. Therefore, according to the present invention, the circuit can be driven even with a low power supply voltage of about 2V.

  In addition, since the detection diode is connected to the base / gate of the first transistor, the load of the detection diode becomes high impedance. Thus, the time constant can be increased and high sensitivity can be realized.

According to the second aspect of the present invention, the current mirror circuit functions by the action of the second dependent transistor and the third dependent transistor, and the first diode, the detection diode, the second diode, and the third diode have a predetermined value. Current mirror current flows, so that a predetermined stable bias state is obtained. As described above, the sensitivity can be increased by using the detection diode in a biased state.
According to the third aspect of the present invention, since the load of the differential amplifier circuit is an active load composed of transistors connected through which the same amount of current mirror current flows, high gain can be obtained.

Hereinafter, the present invention will be described based on specific examples.
However, the embodiments of the present invention are not limited to the following examples.

  FIG. 1 is a circuit diagram of a detection circuit 100 in the present embodiment. A differential amplifier circuit is configured by parallel connection of the pnp-type first transistor Tr13 and the pnp-type second transistor Tr23. The sources of the first transistor Tr13 and the second transistor Tr23 are connected at a connection point a, and a first subordinate transistor Tr31, which is one component of the current mirror circuit, is disposed between these sources and the power supply Vcc. Has been. A load transistor Tr15 and a load transistor Tr25, which are active loads, are connected between the drains of the first transistor Tr13 and the second transistor Tr23 and the ground, respectively. The drain and gate of the load transistor Tr15 are connected to each other, and the same bias voltage is applied to the load transistor Tr15 and the load transistor Tr25. By this current mirror connection, the same amount of current flows through the two transistors.

  On the other hand, a first series connection circuit of a first diode Tr11 connected in the forward direction, a detection diode Tr12 connected in the forward direction, and a first capacitor C11 is disposed between the power supply Vcc and the ground. The first diode Tr11 and the detection diode Tr12 are constituted by diode-connected transistors in which a base and a collector are connected. A connection point b between the detection diode Tr12 and the first capacitor C11 is connected to the gate of the first transistor Tr13. Further, a second subordinate transistor Tr14 constituting a current mirror circuit is connected between the connection point b and the ground.

  Similarly, a second series connection circuit of a second diode Tr21 connected in the forward direction, a third diode Tr22 connected in the forward direction, and the second capacitor C21 is disposed between the power supply Vcc and the ground. . The second diode Tr21 and the third diode Tr22 are also constituted by transistors having a diode connection structure. A connection point c between the third diode Tr22 and the second capacitor C21 is connected to the gate of the second transistor Tr23. Further, a third dependent transistor Tr24 constituting a current mirror circuit is connected between the connection point c and the ground.

  A matching circuit 10 including a series capacitor C <b> 10 is connected to the anode of the detection diode Tr <b> 12, and the matching circuit 10 is connected to the antenna 11. The current mirror circuit includes a reference transistor Tr34 that determines a current value, a first subordinate transistor Tr31, a second subordinate transistor Tr14, and a second subordinate transistor Tr14 that are connected in parallel to the reference transistor Tr34 so as to have the same bias as the reference transistor Tr34. 3 subordinate transistors Tr24, subordinate transistor Tr33, and subordinate transistor Tr32. However, the dependent transistor Tr33 and the dependent transistor Tr32 are connected in series, and the dependent transistor Tr32 is a pnp type transistor. Only the first transistor Tr13, the second transistor Tr23, the first dependent transistor Tr31, and the dependent transistor Tr32 are pnp type, and the other transistors are all npn type. The drain and gate of the subordinate transistor Tr32 are connected to each other. A current determined by the subordinate transistor Tr33 flows in the subordinate transistor Tr32, and the source and the gate are self-biased so that the current flows.

  Since the drain voltage of the dependent transistor Tr32 is applied to the gate of the first dependent transistor Tr31, the bias voltages between the source and gate of the first dependent transistor Tr31 and the dependent transistor Tr32 become equal. As a result, the current flowing through the first dependent transistor Tr31 is equal to the current flowing through the reference transistor Tr34. Since the base-emitter voltage of the second dependent transistor Tr14 and the third dependent transistor Tr24 is equal to the base-emitter voltage of the reference transistor Tr34, the same amount of current as that flowing through the reference transistor Tr34 flows through each of these transistors. The current mirror circuit is configured in this way.

  Next, the operation of the detection circuit 100 will be described. The high frequency signal received by the antenna 11 is input to the anode of the detection diode Tr12 through the matching circuit 10. The high-frequency signal is rectified by the detection diode Tr12 and charges the first capacitor C11. By this action, the voltage across the first capacitor C11 becomes a value corresponding to the amplitude (envelope) of the high frequency signal. In other words, the charging and discharging time constants of the charging circuit are set to be values corresponding to the amplitude of the high frequency signal in the steady state during the reception period of the modulated high frequency signal. On the other hand, since the high frequency signal does not flow through the second series connection circuit, the voltage across the second capacitor C21 does not increase. That is, the inter-terminal voltage of the second capacitor C21 indicates the background rectified voltage when no high frequency signal is received. The voltage difference between the two is amplified by the differential amplifier circuit, and is output as a voltage difference between the drains of the first transistor Tr13 and the second transistor Tr23 to the amplification unit 200 (FIG. 3) at the next stage.

  Incidentally, the series capacitor C10, the first diode Tr11, the detector diode Tr12, and the first capacitor C11 included in the matching circuit 10 constitute the voltage doubler rectifier circuit shown in FIG. For this reason, the terminal voltage of the first capacitor C11 is twice the amplitude of the high-frequency signal. As a result, the difference between the two inputs to the differential amplifier circuit is doubled, and the sensitivity is improved.

  Next, the bias voltage of each transistor when the voltage of the power supply Vcc is 2V will be described. Since a constant current mirror current is supplied to the first diode Tr11 and the detection diode Tr12 by the action of the first dependent transistor Tr14, each voltage drop of the first diode Tr11 and the detection diode Tr12 is 0.7V. Therefore, the gate voltage of the first transistor Tr13 (voltage at the connection point b) is 2V−2 × 0.7V = 0.6V. However, since the first transistor Tr13 is a pnp type transistor, the gate bias voltage with respect to the emitter side (or Vcc side) is 1.4V. When a conventional npn-type transistor is used as the first transistor, the gate bias voltage of this transistor is 0.6 V, and a sufficient bias voltage cannot be applied. As a result, when the power supply voltage Vcc is 2 V, This detection circuit will not operate.

  If the power supply voltage Vcc is 2.8V, the total voltage drop 1.4V of the first diode Tr11 and the detection diode Tr12 becomes 1/2 of the power supply voltage Vcc, and the npn type is used for the first transistor Tr13. Even if the pnp type is used, both have the same gate bias voltage. However, when the power supply voltage Vcc is lower than 2.8 V, the gate bias voltage of the first transistor Tr13 is higher in the pnp type than in the npn type, and the gain can be increased. The same applies to the second transistor Tr23.

  Thus, in the present invention, the first transistor Tr13 and the second transistor Tr23 constituting the differential amplifier circuit are pnp-type, so that the power supply voltage Vcc can be lowered. It can be in an operable state at 2V.

  The first dependent transistor Tr31 and the dependent transistor Tr32 are pnp type, and a series connection circuit of the dependent transistor Tr32 and the dependent transistor Tr33 is provided, and the bias circuit as shown in the figure is configured by the first transistor Tr13 and the second transistor Tr23. This is because the pnp type is configured.

  In FIG. 1, the first transistor Tr13, the second transistor Tr23, the first subordinate transistor Tr31, and the load transistors Tr15 and Tr25 constituting the differential amplifier circuit are FETs, and the other transistors are bipolar transistors. All of these transistors are bipolar. Also in this case, the target transistor to be a pnp type is the same as that shown in FIG.

  FIG. 3 shows an example in which the differential output of the detection circuit 100 shown in FIG. 1 is input to the amplification unit 200 at the next stage. In the circuit of FIG. 3, as shown in FIG. 4, a high-frequency signal with a frequency of 5.8 GHz is output at a power of −60 dBm, 781.25 μs, twice as long, and output for the same period. A high frequency signal of ASK modulation was used as an input signal. At the time of this input signal, in the circuit of FIG. 3, the output Vout1 of the differential amplifier circuit of the detection circuit 100 and the output Vout2 of the final stage of the amplifier unit 200 were obtained by simulation. The result is shown in FIG. It is understood that when the power supply voltage Vcc is 1.8 V and the power supply current is 11.14 μA, a voltage difference of 0.018 V is obtained at Vout1 and a voltage difference of 1.1 V is obtained at Vout2. In this way, the detection circuit of the present invention operates with sufficient sensitivity.

  The present invention can be applied to any circuit that wakes up by receiving a high-frequency signal. The present invention can be driven at an extremely low voltage and can greatly reduce the current consumption during standby, and thus is extremely effective for use in mobile communication devices such as ETC, RFID, DSRC, and smart plate.

1 is a circuit diagram of a detection circuit according to an embodiment of the present invention. The circuit diagram of the detection circuit concerning the other example of this invention 1 is a circuit diagram of a device having a detection circuit and an amplification unit according to an embodiment of the present invention. Schematic diagram showing the high-frequency signal input to the detector circuit Output signal waveform diagram showing simulation results of this circuit Circuit diagram of conventional detector circuit Conventional detection circuit and equivalent circuit showing the rectification part of the detection circuit of the present invention

DESCRIPTION OF SYMBOLS 10 ... Matching circuit 11 ... Antenna Tr13 ... 1st transistor Tr23 ... 2nd transistor Tr11 ... 1st diode Tr12 ... Detection diode Tr21 ... 2nd diode Tr22 ... 3rd diode Tr31 ... 1st dependent transistor Tr14 ... 2nd dependent transistor Tr24 ... Third subordinate transistor Tr34 ... reference transistor C11 ... first capacitor C21 ... second capacitor 100 ... detection circuit 200 ... amplifying unit

Claims (2)

In a detection circuit that inputs a predetermined high-frequency signal from an antenna and detects a value according to its amplitude,
A current mirror circuit comprising a reference transistor for controlling the current and a plurality of subordinate transistors for supplying the same amount of current as that flowing through the reference transistor;
A pnp / p-channel first transistor, a pnp / p-channel second transistor, and the emitters / sources of the first and second transistors are connected, and are arranged between the connection point and the power supply. A differential amplifier circuit comprising: a first subordinate transistor that is one of the subordinate transistors provided; and a load disposed between a collector / drain of the first and second transistors and a ground;
A first series connection circuit comprising a first diode disposed in the forward direction between the power source and the ground, a detection diode for inputting the high-frequency signal disposed in the forward direction, and a first capacitor;
A second series connection circuit comprising a second diode disposed in the forward direction, a third diode disposed in the forward direction, and a second capacitor between the power source and the ground ;
A matching circuit including a third capacitor connected to a connection point between the first diode and the detection diode, outputting the high-frequency signal received from an antenna to the detection diode, and inserted in series in a transmission path;
A second subordinate transistor that is one of the subordinate transistors connected between a node between the detection diode and the first capacitor and ground;
A third subordinate transistor that is one of the subordinate transistors connected between a connection point of the third diode and the second capacitor and a ground;
A connection point between the detection diode and the first capacitor is connected to a base / gate of the first transistor;
A connection point between the third diode and the second capacitor is connected to a base / gate of the second transistor;
A detection circuit that outputs a voltage difference between the collector / drain of the first transistor and the collector / drain of the second transistor of the differential amplifier circuit as a value corresponding to the detected amplitude. The load includes a first load transistor connected between the collector / drain of the first transistor and the ground, and a second load transistor connected between the collector / drain of the second transistor and the ground. The base / gate of one load transistor is connected to the base / gate of the second load transistor, and the active load is connected to the collector / drain of the first load transistor or the second load transistor and the base / gate. The detection circuit according to claim 1 .