JP4318993B2 - 薄膜半導体装置の製造方法 - Google Patents
薄膜半導体装置の製造方法 Download PDFInfo
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- JP4318993B2 JP4318993B2 JP2003311197A JP2003311197A JP4318993B2 JP 4318993 B2 JP4318993 B2 JP 4318993B2 JP 2003311197 A JP2003311197 A JP 2003311197A JP 2003311197 A JP2003311197 A JP 2003311197A JP 4318993 B2 JP4318993 B2 JP 4318993B2
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- film
- photoresist
- thin film
- exposure
- semiconductor device
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- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
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Description
2,44…フォトレジスト膜、
2a…ゲート電極パターン、
3,41…シリコン膜、
4…露光マスク、
21…レーザ、
22…音響光学変調器(AOM)、
23…音響光学偏光器(AOD)、
24…半透過ミラー、
25…集光レンズユニット、
26…モニタ、
27…ガス供給源、
30…ステージ、
31…X軸駆動モータ、
32…Y軸駆動モータ、
33,34…レーザ干渉計、
42…ゲート絶縁膜、
43…導電体膜、
43a…ゲート電極。
Claims (3)
- 基板上に半導体膜を形成する工程と、
前記半導体膜をパターニングする工程と、
前記基板及び前記半導体膜上にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上に導電体膜を形成する工程と、
前記導電体膜上にフォトレジスト膜を形成する工程と、
前記フォトレジスト膜をレーザ直接描画露光装置により露光する露光工程と、
前記フォトレジスト膜を現像処理する工程と、
前記現像処理後に残存する前記フォトレジスト膜をマスクとして前記導電体膜をエッチングし、ゲート電極を形成する工程とを有し、
前記露光工程において、前記半導体膜の上方の前記フォトレジスト膜を露光するときにはレーザビームの焦点位置を前記フォトレジスト膜の厚さ方向の中央に合わせ、前記半導体膜がない部分の前記フォトレジスト膜を露光するときにはレーザビームの焦点位置を前記フォトレジスト膜の厚さ方向の中央からずれた位置に合わせることを特徴とする薄膜半導体装置の製造方法。 - 前記ゲート電極のうち前記半導体膜の上方の部分は、それ以外の部分よりも幅が狭いことを特徴とする請求項1に記載の薄膜半導体装置の製造方法。
- 前記ゲート電極のうち前記半導体膜の上方の部分の幅が1μm未満であることを特徴とする請求項1に記載の薄膜半導体装置の製造方法。
Priority Applications (1)
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JP2003311197A JP4318993B2 (ja) | 2003-09-03 | 2003-09-03 | 薄膜半導体装置の製造方法 |
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JP2003311197A JP4318993B2 (ja) | 2003-09-03 | 2003-09-03 | 薄膜半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2005079502A JP2005079502A (ja) | 2005-03-24 |
JP4318993B2 true JP4318993B2 (ja) | 2009-08-26 |
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Application Number | Title | Priority Date | Filing Date |
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JP2003311197A Expired - Fee Related JP4318993B2 (ja) | 2003-09-03 | 2003-09-03 | 薄膜半導体装置の製造方法 |
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JP (1) | JP4318993B2 (ja) |
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2003
- 2003-09-03 JP JP2003311197A patent/JP4318993B2/ja not_active Expired - Fee Related
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JP2005079502A (ja) | 2005-03-24 |
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