JP4313226B2 - Pulse width adjustment device - Google Patents

Description

  The present invention relates to a pulse width adjusting device, and more particularly to a device for adjusting the pulse width of a data write clock such as a magneto-optical recording / reproducing device.

Digital circuits such as a CPU operate on the basis of a reference clock generated by a clock generation circuit. The pulse width of the reference clock has a range in which normal operation is guaranteed by the device. When a pulse width outside the range is given to the device, normal operation of the device is not guaranteed.
In recent years, in order to increase the operation speed, the frequency of the reference clock is increased and the allowable range of the pulse width tends to be narrowed.
In general, the reference clock varies depending on the operating environment such as temperature and voltage, but if the pulse width of the reference clock exceeds an allowable range, the operation of the device becomes unstable.

  In addition, the reference clock generated by the clock generation circuit is rarely supplied directly to the logic circuit, and usually the reference clock is supplied via a delay element in order to obtain a desired timing and pulse width. However, since the delay time fluctuates due to variations in delay elements, this also causes unstable operation. In view of this, various delay control circuits have been proposed in consideration of such delay variations (for example, Patent Documents 1 and 2).

FIG. 1 is a block diagram showing the configuration of an embodiment of a conventional pulse width adjusting circuit. This pulse width adjustment circuit is mainly composed of the following elements.
(1) A calibration circuit 11 (Cal Pulse Gen) that generates a calibration pulse (Calibrate-pls) based on a given reference clock (CLK),
(2) Selector 12 (Sel) for selecting one of the two input pulses,
(3) Delay circuit 13 (Delay Element String) for generating pulses (Tap1 to N) delayed for a certain time,
(4) Delay state holding circuit 14 (REG) that holds a delay pulse at the rising edge of the clock,
(5) An encoder 15 (Encoder Logic) that counts the number of held delay pulses and outputs the value (ENC0);
(6) a selection circuit 16 (multiplexer MUX) for selecting a delay pulse corresponding to the delay amount DLYSEL during normal operation;
(7) Delay element 18 (Delay B) having the same delay time as MUX 16;
(8) An AND element 17 that takes a logical product of the pulse CLK1 output from the MUX 16 and the pulse CLK2 output from the delay element 18.
However, an OR element or the like may be used as the element 17 as necessary.

The clock CLKW output from the AND element 17 is a signal that is output at a desired timing as designed and whose pulse width is adjusted, and is used, for example, as a write clock for an optical recording / reproducing apparatus. .
This conventional pulse adjustment circuit is first operated in the calibration mode in which the delay time is measured using the calibration circuit 11, and then operated in the normal mode using the adjusted pulse.
In the “calibration mode”, an ideal delay amount of a pulse at the time of design and an actual pulse deviation are measured, and how much delay is delayed in the normal mode to obtain an ideal delay amount.

FIG. 2 shows an ideal timing chart of the conventional calibration mode.
Originally, a delay always occurs in the circuits 11 and 12, but when the delay by these circuits is sufficiently small to be negligible with respect to the cycle of the clock CLK, an ideal time chart as shown in FIG. 2 is obtained.
2, when calibration signal (calibrate) is input to the calibration circuit 11, at the rising edge A ₀ of the clock CLK, the pulse from the calibration circuit 11 of the clock one period (Calibrate-pls) is output.
When this pulse (Calibrate-pls) passes through the selector 12 and is input to the delay circuit 13, tap pulses (Tap1 to Tap9) delayed by a predetermined time are sequentially output. FIG. 2 shows a case where N = 9, and a total of 10 tap pulses are output with a time T offset.

In the next timing of the rising A ₁ of the clock CLK, the delay state holding circuit REG14, given the latches tap pulse encoder 15, the encoder 15, the numerical data ENC0 corresponding to the number of pulses at the high state Is output.
In FIG. 2, the output value ENC0 of the encoder is 6. By looking at the encoder output value ENC0, it can be understood how many taps of delay are required in one clock cycle. That is, the output value ENC0 means a passing TAP per clock cycle.

Assuming that the delay time for 1 TAP is “T”, this time T is obtained by the following equation (Equation 1).
Delay time (T) for 1 TAP clock = 1 clock cycle (T _o ) /
Number of passing TAPs per clock cycle (ENC0)
According to FIG. 2, it means that the output value of the encoder should be 6 in the ideal state as shown in FIG. 2 in the calibration mode.

FIG. 3 shows an ideal timing chart of the conventional normal mode. In the normal mode, the calibration signal Calibrate is operated in the low state. At this time, the clock CLK passes through the selector 12 and is directly input to the delay circuit 13, and tap pulses (Tap 1 to Tap 9) as shown in FIG. 3 are output from the delay circuit 13. These tap pulses (Tap0 to Tap9) including the output Tap0 of the selector 12 are given to the delay state holding circuit REG14 and the selection circuit MUX16.
In addition, a delay setting value (DLYSEL) given from a microcomputer (MPU) (not shown) or the like is input to the selection circuit MUX16, and a tap pulse having a tap number corresponding to this DLYSEL value is selected. The selected tap pulse is output from the MUX 16 as the clock CLK1.
In the case of FIG. 3, since “2” is set as DLYSEL, the tap pulse Tap2 is selected, and Tap2 is output as it is from the MUX 16 as the clock CLK1.

On the other hand, the Delay B18 is a delay element having the same delay time as the MUX 16, but a clock CLK2 as shown in FIG. 3 is output. Then, the AND circuit 17 ANDs the clock CLK1 output from the MUX 16 and the clock CLK2 that has passed through the Delay B18, and outputs the clock CLKW whose pulse width has been adjusted.
The number of taps obtained in the calibration mode of FIG. 2 was “6” for one clock cycle. In the normal mode of FIG. 3, the DLYSEL value corresponding to the number of taps for delay is set to “2”. ing.
That is, the clock CLK1 is a clock delayed by 33% (2 / 6≈0.33) with respect to the original clock CLK. In an ideal case as shown in FIG. The clock CLKW corresponding to the delay amount (33%) is output. For example, the clock CLKW is used as a data write clock signal for the recording / reproducing apparatus.

Here, the “shift amount (%)” set by the setting value DLYSEL that determines the delay amount of the clock is obtained by the following equation (Equation 2).
Shift amount (%) = DLYSEL value / number of passing TAPs per clock cycle

JP 2002-334434 A JP 2002-16492 A

Conventionally, when the length of one cycle of the clock CLK is sufficiently large with respect to the delay time T of the tap pulse, that is, when the frequency of the write clock is low, the delay amount of the calibration circuit 11 and the selector 12 can be ignored. Thus, even if the delay amount slightly fluctuated, the write pulse CLKW was hardly affected.
However, as the recording / reproducing apparatus increases in speed and density, it is required to increase the frequency of the write clock. When the length of one cycle of the reference clock CLK becomes shorter, the calibration circuit 11 And the delay amount of the selector cannot be ignored. That is, only a slight delay amount deviation occurs in the calibration circuit 11 and the like, and the period of the output write clock is found, which causes a great inconvenience in the recording / reproducing process.

The operation when such an unexpected delay occurs will be described below.
FIG. 4 shows a timing chart when a delay occurs in the conventional calibration mode.
Compared with the ideal case of FIG. 2, the output pulse (Calibrate-pls) of the calibration circuit 11 and the output pulse Tap0 of the selector 12 are delayed with respect to the clock CLK.
In Figure 2, the rising A _o of the clock CLK, the pulse (Calibrate-pls) had risen almost simultaneously, in FIG. 4, a pulse (Calibrate-pls), only rising A _o than the time T _c of the clock CLK It shows the state of standing up with a delay.
Further, FIG. 4 shows a state in which the tap pulse Tap0 which is the output of the selector 12 is also delayed, and the tap pulse Tap0 rises with a delay of time T _s from the pulse (Calibrate-pls).

In the case of FIG. 4, since the tap pulse Tap0 is delayed, the other tap pulses (Tap1 to Tap9) generated by the delay circuit 13 are also delayed compared to the ideal case of FIG.
Therefore, when the high level tap pulse is counted at the timing of the next rising edge A ₁ of the clock CLK, the result is 4 in the case of FIG. 4, and the output value ENC0 of the encoder 15 should ideally be “6”. , “4”. That is, the number of passing TAPs per clock cycle is measured as “4”.
The reason why the delay amount obtained during calibration changes in this way is that a delay (Tc and Ts) is generated by the calibration circuit 11 and the selector 12.
When the clock shift amount is set to 25%, using the measurement result in the calibration mode (ENC0 = 4), it can be seen from the above-described equation 2 that the value of DLYSEL should be “1”.

FIG. 5 shows a time chart when the operation is performed by shifting the clock by 25% in the normal mode. However, in FIG. 5, the clock pulse CLKW has a delay amount of about 17% instead of the desired delay amount of 25%. This is caused by the delay (Tc and Ts) of the calibration circuit 11 and the selector 12. In general, if these two delays are taken into consideration, it is necessary to determine the clock shift amount (%) using the following equation 3 instead of equation 2.
Shift amount (%) = DLYSEL value /
(Number of passing taps per clock cycle + Tc + Ts)

However, both the delay Tc generated in the calibration circuit 11 and the delay Ts generated in the selector 12 fluctuate due to changes in temperature and power supply voltage. Therefore, since the value of the denominator in Equation 3 varies, it is necessary to change the DLYSEL value in order to obtain a desired shift amount.
However, in reality, it is difficult to make the value of Equation 3 constant according to changes in temperature and voltage, and the conventional method cannot set an accurate pulse width corresponding to the delay.

  Therefore, the present invention has been made in consideration of the above-described circumstances. Even if one cycle of the clock CLK is shortened, there is no influence of the delay of the circuit element, and the desired accurate pulse width is obtained. It is an object of the present invention to provide a pulse width adjusting device capable of generating a clock.

  According to the present invention, a delay circuit that generates a plurality of delay pulses having a predetermined delay amount using an input clock CLK having a fixed period, and measures a delay amount per clock CLK cycle using the plurality of delay pulses. A plurality of delay state holding circuits for generating a holding signal for generating, a holding timing circuit for generating a pulse indicating a timing for outputting the holding signal and giving the pulse to the delay state holding circuit, and for each delay state holding circuit A plurality of encoders that are connected and count the number of holding signals measured during one cycle using the holding signals given from the connected delay state holding circuit, and holding signals output from each encoder A calculation value output circuit that performs a predetermined calculation on the count value of the clock and outputs a calculation value corresponding to a delay amount per cycle of the clock CLK. There is provided a pulse width adjustment device, characterized in that was e.

A selection for selecting and outputting the delay pulse CLK1 corresponding to the delay timing set value DLYSEL obtained from the operation value output from the operation value output circuit using a plurality of delay pulses output from the delay circuit. A circuit, a second delay circuit that has the same delay time as the selection circuit and outputs a clock CLK2 in which the clock CLK is shifted by the delay time, and a logical operation circuit that performs a logical operation of the delay pulse CLK1 and the clock CLK2 And a pulse width adjusting device that outputs a clock whose pulse width is adjusted with respect to the input clock CLK from a logic operation circuit.
The logical operation circuit is a circuit for calculating logical sum or logical product, and various circuits can be used depending on design specifications.

Here, a delay amount automatic adjustment circuit that determines the set value DLYSEL so that a clock having a desired pulse width is output from the logic operation circuit using the operation value output from the operation value output circuit, Further, it may be provided.
Further, two delay state holding circuits and two encoders may be provided, and a subtraction circuit that subtracts count values respectively output from the two encoders may be used as the arithmetic value output circuit.

Further, when the number of the delay state holding circuits is two, the holding timing circuit causes the pulse applied to the second delay state holding circuit to have a higher pulse of the clock CLK than the pulse applied to the first delay state holding circuit. You may make it output at the timing delayed by 1 period.
The delay timing set value DLYSEL is obtained by multiplying the calculated value (SUB0) output from the calculated value output circuit by a pulse adjustment value (K / L) corresponding to a preset pulse width adjustment amount. You may make it obtain | require by. Here, the pulse adjustment value means a shift amount of the clock CLK, and corresponds to K / L in an embodiment described later. That is, it can be expressed by DLYSEL = SUB0 × (K / L).

In the present invention, the delayed pulse corresponds to tap pulses (Tap0 to TapN) shown in the embodiments described later.
Further, the holding signal means Tapn_L and Tapn_L2 shown in FIGS. The pulse indicating the timing for outputting the holding signal means Latch-timing-pls (LP1, LP2) shown in FIG.
Two or more delay state holding circuits and encoders according to the present invention may be provided, but at least two each may be provided. When two each are provided, a subtraction circuit is provided as the calculation value output circuit. Use it. In this case, the count value from the two encoders is given to the subtraction circuit, and the smaller one of the count values may be subtracted.

  According to this invention, a plurality of delay state holding circuits, a plurality of encoders, and a calculation value corresponding to a delay amount per cycle by performing a predetermined calculation on the count value output from each encoder. Therefore, even when the reference clock pulse width is reduced, the clock pulse pulse is not affected by delays due to changes in the operating environment such as temperature and voltage, and variations in circuit element characteristics. The width can be adjusted accurately.

Hereinafter, the present invention will be described in detail based on the embodiments shown in the drawings. In addition, this invention is not limited by this.
FIG. 6 shows a block diagram of the configuration of the pulse width adjusting device of the present invention. The same blocks as those in the conventional apparatus shown in FIG.
In FIG. 6, unlike FIG. 1, a holding timing circuit 21 (Latch Timing Pulse Gen), a second delay state holding circuit 22 (REG2), a second encoder 23 (Encoder2), and a subtraction circuit 24 ( SUB) and have been added.

Further, the difference is that the output value ENC0 of the encoder 15 is not used as the output in the calibration mode, but the value SUB0 obtained by subtracting the outputs of the two encoders (15, 23) is used. The output value SUB0 indicates the number of passing TAPs per one clock cycle that does not include the delay (Tc, Ts) by the calibration circuit 11 and the selector 12, as will be described below.
That is, according to the configuration of the present invention shown in FIG. 6, the influence of the delay amount (Tc, Ts) can be canceled, and the accurate number of passing TAPs per clock cycle can be obtained.

  The pulse (Calibrate-pls) output from the calibration circuit 11 is output so as to have a width corresponding to two clock cycles (see FIG. 8). Since two delay state holding circuits (14, 22) are used, two cycles of pulses (Calibrate-pls) are required to hold tap pulses at different clock timings. Because.

FIG. 9 shows a detailed circuit of an embodiment of the calibration circuit 11 (Cal Pulse Gen) of the present invention shown in FIG. As shown in FIG. 9, the calibration circuit 11 includes three D flip-flops and an AND circuit.
When the Calibrate signal, which is an input signal, is input to the CL terminal, the rising edge of the output pulse (Calibrate-pls) is generated at the next rising timing of the clock CLK, and at the next rising timing of the next clock, A falling edge of the output pulse (Calibrate-pls) is generated (see pulse Calibrate-pls in FIG. 8).

FIG. 10 shows a detailed circuit of one embodiment of the holding timing generation circuit 21 (Latch Timing Pulse Gen) of the present invention. FIG. 11 shows a timing chart of two pulse signals (LP1, LP2) output from the holding timing generation circuit 21.
As shown in FIG. 10, the holding timing generation circuit 21 includes two D flip-flops and one AND circuit. The pulse LP1 (Latch-timing-pls) is a timing pulse given to the first delay state holding circuit 14 (REG), and the pulse LP2 (Latch-timing-pls2) is the second delay state holding circuit 22 (REG2). ) Is a timing pulse.
As shown in FIG. 11, the pulse LP1 is a pulse that rises at the rising timing of the pulse (Calibrate-pls) and falls after one clock. The pulse LP2 is a pulse generated with a delay of one clock period with respect to the pulse LP1.

FIG. 12 shows a detailed circuit of an embodiment of the delay circuit 13 (Delay element String).
As shown in FIG. 12, the delay circuit 13 has a number of delay elements (D) equal to the number (T) of tap pulses to be taken out connected in series. Tap pulses (TAP1 to TAPN) are extracted from the output of each delay element (D).
Further, the delay amount of each delay element (D) is related to the amount of time deviation of the tap pulse, but this delay amount varies depending on the design specifications of the entire apparatus and cannot be uniquely determined. For example, the delay amount of the delay element (D) is determined by the period of the reference clock CLK and the resolution required by the recording / reproducing apparatus.

FIG. 13 shows a detailed circuit of one embodiment of the delay state holding circuits 14 and 22 (REG, REG2).
As shown in FIG. 13, it is composed of a D flip-flop with an enable (EN) terminal provided for each tap pulse. The timing pulse (LP1 or LP2) generated by the holding timing generation circuit 21 is input to each enable terminal (EN).
FIG. 13 shows the REG 14, but the REG2 (22) has the same configuration. According to this delay state holding circuit (14, 22), the value of each tap pulse (Tap0-N) is output (Tap0_L-TapN_L) at the timing of pulse input to the enable terminal.

The pulse width adjusting device of the present invention is composed of the circuit blocks as described above. Next, the adjustment contents of the pulse width of this device will be described.
FIG. 8 shows a time chart of the calibration mode when a delay occurs in the calibration circuit 11 and the selector 12 in the pulse width adjusting device of the present invention. Here, the number of taps (N) of the delay circuit 13 is 11.
In FIG. 8, as described above, the pulse (Calibrate-pls) is a clock having a width corresponding to two periods of the clock CLK, and a predetermined delay is applied after the pulse (Calibrate-pls) as in FIG. Along with this, tap pulses (Tap 0 to Tap 11) are output. Each tap pulse (Tap0 to Tap11) also has a width corresponding to two cycles of the clock CLK.

In FIG. 8, the number of tap pulses passed (= 4) held by the REG 14 is output from the encoder 15 at the rising timing A ₀ of the first clock CLK after the rising of the pulse (Calibrate-pls). The same as FIG.
Although not shown in FIG. 8, REG14 outputs four pulses from Tap0_L to Tap3_L, and encoder 15 outputs ENC0 having a value of “4”.

On the other hand, the pulses from Tap0_L2 to Tap11_L2 shown in FIG. 8 indicate the output of the second delay state holding circuit 22 (REG2).
Here, in REG 2 (22), each tap pulse is latched at the timing A ₁ when the clock CLK of FIG. 8 rises, and a value (ENC 20) corresponding to the number of tap pulses at this time is output from the encoder 23. Is done. In FIG. 8, at timing A ₁ , Tap 0 to Tap 9 are latched, and “10” is output as the value of ENC 20.

  From the above, as shown in FIG. 8, ENC0 = “4” is output from the first encoder 15, and ENC20 = “10” is output from the second encoder 23. Therefore, in the subtraction circuit 24 (SUB) shown in FIG. 6, the difference between the two outputs (ENC0, ENC20) is calculated, and “6” = (10−4) is output as SUB0.

  SUB0 (= 6) obtained as a result of the latch and subtraction process as described above passes through an accurate clock cycle that does not include the delay (Tc, Ts) caused by the calibration circuit 11 and the selector 12. The Tap number is shown. This is because the effects of the two delays (Tc, Ts) are the same in both paths of the two delay state holding circuits and the encoder, but the numerical values obtained from both encoders are subtracted by the subtraction circuit. This is because the portions corresponding to the two delays (Tc, Ts) are canceled out.

According to the configuration of FIG. 6, the number of passing taps as represented by the following formula (Formula 4) is obtained as the value of SUB0.
Number of passing taps per clock cycle = T2-T1
Here, T2 = number of passing taps per two clock cycles + Tc + Ts,
T1 = number of passing taps per clock cycle + Tc + Ts
It is. The number of passing Taps per clock cycle is the value (ENC20) output from the second encoder 23, and the number of passing Taps per clock cycle is the value (ENC0) output from the first encoder 14. means. According to Equation 4, it can be seen that Tc and Ts are canceled by calculating T2-T1. That is, Equation 4 means the number of passing taps per clock cycle = ENC20−ENC0.

As described above, since the value of SUB0 obtained in the calibration mode operation does not include two delays (Tc, Ts), the output value (= 6) obtained from the ideal time chart shown in FIG. be equivalent to.
A clock having an ideal pulse width can be generated by determining the DLYSEL value to be given to the selection circuit MUX by using the SUB0 value obtained in the calibration mode in this way and performing the operation in the normal mode.

As shown in FIG. 8, the operation in the normal mode when the calibration circuit 11 and the selector 12 are delayed is almost the same as the timing chart shown in FIG.
In the present invention, “1” is given to the MUX 16 as the DLYSEL value in the apparatus having the configuration of FIG. Further, as described above, the number of passing taps per clock cycle obtained in the calibration mode is “6”. Therefore, since the shift amount (%) = 1 (DLYSEL value) / 6 (the number of passing taps in one clock cycle), the clock pulse CLKW having a shift amount of approximately 17% can be obtained from the above-described equation 2.

On the other hand, in the conventional normal mode operation shown in FIG. 5, since the number of passing TAPs in one clock cycle is 4, the DLYSEL value is set to 1 so that the shift amount is 25%. No clock was obtained, and a 17% shift amount of clock was obtained.
That is, with the conventional configuration of FIG. 1, an accurate shift amount cannot be obtained. However, even if there is a delay of the calibration circuit 11 or the selector 12, according to the calibration of the present application of FIG. A shift amount is obtained.

  In the configuration shown in FIG. 6, after the SUB0 value is once measured by the calibration mode process, the user looks at the SUB0 value and sets an appropriate DLYSEL value. The DLYSEL value may be set, for example, by key input from a personal computer (not shown) or using a setting device such as a dip switch (not shown). Or you may make it set from MPU by the structure shown by FIG.

Further, a delay amount automatic adjustment circuit 25 that automatically calculates the DLYSEL value using the SUB0 value obtained in the calibration mode may be added to the configuration of FIG. If this circuit 25 is added, after the calibration mode process, it is possible to smoothly shift to the normal mode process without interrupting the process once.
FIG. 7 shows a block diagram of an embodiment of the delay amount automatic adjustment circuit 25 of the present invention. As shown in FIG. 7, the delay amount automatic adjustment circuit 25 includes a multiplier 26 and a divider 27.

The multiplier 26 receives SUB0, which is the output of the subtraction circuit 24 of FIG. 6, and performs multiplication with a parameter “K” as will be described later. In the divider 27, the calculation result in the multiplier 26 is divided by the parameter “L”, and the calculation result is output to the selection circuit MUX16 in FIG. 6 as a DLYSEL value.
In FIG. 7, parameters K and L are numerical parameters for determining the shift amount (%), are given from an MPU (not shown), and are set in advance by the user according to the design specifications.

According to Equation 4 described above, the number of passing TAPs in one clock cycle = T2−T1 = ENC20−ENC0 = SUB0.
Further, according to Expression 2, the shift amount (%) = DLYSEL / number of passing TAPs in one clock cycle = DLYSEL / SUB0. If this equation is modified, DLYSEL = SUB0 × shift amount (%) (Equation 5).
Therefore, the shift amount (%) is defined as K / L (Formula 6). Here, K means a numerator value of the shift amount with respect to one clock cycle, and L means a denominator value of the shift amount with respect to one clock cycle. Substituting Equation 6 into Equation 5, DLYSEL = SUB0 × K / L.

For example, if it is desired to set the shift amount (%) to 18%, arbitrary K and L are set to be 18% in Equation 6. Considering that the shift amount = 18% = 18/100, K = 18 and L = 100 may be set. However, if 18% = 9/50, K = 9 and L = 50 may be set. However, the L value is preferably a power of 2 in order to simplify the circuit. This is because the divider 27 can be easily configured with a shifter.
Here, in order to set the shift amount to 18%, assuming that numerical values of K = 18 and L = 100 are given from the MPU to the delay amount automatic adjustment circuit 25, when SUB0 is 6, the DLYSEL value is calculated by the operation of the circuit 25. DLYSEL = 6 × 18/100 = 1 is output. Here, 6 × 18/100 = 1.08, but the decimal part is rounded down.
As described above, when the delay amount automatic adjustment circuit 25 is provided and the DLYSEL value is calculated using SUB0 obtained in the calibration mode, the transition from the calibration mode to the normal mode is performed smoothly.

FIG. 14 is a schematic flowchart when the calibration mode process and the normal mode process are continuously performed.
(Step S1)
In FIG. 14, first, the signal Calibrate is turned on (high level) in order to perform the calibration mode processing.
(Step S2)
Calibration mode processing as shown in FIG. 8 is executed. As a result, the SUB0 value that is the output of the subtraction circuit 24 is measured and stored in a memory such as a RAM. Here, as described above, the SUB0 value indicates the number of Taps per cycle that is not affected by the delay of the calibration circuit 11 or the like.

(Step S3)
The signal Calibrate is turned off (low level). This ends the calibration mode.
(Step S4)
The parameters K and L are given, the delay amount automatic adjustment circuit 25 is operated, and the calculated DLYSEL value is given to the MUX 16.
(Step S5)
The clock CLK is supplied and normal mode processing is executed. As a result, the clock CLKW having a pulse width corresponding to the shift amount (%) set by K and L is output.

(Step S6)
Here, it is determined whether or not recalibration is performed after the normal mode processing is completed. A predetermined display meaning recalibration may be presented to the user and judged by the user's key input or the like. Alternatively, by using a preset parameter indicating the presence / absence of recalibration, the parameter may be read to return to the recalibration process, that is, the process of step S1. However, this branch determination is not necessarily an essential determination.
If recalibration is not necessary, all processing is terminated. Judgment whether or not recalibration is necessary is not uniquely determined, but recalibration was performed as much as possible, for example, when it was necessary to adjust the pulse width in response to clock fluctuations due to temperature changes. Better. In a recording / reproducing apparatus that attaches / detaches a portable recording medium, the processing from steps S1 to S5 may be repeated each time the data recording processing is executed.

FIG. 15 shows an embodiment of a setting parameter setting circuit portion used in the present invention. Here, three registers (32, 33, 34) are provided as data write registers from the MPU 36, and one register 35 is provided as a data read register.
The MPU 36 and each register are connected by a data bus, an address bus, a write signal (WT), and a read signal (RD). As write registers, there are a K value setting register 32, an L value setting register 33, and a DLYSEL setting register. Here, appropriate numerical values are written from the MPU, and each numerical value is given to a predetermined constituent block of FIG. When the delay amount automatic adjustment circuit 25 is used, the register 34 is not necessary. The data reading register is written with the SUB0 value output from the subtraction circuit, and the MPU 36 reads the numerical value.

  As described above, even if the pulse width of the clock is reduced due to the increase in speed by performing the configuration and operation as shown in FIG. 6, FIG. 7, FIG. 8, and FIG. Therefore, the width of the clock pulse can be accurately adjusted so as not to be affected by the delay. The clock pulse width adjusting device of the present invention can also be applied to the following devices.

FIG. 16 is a block diagram showing an embodiment of the clock phase adjusting apparatus according to the present invention.
Here, the input clock CLKW is a clock whose pulse width is adjusted by the circuit shown in FIG. If this circuit is used, not only the pulse width of the clock but also the phase of the clock can be adjusted accurately.
The circuit shown in FIG. 16 corresponds to a circuit obtained by deleting the AND circuit 17 from the circuit shown in FIG. 6, and the signal CLKP becomes a clock pulse whose phase is adjusted. DLYSEL_P set from an MPU (not shown) is input to the MUX 16. However, DLYSEL_P may be set by providing a setting register in the same manner as DLYSEL shown in FIG.

  Here, the Delay B 18 uses an element having the same delay amount as that of the MUX 16, and the phase of the signal CLKP is adjusted with respect to CLKP_ 0. That is, by changing the value of DLYSEL_P, it is possible to obtain a clock CLKP having a phase shift as desired by the user.

FIG. 17 shows a block diagram of an embodiment of a data (DATA) phase adjustment device as another application example. Here, the clock CLKW is generated by the circuit of FIG. 6 or FIG.
17 differs from FIG. 6 in that a D flip-flop 30 is added between the selector 12 and the delay circuit 13, that there is no AND circuit 17, and that a Delay C 31 is added. The output of the MUX 16 itself is used as phase-adjusted DATA. If this circuit is used, the phase in which data (DATA) is output can be accurately adjusted.

Since DATA is input to the selector 12 instead of the clock CLK having a regular fixed period, the D flip-flop 30 is used to provide the delay element 13 with data synchronized with the clock CLKW.
Further, in the calibration mode processing, the same operation as shown in FIG. 8 is performed, but since the D flip-flop 30 is added, it is necessary to consider the delay of the clock for one cycle by the D flip-flop 30. is there. That is, in accordance with the delay of one pulse of the clock of the D flip-flop 30, the holding timing circuit 21 is also controlled to output a pulse delayed by one clock compared to the case of FIG.

  Delay C31 is also added to match the delay associated with the addition of the D flip-flop 30. The data DATA_D output in FIG. 17 is phase-adjusted with reference to the clock CLK_D output from Delay B18, and is adjusted to a desired phase by DLYSEL_D applied to the MUX 16.

FIG. 18 is a block diagram showing a schematic configuration of a magneto-optical disk apparatus using the pulse width adjusting apparatus of the present invention.
In FIG. 18, a pulse width adjusting device 41 corresponds to the device of the present invention. However, phase adjustment is performed on the write data WDATA given from the encoder 42, and the adjusted data WDATA is transferred to the bias driver 43. Is given to.
Further, the pulse width of the clock WCLK supplied from the encoder 42 is adjusted, and the adjusted clock WCLK is supplied to the LD driver 44.

It is a block diagram of the conventional pulse adjustment circuit. It is an ideal timing chart of the conventional calibration mode. It is an ideal timing chart (shift amount setting value 33%) of the conventional normal mode. It is a timing chart at the time of delay generation in the conventional calibration mode. It is a timing chart at the time of occurrence of delay in the conventional normal mode (shift amount setting value 25%). It is a block diagram of the pulse adjustment apparatus of one Example of this invention. It is a block diagram of the delay amount automatic adjustment circuit of this invention. 4 is a timing chart when a delay occurs in the calibration mode of the present invention. It is a block diagram of the calibration circuit (Cal Pulse Gen) of this invention. It is a block diagram of the holding | maintenance timing circuit (Latch Timing Plus Gen) of this invention. It is a timing chart of the delay timing pulse created by the holding timing circuit of the present invention. It is a block diagram of the delay circuit (Delay Element String) of this invention. It is a block diagram of the delay state holding circuit (REG, REG2) of the present invention. It is a flowchart of the pulse width adjustment process of this invention. It is a block diagram of the register for setting of this invention. It is a block diagram of the clock phase adjusting device of one Example of this invention. It is a block diagram of the data phase adjustment apparatus of one Example of this invention. 1 is a configuration diagram of a magneto-optical disk device including a pulse width adjusting device of the present invention. FIG.

Explanation of symbols

11 Calibration circuit 12 Selector 13 Delay circuit 14 Delay state holding circuit REG
15 Encoder 16 Selection circuit MUX
17 AND circuit 18 DelayB
21 Holding Timing Circuit 22 Delay State Holding Circuit 23 Encoder 24 Subtraction Circuit SUB
25 Delay amount automatic adjustment circuit 30 D-FF
31 DelayC

Claims (4)

A first delay circuit that generates a plurality of delay pulses having a predetermined delay amount using the input clock CLK having a fixed period, and a delay amount per cycle of the clock CLK is measured using the plurality of delay pulses. First and second delay state holding circuits for generating a holding signal for generating, a holding timing circuit for generating a pulse indicating a timing for outputting the holding signal and supplying the pulse to the delay state holding circuit, and each delay state holding circuit First and second encoders that are connected to each other and count the number of held signals measured during one cycle using the held signals given from the connected delay state holding circuit, and from each encoder A predetermined calculation is performed on the count value of the output holding signal, and a calculation value output that outputs a calculation value corresponding to the delay amount per cycle of the clock CLK And the circuit,
Using a plurality of delay pulses output from the first delay circuit, a delay pulse CLK1 corresponding to the delay timing set value DLYSEL obtained from the calculation value output from the calculation value output circuit is selected and output. A selection circuit, a second delay circuit having the same delay time as the selection circuit and outputting a clock CLK2 in which the clock CLK is shifted by the delay time, and a logical operation circuit for performing a logical operation on the delay pulse CLK1 and the clock CLK2 And a clock whose pulse width is adjusted with respect to the input clock CLK is output from the logic operation circuit . A delay amount automatic adjustment circuit for determining the delay timing set value DLYSEL so that a clock having a desired pulse width is output from the logic operation circuit using the operation value output from the operation value output circuit; The pulse width adjusting device according to claim 1 , further comprising: Consists of a subtraction circuit to subtract the count value before Symbol operation value output circuit is output from the first and second encoder,
Before Symbol hold timing circuitry than the pulse to be supplied to the first delay state holding circuit, and characterized in that toward the pulse to be supplied to the second delay state holding circuit, and outputs in one cycle delayed timing of the clock CLK The pulse width adjusting device according to claim 1. The delay timing set value DLYSEL is obtained by multiplying a calculation value output from the calculation value output circuit by a pulse adjustment value corresponding to a preset adjustment amount of a pulse width. 1 pulse width adjusting device.

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