JP4295808B2 - Composite image processing circuit - Google Patents

Description

  The present invention relates to an image processing apparatus that performs image processing using a line buffer.

  In image processing such as filter processing and gradation processing, not only one pixel to be processed but also a plurality of peripheral pixels located in the vicinity thereof may be used. FIG. 9 is a diagram illustrating a pixel to be processed in 3 × 3 matrix processing and its peripheral pixels. In the 3 × 3 matrix processing, when processing the pixel D11 to be processed, the pixels D10 and D12 before and after it, the pixel D01 on one line and the pixels D00 and D02 before and after it, the pixel D21 below the line and the pixel D20 before and after that, The pixel data of D22 is referred to and used.

  The pixel data of the pixels on the previous line including the pixels (D0n, D1n (n: 0, 1, 2)) is held (delayed) in a memory circuit called a line buffer and used in subsequent image processing. The storage capacity of the line buffer is determined according to the content of the target image processing. For example, in order to process pixels in the short direction of A3 size with an accuracy of 600 DPI in which 600 pixels are included in one inch, about 8 KB of memory is required (about 7500 pixels / line). Similarly, when image processing is performed with an accuracy of 1200 DPI for A3 size, a line buffer of 16 KB, which is about twice that of A3 size, is required.

  As the number of types of image processing increases, the number of necessary line buffers also increases. For example, when performing five types of processing (for example, gain adjustment, 5 × 5 matrix filtering, 3 × 3 matrix noise removal, scaling, and 3 × 3 matrix error diffusion processing), a total of 10 8 KB line buffers are required. become. Therefore, in order to realize these processes with a single-chip large-scale integrated circuit (LSI), ten 8 KB line buffers must be mounted on the LSI. When the above-described five types of image processing are performed with an accuracy of 600 DPI for the A0 size, the short direction of the A0 size is handled as a line, so the data amount is about three times that of the A3 size. Therefore, a total of 10 24 KB line buffers are required.

Although different from the present invention, there has been a method of reducing the number of line buffers by sharing one memory as a plurality of line buffers (see, for example, Patent Document 1). However, it cannot cope with a case where a plurality of image processes are performed simultaneously. Further, although there has been disclosed a method for reducing the line buffer (see, for example, Patent Document 2), it cannot cope with the case where the number of pixels increases to exceed the capacity of the line buffer. A technique has been disclosed in which the line buffer allocation is changed in the bit direction, thereby changing the number of effective bits for each image process, that is, the accuracy of the image process (see, for example, Patent Document 3). Similarly, the increase in the number of pixels cannot be accommodated.
JP-A-6-149994 Japanese Patent Laid-Open No. 7-44696 Japanese Patent Laid-Open No. 10-340340

  As described above, when developing an LSI capable of handling various image processing with one chip, it is necessary to mount a line buffer having the maximum capacity necessary for each processing. In this case, in the image processing with lower accuracy, since the large-capacity line buffer is not used up, the mounting of the line buffer increases only the manufacturing cost, which is inefficient. For example, the A3 size 600 DPI process does not use up the line buffer capacity required for the A3 size 1200 DPI process.

  For the above-described problem, it may be possible to optimize the manufacturing cost by changing the capacity or number of line buffers mounted on the LSI depending on the contents of image processing. For example, for high-grade models that achieve high-precision processing, we have developed LSIs with large capacity and many line buffers, while for low-grade models that do not perform high-precision processing. An LSI having a smaller capacity and a small number of line buffers can be developed. However, if an optimum LSI is developed for each model, the development cost will increase.

  An object of the present invention is to cope with an increase / decrease in the number of pixels and an increase / decrease in the type of image processing, and to minimize an increase in overall cost including manufacturing cost and development cost.

The composite image processing circuit of the present invention performs a predetermined image process on input pixel data of a plurality of pixels constituting an image and outputs the processed image data from an output terminal. In the circuit
Each of the image processing circuits
First and second line buffer units each including one or more line buffers that hold the pixel data as line data in units of pixel lines;
A first image processing unit that performs predetermined first image processing on the input pixel data using line data held in at least one of the line buffer units; and
A second image processing unit that performs predetermined second image processing on the output data of the first image processing unit using line data held in at least one of the line buffer units and outputs the second image processing unit When,
A buffer selector for controlling connection between each of the first and second image processing units and each of the first and second line buffer units;
A first output selector that exclusively selects one of the output data of each of the first and second image processing units and outputs the selected data from the output end;
A second output selector that exclusively selects one of the input pixel data and the output data of the first image processing unit and outputs the selected data to the second image processing unit;
Consisting of
The buffer selector connects the first line buffer unit to the first image processing unit when the first output selector outputs the output data of the second image processing unit from the output terminal. When the second line buffer unit is connected to the second image processing unit, and the first output selector outputs the output data of the first image processing unit from the output terminal, When the first and second line buffer units are connected to the first image processing unit, respectively, and the second output selector selects and outputs the input pixel data, the first and second line buffer units are connected to the first image processing unit. When each of the second line buffer units is connected to the second image processing unit, and the second output selector selects and outputs the output data of the first image processing unit, the first line buffer unit According to the selection operation of the output selector, Performing the connection operation between the first and second image processing units and the first and second line buffer units, the first image processing units and the second image processing units, and Each includes a plurality of circuit blocks configured to perform connection control with the first line buffer unit and each second line buffer unit,
A series circuit of a first image processing unit, a first output selector, a second image processing unit, and a second output selector in each circuit block is connected in series, and the buffer selector Connection control between one image processing unit and each second image processing unit, and each first line buffer unit and each second line buffer unit is performed .

  A selector 6 is provided as a buffer selector so that the first image processing unit can access two or more line buffers. As a result, it is possible to perform image processing using more line data than when only one line buffer is used. Since the first image processing unit can perform image processing using line data held in one of a plurality of line buffers, one image processing circuit can handle image data of various sizes. The number of two or more line buffers is the number of lines necessary for image processing in the first image processing unit. Further, the image processing of the second image processing unit is bypassed, and the first image processing unit has an output selector that selects an output path for outputting the pixel data subjected to the image processing. Can be selected.

  Further, the second image processing unit is connected to a line buffer different from the line buffer accessed by the first image processing unit and performs image processing using line data, so that all necessary image processing is performed. Can do.

  Since necessary image processing is performed in each image processing circuit using two image processing circuits, all necessary image processing can be realized without changing the design.

  Since the image processing unit is made accessible to a plurality of line buffers, image processing independent of the size of the image data can be realized. There is no increase in cost because only the minimum necessary line buffer is installed for normal image processing. In addition, when processing large image data, it is not necessary to design and develop a new dedicated circuit because some of the functions of the same circuit are selected and combined and all the image processing is performed with multiple circuits. Become.

  Since image processing is performed using the above-described image processing circuit, even when image data increases, all image processing can be realized by adding the number of image processing circuits. This eliminates the need to design and develop new circuits depending on the model grade even when used in printers and facsimile machines that print images, minimizing the increase in overall costs, including manufacturing and development costs. Can be suppressed.

  Embodiments 1 to 4 of the present invention will be described below with reference to the accompanying drawings. In Embodiment 1, the basic principle of the present invention will be described. The second and third embodiments are modifications of the first embodiment, and the fourth embodiment is an application example of the present invention. In the accompanying drawings, components having the same function are denoted by the same reference numerals.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of an image processing circuit 10 according to the first embodiment. The image processing circuit 10 is formed on one large-scale semiconductor integrated circuit (LSI) or IC chip, receives original image data to be processed, performs predetermined image processing, and performs processing as image data. Output. The original image data is, for example, pixel data of a plurality of pixels constituting an image read by a scanner (not shown), or pixel data of a plurality of pixels transmitted from a computer (not shown). The processed image data is pixel data of pixels subjected to image processing by an image processing unit described later.

  The image processing circuit 10 includes two image processing units 2-1 and 2-2, line buffers 4-1 and 4-2, and selectors 6 and 8. The image processing units 2-1 and 2-2 simultaneously process image processing with the same or different contents and output processed image data. For example, the image processing unit 2-1 is a circuit that performs gain adjustment processing, and the image processing unit 2-2 is a circuit that performs error diffusion processing. Each of the line buffers 4-1 and 4-2 has a storage capacity of 8 KB. For example, each line buffer 4-1 and 4-2 has an accuracy of 600 DPI in which 600 pixels are included in one inch, and one line pixel (approximately 7500 in the A3 size). Pixel) pixel data can be stored. That is, the line buffers 4-1 and 4-2 hold the image data in units of lines. Image data in units of lines is also referred to as line data. The selector 6 is provided between the image processing unit and the line buffer 4 and selectively connects a plurality of existing image processing units and line buffers. The selector 8 is connected to the outputs of the image processing unit 2-1 and the image processing unit 2-2, and selectively outputs one of the processing results as processed image data.

  Hereinafter, the selection operation of the selectors 6 and 8 will be described. The selector 6 and the selector 8 are a selection signal from a control unit (not shown) such as a central processing unit (CPU) provided outside the image processing circuit 10, a value of a register (not shown), or A selection operation is performed based on a selection switch provided outside the image processing circuit 10.

  First, the selector 6 performs two types of selection operations. That is, a one-to-one selection operation in which the line buffer 4-1 is connected to the image processing unit 2-1, and the line buffer 4-2 is connected to the image processing unit 2-2, and the line buffers 4-1, 4 and 4 are connected. -2 is a two-to-one selection operation in which one line buffer having a capacity of 16 KB is connected to one image processing unit (for example, the image processing unit image processing unit 2-1).

  On the other hand, the selector 8 also performs two types of selection operations. That is, a bypass selection operation for outputting the processing result of only the image processing unit 2-1, and a serial processing selection operation for outputting the processing result of the image processing unit 2-2. When the selector 8 performs a bypass selection operation, the processing result of the image processing unit 2-1 is bypassed without being processed by the image processing unit 2-2 and is output as processed image data. In the above example, only the gain adjustment processing of the original image data is performed and output. When the selector 8 performs the serial processing selection operation, the processing result of the image processing unit 2-1 is further processed by the image processing unit 2-2. In the above example, the processed image data is output after performing the gain adjustment processing and error diffusion processing of the original image data.

  The reason why the selectors 6 and 8 are provided is to enable the image processing circuit 10 to be used for a plurality of types of products having functional differences. For example, when the selector 8 is set to perform only the bypass selection operation and the selector 8 is set to perform the serial processing selection operation, the latter performs more complicated image processing than the former. Can do. On the other hand, comparing the case where the selector 6 is set to perform only the one-to-one selection operation and the case where the selector 6 is set to perform the two-to-one selection operation, the latter is one image. Since the buffer capacity available to the processing unit is twice that of the former, image processing with twice the number of pixels can be performed. Therefore, in either case, the former setting is suitable for a low-functional model, and the latter setting is suitable for a high-functional model. Note that when the selector 8 is set so as to perform only the bypass selection operation, the image processing unit 2-2 is not used, and the component cost (manufacturing cost) is wasted. However, if one type of image processing circuit 10 is manufactured, it can be used for a plurality of types of products having functional differences, so that it is not necessary to design an image processing circuit for each function, and development costs can be reduced. Therefore, an increase in overall cost including manufacturing cost and development cost can be minimized.

  FIG. 2 is a block diagram showing a configuration of an image processing circuit 10 including a selector 6 that performs a one-to-one selection operation and a selector 8 that performs a serial processing selection operation. The image processing unit 2-1 reads line data stored in the line buffer 4-1 via the selector 6. On the other hand, the image processing unit 2-2 reads line data stored in the line buffer 4-2 via the selector 6. The image processing unit 2-1 does not access the line buffer 4-2. Since each of the image processing units 2-1 and 2-2 can access a line buffer of 8 KB, as described above, for example, it can hold one line in the short direction of A3 size with an accuracy of 600 DPI. The image processing circuit 10 outputs the data processed by the image processing units 2-1 and 2-2 as processed image data via the selector 8.

  On the other hand, FIG. 3 is a block diagram showing a configuration of an image processing circuit 10 including a selector 6 that performs a 2-to-1 selection operation and a selector 8 that performs a bypass selection operation. With the 2-to-1 selection operation, the image processing unit 2-1 can use the line buffers 4-1 and 4-2 as one line buffer having a capacity of 16 KB. Compared with a one-to-one selection operation using an 8 KB buffer, the image processing unit 2-1 can perform image processing that requires twice as much data. For example, image processing with an accuracy of 1200 DPI can be performed. After the image processing unit 2-1 performs image processing, the processing of the image processing unit 2-2 is bypassed and output as processed image data.

  The line buffer is often configured with a FIFO memory, but the circuit configuration and memory type for realizing the FIFO are not particularly limited. For example, a random access memory (RAM) may be used or a register may be used. Further, the bit width and word size of the line buffer are not particularly limited.

(Embodiment 2)
Next, a modified example of the image processing circuit 10 will be described. FIG. 4 is a block diagram showing a configuration of the image processing circuit 40 according to the second embodiment. The basic function of the image processing circuit 40 is the same as that of the image processing circuit 10 (FIG. 1) of the first embodiment.

  The image processing circuit 40 is different from the image processing circuit 10 (FIG. 1) in that a selector 8-1 is provided. In the image processing circuit 40, the selector 8-2 has the same function as the selector 8 shown in FIG.

  The selector 8-1 is connected to the signal path from the outside and the output of the image processing unit 2-1, and performs two types of selection operations. That is, the bypass selection operation for sending the input original image data to the next stage without being processed by the image processing unit 2-1, or the serial processing selection operation for outputting the processing result of the image processing unit 2-1 as processed image data It is. Since the selector 8-1 is provided, the image processor 2-2 can directly process the original image data. Therefore, the selector 6 also receives line buffers 4-1 and 4 from the image processor 2-2. -2 can be further performed so that a one-to-one selection operation or a two-to-one selection operation is performed. Using the example of the first embodiment, the original image data is not subjected to gain adjustment processing in the image processing unit 2-1, but is subjected to error diffusion processing in the image processing unit 2-2.

  For example, FIG. 5 shows a configuration of an image processing circuit 40 including a selector 6 that performs a 2-to-1 selection operation, and selectors 8-1 and 8-2 that perform a bypass selection operation and a serial processing selection operation, respectively. FIG. As can be seen from the figure, the image processor 2-2 which received the original image data by the bypass selection operation of the selector 8-1 makes the two line buffers 4-1 and 4-2 one buffer of 16KB. Can be used as a high-accuracy image processing.

  By combining a plurality of image processing circuits, an image processing circuit that performs more various image processing can be realized. FIG. 6 is a block diagram showing a configuration of a composite image processing circuit 60 in which two image processing circuits 40-1 and 40-2 are connected in series. Assume that each of the image processing circuits 40-1 and 40-2 includes an image processing circuit 40 (FIG. 4). Data output from the image processing circuit 40-1 and input to the image processing circuit 40-2 is shown as intermediate data in the figure.

  Since the image processing unit 2-1 of the image processing unit 40-1 can access the two line buffers 4-1 and 4-2, one line of data can be processed up to 16KB. On the other hand, the processing of the image processing unit 2-2 is bypassed. The image processing circuit 40-2 is the image processing circuit 40 shown in FIG.

  By connecting two image processing circuits, the image processing unit can handle image processing up to twice the amount of data (16 KB) per line. Since it is not necessary to design a new image processing circuit in which the capacity of the line buffer is changed, the number of pixels to be processed can be increased without requiring a design and development cost.

(Embodiment 3)
FIG. 7 is a block diagram showing a configuration of the image processing circuit 70 according to the third embodiment. The image processing circuit 70 is formed on one large-scale semiconductor integrated circuit (LSI) or IC chip.

  The image processing circuit 70 includes image processing units 2-1 to 2-5, line buffers 4-1 to 4-10, a selector 6, and selectors 8-1 to 8-5. The image processing circuit 70 is a circuit configured by increasing the number of image processing units, line buffers, and selectors of the image processing circuit 40 (FIG. 4) to 5, 10, and 5, respectively. is there.

  The image processing units 2-1 to 2-5 include five different types of image processing, specifically, gain adjustment processing, 3 × 3 matrix filter processing, scaling processing, 4 × 4 matrix noise removal processing, and 3 × 3 matrix, respectively. The error diffusion process is performed. Each image processing unit can separately access an arbitrary number of line buffers and acquire image data of the number of lines necessary for image processing. Since the number of lines in the line buffer required according to the processing contents is determined, for example, when the image processing unit 2-4 needs three lines of data, each stores one line of data. By assigning three line buffers, it is possible to process an image having a normal size (for example, data in which one line is 8 KB). If data for one line is stored in two line buffers, two line buffers may be allocated for each line. As a result, an image having twice the normal quality or size (for example, data of 16 KB per line) can be processed.

  For example, in the case of data of 8 KB for one line, that is, a normal image in which one line has the same capacity as one line buffer, the number of lines necessary for the image processing units 2-1 to 2-5 to perform image processing The relationship of the number of line buffers to be allocated is as shown in Table 1 below.

  According to Table 1, since the processing of each image processing unit is “valid”, all image processing is performed on an image of one line up to 8 KB by one LSI in which the image processing circuit 70 is formed. Can be realized. Note that each of the selectors 8-1 to 8-5 selects a route for receiving an output result from each image processing unit. The selector 6 operates to connect the number of line buffers shown in “Number of line buffer allocation” in Table 1 to each image processing unit.

  Next, consider the case of an image in which one line of data is 16 KB, that is, a normal image in which one line is equal to the capacity of two line buffers. In this case, an image having a size twice that of the normal image in Table 1 is considered as a processing target.

  As is apparent from Table 2, all line buffers are allocated to the image processing units 2-1 to 2-3, and data corresponding to necessary lines can be secured. Therefore, image processing (gain adjustment processing, 3 × 3 matrix filter processing, scaling processing) for the image processing units 2-1 to 2-3 can be realized with one LSI for an image of one line up to 16KB. . However, in other words, this means that image processing of the image processing units 2-4 and 2-5 (4 × 4 matrix noise removal processing and 3 × 3 matrix error diffusion processing) is not performed in one LSI. Therefore, in order to perform further image processing by the image processing units 2-4 and 2-5, it is necessary to provide a new image processing circuit 70 and assign the pattern B shown in Table 3.

  As shown in Table 3, by disabling the processing of the image processing units 2-1 to 2-3 that have already been processed and assigning the line buffer only to the image processing units 2-4 and 2-5, one LSI Thus, the image processing of the image processing units 2-4 and 2-5 can be performed on an image with one line up to 16KB. From the above, by combining the two patterns A and B described above, all five types of image processing can be realized.

  Finally, consider the processing of a normal image in which one line of data is a 24 KB image, that is, one line is equal to the capacity of three line buffers. This is processing of an image having a size three times that of the normal image in Table 1.

  As is apparent from Table 4, all line buffers are allocated to the image processing units 2-1 and 2-2, and data corresponding to necessary lines can be secured. Therefore, image processing (gain adjustment processing, 3 × 3 matrix filter processing) of the image processing units 2-1 and 2-2 can be realized with one LSI for an image of one line up to 24 KB.

  Furthermore, in order to perform subsequent processing, it is necessary to provide a new image processing circuit 70 and assign the pattern B shown in Table 5.

  As shown in Table 5, by disabling the processing of the image processing units 2-1 and 2-2 that have already been processed and assigning a line buffer to the image processing unit 2-3, one line can be 24 KB in one LSI. Image processing (magnification processing) of the image processing unit 2-3 can be performed on the images up to the above. The reason why only the image processing unit 2-3 is enabled and the image processing unit 2-4 is not enabled is that the subsequent image processing unit 2-4 is assigned after the line allocation of the image processing unit 2-3. This is because the necessary number of lines cannot be secured. Therefore, in order to perform image processing in the image processing unit 2-4, it is necessary to provide a new image processing circuit 70 and assign the pattern C shown in Table 6.

  If one LSI provided with the third image processing circuit 70 is used, the image processing (4 × 4 matrix noise removal processing) of the image processing unit 2-4 can be realized for an image with one line up to 24 KB. Further, in order to perform image processing by the image processing unit 2-5, it is necessary to provide a fourth image processing circuit 70 and assign a pattern D shown in Table 7.

となり、１つのＬＳＩで１ラインが２４ＫＢまでの画像に対して画像処理部２−５の画像処理（３ｘ３マトリックスの誤差拡散処理）が実現できる。

Thus, the image processing (error diffusion processing of 3 × 3 matrix) of the image processing unit 2-5 can be realized for an image of one line up to 24 KB with one LSI.

  From the above, in order to perform five types of image processing of the image processing units 2-1 to 2-5 on an image having a data amount of 24 KB per line, the four image processing circuits 70 are provided and the four patterns described above are provided. It will be understood that A to D may be combined.

(Embodiment 4)
In this embodiment, an application example of the image processing circuit of the present invention will be described.

  FIG. 8A is a block diagram illustrating a configuration of a copier that is an image forming apparatus. The copier includes a scan unit 81, an image processing chip 80 on which the image processing circuit according to the first to third embodiments is mounted, a print data generation unit 82, and a print unit 83. The scanning unit 81 scans a document and generates original image data. The scanning unit 81 includes an exposure lamp that irradiates light on a document, a lens array that collects reflected light from the document, and a CCD image sensor that converts the collected light into an electrical signal (both shown in FIG. Not shown).

  The image processing chip 80 includes, for example, the image processing circuit 10 (FIG. 1), the image processing circuit 40 (FIG. 2), the composite image processing circuit 60 (FIG. 6), or the image processing circuit 70 (FIG. 7). One chip. The image processing chip 80 receives original image data from the scanning unit 81, performs image processing by the image processing circuit 70, and then outputs processed image data. Since specific examples of image processing have been described in the first to third embodiments, a description thereof will be omitted.

  The print data generation unit 82 performs processing for print output on the processed image data output from the image processing chip 80, for example, gradation correction (γ correction) according to the gradation characteristics of the photoreceptor. Further, the print data generation unit 82 generates a laser diode drive signal based on the image data after gradation correction. This laser diode drive signal is output as print data. The print unit 83 receives print data from the print data generation unit 82, and performs printing based on the received print data. More specifically, the printing unit 83 causes the semiconductor laser to emit light based on the print data. The laser beam exposes a charged and rotating photosensitive drum. Further, the electrostatic latent image is developed on the photosensitive drum with toner, and then transferred onto a copy paper wound around a transfer drum.

  FIG. 8B is a block diagram illustrating a configuration of a facsimile machine (FAX) that is an image forming apparatus. The facsimile apparatus includes a scanning unit 84, an image processing chip 80, a transmission data generation unit 85, and a transmission unit 86. The difference from (a) is that instead of the print data generation unit 82 and the print unit 83, a transmission data generation unit 85 and a transmission unit 86 for FAX transmission are provided. Explaining only the difference, the transmission data generation unit 85 receives the processed image data output from the image processing chip 80, and performs data processing conforming to a predetermined standard for FAX transmission, for example, MH (Modified Huffman) processing. Redundancy suppression encoding processing such as MR (Modified READ) processing is performed. The transmission data generation unit 85 outputs the processed data as transmission data. The transmission unit 86 transmits the transmission data received from the transmission data generation unit 85 to the other party via an analog or digital signal line.

1 is a block diagram illustrating a configuration of an image processing circuit according to a first embodiment. It is a block diagram which shows the structure of an image processing circuit including the selector which performs 1-to-1 selection operation, and the selector which performs serial processing selection operation. FIG. 3 is a block diagram illustrating a configuration of an image processing circuit including a selector that performs a 2-to-1 selection operation and a selector that performs a bypass selection operation. FIG. 5 is a block diagram illustrating a configuration of an image processing circuit according to a second embodiment. FIG. 3 is a block diagram showing a configuration of an image processing circuit including a selector that performs a 2-to-1 selection operation and two selectors that respectively perform a bypass selection operation and a serial processing selection operation. It is a block diagram which shows the structure of the composite image processing circuit which connected two image processing circuits in series. FIG. 10 is a block diagram illustrating a configuration of an image processing circuit according to a third embodiment. (A) is a block diagram showing a configuration of a copier. FIG. 2B is a block diagram illustrating a configuration of the facsimile apparatus. It is a figure which shows the pixel used as the process target in 3x3 matrix processing, and its peripheral pixel.

Explanation of symbols

2, 2-n image processing unit 4, 4-n line buffer 6 selector 8, 8-n selector 10 image processing circuit 40 image processing circuit 60 composite image processing circuit

Claims (1)

In the composite image processing circuit composed of a plurality of image processing circuits that perform predetermined image processing on the input pixel data of a plurality of pixels constituting the image and output from the output end ,
Each of the image processing circuits
First and second line buffer units each including one or more line buffers that hold the pixel data as line data in units of pixel lines;
A first image processing unit that performs predetermined first image processing on the input pixel data using line data held in at least one of the line buffer units; and
A second image processing unit that performs predetermined second image processing on the output data of the first image processing unit using line data held in at least one of the line buffer units and outputs the second image processing unit When,
A buffer selector for controlling connection between each of the first and second image processing units and each of the first and second line buffer units;
A first output selector that exclusively selects one of the output data of each of the first and second image processing units and outputs the selected data from the output end;
A second output selector that exclusively selects one of the input pixel data and the output data of the first image processing unit and outputs the selected data to the second image processing unit;
Consisting of
The buffer selector connects the first line buffer unit to the first image processing unit when the first output selector outputs the output data of the second image processing unit from the output terminal. When the second line buffer unit is connected to the second image processing unit, and the first output selector outputs the output data of the first image processing unit from the output terminal, When the first and second line buffer units are connected to the first image processing unit, respectively, and the second output selector selects and outputs the input pixel data, the first and second line buffer units are connected to the first image processing unit. When each of the second line buffer units is connected to the second image processing unit, and the second output selector selects and outputs the output data of the first image processing unit, the first line buffer unit According to the selection operation of the output selector, Performing the connection operation between the first and second image processing units and the first and second line buffer units, the first image processing units and the second image processing units, and Each includes a plurality of circuit blocks configured to perform connection control with the first line buffer unit and each second line buffer unit,
A series circuit of a first image processing unit, a first output selector, a second image processing unit, and a second output selector in each circuit block is connected in series, and the buffer selector A composite image processing circuit which performs connection control between one image processing unit and each second image processing unit, and each first line buffer unit and each second line buffer unit .

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