JP4257484B2 - PWM generator - Google Patents

Description

【００５０】
図６は三角波とPWMパルスパターンの関係を示している。図５に示すPWMパルスパターンテーブル４７ではアドレスADRから対応するPWMパターンが選択され、U相、V相、W相、U２相、V２相、W２相のＰＷＭ信号４７a、４７b、４７c、４７d、４７e、４７fとして出力される。
【００５１】
次に、本実施形態のPWM発生装置の動作を説明する。キャリア発生回路４２をカウントクロック４９でカウント動作させる。そして、演算回路４１により各相のPWM比較データと空間ベクトル演算が処理される毎に三角波比較値レジスタ４３および波形パターンレジスタ４５に三角波比較値と波形パターンが順次書き込まれている。キャリア発生回路出力であるカウント値４２aと三角波比較値レジスタ４３に書き込まれている三角波比較値が比較回路４４で比較される。比較結果は常にアドレスエンコーダ４６でアドレスに変換される。アドレスエンコーダ出力によってPWMパルスパターンテーブル４７から、常に一個の波形パターンレジスタが選択され、レジスタの各ビットが出力４７a、４７b、４７c、４７d、４７e、４７fとして出力される。
【００５２】
したがって、前記比較結果により空間ベクトル演算結果から得られた３レベル三相PWMパルスパターンがU相、／U相、V相、／V相、W相、／W相、U２相、／U２相、V２相、／V２相、W２相、／W２相の図示されないIGBTのドライブ信号として出力される。
【００５３】
ここで図７と図８により具体例を説明する。
【００５４】
キャリア発生回路４２が発生する三角波TRの最大値を９５９６、三角波比較値レジスタ４３に保持されている三角波比較値T０、T１、T２、・・・・T１１の値をそれぞれ４９０、４９０、２１５３、２６４５、２６４５、４３０８、５２９０、６９５３、６９５３、７４４５、９１０８、９１０８とすると、比較回路４４の各出力C１、C２、・・・・、C１１は図７に示すようなパルスとなり、これらを束ねた１２ビットの出力Tout （比較回路出力４４a）は図７に示すように、FFF、３FF、１FF、０７F、０３F、０１F、００７、００３、０００、００３、００７、０１F、０３F、０７F、１FF、３FF、FFF、・・・・となる。一方、PWMパルスパターンテーブル４７にはアドレス０、１、３、７、・・・・、FFFに表１に示すようなPWM波形パターンPT０、PT１、PT２、PT３、・・・・、PT１２が記憶されている。したがって、PWMパルスパターンテーブル４７からは図８（１）に示すようなU相ＰＷＭ出力U1、U２、V相ＰＷＭ出力V１、V２、W相ＰＷＭ出力W１、W２が出力される。そして図８（２）に示すようなU相のベースドライブ信号PU、PU２、NU、NU２、V相のベースドライブ信号PV、PV２、NV、NV２、W相のベースドライブ信号PW、PW２、NW、NW2が生成される。なお、三角波比較値レジスタ４３、したがって比較回路４４と波形パターンレジスタ４５の数は任意である。
【００５５】
図９は本発明の第３の実施形態のPWM発生装置のブロック図である。
【００５６】
キャリア発生回路５２はカウントクロック６５でカウント動作し、カウント値５２aと、キャリアの山でロウレベルとなるキャリア山パルス５２b、キャリアの谷でロウレベルとなるキャリア谷パルス５２cを出力する。１２個の通常運転用三角波比較値レジスタ５３と２個の電流制限用三角波比較値レジスタ５４は演算回路５１からデータバス６３に出力されたデータ（通常運転用三角波比較値、電流制限用三角波比較値）を、同じく演算回路５１から出力された書き込み信号５４aにより保持する。三角波比較値セレクタ５５は後述する切替信号６２cのロウレベル、ハイレベルに応じて通常運転用三角波比較値レジスタ５３のデータ、電流制限用三角波比較値レジスタ５４のデータを選択し、出力する。１２個の比較回路５６は三角波比較値セレクタ５５から出力された各データをキャリア発生回路５２の出力であるカウント値５２aと比較し、後者が前者より大きいとハイレベル、小さいとロウレベルの出力を出力する。１３個の通常運転用波形パターンレジスタ５７と、６個の電流制限用波形パターンレジスタ５８は演算回路５１からデータバス６３に出力されたデータ（通常運転用波形パターン、電流制限用波形パターン）を、同じく演算回路５１から出力された書き込み信号５４bにより保持する。波形パターンセレクタ５９は、後述する切替信号６２cのロウレベル、ハイレベルに応じて通常運転用波形パターンレジスタ５７のデータ、電流制限用波形パターンレジスタ５８のデータを選択し、出力する。アドレスエンコーダ６０は、１２ビットの比較回路出力５６aをアドレス信号に変換する。PWMパルスパターンテーブル６１は波形パターンセレクタ５９の出力（データ）が、当該データの通常運転用波形パターンレジスタ５７または電流制限用波形パターンレジスタ５８に割り付けられたアドレスに書き込まれ、アドレスエンコーダ６０から出力されたアドレスのパターンレジスタ値を、図示されないIGBTのベースドライバに接続されたU相、V相、W相、U２相、V２相、W２相のPWM出力６１ａとして出力する。電流制限パターン発生回路６４はPWMパルスパターンテーブル６１から出力されたPWM出力６１aからベースドライブ信号PU、NU、PV、NV、PW、NW、PU２、NU２、PV２、NV２、PW２、NW２を出力し、後述するロウレベルの固定値出力信号６２bを受けると、ベースドライブ信号NU、PU２、NV、PV２、NW、PW２をハイレベル出力とし、それ以外のベースドライブ信号はロウレベル出力とする。電流制限制御回路６２は、不図示の過電流検出回路から過電流検出を示す過電流検出信号６２aが入力されると、固定値出力信号６２bをロウレベルにし、次のキャリア山パルス５２bまたはキャリア谷パルス５２cで切替信号６２cをハイレベルからロウレベルにし、過電流検出信号６２aが入力されなくなると、切替信号６２cを再びハイレベルにする。三角波と通常運転用波形パターンの関係は第２の実施形態の図６に示したものと同じである。
【００５７】
図１０は三角波と電流制限用三角波比較値と電流制限用波形パターンとU相のベース信号の間の関係を示している。
【００５８】
次に、本実施形態のPWM発生装置の動作について説明する。まず、キャリア発生回路５２をカウントクロック６５でカウント動作させる。そして、演算回路５１により各相のPWM比較データと空間ベクトル演算が処理される毎に通常運転用三角波比較値レジスタ５３と通常運転用波形パターンレジスタ５７に通常運転用三角波比較値と通常運転用波形パターンが順次に書き込まれている。キャリア発生回路５２の出力のカウント値５２ａと通常運転用三角波比較値レジスタ５３に保持されているデータが比較回路５６で比較され、１２ビットの比較結果５６aはアドレスエンコーダ６０でアドレスに変換される。一方、PWMパルスパターンテーブル６１ではアドレスエンコーダ出力によって常に一個の波形パターンが選択され、パターンの各ビットがＰＷＭ信号U１、U２、V１、V２、W１、W２として出力される。したがって、前記比較結果により空間ベクトル演算結果から得られた３レベル三相パルスパターンが電流制限パターン発生回路６４を通過して、PU、NU、PV、NV、PW、NW、PU２、NU２、PV２、NV２、PW２、NW２のベースドライブ信号が出力される。ここで、過電流が発生すると、図には示されない過電流検出回路から過電流検出信号６２aが電流制限制御回路６２に入力される。電流制限制御回路６２は過電流検出信号６２aを受けると、固定値出力信号６２bをロウレベルにする。電流制限パターン発生回路６４はロウレベルの固定値出力信号６２bを受けると、電流制限パターン発生回路出力であるNU、PU２とNV、PV２とNW、PW２のベースドライブ信号の出力を導通し、PUとNU２、PVとNV２、PWとNW２のベースドライブ信号の出力を遮断する。この間に電流制限用三角波比較値と電流制限パターンを演算回路５１で演算し、電流制限用三角波比較値レジスタ５４と電流制限用波形パターンレジスタ５８に書き込んでおく。次の任意のキャリアの山または谷で、電流制限用パターンデータから電流制限PWM波形を発生する。過電流が抑制されると、次の任意のキャリアの山または谷で通常運転のデータが切替信号６２cによって選択され、速やかに通常運転に復帰することができる。
【００５９】
したがって、本実施形態によれば、過電流が発生してもスイッチング素子を絶縁破壊させることなく電流制限でき、また、過電流が抑制されたときには速やかに通常運転に復帰でき、幅広いインバータ用途に対応できるPWM波形を生成することができる。
【００６０】
図１１、図１２は具体例のタイミングチャートである。図１１に示すようにキャリア発生回路５２が発生するカウント値５２ａ（図１１、１２中、TRと表示）の最大値を９５６９、通常運転用三角波比較値レジスタ５３に保持されている通常運転用三角波比較値T０、T１、T２、・・・・T１１の値をそれぞれ４９０、４９０、２１５３、２６４５、２６４５、４３０８、５２９０、６９５３、６９５３、７４４５、９１０８、９１０８、電流制限用三角波比較値レジスタ５４に保持されている電流制限用三角波比較値Z０、Z１をそれぞれ３９９、１９９７とする。さらに、通常運転用波形パターンレジスタ５７、電流制限用波形パターンレジスタ５８に図１１に示すような通常運転用波形パターンがPT０、PT１、PT２、・・・・、PT１２、ZP０、ZP１、・・・・ZP５に保持されているものとする。このとき、比較回路５６の比較結果を示す信号５６ａ（図１２中Toutと表示）、キャリア山パルスOVFL、キャリア谷パルスUNFL、過電流を検出するとロウレベルになる過電流検出信号CAL、ハイレベルのとき通常PWM、ロウレベルのとき電流制限PWMを示す切替信号PWM＿ZP、過電流が検出されるとロウレベルになる固定値出力信号PWM＿ZERO＿Lは図１２に示すようになり、U相、V相、W相のベースドライブ信号が得られる。図の例では時刻t1に過電流が検出されて過電流検出信号CALがロウレベルになり、したがって固定値出力信号PWM＿ZERO＿Lがロウレベルになる。固定値出力信号PWM＿ZERO＿Lがロウレベルになると、ベースドライブ信号PU２とNU がオンし、PUとNU２はオフする。V相、W相のベースドライブ信号も同じ動作になる。時刻t2にカウント値５２ａがキャリアの山にき、キャリア山パルスOVFLが出力されると、固定値出力信号PWM＿ZERO＿Ｌがロウレベルからハイレベルになる。この切り替りと同時に切替信号PWM＿ZPはハイレベルからロウレベルになり、電流制限用三角波比較値レジスタ５４の値Z0、Z１、電流制限用波形パターンレジスタ５８の値ZP０〜ZP５が選択される。切替信号PWM＿ZPがロウレベルの区間では値Z０とZ１から作成されたアドレスで選択された電流制限用パターンの値がベース信号として出力される。
【００６１】
なお、通常運転用三角波比較値レジスタ５３と電流制限用三角波比較値レジスタ５４の数、したがって通常運転用波形パターンレジスタ５７、電流制限用波形パターンレジスタ５８の数は任意である。
【００６２】
【発明の効果】
以上説明したように、本発明は、下記の効果がある。
【００６３】
１）請求項１の発明は、ある任意のキャリア周期におけるPWM信号のデータを１つ前のキャリア周期中において設定でき、演算回路がキャリア周波数発生回路から出力されるカウンタ値、オーバフロー信号およびアンダフロー信号の監視による待ち時間をなくし、インバータ装置のその他の機能のための多くの処理時間を提供できる。また、キャリア周波数の高速化においても、演算回路の処理能力に対する負担が軽減されるため、幅広いインバータ用途に対応できるPWM波形を生成することができる。さらに、PWM設定レジスタのみへの書き込みの場合、キャリアの山でも、それぞれ各相のPWM信号の比較値が更新できるためキャリア周波数の低い制御においても、各相のPWM信号のパルス幅を高精度に制御することができるため安定したPWM信号の波形を実現することができる。
【００６４】
２）請求項２の発明は、従来のように三角波比較値を空間ベクトル演算結果に変換する処理が不要となり、演算回路の負担が軽減され、また、２レベル方式の場合においても従来と同等に動作することができるため２レベル方式および３レベル方式のインバータに適用でき、幅広いインバータ用途に対応できるPWM発生装置を提供することができる。
【００６５】
３）請求項３の発明は、過電流が発生すると一対のコンデンサの中点側に接続された２つのスイッチング素子を導通にし、残りのスイッチング素子を非導通にする電流制限パターンを発生し、次の所望のキャリアの山または谷から切替信号で選択された電流制限用三角波比較値および電流制限用波形パターンからPWMを発生し、過電流が抑制されると通常電流制限用三角波比較値および通常電流制限用波形パターンからPWMを発生することにより、幅広いインバータ用途に対応できるPWM発生装置を提供することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態のPWM発生装置のブロック図である。
【図２】図１のPWM発生装置のタイミングチャートである。
【図３】PWM比較設定値ロード回路７の回路図とタイミングチャートである。
【図４】周波数設定値ロード回路６の回路図のタイミングチャートである。
【図５】本発明の第２の実施形態のPWM発生装置のブロック図である。
【図６】第２の実施形態のPWM発生装置における三角波とPWMパルスパターンの関係を示す図である。
【図７】図５中の比較回路４４の出力４４aの一例の波形図である。
【図８】図５中のPWMパルスパターンテーブル４７の出力波形（同図（１））と、U 相、V相、W相の各ベースドライブ信号の波形図（同図（２））である。
【図９】本発明の第３の実施形態のPWM発生装置のブロック図である。
【図１０】第３の実施形態のPWM発生装置における三角波と電流制限用三角波と電流制限波形パターンレジスタとU相のPWM波形の間の関係を示す図である。
【図１１】第３の実施形態における三角波、通常運転用三角波比較値、電流制限用三角波比較値、通常運転用波形パターン、電流制限用波形パターンの具体例を示す図である。
【図１２】第３の実施形態のタイミングチャートである。
【図１３】第１の従来例のPWM発生装置のブロック図である。
【図１４】第１の従来例のタイミングチャートである。
【図１５】第２の従来例のPWM発生装置のブロック図である。
【図１６】第３の従来例のPWM発生装置のブロック図である。
【符号の説明】
１ 演算回路
２ キャリア周波数設定レジスタ
２a PWM信号発生の周波数のデータ
２b PWM信号発生の周波数のデータ２aの書き込み信号
２c キャリア周波数設定レジスタ２の出力データ
３ U相PWM設定レジスタ
３a U相PWM信号発生用データ
３b U相PWM設定レジスタ３に書き込む信号
３c U相PWM設定レジスタ３の出力データ
４ V相PWM設定レジスタ
４a V相PWM信号発生用データ
４b V相PWM設定レジスタ４に書き込む信号
４c V相PWM設定レジスタ４の出力データ
５ W相PWM設定レジスタ
５a W相PWM信号発生用データ
５b W相PWM設定レジスタ５に書き込む信号
５c U相PWM設定レジスタ５の出力データ
６ 周波数設定値ロード回路
６a キャリア周期値レジスタ書き込み信号
６b 書き込み信号選択信号
７ PWM比較設定値ロード回路
７a PWM比較設定値レジスタ書き込み信号
８ キャリア周期値レジスタ
８c キャリア周期値レジスタ出力データ
９ U相PWM比較値レジスタ
９c U相PWM比較値レジスタ出力データ
１０ V相PWM比較値レジスタ
１０c V相PWM比較値レジスタ出力データ
１１ W相PWM比較値レジスタ
１１c W相PWM比較値レジスタ出力データ
１２ キャリア発生回路
１２a カウントクロック
１２b カウンタ値
１２c オーバフロー信号
１２d アンダフロー信号
１３ PWM発生回路
１３a U相PWM発生回路
１３c V相PWM発生回路
１３e W相PWM発生回路
１３b U相PWM信号
１３d V相PWM信号
１３f W相PWM信号
１４a U相比較器
１４b V相比較器
１４c W相比較器
２１、２５、２６、３３、３５ ANDゲート
２２、２３、２４、２７、２８、３１、３２、３４、３６、３７、３８、４０ Dフリップフロップ
３９ セレクタ
４１ 演算回路
４１a、４１b 書き込み信号
４２ キャリア発生回路
４２a カウント値
４３ 三角波比較値レジスタ
４４ 比較回路
４４a 比較回路出力
４５ 波形パターンレジスタ
４６ アドレスエンコーダ
４７ PWMパルスパターンテーブル
４７a〜４７f PWM出力
４８ データバス
４９ カウントクロック
５１ 演算回路
５２ キャリア発生回路
５２a カウント値
５２b キャリア山パルス
５２c キャリア谷パルス
５３ 通常運転用三角波比較値レジスタ
５４ 電流制限用三角波比較値レジスタ
５５ 三角波比較値セレクタ
５６ 比較回路
５６a 比較回路出力
５７ 通常運転用波形パターンレジスタ
５８ 電流制限用波形パターンレジスタ
５９ 波形パターンセレクタ
６０ アドレスエンコーダ
６１ PWMパルスパターンテーブル
６１a PWM出力
６２ 電流制限制御回路
６２a 過電流検出信号
６２b 固定値出力信号
６２c 切替信号
６３ データバス
６４ 電流制限パターン発生回路
６４a ベースドライブ信号
６５ カウントクロック[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a voltage-type PWM inverter that varies the speed of an AC motor or the like, and more particularly to a PWM generator used in an inverter that uses a high-speed switching element such as IGBT.
[0002]
[Prior art]
FIG. 13 is a block diagram showing a configuration of a conventional PWM generator (hereinafter referred to as a first conventional example).
[0003]
  The carrier frequency setting register 2 is a register for setting the PWM signal generation frequency, and the PWM signal generation frequency data 2 a output from the arithmetic circuit 1 is written by the write signal 2 b output from the arithmetic circuit 1. The U-phase PWM setting register 3 holds U-phase PWM signal generation data. The U-phase PWM signal generation data 3a output from the arithmetic circuit 1 is written by the write signal 3b output from the arithmetic circuit 1. It is. The V-phase PWM setting register 4 holds V-phase PWM signal generation data. The V-phase PWM signal generation data 4a output from the arithmetic circuit 1 is generated by the write signal 4b output from the arithmetic circuit 1. Written. The W-phase PWM setting register 5 is a register that holds W-phase PWM signal generation data. The W-phase PWM signal generation data 5a output from the arithmetic circuit 1 is generated by the write signal 5b output from the arithmetic circuit 1. Written. The carrier generation circuit 12 is composed of an up / down counter to generate a triangular wave, and receives the output data 2c of the carrier frequency setting register 2 and the count clock 12a, and the counter value 12b.AndRear period 2cButOverflow signal 12 when matchedcAnd counter value 12bUnderflow signal 12 when 0 matches 0dIs output. The PWM signal generation circuit 13 includes a U-phase PWM signal generation circuit 13 a and a V-phase PWM signal generation circuit 13.cAnd W-phase PWM signal generation circuit 13eConsists of. The U-phase comparator 14a compares the counter value 12b with the U-phase PWM signal generation data 3c to obtain the U-phase PWM signal 13b.TheOutput. The U-phase PWM signal 13b is applied to an IGBT (Insulated Gate Bipolar Transiston) base driver (not shown) to output U-phase and / U-phase base drive signals. The V-phase comparator 14b compares the counter value 12b with the V-phase PWM signal generation data 4c and outputs a V-phase PWM signal 13d. The V-phase PWM signal 13d is applied to an IGBT base driver (not shown), and V-phase and / V-phase base drive signals are output.
[0004]
The W-phase comparator 14c compares the counter value 12b with the W-phase PWM signal generation data 5c and outputs a W-phase PWM signal 13f. The W-phase PWM signal 13f is applied to an IGBT base driver (not shown), and W-phase and / W-phase base drive signals are output.
[0005]
The PWM signal generation data 3a, 4a and 5a written in the PWM setting registers 3, 4 and 5 by the arithmetic circuit 1 are determined by the combination of PWM waveforms to be generated, and the high level period and low level period of the PWM signal are set. It is data to do. The carrier generation circuit 12 is shared by three phases.
[0006]
  Next, the operation of the conventional PWM generator will be described. In order to generate a PWM waveform, first, the carrier generation circuit 12 is caused to perform a count operation with the count clock 12a. The U-phase PWM signal held in the U-phase PWM setting register 3 that can be rewritten by the arithmetic circuit 1OccurrenceWhen the content of the counter value 12b matches the data 3c for use, the U-phase PWM signal is output from the comparator 14a.ButThe output is connected to an IGBT base driver (not shown) to generate U-phase IGBT base drive signals U and / U. When the arithmetic circuit 1 writes the data 2a of the PWM signal generation cycle in the carrier frequency setting register 2, the PWM comparison cycle is changed. If a large value is entered, the operation cycle of the comparator that generates the PWM is lengthened, and if a small value is entered, the operation cycle of the comparator is shortened.
[0007]
Here, a signal waveform diagram in the case of the triangular wave modulation method is shown in FIG. In FIG. 14, the overflow signal 12c is low when the output data 2c of the carrier frequency setting register matches the counter value 12b, and the underflow signal 12d is low when the counter value 12b matches zero.
[0008]
In addition, writing to the PWM setting registers 3, 4, 5 and the carrier frequency setting register 2 for each phase is always performed before the trough of the carrier, and writing to only the PWM setting registers 3, 4, 5 for each phase is always performed by the carrier. In front of a mountain or valley.
[0009]
FIG. 15 is a block diagram showing the configuration of another conventional PWM generator (hereinafter referred to as a second conventional example).
[0010]
  The carrier generation circuit 72 includes an up / down counter to generate a triangular wave, counts the clock 77, and outputs a count value 72a. Each of the three triangular wave comparison value registers 73 receives the data (triangular wave comparison value) output from the arithmetic circuit 71 to the data bus 76, and the arithmetic circuit similarly.71Is held by the write signal 71a output from. The three comparison circuits 74 compare the count value 72a output from the carrier generation circuit 72 with the data held in each of the triangular wave comparison value registers 73. 74a, 74b, and 74c are output. The signal 74a is a U-phase PWM signal, which is connected to an IGBT base driver (not shown) to output U-phase and / U-phase base drive signals. The signal 74b is a V-phase PWM signal, and is connected to an IGBT base driver (not shown) to output V-phase and / V-phase base drive signals. The signal 74c is a W-phase PWM signal, which is connected to an IGBT base driver (not shown) to output W-phase and / W-phase base drive signals. The data written to each triangular wave comparison value register 73 by the arithmetic circuit 71 is determined by the combination of PWM waveforms to be generated, and is data for setting the high level period and low level period of the PWM signal. The carrier generation circuit 72 is shared by three phases.
[0011]
The operation of this conventional PWM generator will be described. First, the carrier generation circuit 72 is caused to count with the count clock 77. Then, the comparison value is held in T 0 of the U-phase triangular wave comparison value register 73 that can be rewritten by the arithmetic circuit 71. When the carrier generation circuit output 72a exceeds the held U-phase triangular wave comparison data, the comparison circuit 74 outputs a high-level U-phase PWM signal 74a. The PWM signal 74a is connected to an IGBT base driver (not shown) and generates U-phase IGBT base drive signals U and / U. Since the V phase and the W phase are the same as the U phase, description of the operation is omitted.
[0012]
FIG. 16 is a block diagram of another conventional PWM generator (hereinafter referred to as a third conventional example).
[0013]
  The carrier generation circuit 82 includes an up / down counter to generate a triangular wave, counts the clock 87, and outputs a count value 82a. Each of the six triangular wave comparison value registers 83 holds the data (triangular wave comparison value) output from the arithmetic circuit 81 to the data bus 86 by the write signal 81 a output from the arithmetic circuit 81. Each of the six comparison circuits 84 has a high level when the count value 82a output from the carrier generation circuit 82 is larger than the data held in the corresponding triangular wave comparison value register 83, and a low level signal 84a, 84b when the count value 82a is smaller. 84c, 84d, 84e, 84f is output. The signal 84a is a PWM signal for controlling the U-phase IGBT upper arm, and the power module 90Switching elementConnected to S1 and S3. The signal 84d is a PWM signal for controlling the U-phase IGBT lower arm,Switching element of power module 90Connected to S2 and S4. The same applies to the V phase and the W phase. Further, the data written in each triangular wave comparison value register 83 by the arithmetic circuit 81 is determined by the combination of PWM waveforms to be generated, and is data for setting the high level period and low level period of the PWM signal. The carrier generation circuit 82 is shared by three phases.
[0014]
  The operation of this conventional PWM generator will be described. First, the carrier generation circuit 82 is caused to count with the count clock 87. Then, the triangular wave comparison value is held in T 0 of the U-phase triangular wave comparison value register 83 that can be rewritten by the arithmetic circuit 81. When the carrier generation circuit output 82a exceeds the held U-phase triangular wave comparison data, the comparison circuit 84 outputs a high-level U-phase PWM signal 84a. 84a and 84d are PWM signals for U-phase IGBT control.Switching element of power module 90It is connected to S1, S2, S3, S4 and becomes U-phase output. Since the V phase and the W phase are the same as the U phase, description of the operation is omitted.
[0015]
[Problems to be solved by the invention]
  In the PWM generator of the first conventional example, an arithmetic circuit is used for writing to the PWM setting registers 3 to 5 and the carrier frequency setting register 2 and for writing only to the PWM setting registers 3 to 5 for each phase. 1 always monitors the counter value 12b, the overflow signal 12c, and the underflow signal 12d, and writes data to the setting registers 2, 3, 4, and 5. Therefore, the PWM signals 13b, 13d, and 13f of each phase are repeatedly output by comparing and detecting the contents of the counter value 12b of the carrier generation circuit 12 and the contents of the PWM setting registers 3 to 5. However, if the carrier period is shortened, the PWM signal is output. In order to generate the signal, it is necessary to wait until the timing of writing the data of the PWM setting registers 3, 4, 51There is a problem that the burden on the processing capacity is large. That is, in order to control the PWM output with high accuracy, it is necessary to calculate and write the write data to the PWM setting registers 3 to 5 and the carrier frequency setting register 2 at high speed. In FIG. 14, the PWM waveform is U phase and is shown only when the PWM setting register 3 is written, but in reality, the PWM setting data 3a, 4a, 5a for three phases and the carrier comparison value are the carrier period. Is calculated and written to each of the registers 3, 4, and 5. Such a waveform is output for many cycles. In each cycle, the counter value 12b, overflow signal 12c and underflow signal 12d are frequently monitored by the arithmetic circuit 1, data is written to the registers 3, 4, and 5, and the comparators 14a, 14b and 14c detect coincidence. Thus, it is necessary to realize the PWM signals 13b, 13d, and 13f for each phase of the PWM. Each register3In order to write the set values to 4, 5 and 5, the arithmetic circuit 1 spends most of the processing contents in monitoring the counter value 12b, the overflow signal 12c and the underflow signal 12d. Further, if the carrier frequency is increased to reduce the noise of the inverter, processing other than PWM calculation is limited, and the burden on the arithmetic circuit 1 is increased.
[0016]
The PWM generator of the second conventional example can only deal with a two-level output type inverter, and when it corresponds to a three-level inverter, two comparison circuits are required, and two comparison circuits are used. On the other hand, it is common to use a space vector for the arithmetic processing of the three-level inverter. When two comparison circuits are used in the conventional apparatus, it is necessary to convert the triangular wave comparison value data into a space vector. Since the space vector requires many calculation processes at the same carrier frequency and takes a long calculation time, the calculation period becomes longer and the update of the comparison value increases, so that the calculation process is completed within the carrier period, the carrier frequency becomes lower.
[0017]
  In the third conventional PWM generator, when an overcurrent occurs, the UVW phase upper arm is simultaneously turned on and the upper arm is then turned off to create a reflux pattern in order to limit the current. However, this method can be applied only to a two-level output type inverter. This is because, in the case of corresponding to the three-level inverter, the IGBT may be destroyed depending on the pattern before the transition to the reflux pattern. The reflux pattern is a pattern that turns on the upper or lower arm at the same time for all three phases.elementSwitching when the normal pattern of S1 and S2 is high levelelementWhen S1 and S2 are turned off at the same time, switching is performed due to variations in IGBT turn-off time.elementThe case where S2 turns off first occurs. Switching in this caseelementSwitching is performed by applying the induced electromotive force and bus voltage to S2.elementS2 is destroyed. The same problem occurs when performing an emergency stop. Ie switchingelementIf all base drive signals are turned off while S1, S2 or S3, S4 are on, switching will occur due to variations in IGBT switching time.elementAn excessive voltage is applied to S2 or S3, causing dielectric breakdown.
[0018]
A first object of the present invention is to provide a PWM generator capable of reducing the burden on the processing capability of an arithmetic circuit and adapting to a wide range of inverter applications.
[0019]
The second object of the present invention is to generate a PWM that can quickly limit normal current without causing a power failure when an overcurrent occurs, and can quickly return to normal operation when the overcurrent is suppressed, and can be used for a wide range of inverter applications. Is to provide a device.
[0020]
[Means for Solving the Problems]
The PWM generator according to the first aspect of the present invention corresponds to the first conventional example. The carrier period value register, the U-phase, V-phase, and W-phase PWM comparison value registers, the frequency setting value load circuit, and the PWM comparison A setting value load circuit is newly provided.
[0021]
The carrier cycle value register receives the carrier cycle value register write signal, holds the data in the carrier frequency setting register, and outputs it to the carrier generation circuit.
[0022]
The U-phase PWM comparison value register, V-phase PWM comparison value register, and W-phase PWM comparison value register each receive the PWM comparison setting value register write signal and hold the data in the U-phase, V-phase, and W-phase PWM setting registers, respectively. .
[0023]
The U-phase PWM generation circuit, V-phase PWM generation circuit, and W-phase PWM generation circuit compare the U-phase, V-phase, and W-phase PWM comparison value data with the count value of the carrier generation circuit, respectively. Outputs V-phase and W-phase PWM signals.
[0024]
When data is set in the carrier frequency setting register, the frequency set value load circuit sets the write signal selection signal to the first logic level, and when the underflow signal is output next, this is used as the cycle value register write signal. At the same time, the write selection signal is set to the second logic level.
[0025]
When the write signal for the PWM comparison set value load circuit finishes writing the PWM signal generation data for each phase to the PWM setting register, and the write selection signal is at the first logic level, the next underflow signal is used as the PWM comparison value set value. If the write signal is the second logic level, the next underflow signal or overflow signal is output as the PWM comparison value register write signal.
[0026]
Therefore, the PWM signal data in any given carrier cycle can be set in the previous carrier cycle, the waiting time for detecting the write timing to the register by the arithmetic circuit is reduced, and the load on the processing capability of the arithmetic circuit is reduced. It is possible to generate PWM waveforms that can be used for a wide range of inverter applications.
[0027]
The PWM generator according to the second aspect of the present invention corresponds to the second conventional example, an address encoder for converting the output of the comparison circuit into an address, a waveform pattern register for holding a waveform pattern, and a waveform pattern at the address. A PWM pattern table is newly provided which outputs waveform patterns of addresses stored and output from the address encoder as PWM outputs of U phase, V phase, W phase, U2 phase, V2 phase and W2 phase.
[0028]
By directly writing the space vector calculation result to the waveform pattern register, the load on the calculation circuit is reduced, and the calculation process can be completed within the conventional carrier cycle. According to this aspect, a two-level inverter can also be controlled, and a PWM waveform that can be used for a wide range of inverter applications can be generated.
[0029]
The PWM generator according to the third aspect of the present invention corresponds to the third conventional example. Further, the PWM generator according to the second aspect further includes a current limiting triangular wave comparison value register, a triangular wave comparison value selector, and a current limiting waveform pattern. The circuit includes a register, a waveform pattern selector, a current limit control circuit, and a current limit pattern generation circuit. The carrier generation circuit generates a carrier peak pulse and a carrier valley pulse indicating a triangular wave peak and valley, respectively, in addition to the count value. Here, the triangular wave comparison value register and the waveform pattern register in the PWM generator of the second aspect are referred to as a normal operation triangular wave comparison value register and a normal operation waveform pattern register, respectively.
[0030]
During normal operation (overcurrent is not detected), the output of the normal operation triangular wave comparison value register is selected by the triangular wave comparison value selector, compared with the count value of the carrier generation circuit by the comparison circuit, and the normal operation waveform pattern register Data is selected by the waveform pattern selector and written to the PWM pattern table, and operates in the same manner as the PWM generator of the second mode.
[0031]
When an overcurrent is detected, a fixed value output signal is output to the current limit pattern generating circuit, and a predetermined base drive signal output from the current limit pattern generating circuit is set to a fixed value. At the next carrier peak pulse or carrier valley pulse, the fixed value output signal output to the current limit pattern generation circuit is stopped, and the current limit control circuit switches between the triangular wave comparison value selector and the waveform pattern selector, for current limit Select the data of the triangular wave comparison value register and the pattern of the current limiting waveform pattern register.
[0032]
When an overcurrent occurs, a current limiting pattern is generated that makes two switching elements connected to the middle point of the pair of capacitors conductive and makes the remaining switching elements non-conductive. The switching elements connected to the midpoint side of the pair of capacitors do not break down without the connected switching elements being turned off and the remaining switching elements being turned on. Further, when the overcurrent is limited, it is possible to return to the energization operation. Further, even if an emergency stop pattern is written in the current limiting waveform pattern, the dielectric breakdown does not occur in the same manner.
[0033]
According to this aspect, overcurrent limitation can be controlled, and a PWM waveform that can be used for a wide range of inverter applications can be generated.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0035]
FIG. 1 is a block diagram showing a configuration of a PWM signal generator according to a first embodiment of the present invention.
[0036]
  The carrier frequency setting register 2, the U phase PWM setting register 3, the V phase PWM setting register 4, and the W phase PWM setting register 5 are the same as those shown in FIG. When there is a write to the carrier frequency setting register 2, the frequency set value load circuit 6 outputs a carrier cycle value register write signal 6a and a write signal selection signal 6b according to the condition of the underflow signal 12d. PWM ratioComparisonWhen there is a write signal 5b of the W-phase PWM signal generation data 5a to the W-phase PWM setting register 5, the constant value load circuit 7 performs PWM comparison according to the conditions of the write signal selection signal 6b, the overflow signal 12c and the underflow signal 12d.Set valueA register write signal 7a is output. The carrier cycle value register 8 holds the output 2c of the carrier frequency setting register 2 as a carrier cycle value register write signal 6a. The U-phase PWM comparison value register 9 compares the output 3c of the U-phase PWM setting register 3 with PWM.Set valueIt is held by the register write signal 7a. The V-phase PWM comparison value register 10 compares the output 4c of the V-phase PWM setting register 4 with PWM.Set valueIt is held by the register write signal 7a. W-phase PWM comparisonvalueThe register 11 holds the output 5c of the W-phase PWM setting register 5 with the PWM comparison value register write signal 7a. The U-phase PWM generation circuit 13a, the V-phase PWM generation circuit 13c, and the W-phase PWM generation circuit 13e are respectively output data 9c of the U-phase PWM comparison value register 9, the V-phase PWM comparison value register 10, and the W-phase PWM comparison value register 11. 10c and 11c are compared with the counter value 12b, and a U-phase PWM signal 13b, a V-phase PWM signal 13d, and a W-phase PWM signal 13f are output.
[0037]
The operation of the thus configured PWM generator will be described.
[0038]
First, the carrier generation circuit 12 is operated to count with the count clock 12a. Each time the arithmetic circuit 1 calculates the carrier frequency setting 2a and the PWM signal generation data 3a, 4a, and 5a for each phase, they are sequentially written in the PWM setting registers 3, 4, and 5.
[0039]
First, the operation when the frequency data 2a for generating the PWM signal is set will be described. When data is written to the carrier frequency setting register 2, the frequency setting value load circuit 6 sets the signal 6b to the high level at the falling edge of the write signal 2b to the carrier frequency setting register 2. Next, the signal 6b is reset to a low level at the rising edge of the underflow signal 12d. The signal 6a outputs the same signal as the underflow signal 12d when the signal 6b is at a high level. Therefore, the frequency is updated at the trough of the carrier that comes first after the calculation result is output.
[0040]
Next, an operation when the PWM setting of each phase is updated will be described. When the calculation result of each phase PWM comparison data is sequentially written in the PWM setting registers 3, 4, 5 and written in the W phase PWM setting register 5, the write signal 5 b is input to the PWM comparison setting value load circuit 7. The PWM comparison set value load circuit 7 sets the internal signal to a high level at the falling edge of the W-phase PWM setting register write signal 5b. Next, when the signal 6b is at a low level, the logical product signal of the overflow signal 12c and the underflow signal is reset. When the signal 6b is at a high level, the internal signal is reset to a low level at the rising edge of the underflow signal 12d. The signal 7a is the signal selected by the signal 6b when the internal signal is high level, that is, the overflow signal 12c and the underflow signal 12d when the signal 6b is low level, and the underflow when the signal 6b is high level. It becomes signal 12d. Therefore, when the PWM setting value and carrier frequency setting are performed, the calculation result is output, the carrier frequency is updated at the first carrier valley, only the PWM setting value is updated, and the carrier frequency setting is not performed The calculation result is output and updated at the peak or valley of the carrier that comes first.
[0041]
FIG. 2 shows the carrier generation circuit 12 when the carrier frequency setting and the PWM setting are performed twice and only the PWM setting is performed once and the last carrier frequency setting and the PWM setting are performed in the present embodiment. The waveform of the U-phase PWM generation circuit 13a is shown. The underflow signal 12d, the overflow signal 12c, and the write signal to each register are normally at a high level, and during operation, for example, a low pulse corresponding to one pulse of the count clock is used.
[0042]
  The operation of the PWM generator of FIG. 1 will be described in more detail with reference to FIG. In FIG. 2, when the carrier generation circuit 12 is operating with the count clock, the arithmetic circuit 1 repeats various operations in order to control the PWM generation. The PWM operation is one of these processes. When PWM calculation is performed, the carrier frequency value isWhenWhen the PWM comparison value is calculated and the result is different from the previous one, the calculation result is written in the carrier frequency setting register 2, the U-phase PWM setting register 3, the V-phase PWM setting register 4, and the W-phase PWM setting register 5. First, regarding the change of the carrier frequency, when data is written in the carrier frequency setting register 2, the carrier frequency write signal 2b becomes a low level pulse. When receiving the falling edge of the signal 2b, the frequency set value load circuit 6 sets the signal 6b to a high level. On the other hand, the underflow signal 12d is also input to the frequency set value load circuit 6, and a low level pulse is input when a carrier valley comes. When the rising edge of the underflow signal 12d is received, the signal 6b is reset to the low level. When the signal 6b is at a high level, an underflow signal 12d is output as the carrier frequency write signal 6a. The carrier cycle value register 8 holds the output 2c of the carrier frequency setting register 2 when a low level pulse is output from the carrier frequency write signal 6a. Therefore, the period of the carrier that is written in the carrier frequency setting register 2 from the arithmetic circuit 1 at an arbitrary time and is immediately updated is updated in the carrier frequency register 8 at the valley of the carrier. Next, regarding the PWM setting change, when data is written to the W-phase PWM setting register 5, the PWM setting register write signal 5b becomes a low level pulse. When receiving the falling edge of the 5b signal, the PWM comparison set value load circuit 7 sets the internal signal to a high level. On the other hand, the PWM comparison set value load circuit 7 is also input with an overflow signal 12c and an underflow signal 12d, and a low level pulse is input when a peak or valley of the carrier comes. The internal signal is reset at the rising edge of the overflow signal 12c or the underflow signal 12d. Therefore, when the signal 6b is high level, the signal 12d is compared with PWM.Set valueIt is output as a register write signal 7a. When a low-level pulse is output as the W-phase PWM setting register write signal 5b, the PWM setting registers 3, 4 and 5 of each phase are held as internal signals of the PWM comparison setting value load circuit 7, and this signal and the signal 6b Depending on the conditions, the PWM comparison value registers 9, 10, and 11 of each phase hold the outputs 3 c, 4 c, and 5 c of the PWM register at the peak or valley of the next carrier, respectively. Therefore, the PWM setting is calculated for the previous carrier, and if there is no change in the carrier frequency, it is updated at the peak or valley of the next carrier, and if there is a change in the carrier frequency, it is updated at the valley of the next carrier. The
[0043]
  In this way, the PWM comparison with the frequency set value load circuit 6 that generates the control signal for switching the update timing of the carrier cycle value and the comparison data of each phase at a certain carrier peak or valleySettingBy providing the value load circuit 7, the waiting time between detecting the timing of writing the carrier frequency setting value and the PWM setting value of each phase to the carrier generation circuit 12 and the PWM generation circuit 13 by the arithmetic circuit 1 is reduced, The burden on the processing capability of the arithmetic circuit 1 can be reduced and a PWM waveform that can be used for a wide range of inverter applications can be generated.
[0044]
In the above embodiment, the U-phase waveform has been described, but it goes without saying that the V-phase and W-phase waveforms can be realized in the same manner as the U-phase waveform.
[0045]
  FIG. 3 is a circuit diagram and timing chart of the PWM comparison set value load circuit 7. The PWM comparison set value load circuit 7 includes D flip-flops 22, 23, 24, 27, 28 and 40, AND circuits 21, 25 and 26, and a selector 39. AND circuit 21 is underflow 12dAnd overflow signal 12cThe logical product of When the power is turned on, the D flip-flops 22, 23, 24, 27, and 40 are reset or preset by a reset signal reset. Therefore, when writing is performed in the W-phase PWM setting register 5, the write signal reg_wrL is input, and reg_wrL_temp which is the output of the D flip-flop 22 becomes “H”. This signal is a gate signal of the AND circuit 26 of the next stage, and the other input signal PWMCYLp of the AND circuit 26 is output. The output of the AND circuit 26 is held in the D flip-flop 27 for waveform shaping, and then selected by the selector 39 when the signal 6b is "L", held in the D flip-flop 40, and the PWM comparison set value register The write signal 7a is obtained. Therefore, this signal 7a corresponds to the peak or valley of the carrier.
[0046]
  FIG. 4 is a circuit diagram and timing chart of the frequency set value load circuit 6. The frequency set value load circuit 6 is composed of D flip-flops 31, 32, 36, 37 and AND circuits 33, 35. D flip-flop 31IsThe underflow signal 12d is held. When the power is turned on, the D flip-flops 31, 32, 36, and 37 are reset or preset by a reset signal reset. Then, the write signal 2b (reg_weL) having the PWM signal frequency is input, and the output reg_wrL_temp of the D flip-flop 34 becomes “H”. This signal reg_wrL_temp is a gate signal of the AND circuit 35 in the next stage, and when the signal is “H”, the other input signal UNFLp of the AND circuit 35 is passed. The output of the AND circuit 35 is held in the D flip-flop 36 for waveform shaping, and is output as a carrier cycle value register write signal 6a. The difference from the PWM comparison set value load circuit 7 is that only the carrier trough signal generated first after the carrier writing is output. At this time, the signal reg_wrL_temp is output as the write signal selection signal 6b,Of FIG.A switching signal for the selector 39 is used.
[0047]
FIG. 5 is a block diagram showing the configuration of the PWM signal generator according to the second embodiment of the present invention.
[0048]
  The carrier generation circuit 42 operates with a count clock 49 and generates a triangular wave. The twelve triangular wave comparison value registers 43 hold the data (triangular wave comparison value) output from the arithmetic circuit 41 to the data bus 48 by the write signal 41 a output from the arithmetic circuit 41. The twelve comparison circuits 44 output a comparison circuit output 44a of a high level when the count value 42a output from the carrier generation circuit 42 is larger than the data held in the corresponding triangular wave comparison value register 43, and a low level when the count value 42a is smaller. To do. The 13 waveform pattern registers 45 hold the data (waveform pattern) output from the arithmetic circuit 41 to the data bus 48 by the write signal 41 b output from the arithmetic circuit 41. The address encoder 46 converts the 12-bit comparison circuit output 44a into an address signal. In the PWM pulse pattern table 47, as shown in Table 1, the data of the waveform pattern register 45 is written to the address assigned to the waveform pattern register, and the address encoder46The pattern register value of the address output from the U-phase, V-phase, W-phase, U2-phase, V2-phase, W2-phase PWM outputs 47a, 47b, 47c, 47d, connected to an IGBT base driver (not shown) 47e and 47f are output.
[0049]
[Table 1]

[0050]
  FIG. 6 shows the relationship between the triangular wave and the PWM pulse pattern.As shown in FIG.In the PWM pulse pattern table 47, a corresponding PWM pattern is selected from the address ADR, and output as PWM signals 47a, 47b, 47c, 47d, 47e, 47f of U phase, V phase, W phase, U2 phase, V2 phase, W2 phase. Is done.
[0051]
  Next, the operation of the PWM generator according to this embodiment will be described. The carrier generation circuit 42 is counted by the count clock 49. Each time the arithmetic circuit 41 processes the PWM comparison data of each phase and the space vector calculation, the triangular wave comparison value and the waveform pattern are sequentially written in the triangular wave comparison value register 43 and the waveform pattern register 45. Count that is the carrier generation circuit outputGThe comparison circuit 44 compares the value 42 a with the triangular wave comparison value written in the triangular wave comparison value register 43. The comparison result is always converted into an address by the address encoder 46. One waveform pattern register is always selected from the PWM pulse pattern table 47 by the address encoder output, and each bit of the register is output as an output 47a, 47b, 47c, 47d, 47e, 47f.
[0052]
  Therefore, the three-level three-phase PWM pulse pattern obtained from the space vector calculation result based on the comparison result is the U phase, / U phase, V phase, / V phase, W phase, / W phase, U2 phase, / U2 phase, V2 phase, / V2 phase, W2 phase, / W2 phaseIGBT not shownIs output as a drive signal.
[0053]
A specific example will now be described with reference to FIGS.
[0054]
  The maximum value of the triangular wave TR generated by the carrier generation circuit 42 is 9596, and the values of the triangular wave comparison values T0, T1, T2,... T11 held in the triangular wave comparison value register 43 are 490, 490, 2153, and 2645, respectively. , 2645, 4308, 5290, 6953, 6953, 7445, 9108, 9108, the outputs C1, C2,..., C11 of the comparison circuit 44 become pulses as shown in FIG. As shown in FIG. 7, the bit output Tout (comparison circuit output 44a) is FFF, 3FF, 1FF,07F, 03F, 01F, 007, 003,000,003, 007, 01F, 03F, 07F, 1FF, 3FF, FFF,... On the other hand, the PWM pulse pattern table 47 stores addresses 0, 1, 3, 7,..., And PWM waveform patterns PT0, PT1, PT2, PT3,. Has been. Therefore, the PWM pulse pattern table 47 outputs U-phase PWM outputs U1 and U2, V-phase PWM outputs V1 and V2, and W-phase PWM outputs W1 and W2 as shown in FIG. Then, U-phase base drive signals PU, PU2, NU, NU2, V-phase base drive signals PV, PV2, NV, NV2, W-phase base drive signals PW, PW2, NW, as shown in FIG. NW2 is generated. Note that the number of triangular wave comparison value registers 43, and therefore the number of comparison circuits 44 and waveform pattern registers 45 are arbitrary.
[0055]
FIG. 9 is a block diagram of a PWM generator according to a third embodiment of the present invention.
[0056]
  The carrier generation circuit 52 performs a count operation with the count clock 65, and outputs a count value 52a, a carrier peak pulse 52b that becomes a low level at a carrier peak, and a carrier valley pulse 52c that becomes a low level at a carrier peak. The twelve normal operation triangular wave comparison value registers 53 and the two current limiting triangular wave comparison value registers 54 include data (normal operation triangular wave comparison value, current limiting triangular wave comparison value) output from the arithmetic circuit 51 to the data bus 63. ) Is held by the write signal 54a similarly output from the arithmetic circuit 51. The triangular wave comparison value selector 55 selects and outputs the data of the normal operation triangular wave comparison value register 53 and the data of the current limiting triangular wave comparison value register 54 according to the low level and high level of a switching signal 62c described later. The twelve comparison circuits 56 compare each data output from the triangular wave comparison value selector 55 with the count value 52a which is the output of the carrier generation circuit 52, and output a high level if the latter is larger than the former and a low level output if the latter is smaller. To do. Thirteen normal operation waveform pattern registers 57 and six current limiting waveform pattern registers 58 store the data (normal operation waveform pattern, current limiting waveform pattern) output from the arithmetic circuit 51 to the data bus 63. Similarly, it is held by the write signal 54 b output from the arithmetic circuit 51. The waveform pattern selector 59 selects and outputs the data of the normal operation waveform pattern register 57 and the data of the current limiting waveform pattern register 58 according to the low level and high level of a switching signal 62c described later. The address encoder 60 converts the 12-bit comparison circuit output 56a into an address signal. In the PWM pulse pattern table 61, the output (data) of the waveform pattern selector 59 is written to the address assigned to the waveform pattern register 57 for normal operation or the waveform pattern register 58 for current limitation of the data, and is output from the address encoder 60. The pattern register value at the specified address is output as a U-phase, V-phase, W-phase, U2-phase, V2-phase, and W2-phase PWM output 61a connected to an IGBT base driver (not shown)..The current limit pattern generation circuit 64 generates base drive signals PU, NU, PV, NV, PW, and PWM signals from the PWM output 61a output from the PWM pulse pattern table 61.NW, PU2, NU2, PV2, NV2, PW2, and NW2 are output, and a low level fixed value output signal 62b described later is output.TheUpon receipt, base drive signals NU, PU2, NV, PV2, NW, PW2Are set to a high level output, and other base drive signals are set to a low level output. When an overcurrent detection signal 62a indicating overcurrent detection is input from an unillustrated overcurrent detection circuit, the current limit control circuit 62 sets the fixed value output signal 62b to a low level, and the next carrier peak pulse 52b or carrier valley pulse When the switching signal 62c is changed from the high level to the low level at 52c and the overcurrent detection signal 62a is not input, the switching signal 62c is set to the high level again. The relationship between the triangular wave and the waveform pattern for normal operation is the same as that shown in FIG. 6 of the second embodiment.
[0057]
FIG. 10 shows the relationship among the triangular wave, the current limiting triangular wave comparison value, the current limiting waveform pattern, and the U-phase base signal.
[0058]
  Next, the operation of the PWM generator according to this embodiment will be described. First, the carrier generation circuit 52 is caused to count with the count clock 65. Each time the arithmetic circuit 51 processes the PWM comparison data of each phase and the space vector calculation, the normal operation triangular wave comparison value register 53 and the normal operationforA normal operation triangular wave comparison value and a normal operation waveform pattern are sequentially written in the waveform pattern register 57. The count value 52 a output from the carrier generation circuit 52 and the data held in the normal operation triangular wave comparison value register 53 are compared by the comparison circuit 56, and the 12-bit comparison result 56 a is converted into an address by the address encoder 60. On the other hand, in the PWM pulse pattern table 61, one waveform pattern is always selected by the output of the address encoder, and each bit of the pattern is output as a PWM signal U1, U2, V1, V2, W1, W2. Therefore, the three-level three-phase pulse pattern obtained from the space vector calculation result by the comparison result passes through the current limiting pattern generation circuit 64, and PU, NU, PV, NV, PW, NW, PU2, NU2, PV2, NV2, PW2, and NW2 base drive signals are output. Here, when an overcurrent occurs, an overcurrent detection signal 62a is input to the current limit control circuit 62 from an overcurrent detection circuit (not shown). Upon receiving the overcurrent detection signal 62a, the current limit control circuit 62 sets the fixed value output signal 62b to the low level. When the current limit pattern generating circuit 64 receives the low level fixed value output signal 62b, the current limit pattern generating circuit outputs NU, PU2 and NV, PV2 and NW, and PW2 are output.The base drive signal output is turned on, PU and NU2, PV and NV2, PW and NW2Shuts off the base drive signal output. During this time, the current limiting triangular wave comparison value and the current limiting pattern are calculated by the arithmetic circuit 51, and the current limiting triangular wave comparison value register 54 and the current limiting triangular register are compared.forThe waveform pattern register 58 is written. Generate current limit PWM waveform from current limit pattern data at the next peak or valley of any carrier.When the overcurrent is suppressed, normal operation data is selected by the switching signal 62c at the next arbitrary peak or valley of the carrier, and the normal operation can be promptly restored.
[0059]
Therefore, according to the present embodiment, even if an overcurrent occurs, the current can be limited without causing dielectric breakdown of the switching element, and when the overcurrent is suppressed, the normal operation can be promptly returned to the wide range of inverter applications. A PWM waveform that can be generated can be generated.
[0060]
  11 and 12 are timing charts of specific examples. As shown in FIG. 11, the carrier generation circuit 52 is generated.Count value 52a (displayed as TR in FIGS. 11 and 12)Of the normal operation triangular wave comparison values T0, T1, T2,... T11 held in the normal operation triangular wave comparison value register 53 are 490, 490, 2153, 2645, 2645, respectively. Reference numerals 4308, 5290, 6953, 6953, 7445, 9108 and 9108, and current limiting triangular wave comparison values Z0 and Z1 held in the current limiting triangular wave comparison value register 54 are denoted by 399 and 1997, respectively. Further, the normal operation waveform pattern register 57 and the current limiting waveform pattern register 58 are shown in FIG.11Waveform pattern for normal operation as shown inButPT0, PT1, PT2, ..., PT12, ZP0, ZP1, ... ZP5InIt shall be retained. At this time, a signal indicating the comparison result of the comparison circuit 5656a (displayed as Tout in FIG. 12)The carrier mountain pulseOVFL, carrier valley pulse UNFL, overcurrent detection signal CAL that goes low when overcurrent is detected, normal PWM when high level, switching signal PWM_ZP that indicates current limit PWM when low level, goes low when overcurrent is detected The fixed value output signal PWM_ZERO_L is as shown in FIG. 12, and U-phase, V-phase, and W-phase base drive signals are obtained. In the example shown in the figure, an overcurrent is detected at time t1, and the overcurrent detection signal CAL becomes low level, and therefore the fixed value output signal PWM_ZERO_L becomes low level. When the fixed value output signal PWM_ZERO_L goes low, the base drive signals PU2 and NU are turned on, and PU and NU2 are turned off..The V-phase and W-phase base drive signals operate in the same way. When the count value 52a reaches the peak of the carrier at time t2 and the carrier peak pulse OVFL is output, the fixed value output signal PWM_ZERO_L changes from the low level to the high level. Simultaneously with this switching, the switching signal PWM_ZP changes from the high level to the low level, and the values Z0 and Z1 of the current limiting triangular wave comparison value register 54 and the values ZP0 to ZP5 of the current limiting waveform pattern register 58 are selected. When the switching signal PWM_ZP is at a low level, the value of the current limiting pattern selected by the address created from the values Z0 and Z1 is output as the base signal.
[0061]
The numbers of the normal operation triangular wave comparison value register 53 and the current limiting triangular wave comparison value register 54, and hence the numbers of the normal operation waveform pattern register 57 and the current limiting waveform pattern register 58, are arbitrary.
[0062]
【The invention's effect】
As described above, the present invention has the following effects.
[0063]
1) According to the first aspect of the present invention, the PWM signal data in a certain arbitrary carrier cycle can be set in the previous carrier cycle, and the arithmetic circuit outputs the counter value, overflow signal, and underflow output from the carrier frequency generation circuit. The waiting time due to signal monitoring can be eliminated and a lot of processing time for other functions of the inverter device can be provided. In addition, even when the carrier frequency is increased, the load on the processing capability of the arithmetic circuit is reduced, so that a PWM waveform that can be used for a wide range of inverter applications can be generated. In addition, when writing only to the PWM setting register, the comparison value of each phase's PWM signal can be updated even on a carrier peak, so the pulse width of each phase's PWM signal can be accurately controlled even when the carrier frequency is low. Since it can be controlled, a stable PWM signal waveform can be realized.
[0064]
2) The invention of claim 2 eliminates the need for the process of converting the triangular wave comparison value into the space vector calculation result as in the prior art, reduces the burden on the arithmetic circuit, and is equivalent to the conventional case even in the case of the two-level method. Since it can operate, it can be applied to 2-level and 3-level inverters, and a PWM generator that can be used for a wide range of inverter applications can be provided.
[0065]
3) The invention of claim 3 generates a current limiting pattern in which two switching elements connected to the middle point side of the pair of capacitors are made conductive when an overcurrent occurs, and the remaining switching elements are made nonconductive. PWM is generated from the current limiting triangular wave comparison value and current limiting waveform pattern selected by the switching signal from the desired peak or valley of the carrier, and when the overcurrent is suppressed, the normal current limiting triangular wave comparison value and the normal current By generating PWM from the waveform pattern for restriction, we can provide a PWM generator that can be used for a wide range of inverter applications.
[Brief description of the drawings]
FIG. 1 is a block diagram of a PWM generator according to a first embodiment of the present invention.
FIG. 2 is a timing chart of the PWM generator of FIG.
FIG. 3 is a circuit diagram and a timing chart of a PWM comparison set value load circuit 7;
FIG. 4 is a timing chart of a circuit diagram of a frequency set value load circuit 6;
FIG. 5 is a block diagram of a PWM generator according to a second embodiment of the present invention.
FIG. 6 is a diagram showing a relationship between a triangular wave and a PWM pulse pattern in the PWM generator of the second embodiment.
7 is a waveform diagram of an example of an output 44a of the comparison circuit 44 in FIG.
8 is an output waveform (FIG. (1)) of the PWM pulse pattern table 47 in FIG. 5 and waveform diagrams of U-phase, V-phase, and W-phase base drive signals ((2) in FIG. 8). .
FIG. 9 is a block diagram of a PWM generator according to a third embodiment of the present invention.
FIG. 10 is a diagram showing a relationship among a triangular wave, a current limiting triangular wave, a current limiting waveform pattern register, and a U-phase PWM waveform in the PWM generator of the third embodiment.
FIG. 11 is a diagram showing specific examples of a triangular wave, a normal operation triangular wave comparison value, a current limiting triangular wave comparison value, a normal operating waveform pattern, and a current limiting waveform pattern in the third embodiment.
FIG. 12 is a timing chart of the third embodiment.
FIG. 13 is a block diagram of a first conventional PWM generator.
FIG. 14 is a timing chart of a first conventional example.
FIG. 15 is a block diagram of a second conventional PWM generator.
FIG. 16 is a block diagram of a PWM generator according to a third conventional example.
[Explanation of symbols]
1 Arithmetic circuit
2 Carrier frequency setting register
2a PWM signal generation frequency data
2b PWM signal generation frequency data 2aofWrite signal
2c Output data of carrier frequency setting register 2
3 U-phase PWM setting register
3a U phase PWM signal generation data
3b Signal to be written to U-phase PWM setting register 3
3c Output data of U-phase PWM setting register 3
4 V-phase PWM setting register
4a V-phase PWM signal generation data
4b V-phase PWM setting register4Signal to write to
4c Output data of V-phase PWM setting register 4
5 W-phase PWM setting register
5a W-phase PWM signal generation data
5b Signal to be written to W-phase PWM setting register 5
5c Output data of U-phase PWM setting register 5
6 Frequency setting value load circuit
6a Carrier cycle value register write signal
6b Write signal selection signal
7 PWM comparison set value load circuit
7a PWM comparison set value register write signal
8 Carrier cycle value register
8c Carrier cycle value register output data
9 U-phase PWM comparison value register
9c U-phase PWM comparison value registeroutput data
10V-phase PWM comparison value register
10c V-phase PWM comparison value register output data
11Phase WPWM comparison value register
11c W-phase PWM comparison value register output data
12 Carrier generation circuit
12a countTheLock
12b Counter value
12c Overflow signal
12d underflow signal
13 PWM generator
13a U-phase PWM generator
13c  V-phase PWM generator
13e  W-phase PWM generator
13b  U-phase PWM signal
13d  V-phase PWM signal
13f W phase PWM signal
14a U-phase comparator
14b V-phase comparator
14c W-phase comparator
21, 25, 26, 33, 35 AND gate
22, 23, 24, 27, 28, 31, 32, 34, 36, 37, 38, 40 D flip-flop
39 Selector
41 Arithmetic circuit
41a, 41b Write signal
42 Carrier generation circuit
42a Count value
43 Triangle wave comparison value register
44 Comparison circuit
44a Comparison circuit output
45 Waveform pattern register
46 Address encoder
47 PWM pulse pattern table
47a to 47f PWM output
48 Data bus
49countclock
51 Arithmetic circuit
52 Carrier generation circuit
52a count value
52b Carrier mountain pulse
52c carrier valley pulse
53 Triangular wave comparison value register for normal operation
54 Triangular wave comparison value register for current limit
55 Triangular wave comparison value selector
56 Comparison circuit
56a Comparison circuit output
57 Waveform pattern register for normal operation
58 Waveform pattern register for current limit
59 Waveform pattern selector
60 address encoder
61 PWM pulse pattern table
61a PWM output
62 Current limit control circuit
62a Overcurrent detection signal
62b Fixed value output signal
62c switching signal
63 Data bus
64 Current Limit Pattern Generation Circuit
64a Base drive signal
65countclock

Claims (3)

A PWM generator that performs pulse width modulation from comparison data output from an arithmetic circuit and carrier,
U-phase, V-phase, and W-phase PWM setting registers for holding U-phase PWM signal generation data, V-phase PWM signal generation data, and W-phase PWM signal generation data input from the arithmetic circuit, ,
A carrier frequency setting register for holding an upper limit value and a lower limit value of the period of the carrier inputted from the arithmetic circuit;
It said count value is output and each of the upper limit value, an O-buff low signal and underflow signal indicating that coincides with the lower limit value and outputs the counted value after counting at a fixed frequency in order to generate a triangular wave A carrier generating circuit composed of an up / down counter,
Receiving a carrier cycle value register write signal, holding the carrier frequency setting register data, and outputting to the carrier generation circuit, a carrier cycle value register;
A U-phase PWM comparison value register, V-phase PWM comparison value register, and W-phase PWM comparison value register that receive the PWM comparison setting value register write signal and retain the U-phase, V-phase, and W-phase PWM setting register data, respectively. ,
Each of the U-phase, V-phase, the data of the PWM comparison value register W-phase as compared with the count value of the career onset raw circuit, U-phase, respectively, V phase, U-phase PWM generator that outputs a PWM signal of the W phase Circuit, V-phase PWM generation circuit, W-phase PWM generation circuit,
When data is set in the carrier frequency setting register, the write signal selection signal is set to the first logic level, and when the underflow signal is output next, it is output as the carrier cycle value register write signal. A frequency setting value load circuit for setting the write selection signal to a second logic level;
When writing of the PWM signal generation data for each phase to the PWM setting register is completed, if the write selection signal is at the first logic level, the next underflow signal is output as the PWM comparison setting value register write signal A PWM comparison set value load circuit that outputs a next underflow signal or overflow signal as the PWM comparison value register write signal if the write selection signal is a second logic level ;
PWM generator with A PWM generator that performs pulse width modulation from comparison data output from an arithmetic circuit and carrier,
A carrier generation circuit composed of an up / down counter that counts at a constant frequency to generate a triangular wave and outputs the count value;
N triangular wave comparison value registers each holding N (N is an integer of 1 or more) triangular wave comparison values output from the arithmetic circuit by a comparison value register write signal also output from the arithmetic circuit;
N comparison circuits for comparing the output of the carrier generation circuit with the triangular wave comparison value held in each triangular wave comparison value register and outputting a signal corresponding to the magnitude;
An address encoder for converting a signal composed of an output signal of each comparison circuit into an address;
(N + 1) waveform pattern registers each holding (N + 1) waveform patterns output from the arithmetic circuit by a waveform pattern register write signal output from the arithmetic circuit,
The waveform pattern of each waveform pattern register is written to the address assigned to the waveform pattern register, and the waveform pattern of the address output from the address encoder is the U phase, V phase, W phase, U2 phase, and V2 phase. PWM pulse pattern table output as PWM output of W2 phase ,
PWM generator with A PWM generator that performs pulse width modulation from comparison data output from an arithmetic circuit and carrier,
A carrier consisting of an up / down counter that counts at a fixed frequency to generate a triangular wave, outputs the count value, and generates a peak of a triangular wave, a carrier peak pulse indicating a triangular wave valley, and a carrier valley pulse. Generating circuit;
Each of N (N is an integer of 1 or more) normal operation triangular wave comparison values output from the arithmetic circuit is held by a comparison value register write signal also output from the arithmetic circuit. Triangle wave comparison value register,
Each of M (M is an integer of 1 or more and M ≦ N) current limit triangular wave comparison values output from the arithmetic circuit is held by a comparison value register write signal output from the arithmetic circuit. Current limit triangle wave comparison value registers,
When the switching signal is at the first logic level, the data held in the normal operation triangular wave comparison value register is selected and output, and when the switching signal is at the second logic level, the current limiting triangular wave comparison value register A triangular wave comparison value selector that selects and outputs data stored in
N comparison circuits for comparing the output of the carrier generation circuit with each output of the triangular wave comparison value selector and outputting a signal corresponding to the magnitude;
An address encoder that converts a signal composed of signals output from each comparison circuit into an address;
(N + 1) normal operation waveform pattern registers each holding (N + 1) normal operation waveform patterns output from the arithmetic circuit by a waveform pattern register write signal also output from the arithmetic circuit;
Each of the 2 (M + 1) current limiting waveform patterns output from the arithmetic circuit is held by the current limiting waveform pattern write signal output from the same arithmetic circuit. A pattern register;
When the switching signal is at the first logic level, the data held in the normal operation waveform pattern register is selected and output, and when the switching signal is at the second logic level, the current limiting pattern register A waveform pattern selector that selects and outputs the stored data, and
Each output data of the waveform pattern selector is written to the address assigned to the data, and the address data output from the address encoder is the U phase, V phase, W phase, U2 phase, V2 phase, W2 phase. PWM pulse pattern table output as PWM output,
The base of each phase of PU, NU, PV, NV, PW, NW, PU2, NU2, PV2, NV2, PW2, and NW2 from the U phase, V phase, W phase, U2 phase, V2 phase, and W2 phase PWM output When a drive signal is output and a fixed value output signal of the second logic level is received, the switching elements of PU2 and NU, PV2 and NV, PW2 and NW are turned on, PU and NU2, PV and NV2, PW And a current limiting pattern generating circuit for outputting a signal for turning off the switching element of NW2 ,
During normal operation, the switching signal and the fixed value output signal are set to the first logic level, and when the overcurrent detection signal is input, the fixed value output signal is set to the second logic level and the next carrier peak pulse or When the carrier trough pulse causes the fixed value output signal to the first logic level and at the same time the switching signal is set to the second logic level and the overcurrent detection signal is not input, the switching signal is set to the first logic level. Current limit control circuit to level ,
PWM generator with

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