JP2002153074A - Pwm generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PWM generator which can alleviate a load corresponding to the processing capability of an arithmetic circuit for covering the wide application field. SOLUTION: A carrier generation circuit 42 is operated for the counting with a count clock 49. Data is sequentially written into a triangular wave comparison value register 43 and a waveform pattern register 45, whenever the PWM comparison data of each phase and space vector arithmetic operation are processed with an arithmetic operation circuit 41. First, a counter value 42a as an output of the carrier generation circuit 42 is compared with the data written in the triangular wave comparison value register 43 with a comparison circuit 44. A comparison result is always converted to an address with an address encoder 46. One waveform pattern register is always selected with an address encoder output from a PWM pulse pattern table 47, and each bit of register is outputted as the PWM outputs 47a, 47b, 47c, 47d, 47e and 47f.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage-type PWM inverter for changing the speed of an AC motor or the like, and more particularly to a PWM generator used for an inverter using a high-speed switching element such as an IGBT.

[0002]

2. Description of the Related Art FIG. 13 is a block diagram showing a configuration of a conventional PWM generator (hereinafter, referred to as a first conventional example).

The carrier frequency setting register 2 is a register in which the frequency of the PWM signal generation is set. The data 2a of the PWM signal generation frequency output from the arithmetic circuit 1 is written by the write signal 2b output from the arithmetic circuit 1. . The U-phase PWM setting register 3 is a register for holding U-phase PWM signal generation data. The U-phase PWM signal generation data 3a output from the arithmetic circuit 1 is written by the write signal 3b output from the arithmetic circuit 1. It is. The V-phase PWM setting register 4 is a register for holding V-phase PWM signal generation data. The V-phase PWM signal generation data 4a output from the arithmetic circuit 1 is used by the write signal 4b output from the arithmetic circuit 1. Written. The W-phase PWM setting register 5 is a register for holding W-phase PWM signal generation data. The W-phase PWM signal generation data 5a output from the arithmetic circuit 1 is used by the write signal 5b output from the arithmetic circuit 1. Written. The carrier generation circuit 12 is composed of an up / down counter for generating a triangular wave. The output data 2c of the carrier frequency setting register 2 and the count clock 12a are input. When the counter value 12b and the counter value 12b match the carrier cycle 2c. The overflow signal 12d and the underflow signal 12 when the counter value 12 matches 0
Output c. The PWM signal generation circuit 13 includes a U-phase PWM signal generation circuit 13a, a V-phase PWM signal generation circuit 13b, and a W-phase PWM signal generation circuit 13c. The U-phase comparator 14a calculates the counter value 12b
U-phase PWM signal generation data 3c is compared, and U-phase PWM signal 13b is compared.
Output to The U-phase PWM signal 13b is connected to an IGBT (Insulat
ed Gate Bipolar Transiston), and a U-phase // U-phase base drive signal is output. The V-phase comparator 14b compares the counter value 12b with the V-phase PWM signal generation data 4c and outputs a V-phase PWM signal 13d.
The V-phase PWM signal 13d is applied to an IGBT base driver (not shown), and V-phase and / V-phase base drive signals are output.

The W-phase comparator 14c has a counter value 12b and a W-phase PW
It compares the M signal generation data 5c and outputs a W-phase PWM signal 13f. The W-phase PWM signal 13f is applied to an IGBT base driver (not shown), and W-phase and / W-phase base drive signals are output.

The PWM signal generation data 3a, which is written into each of the PWM setting registers 3, 4, and 5 by the arithmetic circuit 1,
4a and 5a are data for setting a high level period and a low level period of the PWM signal, which are determined by a combination of PWM waveforms to be generated. The carrier generation circuit 12
Is a three-phase common use.

Next, the operation of the conventional PWM generator will be described. In order to generate a PWM waveform, first, the carrier generation circuit 12 is operated to count by the count clock 12a. Then, U rewritable by the arithmetic circuit 1
When the content of the counter value 12b matches the U-phase PWM signal generation data 3c held in the phase PWM setting register 3, the comparator 14a outputs a U-phase PWM signal and is connected to an IGBT base driver (not shown). To generate U-phase IGBT base drive signals U and / U. The arithmetic circuit 1
When the data 2a of the PWM signal generation cycle is written in the carrier frequency setting register 2, the PWM comparison cycle is changed. Entering a large value increases the operating cycle of the comparator that generates PWM, and entering a small value decreases the operating cycle of the comparator.

Here, a signal waveform diagram in the case of the triangular wave modulation system is shown in FIG. In FIG. 14, the overflow signal 12c is at a low level when the output data 2c of the carrier frequency setting register matches the counter value 12b, and the underflow signal 12d is at a low level when the counter value 12b matches 0.

The PWM setting registers 3, 4, 5,
Writing to the carrier frequency setting register 2 is always performed just before the valley of the carrier, and writing to only the PWM setting registers 3, 4, and 5 of each phase is always performed just before the hill or valley of the carrier.

FIG. 15 shows another conventional PWM generator (hereinafter referred to as “PWM generator”).
FIG. 9 is a block diagram showing a configuration of a second conventional example).

The carrier generation circuit 72 is constituted by an up / down counter for generating a triangular wave, counts the clock 77, and outputs a count value 72a. Each of the three triangular wave comparison value registers 73 holds the data (triangle wave comparison value) output from the arithmetic circuit 71 to the data bus 76 based on the write signal 71a also output from the arithmetic circuit 72. The three comparison circuits 74 compare the count value 72a output from the carrier generation circuit 72 with the data held in each of the triangular wave comparison value registers 73, and when the former is larger than the latter, the high level signal is output. 74a, 74b and 74c are output. Signal 74a is U-phase PWM
The signal is connected to a base driver of an IGBT (not shown) to output U-phase and / U-phase base drive signals. The signal 74b is a V-phase PWM signal, and is connected to an IGBT base driver (not shown) to output V-phase and / V-phase base drive signals. The signal 74c is a W-phase PWM signal, which is connected to an IGBT base driver (not shown) to output a W-phase // W-phase base drive signal. Note that the data written to each triangular wave comparison value register 73 by the arithmetic circuit 71 is determined by the combination of the PWM waveforms to be generated, and is data for setting a high level period and a low level period of the PWM signal. The carrier generation circuit 72 is shared for three phases.

The operation of the conventional PWM generator will be described. First, the carrier generation circuit 72 is operated to count by the count clock 77. Then, T0 of the U-phase triangular wave comparison value register 73 rewritable by the arithmetic circuit 71
Holds the comparison value. When the carrier generation circuit output 72a exceeds the held U-phase triangular wave comparison data, the comparison circuit 74 outputs a high-level U-phase PWM signal 74a. The PWM signal 74a is connected to a base driver of an IGBT (not shown) and generates base drive signals U and / U of a U-phase IGBT. Since the V-phase and W-phase are the same as the U-phase, the description of the operation is omitted.

FIG. 16 is a block diagram of still another conventional PWM generator (hereinafter, referred to as a third conventional example).

The carrier generation circuit 82 includes an up / down counter for generating a triangular wave, counts the clock 87, and outputs a count value 82a. Each of the six triangular wave comparison value registers 83 holds the data (triangular wave comparison value) output from the arithmetic circuit 81 to the data bus 86 by the write signal 81a also output from the arithmetic circuit 81. Each of the six comparison circuits 84 outputs a high level signal 84a, 84b when the count value 82a output from the carrier generation circuit 82 becomes larger than the data held in the corresponding triangular wave comparison value register 83, and a low level signal 84a, 84b, 84c, 84d, 84e, 84e and 84f are output. The signal 84a is a PWM signal for controlling the U-phase IGBT upper arm, and is connected to the IGBT base drivers S1 and S3 of the power module 90. A signal 84d is a PWM signal for controlling the lower arm of the U-phase IGBT, and is connected to the base drivers S2 and S4 of the IGBT. The same applies to the V phase and the W phase. It is also desired to generate data to be written into each triangular wave comparison value register 83 by the arithmetic circuit 81.
This data is determined by a combination of PWM waveforms and is used to set a high-level period and a low-level period of a PWM signal.
Further, the carrier generation circuit 82 is commonly used for three phases.

The operation of the conventional PWM generator will be described. First, the carrier generation circuit 82 is operated to count by the count clock 87. Then, T0 of the U-phase triangular wave comparison value register 83 rewritable by the arithmetic circuit 81
Holds the triangular wave comparison value. When the carrier generation circuit output 82a exceeds the held U-phase triangular wave comparison data, the comparison circuit 84 outputs a high-level U-phase PWM signal 84a.
Is output. 84a and 84d are PWM signals for U-phase IGBT control, and IGBT base drivers S1, S2, S3,
Connected to S4 for U-phase output. Since the V-phase and W-phase are the same as the U-phase, the description of the operation is omitted.

[0015]

The PW of the first conventional example described above
In the M generator, the case of writing to the PWM setting registers 3 to 5 and the carrier frequency setting register 2 and the PW of each phase
The arithmetic circuit 1 always keeps the counter value 12b and the overflow signal 12 when writing only to the M setting registers 3 to 5.
c, while monitoring the underflow signal 12d, data was written to each of the setting registers 2, 3, 4, and 5. Therefore, the contents of the counter value 12b of the carrier generation circuit 12 and P
By comparing and detecting with the contents of WM setting registers 3 to 5,
Although the PWM signals 13b, 13d, and 13f are repeatedly output, when the carrier cycle becomes short, it is necessary to wait until the timing of writing the data of the PWM setting registers 3, 4, and 5 to generate the PWM signal. There is a problem that the burden on processing capacity is large. That is, in order to control the PWM output with high accuracy, it is necessary to calculate and write the write data to the PWM setting registers 3 to 5 and the carrier frequency setting register 2 at high speed. In FIG. 14, the PWM
The waveform is U-phase, and is shown only when data is written to the PWM setting register 3. However, actually, the PWM setting data 3a, 4a, 5a for three phases and the carrier comparison value are calculated during the carrier cycle, and The data has been written to the registers 3, 4, and 5. Such a waveform is output for many cycles. The arithmetic circuit 1 frequently monitors the counter value 12b, the overflow signal 12c, and the underflow signal 12d in each cycle,
Data is written to each of the registers 23, 4, and 5, and the comparator 1
It is necessary to detect coincidence at 4a, 14b and 14c to realize the PWM signals 13b, 13d and 13f of each phase of PWM. In order to write the set values to the registers 3, 4, and 5, the arithmetic circuit 1 spends most of the processing contents on monitoring the counter value 12b, the overflow signal 12c, and the underflow signal 12d. In addition, if an attempt is made to increase the carrier frequency in order to reduce the noise of the inverter, processing other than the PWM calculation is restricted, and the burden on the arithmetic circuit 1 is further increased.

The second prior art PWM generator can support only a two-level output type inverter. If it supports a three-level inverter, two comparison circuits are required and two comparison circuits are used. Was. On the other hand, it is common to use a space vector for the arithmetic processing of the three-level inverter. When two comparison circuits are used in a conventional device, it is necessary to convert triangular wave comparison value data into a space vector. Since the space vector requires a large amount of arithmetic processing at the same carrier frequency and requires a long arithmetic time, the arithmetic cycle becomes longer, and the update of the comparison value is extended. Therefore, the carrier frequency becomes lower in order for the arithmetic processing to end within the carrier cycle.

In the third prior art PWM generator, when an overcurrent occurs, the upper arm of the UVW phase is simultaneously turned on to limit the current, and then the operation of turning off the upper arm is repeated to recirculate the current. There is a method of limiting the current by forming a pattern, but this method can be applied only to a two-level output type inverter. This is because when a three-level inverter is used, the IGBT may be destroyed depending on the pattern before transition to the circulation pattern. The recirculation pattern is a pattern that turns on the upper or lower arm at the same time for all three phases.
If the switching transistors S1 and S2 are simultaneously turned off while the normal patterns of S1 and S2 are at the high level, the switching transistor S2 may be turned off first due to the variation in the off time of the IGBT turn. In this case, the induced electromotive force of the load and the bus voltage are applied to the switching transistor S2, and the switching transistor S2 is destroyed. A similar problem occurs when an emergency stop is performed. That is, if all of the base drive signals are turned off while the switching transistors S1, S2 or S3, S4 are on, an excessive voltage is applied to the switching transistor S2 or S3 due to variation in the switching time of the IGBT, thereby causing dielectric breakdown.

A first object of the present invention is to provide a PWM generator which can reduce the load on the processing capability of an arithmetic circuit and can be used for a wide range of inverter applications.

A second object of the present invention is to quickly limit the current without causing a power failure when an overcurrent occurs, and to quickly return to normal operation when the overcurrent is suppressed. It is to provide a PWM generator capable of.

[0020]

A PWM generator according to a first embodiment of the present invention corresponds to a first conventional example, and includes a carrier cycle value register and U-phase, V-phase, and W-phase PWM comparison value registers. And a frequency set value load circuit and a PWM comparison set value load circuit.

The carrier cycle value register receives the carrier cycle value register write signal, holds the data of the carrier frequency setting register, and outputs the data to the carrier generation circuit.

The U-phase PWM comparison value register, the V-phase PWM comparison value register, and the W-phase PWM comparison value register respectively receive the PWM comparison setting value register write signal and receive the data of the U-phase, V-phase, and W-phase PWM setting registers, respectively. Hold.

U-phase PWM generator, V-phase PWM generator, W-phase PWM
The generator compares the data of the U-phase, V-phase, and W-phase PWM comparison value registers with the count value of the carrier generator,
Outputs U-phase, V-phase, and W-phase PWM signals, respectively.

When the data is set in the carrier frequency setting register, the frequency setting value load circuit sets the write signal selection signal to the first logic level, and then, when the underflow signal is output, changes this to the period value register. The write selection signal is output as a second signal.
Logical level.

When the PWM comparison setting value load circuit finishes writing the PWM signal generation data of each phase to the PWM setting register, the next underflow signal is compared with the next underflow signal if the write selection signal is at the first logical level. The signal is output as a value setting value register write signal, and if the write signal is at the second logical level, the next underflow signal or overflow signal is output as a PWM comparison value register write signal.

Therefore, the data of the PWM signal in an arbitrary carrier cycle can be set in the immediately preceding carrier cycle, the waiting time for the arithmetic circuit to detect the timing of writing to the register is reduced, and the load on the processing capability of the arithmetic circuit is reduced. And a PWM waveform that can be used for a wide range of inverter applications can be generated.

The PWM generator according to the second embodiment of the present invention corresponds to the second conventional example, and includes an address encoder for converting the output of the comparison circuit into an address, a waveform pattern register for holding a waveform pattern, and a waveform pattern. The waveform pattern of the address stored in the address and output from the address encoder is represented by U-phase, V-phase, W-phase, U2-phase, V2-phase, and W-phase.
And a PWM pattern table that is output as a two-phase PWM output.

By directly writing the space vector operation result to the waveform pattern register, the load on the operation circuit is reduced,
The arithmetic processing can be completed within the conventional carrier cycle. According to this embodiment, a two-level inverter can also be controlled, and a PWM waveform that can be used for a wide range of inverter applications can be generated.

The PWM generator according to the third aspect of the present invention corresponds to the third conventional example. The PWM generator according to the second aspect further includes a current limiting triangular wave comparison value register, a triangular wave comparison value selector, a current limiting A waveform pattern register, a waveform pattern selector, a current limit control circuit, and a current limit pattern generation circuit.The carrier generation circuit has a carrier peak pulse indicating a peak and a valley of a triangular wave, in addition to the count value.
Generate a carrier valley pulse. Here, the PW of the second embodiment
The triangular wave comparison value register and the waveform pattern register in the M generator are referred to as a normal operation triangle wave comparison value register and a normal operation waveform pattern register, respectively.

At the time of normal operation (overcurrent is not detected), the output of the triangular wave comparison value register for normal operation is selected by the triangular wave comparison value selector and compared with the count value of the carrier generation circuit by the comparison circuit. When the data in the pattern register is selected by the waveform pattern selector, the PWM
The data is written into the pattern table and operates in the same manner as the PWM generator of the second embodiment.

When an overcurrent is detected, a fixed value output signal is output to the current limit pattern generation circuit, and a predetermined base drive signal output from the current limit pattern generation circuit is set to a fixed value. At the next carrier peak pulse or carrier valley pulse, the fixed value output signal output to the current limit pattern generation circuit is stopped, and the current limit control circuit switches between the triangular wave comparison value selector and the waveform pattern selector, and outputs the current limit signal. The data of the triangular wave comparison value register and the pattern of the current limiting waveform pattern register are selected.

When an overcurrent occurs, a current limiting pattern is generated that turns on the two switching elements connected to the midpoint of the pair of capacitors and turns off the remaining switching elements. The switching element connected to the middle point of the pair of capacitors does not break down without turning off the switching element connected to the point side and turning on the remaining switching elements.
When the overcurrent is limited, the operation can be returned to the energized operation. Further, even if an emergency stop pattern is written in the current limiting waveform pattern, the dielectric breakdown does not occur similarly.

According to this aspect, the overcurrent limit can be controlled,
A PWM waveform that can be used for a wide range of inverter applications can be generated.

[0034]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a PWM signal generator according to a first embodiment of the present invention.

The carrier frequency setting register 2, U-phase PWM setting register 3, V-phase PWM setting register 4, and W-phase PWM setting register 5 are the same as those shown in FIG. Upon writing to the carrier frequency setting register 2, the frequency setting value load circuit 6 outputs a carrier cycle value register writing signal 6a and a writing signal selection signal 6b according to the condition of the underflow signal 12d. When there is a write signal 5b for writing the W-phase PWM signal generation data 5a to the W-phase PWM setting register 5, the PWM comparison value set value load circuit 7 outputs the write signal selection signal 6b, the overflow signal 12c, and the underflow signal 1.
A PWM comparison register write signal 7a is output according to the condition of 2d. The carrier cycle value register 8 holds the output 2c of the carrier frequency setting register 2 as a carrier cycle value register write signal 6a. U-phase PWM comparison value register 9 is U
The output 3c of the phase PWM setting register 3 is held by the PWM comparison register write signal 7a. V-phase PWM comparison value register 10
The output 4c of the phase PWM setting register 4 is held by the PWM comparison register write signal 7a. W-phase PWM comparison register 11 is W-phase
The output 5c of the PWM setting register 5 is held by the PWM comparison value register write signal 7a. U-phase PWM generation circuit 13a, V-phase PWM
The generation circuit 13c and the W-phase PWM generation circuit 13e are respectively U-phase PWM
Comparison value register 9, V-phase PWM comparison value register 10, W-phase PWM
The output data 9c, 10c, and 11c of the comparison value register 11 are compared with the counter value 12b, and a U-phase PWM signal 13b, a V-phase PWM signal 13d, and a W-phase PWM signal 13f are output.

The operation of the thus configured PWM generator will be described.

First, the carrier generation circuit 12 is operated to count by the count clock 12a. Each time the arithmetic circuit 1 calculates the carrier frequency setting 2a and the PWM signal generation data 3a, 4a, 5a of each phase, the data is sequentially written into the PWM setting registers 3, 4, 5.

First, the operation when the data 2a of the frequency of the PWM signal generation is set will be described. When data is written to the carrier frequency setting register 2, the frequency setting value loading circuit 6 sets the signal 6b to a high level at the falling edge of the write signal 2b to the carrier frequency setting register 2. Next, the signal 6b is reset to a low level at the rising edge of the underflow signal 12d. The signal 6a outputs the same signal as the underflow signal 12d when the signal 6b is at a high level. Therefore, the frequency is updated at the valley of the carrier that comes first after the calculation result is output.

Next, the operation when the PWM setting of each phase is updated will be described. The calculation result of each phase PWM comparison data is sequentially written to the PWM setting registers 3, 4, and 5, and the W phase PW
When written to the M setting register 5, the write signal 5b is
It is input to the PWM comparison set value load circuit 7. The PWM comparison setting value load circuit 7 outputs a W-phase PWM setting register write signal 5b.
Set the internal signal to high level at the falling edge of. Next, when the signal 6b is at a low level, an AND signal of the overflow signal 12c and the underflow signal is output. When the signal 6b is at a high level, the internal signal is reset to a low level at the rising edge of the underflow signal 12d. Signal 7
a is a signal selected by the signal 6b when the internal signal is at a high level, that is, an overflow signal 12c and an underflow signal 12d when the signal 6b is at a low level;
When the signal 6b is at the high level, it becomes the underflow signal 12d. Therefore, when the PWM setting value and carrier frequency setting are performed, the calculation result is output, the carrier frequency is updated at the first carrier valley, only the PWM setting value is updated, and the carrier frequency setting is not performed. The calculation result is output and updated at the first peak or valley of the carrier.

FIG. 2 shows the carrier generation when only the PWM setting is performed once after the carrier frequency setting and the PWM setting are performed twice in the present embodiment, and the last carrier frequency setting and the PWM setting are performed. Circuit 12 and U-phase PWM generation circuit 13
The waveform of a is shown. The underflow signal 12d, the overflow signal 12c, and the write signal to each register are normally at the high level, and at the time of operation, they are, for example, low pulses of one count clock pulse.

The operation of the PWM generator of FIG. 1 will be described in more detail with reference to FIG. In FIG. 2, when the carrier generation circuit 12 operates with the count clock, the arithmetic circuit 1 repeats various arithmetic operations to control the PWM generation. PWM calculation is one of these processes. P
When the WM operation is performed, the carrier frequency value: PW
The M comparison value is calculated, and if the result is different from the previous one, the carrier frequency setting register 2, U-phase PWM setting register 3, V-phase P
The calculation result is written to the WM setting register 4 and the W-phase PWM setting register 5. First, regarding the change of the carrier frequency, when data is written into the carrier frequency setting register 2, the carrier frequency write signal 2b becomes a low level pulse. When receiving the falling edge of the signal 2b, the frequency setting value load circuit 6 sets the signal 6b to a high level. On the other hand, the frequency setting value load circuit 6 also receives the underflow signal 12d, and receives a low-level pulse when the valley of the carrier comes. Underflow signal 12
Upon receiving the rising edge of d, the signal 6b is reset to a low level. When the signal 6b is at the high level, the underflow signal 12d is output as the carrier frequency write signal 6a. When a low-level pulse is output from the carrier frequency write signal 6a, the carrier cycle value register 8 holds the output 2c of the carrier frequency setting register 2. Therefore, the data is written from the arithmetic circuit 1 to the carrier frequency setting register 2 at an arbitrary time, and the cycle of the carrier that occurs immediately thereafter is updated to the carrier frequency register 8 at the valley of the carrier. Next, regarding the change of PWM setting,
When data is written to the PWM setting register 5, the PWM setting register write signal 5b becomes a low level pulse. P
When receiving the falling edge of the 5b signal, the WM comparison set value load circuit 7 sets the internal signal to a high level. On the other hand, the PWM comparison set value load circuit 7 outputs the overflow signal 1
2c and the underflow signal 12d are also input, and when the peak or valley of the carrier comes, a low-level pulse is input. The internal signal is reset at the rising edge of the overflow signal 12c or the underflow signal 12d. Therefore, when the signal 6b is at the high level, the signal 12d is output as the PWM comparison register write signal 7a. When a low-level pulse is output as the W-phase PWM setting register write signal 5b, the PWM setting registers 3, 4, and 5 of each phase are held as internal signals of the PWM comparison setting value load circuit 7, and this signal and the signal 6b are output. Depending on the condition, the PWM comparison value register 9 for each phase at the next carrier peak or valley
, 10 and 11 are the outputs of the PWM registers 3c, 4c,
Hold 5c. Therefore, the PWM setting is calculated for the previous carrier, and is updated at the peak or valley of the next carrier if there is no change in carrier frequency, and updated at the valley of the next carrier if there is a change in carrier frequency. You.

As described above, the frequency setting value load circuit 6 and the PWM comparison value load circuit 7 for generating a control signal for switching the update timing of the carrier cycle value and the comparison data of each phase at an arbitrary carrier peak or valley are provided. The provision of the carrier frequency setting value and the P of each phase to the carrier generation circuit 12 and the PWM generation circuit 13 by the arithmetic circuit 1
It is possible to reduce the waiting time between detection of the timing of writing the WM set value, reduce the load on the processing capability of the arithmetic circuit 1, and generate a PWM waveform that can be used for a wide range of inverter applications.

Although the U-phase waveform has been described in the above embodiment, it goes without saying that the V-phase and W-phase waveforms can be realized in the same manner as the U-phase waveform.

FIG. 3 is a circuit diagram and a timing chart of the PWM comparison set value load circuit 7. The PWM comparison set value load circuit 7 includes D flip-flops 22, 23, 24, 27,
28, 40, AND circuits 21, 25, 26 and selector 39
It is composed of The AND circuit 21 takes the logical product of the underflow signal 12c and the overflow signal 12d. When the power is turned on, the D flip-flops 22, 23, 24, 2
7 and 40 are reset or preset by a reset signal reset. Therefore, when writing is performed on the W-phase PWM setting register 5, the write signal reg_wrL is input, and reg_wrL_temp, which is the output of the D flip-flop 22, becomes "H". This signal is a gate signal of the next AND circuit 26, and the other input signal PWMCYLp of this AND circuit 26
Is output. After the output of the AND circuit 26 is held in the D flip-flop 27 for waveform shaping, the selector 3
At 9, the signal is selected when the signal 6b is "L", held in the D flip-flop 40, and becomes the PWM comparison set value register write signal 7a. Therefore, this signal 7a coincides with the peak or valley of the carrier.

FIG. 4 is a circuit diagram and a timing chart of the frequency set value loading circuit 6. The frequency setting value load circuit 6 is composed of D flip-flops 31, 32, 36, 37 and AND circuits 33, 35. D flip-flop 3
Holds one underflow signal 12d. When the power is turned on, the D flip-flops 31, 32, 36, and 37 are reset or preset by a reset signal reset.
Then, the write signal 2b (reg_weL) of the PWM signal frequency
And the output reg_wrL_t of the D flip-flop 34
emp becomes “H”. This signal reg_wrL_temp is transmitted to the next stage AN
This is the gate signal of the D circuit 35, and when this signal is "H".
The other input signal UNFLp of the AND circuit 35 is passed. AND
The output of the circuit 35 is held in a D flip-flop 36 for waveform shaping, and is output as a carrier cycle value register write signal 6a. The difference from the PWM comparison setting value load circuit 7 is that only the carrier valley signal generated first after the carrier is written is output. Also,
At this time, the signal reg_wrL_temp is changed to the write signal selection signal 6
b is output as a switching signal of the selector 39.

FIG. 5 is a block diagram showing a configuration of a PWM signal generator according to a second embodiment of the present invention.

The carrier generation circuit 42 operates by the count clock 49 and generates a triangular wave. The twelve triangular wave comparison value registers 43 store the data (triangular wave comparison values) output from the arithmetic circuit 41 to the data bus 48 similarly to the arithmetic circuit 4.
It is held by the write signal 41a output from the control signal No. 1.
The twelve comparison circuits 44 output a high-level comparison circuit output 44a when the count value 42a output from the carrier generation circuit 42 is larger than the data held in the corresponding triangular-wave comparison value register 43, and output a low-level comparison circuit output 44a when the count value 42a is smaller. I do. The thirteen waveform pattern registers 45 are
The data (waveform pattern) output from 1 to the data bus 48 is held by the write signal 41b also output from the arithmetic circuit 41. Address encoder 46 is 1
The 2-bit comparison circuit output 44a is converted into an address signal. As shown in Table 1, the PWM pulse pattern table 47 writes the data of the waveform pattern register 45 to the address assigned to the waveform pattern register, and converts the pattern register value of the address output from the address encoder 48 into an IGBT (not shown). U-phase, V-phase, W-phase, U2-phase, V2-phase, W2-phase P connected to the base driver
Output as WM outputs 47a, 47b, 47c, 47d, 47e, 47f.

[0049]

[Table 1]

FIG. 6 shows the relationship between the triangular wave and the PWM pulse pattern. In the PWM pulse pattern table 47, the corresponding PWM pattern is selected from the address ADR, and the U phase,
V-phase, W-phase, U2-phase, V2-phase, W2-phase PWM signals 47a, 4
Output as 7b, 47c, 47d, 47e, 47f.

Next, the operation of the PWM generator of this embodiment will be described. Carrier generation circuit 42 counts clock 4
At 9 the counting operation is performed. Each time the arithmetic circuit 41 processes the PWM comparison data of each phase and the space vector calculation, the triangle wave comparison value and the waveform pattern are sequentially written in the triangle wave comparison value register 43 and the waveform pattern register 45. Counter value 42 which is the carrier generation circuit output
The comparison circuit 44 compares a with the triangular wave comparison value written in the triangular wave comparison value register 43. The comparison result is always converted into an address by the address encoder 46. One waveform pattern register is always selected from the PWM pulse pattern table 47 by the address encoder output, and each bit of the register is used as an output 47a, 47b, 47c,
Output as 47d, 47e, 47f.

Therefore, the three-level three-phase PWM pulse pattern obtained from the space vector operation result based on the comparison result is a U-phase, / U-phase, V-phase, / V-phase, W-phase, / W-phase, U2-phase,
It is output as a drive signal of / U2 phase, V2 phase, / V2 phase, W2 phase, / W2 phase.

Here, a specific example will be described with reference to FIGS.

The triangular wave TR generated by the carrier generation circuit 42
Is the maximum value of 9596, and the triangular wave comparison values T0, T1, T2,... T11 held in the triangular wave comparison value register 43.
Are 490, 490, 2153, 2645, respectively.
2645, 4308, 5290, 6953, 6953,
7445, 9108, and 9108, the comparison circuit 44
, C11 become pulses as shown in FIG. 7, and a 12-bit output Tout obtained by bundling these pulses
(Comparison circuit output 44a) is, as shown in FIG.
F, 1FF, 03F, 01F, 007, 003, 000, 0
07, 01F, 03F, 07F, 1FF, 3FF, FFF, ...
・ It becomes. On the other hand, in the PWM pulse pattern table 47, at addresses 0, 1, 3, 7,..., FFF, the PWM waveform patterns PT0, PT1, PT2, PT3,.
.., PT12 is stored. Therefore, from the PWM pulse pattern table 47, as shown in FIG.
U-phase PWM output U1, U2, V-phase PWM output V1, V2, W-phase P
WM outputs W1 and W2 are output. Then, the U-phase base drive signals PU, PU2, NU, NU as shown in FIG.
2. V-phase base drive signals PV, PV2, NV, NV2, and W-phase base drive signals PW, PW2, NW, NW2 are generated. The number of the triangular wave comparison value registers 43, that is, the number of the comparison circuits 44 and the waveform pattern registers 45 is arbitrary.

FIG. 9 is a block diagram of a PWM generator according to a third embodiment of the present invention.

The carrier generation circuit 52 performs a count operation with a count clock 65, and outputs a count value 52a, a carrier peak pulse 52b having a low level at a carrier peak, and a carrier valley pulse 52c having a low level at a carrier valley. 12 normal operation triangular wave comparison value registers 5
The three and two current limiting triangular wave comparison value registers 54 output the data (normal operation triangular wave comparison value and current limiting triangular wave comparison value) output from the arithmetic circuit 51 to the data bus 63 from the arithmetic circuit 51 as well. It is held by the write signal 54a. The triangular wave comparison value selector 55 selects and outputs the data of the normal operation triangular wave comparison value register 53 and the data of the current limiting triangular wave comparison value register 54 according to a low level and a high level of a switching signal 62c described later.
The twelve comparison circuits 56 compare each data output from the triangular wave comparison value selector 55 with the count value 52a output from the carrier generation circuit 52, and output a high-level output if the latter is larger than the former and a low-level output if the latter is smaller. I do. 1
The three normal operation waveform pattern registers 57 and the six current limiting waveform pattern registers 58 store data (normal operation waveform patterns and current limiting waveform patterns) output from the arithmetic circuit 51 to the data bus 63. Similarly, it is held by a write signal 54b output from the arithmetic circuit 51. The waveform pattern selector 59 outputs a switching signal 6 described later.
The data of the normal operation waveform pattern register 57 and the data of the current limiting waveform pattern register 58 are selected and output according to the low level and the high level of 2c. The address encoder 60 converts the 12-bit comparison circuit output 56a into an address signal. In the PWM pulse pattern table 61, the output (data) of the waveform pattern selector 59 is
The data is written to the address assigned to the normal operation waveform pattern register 57 or the current limiting waveform pattern register 58, and the pattern register value of the address output from the address encoder 60 is connected to the IGBT base driver (not shown). U phase, V phase, W
The current limit pattern generating circuit 64 outputs the PWM output 61a of the two-phase, U2-phase, V2-phase, and W2-phase. The base drive signals PU, NU, PV, NV, and PW are output from the PWM output 61a output from the PWM pulse pattern table 61. , NW, PU2, NU2, P
When V2, NV2, PW2, and NW2 are output and a low-level fixed value output signal 62b described later is received, the base drive signal N
U, PU2, NV, PV2, NW, and PW are output at a high level, and the other base drive signals are output at a low level.
When an overcurrent detection signal 62a indicating overcurrent detection is input from an overcurrent detection circuit (not shown), the current limit control circuit 62 sets the fixed value output signal 62b to a low level, and outputs the next carrier peak pulse 52b or carrier valley pulse. At 52c, the switching signal 62c is changed from the high level to the low level. When the overcurrent detection signal 62a is no longer input, the switching signal 62c is changed to the high level again. The relationship between the triangular wave and the waveform pattern for normal operation is the same as that shown in FIG. 6 of the second embodiment.

FIG. 10 shows the relationship between the triangular wave, the current limiting triangular wave comparison value, the current limiting waveform pattern, and the U-phase base signal.

Next, the operation of the PWM generator of this embodiment will be described. First, the carrier generation circuit 52 is operated to count by the count clock 65. Each time the arithmetic circuit 51 processes the PWM comparison data of each phase and the space vector operation, the normal operation triangular wave comparison value register 53
The normal operation waveform pattern register 57 sequentially stores a normal operation triangular wave comparison value and a normal operation waveform pattern. Count value 52 of output of carrier generation circuit 52
The data held in the normal operation triangular wave comparison value register 53 are compared by the comparison circuit 56, and the 12-bit comparison result 56 a is converted into an address by the address encoder 60. On the other hand, in the PWM pulse pattern table 61, one waveform pattern is always selected by the output of the address encoder, and each bit of the pattern is converted to the PWM signal U1, U1.
2, output as V1, V2, W1, W2. Therefore, the three-level three-phase pulse pattern obtained from the space vector operation result based on the comparison result passes through the current limit pattern generation circuit 64, and the PU, NU, PV, NV, PW, NW, PU
2, NU2, PV2, NV2, PW2, and NW2 base drive signals are output. Here, when an overcurrent occurs, an overcurrent detection signal 62a is input to the current limit control circuit 62 from an overcurrent detection circuit (not shown). When receiving the overcurrent detection signal 62a, the current limit control circuit 62 sets the fixed value output signal 62b to low level. Upon receiving the low-level fixed value output signal 62b, the current limiting pattern generating circuit 64 outputs the current limiting pattern generating circuit outputs NU, PU2 and N
Cut off the output of base drive signals other than V, PV2 and NW, PW2. During this time, the current limiting triangular wave comparison value and the current limiting pattern are calculated by the arithmetic circuit 51, and the current limiting triangular wave comparison value register 54 and the current limiting waveform pattern register 58 are used.
Write it in When an overcurrent that generates a current limiting PWM waveform from the current limiting pattern data is suppressed at the peak or valley of the next arbitrary carrier, the data of the normal operation is switched to the switching signal 62c at the peak or valley of the next arbitrary carrier. And can immediately return to normal operation.

Therefore, according to the present embodiment, even if an overcurrent occurs, the current can be limited without causing the switching element to undergo insulation breakdown, and when the overcurrent is suppressed, the normal operation can be promptly returned to normal operation. A PWM waveform that can be used for a specific purpose can be generated.

FIGS. 11 and 12 show timing charts of a specific example.
It is. As shown in FIG.
The maximum value of the triangular wave TR at which
The normal operation counter held in the square wave comparison value register 53
The values of the square wave comparison values T0, T1, T2,.
490, 490, 2153, 2645, 2645, 4
308, 5290, 6953, 6953, 7445, 9
108, 9108, current limiting triangular wave comparison value register 5
The current limiting triangular wave comparison values Z0 and Z1 held at 4
399 and 1997 respectively. In addition, for normal operation
Waveform pattern register 57, current limiting waveform pattern register
A waveform pattern for normal operation as shown in FIG.
PT0, PT1, PT2, ..., PT12, ZP0, ZP1,
... Assume that ZP5 is held. At this time,
Signals AEB0, AEB1,... Indicating the comparison result of the comparison circuit 56
..AEB11, carrier peak pulse OVFL, carrier valley pass
Lus UNFL, overcurrent that goes low when overcurrent is detected
Detection signal CAL, normal PWM when high level, low level
Switching signal PWM_ZP indicating current limit PWM when overcurrent is detected
Fixed value output signal PWM_ZERO_L which becomes low level when
Is as shown in FIG. 12, and the base of U-phase, V-phase and W-phase
A live signal is obtained. In the example shown, time t ₁Overcurrent is detected
And the overcurrent detection signal CAL goes low,
As a result, the fixed value output signal PWM_ZERO_L becomes low level.
You. Fixed value output signal PWM_ZERO_L becomes low level
And the base drive signals PU2 and NU are turned on, and PU and NU2
Turns off, V-phase and W-phase base drive signals operate in the same way
become. Time t_TwoCount 52a is on the mountain of career
When the carrier peak pulse OVFL is output, a fixed value is output.
The signal PWM_ZERO_L changes from low level to high level.
You. At the same time as this switching, the switching signal PWM_ZP becomes high level.
From low to low level, and the triangular wave comparison value
Value of the resistor 54, Z0, Z1, current limiting waveform pattern register
The values ZP0 to ZP5 of the data 58 are selected. Switching signal PWM_ZP
Is a low-level section, an address created from values Z0 and Z1
The value of the current limit pattern selected in the
Is output as

The normal operation triangular wave comparison value register 5
3 and the number of the current limiting triangular wave comparison value registers 54, and thus the numbers of the normal operation waveform pattern registers 57 and the current limiting waveform pattern registers 58 are arbitrary.

[0062]

As described above, the present invention has the following effects.

According to the first aspect of the present invention, the data of the PWM signal in an arbitrary carrier cycle can be set in the immediately preceding carrier cycle, and the arithmetic circuit outputs the counter value and the overflow signal output from the carrier frequency generating circuit. In addition, the waiting time for monitoring the underflow signal can be eliminated, and more processing time can be provided for other functions of the inverter device. Further, even when the carrier frequency is increased, the load on the processing capability of the arithmetic circuit is reduced, so that a PWM waveform that can be used for a wide range of inverter applications can be generated. Furthermore, in the case of writing only to the PWM setting register, the PW
Since the comparison value of the M signal can be updated, the pulse width of the PWM signal of each phase can be controlled with high accuracy even in control at a low carrier frequency, so that a stable PWM signal waveform can be realized.

2) According to the second aspect of the present invention, the process of converting a triangular wave comparison value into a space vector operation result as in the prior art is not required, the load on the operation circuit is reduced, and even in the case of the two-level system, Therefore, the present invention can be applied to two-level and three-level inverters, and can provide a PWM generator that can be used for a wide range of inverter applications.

3) According to the third aspect of the present invention, when an overcurrent occurs, two switching elements connected to the middle point side of a pair of capacitors are made conductive, and a current limiting pattern for making the remaining switching elements non-conductive is generated. Then, from the peak or valley of the next desired carrier, a PWM is generated from the current limiting triangular wave comparison value and the current limiting waveform pattern selected by the switching signal, and when the overcurrent is suppressed, the normal current limiting triangular wave comparison value And PWM that can be used for a wide range of inverter applications by generating PWM from the normal current limit waveform pattern
A generator can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PWM generator according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the PWM generator of FIG.

FIG. 3 is a circuit diagram and a timing chart of a PWM comparison set value loading circuit 7;

FIG. 4 is a timing chart of a circuit diagram of the frequency set value loading circuit 6;

FIG. 5 is a block diagram of a PWM generator according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating a relationship between a triangular wave and a PWM pulse pattern in the PWM generator according to the second embodiment.

FIG. 7 is a waveform diagram of an example of an output 44a of the comparison circuit 44 in FIG. 5;

8 is a waveform diagram (FIG. 5 (1)) of an output waveform of the PWM pulse pattern table 47 in FIG. 5 and a waveform diagram (FIG. 5 (2)) of each of U-phase, V-phase and W-phase base drive signals. .

FIG. 9 is a block diagram of a PWM generator according to a third embodiment of the present invention.

FIG. 10 is a diagram illustrating a relationship among a triangular wave, a current limiting triangular wave, a current limiting waveform pattern register, and a U-phase PWM waveform in the PWM generator according to the third embodiment.

FIG. 11 is a diagram showing specific examples of a triangular wave, a normal operation triangular wave comparison value, a current limiting triangular wave comparison value, a normal operation waveform pattern, and a current limiting waveform pattern in the third embodiment.

FIG. 12 is a timing chart of the third embodiment.

FIG. 13 is a block diagram of a first conventional PWM generator.

FIG. 14 is a timing chart of the first conventional example.

FIG. 15 is a block diagram of a second conventional PWM generator.

FIG. 16 is a block diagram of a third conventional PWM generator.

[Explanation of symbols]

1 Arithmetic circuit 2 Carrier frequency setting register 2a PWM signal generation frequency data 2b PWM signal generation frequency data 2a write signal 2c Carrier frequency setting register 2 output data 3 U-phase PWM setting register 3a U-phase PWM signal generation Data 3b Signal to be written to U-phase PWM setting register 3 3c Output data of U-phase PWM setting register 3 4V-phase PWM setting register 4a Data for generating V-phase PWM signal 4b Signal to be written to V-phase PWM setting register 4 4c V-phase PWM setting Output data of register 4 5 W-phase PWM setting register 5 a Data for generating W-phase PWM signal 5 b Signal to be written to W-phase PWM setting register 5 5 c Output data of U-phase PWM setting register 5 6 Frequency setting value load circuit 6 a Carrier cycle value register Write signal 6b Write signal selection signal 7 PWM comparison set value load circuit 7a PWM comparison set value register write signal 8 Carry Cycle value register 8c Carrier cycle value register output data 9 U-phase PWM comparison value register 9c U-phase PWM comparison value register 10 W-phase PWM comparison value register output data 11 W-phase PWM comparison value register 11c W-phase PWM comparison value register output data 12 Carrier generation circuit 12a Count lock 12b Counter value 12c Overflow signal 12d Underflow signal 13 PWM generation circuit 13a U-phase PWM generation circuit 13b V-phase PWM generation circuit 13c W-phase PWM generation circuit 13d U-phase PWM signal 13e V-phase PWM signal 13f W Phase PWM signal 14a U-phase comparator 14b V-phase comparator 14c W-phase comparator 21, 25, 26, 33, 35 AND gate 22, 23, 24, 27, 28, 31, 32, 34, 3
6, 37, 38, 40D flip-flop 39 selector 41 arithmetic circuit 41a, 41b write signal 42 carrier generation circuit 42a count value 43 triangular wave comparison value register 44 comparison circuit 44a comparison circuit output 45 waveform pattern register 46 address encoder 47 PWM pulse pattern table 47a to 47f PWM output 48 Data bus 49 Clock 51 Arithmetic circuit 52 Carrier generation circuit 52a Count value 52b Carrier peak pulse 52c Carrier valley pulse 53 Triangular wave comparison value register for normal operation 54 Triangular wave comparison value register for current limiting 55 Triangular wave comparison value selector 56 Comparison circuit 56a Comparison circuit output 57 Normal operation waveform pattern register 58 Current limiting waveform pattern register 59 Waveform pattern selector 60 Address encoder 61 PWM pulse pattern Down table 61a PWM output 62 current limit control circuit 62a overcurrent detection signal 62b fixed value output signal 62c switching signal 63 data bus 64 the current limit pattern generator 64a base drive signals 65 clock

Claims (3)

[Claims] 1. A PWM generator for performing pulse width modulation from comparison data between a comparison value output from an arithmetic circuit and a carrier, comprising: a U-phase PWM signal generation data input from the arithmetic circuit; U-phase, V-phase, and W-phase PWM setting registers that respectively hold the PWM signal generation data and the W-phase PWM signal generation data, and the upper limit value and the lower limit value of the carrier cycle input from the arithmetic circuit. A carrier frequency setting register to be held, a count operation is performed at a constant frequency to generate a triangular wave, the count value is output, and the count value is respectively the upper limit value, an overflow signal indicating that the lower limit value is matched, and A carrier generation circuit comprising an up / down counter for outputting an underflow signal; and a carrier frequency signal receiving a carrier cycle value register write signal. Holds the data of the number setting register and holds the data of the U-phase, V-phase and W-phase PWM setting registers in response to the carrier cycle value register to be output to the carrier generation circuit and the PWM comparison setting value write signal, respectively. U-phase PWM comparison value register, V-phase PWM comparison value register, W-phase P
The WM comparison value register and the data of the U-phase, V-phase, and W-phase PWM comparison value registers are respectively compared with the carrier count value of the generation circuit, and the U-phase, V-phase, and W-phase PWM signals are output, respectively. When data is set in the U-phase PWM generation circuit, the V-phase PWM generation circuit, the W-phase PWM generation circuit, and the carrier frequency setting register, a write signal selection signal is set to a first logical level, and then the underflow is performed. When a signal is output, this signal is output as the carrier cycle value register write signal, and a frequency setting value load circuit that sets the write selection signal to a second logic level; and a PWM signal generation data of each phase. When the writing to the PWM setting register is completed, if the write selection signal is the first logical level, the next underflow signal is output as the PWM comparison setting value register write signal, If serial write selection signal is at a second logic level, PWM generator having a PWM comparator setpoint load circuit for outputting a next underflow signal or overflow signal as the PWM comparison value register write signal. 2. A PWM generator for performing pulse width modulation based on comparison data output from an arithmetic circuit and comparison data with a carrier, performing a count operation at a constant frequency to generate a triangular wave, and calculating the count value. A carrier generating circuit composed of an up / down counter to output, and N (N is an integer of 1 or more) output from the arithmetic circuit
N triangular wave comparison value registers each holding a triangular wave comparison value of the same by a comparison value register write signal also output from the arithmetic circuit, and an output of the carrier generation circuit is held by each of the triangular wave comparison value registers. N comparison circuits that output a signal according to the magnitude of the comparison with the triangular wave comparison value, an address encoder that converts a signal composed of an output signal of each of the comparison circuits into an address, and an output of the arithmetic circuit ( (N + 1) waveform pattern registers holding each of the (N + 1) waveform patterns by a waveform pattern register write signal output from the arithmetic circuit, and the waveform pattern of each of the waveform pattern registers is Is written to the address assigned to the address and the address output from the address encoder. A PWM generator having a PWM pulse pattern table for outputting a waveform pattern of a pulse as a PWM output of a U-phase, a V-phase, a W-phase, a U2-phase, a V2-phase, and a W2-phase. 3. A device for performing pulse width modulation based on comparison data output from an arithmetic circuit and comparison data with a carrier, performing a count operation at a constant frequency to generate a triangular wave, and outputting the count value. A carrier generation circuit composed of an up / down counter for generating a peak of a triangular wave, a carrier peak pulse indicating a trough of a triangular wave, and a carrier trough pulse; and N (N is an integer of 1 or more) output from the arithmetic circuit. )
, N normal operation triangular wave comparison value registers that hold each of the normal operation triangular wave comparison values by the comparison value register write signal output from the arithmetic circuit, and M (M (M) output from the arithmetic circuit) Is an integer of 1 or more, and each of the M current limiting triangle wave comparison values (M ≦ N) is held by a comparison value register write signal output from the arithmetic circuit, and M current limiting triangle wave comparison value registers; When the switching signal is at the first logic level, the data held in the normal operation triangular wave comparison value register is selected and output. When the switching signal is at the second logic level, the data is stored in the current limiting comparison value register. A triangular wave comparison value selector for selecting and holding the held data, and comparing the output of the carrier generation circuit with each output of the triangular wave comparison value selector, N comparison circuits that output signals output from the respective comparison circuits, an address encoder that converts a signal composed of signals output from the respective comparison circuits into an address, and (N + 1) normal operation waveform patterns output from the arithmetic circuit (N + 1) normal operation waveform pattern registers that are held by the waveform pattern register write signal output from the arithmetic circuit, and 2 (M + 1) current limiting waveforms output from the arithmetic circuit 2 (M + 1) current limiting waveform pattern registers for holding each of the patterns by a current limiting waveform pattern write signal output from the same arithmetic circuit; and when the switching signal is at a first logic level, The data held in the normal operation waveform pattern register is selected and output, and the switching signal has a second logic level. Come,
A waveform pattern selector for selecting and holding data held in the current limiting pattern register, and each output data of the waveform pattern selector is written to an address assigned to the data and output from the address encoder. The data at the address
PWM pulse pattern table to be output as the PWM output of the three-phase, W-phase, U2-phase, V2-phase, and W2-phase, and PU, NU from the U-phase, V-phase, W-phase, U2-phase, V2-phase, and W2-phase PWM outputs , PV, NV, PW, NW, PU2, NU2, PV2, NV
2. When the base drive signal of each phase of PW2 and NW2 is output and the fixed value output signal of the second logic level is received, the bases of the switching elements other than the two switching elements connected to the middle point of the pair of capacitors A current limiting pattern generating circuit that does not output a drive signal; and during normal operation, the switching signal and the fixed value output signal are set to a first logic level, and when an overcurrent detection signal is input, the fixed value output signal is changed to a second logic level. 2, the fixed value output signal is set to the first logic level at the next carrier peak pulse or carrier valley pulse, and at the same time the switching signal is set to the second logic level, and the overcurrent detection signal is input. A PWM generation device having a current limit control circuit for setting the switching signal to a first logic level when the switching is not performed.