JP2008113494A - Three-phase pwm signal generator and three-phase voltage-type inverter device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a three-phase PWM signal generator which, with little limitation in the range of output voltage, can prolong the holding time of a switching pattern, using a simple method, without having to add new devices. <P>SOLUTION: When generating a PWM signal using two types of basic voltage vectors having a phase difference of 60 degrees sandwiching a voltage command vector, a basic voltage vector close to the voltage command vector of the two types of basic vectors, and the third type of basic voltage vector; having a phase difference of 60 degrees and differing from the two types of basic voltage vectors, the three-phase PWM signal generator 8 decides the value to be provided to the basic voltage vector that is far from the voltage command vector of the two types of basic voltage vectors, excluding the center basic voltage vector as the generation time ratio, based on the lowest possible ratio of generation time for detecting a current. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to, for example, a three-phase voltage type inverter device using a semiconductor switching element, and more specifically, generates a three-phase PWM (Pulse Width Modulation) signal that defines a switching pattern of the semiconductor switching element. The present invention relates to a three-phase PWM signal generating device and a three-phase voltage type inverter device.

  Conventionally, as a switching method of a three-phase voltage type inverter device, a three-phase modulation method for generating a PWM signal using two types of basic voltage vectors having a phase difference of 60 degrees and two types of zero vectors having no magnitude, There is a two-phase modulation system that generates a PWM signal using two types of basic voltage vectors having a phase difference of 60 degrees and one type of zero vector having no magnitude.

  In recent years, in a three-phase voltage type inverter device, current detection is not performed by CT (Current Trans), but a resistor (hereinafter referred to as a shunt resistor) for detecting an overcurrent mounted on the inverter main circuit is used. In many cases, current detection is performed.

  However, when current detection is performed using a shunt resistor, in the three-phase modulation method or the two-phase modulation method, when the output voltage is low (when the modulation factor is low), the holding time of the switching pattern of the semiconductor switching element is shortened. Even when the phase angle is close to the basic voltage vector, the holding time of the switching pattern for generating the basic voltage vector far from the voltage command vector has been shortened. When the holding time of the switching pattern is shortened, the period in which the current can be detected on the shunt resistor is shortened, so that the current detection cannot be performed correctly, and the controllability may be deteriorated.

  Therefore, in order to lengthen the holding time of the switching pattern, there is no size obtained by switching only two types of basic voltage vectors having a phase difference of 120 degrees and the switching state of these basic voltage vectors. Proposal of a device that generates three-phase PWM signals using a total of three types of voltage vectors with a zero vector, and a device that generates three-phase PWM signals using three types of basic voltage vectors each having a phase difference of 60 degrees (For example, refer to Patent Document 1). In addition, a device that solves the above-described problem by outputting different PWM signals at two consecutive PWM periods has been proposed (see, for example, Patent Document 2).

Japanese Patent No. 3447366 JP 2005-12934 A

  However, the above-described conventional apparatus has the following problems. That is, a total of three types of voltage vectors including two types of basic voltage vectors having a phase difference of 120 degrees and a zero vector having no magnitude obtained by switching only one phase of the switching state of the basic voltage vectors. In the apparatus to be used, the size of the voltage command vector that can be produced is limited, and can be applied only to a low modulation rate range. In addition, since a basic voltage vector having a phase difference of 60 degrees is not used, an effective current is caused to flow more than necessary, the inverter efficiency is reduced, and further, harmonics are increased in the motor current, resulting in vibration and noise. Tended to increase.

  Further, in an apparatus that uses three types of basic voltage vectors each having a phase difference of 60 degrees, efficiency is greatly deteriorated because zero vectors are not used. Further, in this apparatus, since there are many restrictions on the modulation rate or space vector rotation angle in actual use, the load on software becomes large, and as a result, hardware with high performance is required.

  On the other hand, in a device that outputs different PWM signals in two consecutive PWM cycles, the basic voltage vector that is output for each cycle changes, so the sound and efficiency are likely to deteriorate. In addition, since the PWM signal must be recreated for each period, the software is complicated and the load becomes large. As a result, hardware with high performance as described above is required.

  The present invention has been made to solve the above-described problems, and without adding a new device, there are few restrictions on the output voltage range, and the holding time of the switching pattern can be extended by a simple method. An object of the present invention is to provide a possible three-phase PWM signal generator and a three-phase voltage type inverter device.

  A three-phase PWM signal generator according to the present invention is a three-phase PWM signal generator that detects a current flowing through a bus of a three-phase voltage type inverter device by driving a semiconductor switching element of the three-phase voltage type inverter device with a PWM signal. Two types of basic voltage vectors having a phase difference of 60 degrees across the voltage command vector, and the two types of basic voltage vectors having a phase difference of 60 degrees with a basic voltage vector close to the voltage command vector A PWM signal generating means for generating a PWM signal by using a third basic voltage vector different from the basic voltage vector is provided, and the PWM signal generating means includes two basic voltage vectors excluding the central basic voltage vector. The value given as the generation time ratio to the basic voltage vector far from the voltage command vector is the lowest current detectable value. Those having a value determination means for determining based on the generation time ratio.

  According to the present invention, there are two basic voltage vectors having a phase difference of 60 degrees across the voltage command vector, and a basic voltage vector close to the voltage command vector of the two basic voltage vectors and a phase difference of 60 degrees. When generating a PWM signal using a third basic voltage vector different from the two basic voltage vectors, the basic voltage far from the voltage command vector among the two basic voltage vectors excluding the central basic voltage vector. Since the value given to the vector as the generation time ratio is determined based on the minimum generation time ratio at which current can be detected, there is less restriction on the output voltage range without adding a new device, and Since the holding time of the switching pattern can be extended by a simple method, the current detectable range on the shunt resistor can be widened. There is an effect that. In addition, it is possible to produce a PWM signal that prevents noise and extreme deterioration in efficiency.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a three-phase voltage type inverter device to which a three-phase PWM signal generating device according to Embodiment 1 of the present invention is applied, and FIG. 2 is a relationship between a basic voltage vector, a switching pattern, and a detected phase current. FIG. 3 is a diagram showing the phase relationship of the basic voltage vector and the relationship between the inverter rotation angle and the voltage command vector, and FIG. 4 is a configuration of the PWM signal generating unit of the three-phase PWM signal generating device according to the first embodiment. FIG.

  A three-phase voltage type inverter device shown in FIG. 1 generates and controls a three-phase PWM signal for driving an inverter main circuit 1 and semiconductor switching elements 4a to 4f included in the inverter main circuit 1. And. The inverter main circuit 1 includes three sets of semiconductors connected in series between a DC power source 2 that applies a bus voltage Vdc, a DC bus 3a connected to the positive terminal of the DC power source 2, and a DC bus 3b connected to the negative terminal. Three sets of switching elements (4a, 4b), (4c, 4d), (4e, 4f) and flywheel diodes 5a-5f connected in parallel to the six semiconductor switching elements 4a-4f, respectively The electric motor 6 is connected to each connection point of the semiconductor switching elements (4a, 4b), (4c, 4d), (4e, 4f). Further, the DC bus 3b is provided with a DC current detector 7 for detecting a DC bus current Idc used in the three-phase PWM signal generator 8. The DC current detection unit 7 includes a detection element (such as a resistor) inserted in the DC bus 3b and an amplifier that amplifies the voltage across the detection element. The output voltage of the amplifier is converted into a current and the DC bus The current Idc is detected.

The three-phase PWM signal generator 8 includes a phase current determination unit 9 that determines the phase currents Iu, Iv, and Iw from the DC bus current Idc detected by the DC current detection unit 7, and an excitation current from the phase currents Iu, Iv, and Iw. An excitation current / torque current calculation unit 10 for calculating Iγ (γ-axis current) and torque current Iδ (δ-axis current), and a voltage command vector V ^* used in the next control is calculated from the excitation current Iγ and torque current Iδ. A voltage command vector calculation unit 11; a PWM signal generation unit 12 that generates a current phase signal Tup, Tun, Tvp, Tvn, Twp, Twn of a three-phase PWM signal in one carrier cycle from the voltage command vector V ^* ; A PWM signal generator 13 for generating three-phase PWM signals Up, Un, Vp, Vn, Wp, Wn based on the time signals Tup, Tun, Tvp, Tvn, Twp, Twn and outputting them to the semiconductor switching elements 4a-4f; The Eteiru. The subscript “p” indicates the positive electrode side, and “n” indicates the negative electrode side.

Next, each part which comprises the three-phase PWM signal generator 8 is explained in full detail.
When each of the switching elements 4a to 4f of the inverter main circuit 1 is in the ON state, one of the switching elements (4a, 4b), (4c, 4d), (4e, 4f) on the positive electrode side and the negative electrode side is on. Since the other is turned off, there are 8 (= 2 ³ ) switching patterns. The output voltage according to each switching pattern is applied to the electric motor 6.

  Therefore, as the state notation of the positive-side semiconductor switching elements 4a, 4c, and 4e connected to the DC bus 3a, the on state is represented as a logical value 1, the off state is represented as a logical value 0, and 8 to the motor 6 is represented. Corresponding output states to 8 types of voltage vectors V0 to V7. Among these eight types of voltage vectors, V1 to V6 are voltage vectors corresponding to six switching patterns having a vector length, and the remaining V0 and V7 are voltage vectors corresponding to two switching patterns having no vector length. is there. The voltage vectors V0 and V7 are specially called "zero vectors", and the voltage vectors V1 to V6 are called "basic voltage vectors" and are distinguished from "zero vectors".

  That is, in the correspondence relationship between the switching patterns of the positive-side semiconductor switching elements 4a, 4c, and 4e and the basic voltage vectors V1 to V6, for example, as shown in FIG. 2, the W-phase positive-side semiconductor connected to the DC bus 3a. When the logic state of the switching element 4e, the logic state of the semiconductor switching element 4c on the V-phase positive side, and the logic state of the semiconductor switching element 4a on the U-phase positive side are (0, 0, 1), the basic voltage vector V1 is 0, 1, 0) is the basic voltage vector V2, (0, 1, 1) is the basic voltage vector V3, (1, 0, 0) is the basic voltage vector V4, and (1, 0, 1) Is a basic voltage vector V5, and (1, 1, 0) is a basic voltage vector V6. Further, in the correspondence relationship between the switching patterns of the semiconductor switching elements 4a, 4c and 4e on the positive side and the zero vectors V0 and V7, (0, 0, 0) is the zero vector V0 and (1, 1, 1) is the zero vector. V7. The logic states of the negative-side semiconductor switching elements 4b, 4d, and 4f at the time of the zero vector V0 are (1, 1, 1) opposite to the above, and the negative-side semiconductor switching elements 4b, 4d at the basic voltage vector V1. The logical state of 4f is (1, 1, 0) opposite to the above, and in the other basic voltage vectors V2 to V6 and zero vector V7, the logical states of the semiconductor switching elements 4b, 4d and 4f on the negative side are respectively Vice versa.

  Further, during the generation of the six basic voltage vectors V1 to V6, the current flowing through the windings of the motor 6 flows through the DC buses 3a and 3b, so that it can be detected by the DC current detecting means 7, and the DC current can be detected. It can be observed as bus current Idc. On the other hand, the zero vectors V0 and V7 cannot be observed as the DC bus current Idc. As shown in FIG. 2, the phase current cannot be observed in the zero vectors V0 and V7, but is observed as "Iu (U-phase current)" in the basic voltage vector V1, for example. Thereafter, the phase currents can be observed in the same manner for the other basic voltage vectors V2 to V6.

Now, in order to rotate the electric motor 6 smoothly, it is necessary to obtain the magnetic flux corresponding to a desired voltage and frequency. This can be realized by appropriately combining the eight types of voltage vectors described above. As shown in FIG. 3, when the inverter rotation direction is clockwise, the six basic voltage vectors V1 to V6 are 60 in the order of V1, V3, V2, V6, V4, V5 in the clockwise direction on the phase plane. Two zero vectors V0 and V7 are shown at the origin position. It is also shown that the inverter rotation angle θ with the direction of the basic voltage vector V1 (U phase) as the initial phase gives the phase of the voltage command vector V ^* . The phase angle is referred to as space vector rotation angle theta ^* between the inverter one voltage vector in six fundamental voltage vectors V1 to V6 that aforementioned occurring in the rotation direction V ^*. The angle range of the space vector rotation angle θ ^* is 0 degree ≦ θ ^* ≦ 60 degrees.

The generation ratio of each voltage vector is determined by the modulation ratio that is the ratio of the output voltage to the bus voltage Vdc. The generation time of each voltage vector is determined by the voltage command vector V ^* and the space vector rotation angle θ ^* . Therefore, the phase current discriminating section 9 reads the DC bus current Idc according to the list table shown in FIG. 2 during the generation of each voltage vector, and obtains the phase currents Iu, Iv, Iw.

  Next, the excitation current / torque current calculation unit 10 uses, for example, a three-phase two-phase conversion matrix [C1] as shown in Equation (1) and a rotation matrix [C2] as shown in Equation (2) to The phase currents Iu, Iv, Iw obtained by the current discriminating unit 9 are converted into excitation current Iγ (γ-axis current) and torque current Iδ (δ-axis current). In equation (2), θ is the inverter rotation angle, and shows the case where the rotation direction is clockwise.

  Here, the point that the coordinate system to which the excitation current / torque current calculation unit 10 conforms is not the dq axis but the γ-δ axis. That is, let the N pole side on the rotor of the electric motor 6 be a d-axis, and a phase advanced 90 degrees (electrical angle) in the rotation direction be a q-axis. However, when a sensor for detecting the rotor position such as a pulse encoder is not used to drive the synchronous motor, the three-phase PWM signal generator 8 cannot accurately capture the dq axis coordinates of the rotor. Actually, control is performed by shifting from the dq axis coordinate system by a phase difference Δθ. A coordinate system shifted by this phase difference Δθ is generally called a γ-δ axis coordinate, and it is customary to use it. This is the same in the first embodiment.

Next, the voltage command vector calculation unit 11 performs various vector control calculations including speed control based on the excitation current Iγ (γ-axis current) and torque current Iδ (δ-axis current) obtained by the excitation current / torque current calculation unit 10. To obtain the magnitude and phase of the voltage command vector V ^* used for the next control. This phase angle is the inverter rotation angle θ.

The PWM signal generator 12 generates energization time signals Tup, Tun, Tvp, Tvn, Twp, and Twn based on the voltage command vector V ^* by a method that will be described later. As a result, the PWM signal generator 13 generates the three-phase PWM signals Up, Un, Vp, Vn, Wp, and Wn to be applied to the semiconductor switching elements 4a to 4f from the energization time signals Tup, Tun, Tvp, Tvn, Twp, and Twn. It produces | generates and outputs to the semiconductor switching elements 4a-4f, and the electric motor 6 is driven.

Next, the PWM signal generation unit 12 in the first embodiment will be described with reference to FIG. The PWM signal preparation unit 12 receives the voltage command vector V ^* from the voltage command vector calculation unit 11 and regenerates the vector, and receives the output of the vector preparation unit 14 and redistributes the duty of the PWM signal. It is composed of a PWM signal duty redistribution setting unit 15 that converts the energization time signals Tup, Tun, Tvp, Tvn, Twp, and Twn and outputs them to the PWM signal generation unit 13.

  The vector preparation unit 14 includes a three-phase modulation vector preparation unit 16 that generates a three-phase modulation vector, a predetermined value determination unit 18 that specifies the magnitude of at least one basic voltage vector as a predetermined value, and three-phase modulation. The vector redistribution unit 17 redistributes the vectors based on the vector information from the vector generation unit 16 and the predetermined value from the predetermined value determination unit 18. Further, the PWM signal duty redistribution setting unit 15 includes a duty division unit 19 that divides the duty of the basic voltage vectors V1 to V6 or zero vectors V0 and V7 as necessary, and a duty arrangement based on the divided duties. And a duty arrangement determining unit 20 for rearranging the signals.

  The operation of the PWM signal preparation unit 12 will be described with reference to FIGS. FIGS. 5 to 8 are diagrams illustrating examples of vectors created by the vector creation unit 14, and FIGS. 9 to 14 are positive-side semiconductor switching elements 4 a and 4 c created by the PWM signal duty redistribution setting unit 15. It is a time chart which shows the switching pattern of 4e.

In the PWM signal preparation unit 12, the three-phase modulation vector preparation unit 16 of the vector preparation unit 14 receives the voltage command vector V ^* from the voltage command vector calculation unit 11. The three-phase modulation vector preparation unit 16 decomposes the received voltage command vector V ^* in the direction of two basic voltage vectors sandwiching it, and generates each basic voltage vector in the same manner as in the conventional three-phase modulation method. Create a time ratio. For example, when the voltage command vector V ^* is between the basic voltage vectors V1 and V3, as shown in FIG. 5, the voltage command vector V ^* is vector-decomposed in the two directions of the basic voltage vector V1 and the basic voltage vector V3, The generation time ratio of the basic voltage vectors V1 and V3 is created.

In this case, the voltage command vector V ^* is in the vicinity of the basic voltage vector V1, the generation time ratio of the basic voltage vector V1 is long, and the generation time ratio of the basic voltage vector V3 is short. Therefore, the conventional three-phase modulation method has a problem that current detection is difficult when the basic voltage vector V3 is generated.

  Therefore, in the vector redistribution unit 17 that receives the result from the three-phase modulation vector preparation unit 16, some of the components of the basic voltage vector V1 having a long generation time ratio have a phase difference of 120 degrees as shown in FIG. Decomposes into two vectors. The two decomposed vectors become components of the basic voltage vectors V3 and V5, respectively, and these components are added to the vectors prepared by the three-phase modulation vector preparation unit 16, respectively. As a result, the generation time ratio of the basic voltage vectors V3 and V5 becomes long.

In the predetermined value determination unit 18, the vector redistribution unit 17 determines how many components are to be decomposed from the basic voltage vector V1. Since it is sufficient that the current when the basic voltage vector V3 or V5 is generated can be detected, the minimum time during which the current can be detected may be allocated to the basic voltage vector V3 or V5. FIG. 7 shows a case where the predetermined value is determined so that the generation time ratio of the basic voltage vector V5 is the minimum time in which current can be detected. FIG. 8 shows a case where the predetermined value is determined so that the generation time ratio of the basic voltage vector V3 is the minimum time at which current can be detected.
Note that the minimum time during which current can be detected varies depending on the system. Whether the predetermined value is determined based on the basic voltage vector V3 or whether the predetermined value is determined based on the basic voltage vector V5 differs depending on the system. Become.

The vector thus created is transferred to the PWM signal duty redistribution setting unit 15. The PWM signal duty redistribution setting unit 15 calculates the generation time ratio based on the vector and creates a three-phase PWM signal. Duty arrangement determining unit 20 determines the order of generation of switching patterns when generating voltage command vector V ^* . For example, when based on the voltage command vector V ^* of the decomposition results shown in Figure 7, it is possible to generate a voltage command vector V ^* by switching the order of the V0 → V1 → V3 → V7 → V5 as shown in FIG. 9 . From this time chart, the energization time signals Tup, Tun, Tvp, Tvn, Twp, and Twn of the semiconductor switching elements 4a to 4f can be produced. Note that the order does not matter as long as the generation time ratios of the basic voltage vectors V1, V3, and V5 match, so that the order may be switched in the order of V5.fwdarw.V7.fwdarw.V3.fwdarw.V1.fwdarw.V0 contrary to FIG.

  However, if it is assumed that the voltage vectors are switched as shown in FIG. 9, when switching from the last V5 to the first V0 of the next period occurs, the U-phase and W-phase semiconductor switching elements (4a, 4b) ) (4e, 4f) perform switching at the same time. If this simultaneous switching occurs, it causes noise and vibration.

Therefore, the duty dividing means 19 divides one of the basic voltage vectors into two, and uses this to create a switching order that eliminates simultaneous switching. For example, in the case of FIG. 9, the duty dividing unit 19 divides the generation time ratio of the basic voltage vector V1 into two parts, and one of them is placed in the same place as in FIG. 9 (the first half in one cycle). Is placed behind the basic voltage vector V5 (the latter half of one cycle) and is switched in the order of V0.fwdarw.V1.fwdarw.V3.fwdarw.V7.fwdarw.V5.fwdarw.V1 as shown in FIG. By doing so, simultaneous switching does not occur.
By dividing, the generation time ratio of the basic voltage vector V1 is shortened, but the one arranged in the first half is made the minimum length capable of current detection, and the remaining generation time ratio is brought into the second half. As a result, the current corresponding to the basic voltage vector V1 can be detected. If the length is not long enough to divide under the above conditions, the basic voltage vector for detecting the current is changed from V1, V3 to V3, V5, so that 2 required for controlling the motor 6 is obtained. The phase current can be detected.

  Further, when used in combination with other modulation schemes (for example, three-phase modulation scheme and two-phase modulation scheme), other modulation schemes are used in the vicinity of the center of one carrier period (or both ends) within the one period. Among the voltage vectors, a basic voltage vector (V7 if V7 is used) in which the switching elements 4a, 4c, 4e on the positive electrode side are turned on is arranged, and both ends (or near the center) of one carrier period ), A voltage vector (V0 if V0 is used) having a large number of the positive side semiconductor switching elements 4a, 4c, 4e turned off among the basic voltage vectors used in one cycle is arranged. On the other hand, in the switching of the basic voltage vector in FIG. 9, the end of one cycle is the time when the semiconductor switching elements 4a, 4c, 4e on the positive side of the voltage vector used in one cycle are turned off. The number has not put the voltage vector (V0) often that. When considering combination with other modulation methods, the pattern at the end of one cycle is different, which causes noise and vibration.

  Therefore, the duty dividing unit 19 divides one of the zero vectors into two and uses it to make the same shape as other modulation schemes. For example, considering the case of FIG. 9, the duty dividing unit 19 divides the generation time ratio of the zero vector V7 into two. Subsequently, the duty placement determining unit 20 places one at the same location as in FIG. 9 and the other behind V5. In this case, it becomes as shown in FIG. At this time, the meaning of the zero vector is the same regardless of whether it is V7 or V0, so when it is arranged behind V5, it is arranged as V0 (the zero vector V0 is arranged in the first half and the second half in one cycle). If the same thing is implemented also in FIG. 10, it will become like FIG.

  Furthermore, when the basic voltage vector is switched as shown in FIGS. 9 and 10, switching always occurs at the center and both ends of one carrier cycle. That is, switching always occurs every carrier cycle (every half cycle), which causes noise.

  Therefore, the duty divider 19 divides the zero vector so that the center of the zero vector V7 is approximately the center of one cycle. For example, considering the case of FIG. 9, the duty divider 19 divides the duty of the zero vector V0 into two. At that time, in the first half of one cycle, the duty of the basic voltage vectors V1 and V3 and ½ of the duty of the zero vector V7 are subtracted from ½ of one carrier cycle to be arranged in the first half of the zero vector V0. Find the duty. The latter half of the zero vector V0 remains. It is arranged as shown in FIG. 13 by the duty arrangement determining unit 20 so that the center of the zero vector V7 is almost at the center of one cycle. If the same thing is implemented also in FIG. 10, it will become like FIG.

  By doing so, it is possible to extend the holding time of the switching pattern by a simple method without adding a new device, with few restrictions on the output voltage range. Further, it is possible to produce a PWM signal that prevents the noise and the efficiency from deteriorating drastically despite the fact that the current detectable time on the shunt resistor can be increased.

Embodiment 2. FIG.
FIG. 15 is a block diagram showing a configuration of a PWM signal generation unit of the three-phase PWM signal generator according to Embodiment 2 of the present invention. Since the inverter device provided with the three-phase PWM signal generator on which the PWM signal generation unit is mounted is the same as that of the first embodiment, the description thereof is omitted.
The PWM signal generator 12 shown in the figure receives the voltage command vector V ^* from the voltage command vector calculator 11 and recreates the vector. The PWM signal generator 12 receives the output of the vector generator 14 and the duty of the PWM signal. Is re-distributed to change to energization time signals Tup, Tun, Tvp, Tvn, Twp, Twn and output them to the PWM signal generator 13 and a PWM signal duty redistribution setting unit 15.

  The vector preparation unit 14 includes a three-phase modulation vector preparation unit 16 that generates a three-phase modulation vector, a predetermined value determination unit 18 that specifies the magnitude of at least one basic voltage vector as a predetermined value, and three-phase modulation. Vector redistribution unit 17 that redistributes the vectors based on the vector information from the vector generation unit 16 and the predetermined value from the predetermined value determination unit 18, and a vector that performs a modification to increase the basic voltage vector from three to four It consists of a deformation part 21. Further, the PWM signal duty redistribution setting unit 15 includes a duty division unit 19 that divides the duty of the basic voltage vectors V1 to V6 or zero vectors V0 and V7 as necessary, and a duty arrangement based on the divided duties. And a duty arrangement determining unit 20 for rearranging the signals.

  Next, the operation of the PWM signal preparation unit 12 will be described with reference to FIGS. FIGS. 16 and 17 are diagrams showing an example of a vector created by the vector creation unit 14, and FIGS. 18 to 21 are positive-side semiconductor switching elements 4 a, 4 c created by the PWM signal duty redistribution setting unit 15. It is a time chart which shows the switching pattern of 4e.

In the PWM signal preparation unit 12, the three-phase modulation vector preparation unit 16 of the vector preparation unit 14 receives the voltage command vector V ^* from the voltage command vector calculation unit 11. Similar to the first embodiment, the three-phase modulation vector preparation unit 16 decomposes the received voltage command vector V ^* in the direction of two basic voltage vectors sandwiching it, and is the same as the conventional three-phase modulation method. Thus, the generation time ratio of each basic voltage vector is prepared (see FIG. 5).

As in the first embodiment, in the vector redistribution unit 17 that receives the result from the three-phase modulation vector preparation unit 16, some of the components of the basic voltage vector V1 having a long generation time ratio are as shown in FIG. Decompose into two vectors with 120 degree phase difference. As described above, the predetermined value determining unit 18 determines how many components are to be decomposed from the basic voltage vector V1. Since the predetermined value only needs to be able to detect the current when the basic voltage vector V3 or V5 is generated, the minimum time during which the current can be detected is assigned to the basic voltage vector V3 or V5. FIG. 7 shows a case where the predetermined value is determined so that the generation time ratio of the basic voltage vector V5 is the minimum time in which current can be detected.
Note that the minimum time during which current can be detected varies depending on the system. Whether the predetermined value is determined based on the basic voltage vector V3 or whether the predetermined value is determined based on the basic voltage vector V5 differs depending on the system. Become.

As described in the first embodiment, if the semiconductor switching elements are simultaneously switched, it causes noise and vibration. In order to avoid this, the vector deforming unit 21 is used in the second embodiment. In the vector transformation unit 21, one of the three basic voltage vectors created by the vector redistribution unit 17 and the basic voltage vector on both sides excluding the central basic voltage vector, and its vector and about 180 degrees. The same predetermined value is added to both the basic voltage vector having a phase difference. Since the same predetermined value is added to a vector having a phase difference of 180 degrees, the voltage command vector V ^{* as} a result of adding all the vectors does not change.

FIG. 16 shows a basic voltage vector V5 far from the voltage command vector V ^* out of the basic voltage vectors V3 and V5 on both sides except the central basic voltage vector V1, and a basic voltage vector V2 having a phase difference of 180 degrees from the vector V5. The state of the vector after adding a predetermined value to both is shown. FIG. 17 shows a basic voltage vector V3 closer to the voltage command vector V ^* of the basic voltage vectors V3 and V5 on both sides in the same manner as described above, and a basic voltage vector V4 having a 180-degree phase difference from the vector V3. The state of the vector after adding a predetermined value to both is shown.

The vector thus created is transferred to the PWM signal duty redistribution setting unit 15. The PWM signal duty redistribution setting unit 15 calculates the generation time ratio based on the vector and creates a three-phase PWM signal. Duty arrangement determining unit 20 determines the order of generation of switching patterns when generating voltage command vector V ^* . For example, based on the decomposition result of the voltage command vector V ^* shown in FIG. 16, the voltage command vector V ^* can be generated by switching from V0.fwdarw.V1.fwdarw.V5.fwdarw.V3.fwdarw.V2 as shown in FIG. it can. From this time chart, the energization time signals Tup, Tun, Tvp, Tvn, Twp, and Twn of the semiconductor switching elements 14a to 14f can be produced. As long as the generation time ratios of the basic voltage vectors V1, V2, V3, and V5 are the same, the order does not matter. Therefore, contrary to FIG. 18, V2 → V3 → V7 → V5 → V1 → V0 good.

On the other hand, the vectors shown in FIG. 17 are switched as shown in FIG. However, when the voltage command vector V ^* is rotated according to the rule shown in FIG. 17, the voltage command vector V ^* moves from the V1 side to the V3 side within the region between the basic voltage vectors V1 and V3. The vectors to be switched are switched from the four basic voltage vectors V1, V3, V4 and V5 shown in FIG. 17 to the four basic voltage vectors V1, V2, V3 and V6. Since two of the basic voltage vectors are switched at the switching timing, it leads to noise and vibration. Therefore, the switching unit of the duty arrangement determining unit 20 sets the vector pattern of FIG. 16 in the peripheral region where the voltage command vector V ^* moves from the V1 side to the V3 side. In this way, the four basic voltage vectors V1, V3, V4, V5 and the four basic voltage vectors V1, V2, V3, V5 are passed through the basic voltage vectors V1, V2, V3, V6. Noise and vibration can be suppressed because only one basic voltage vector can be replaced.

  Assuming that voltage vectors are switched as shown in FIG. 18, when using in combination with other modulation schemes (for example, a three-phase modulation scheme or a two-phase modulation scheme), the other modulation schemes have one carrier period. Near the center (or both ends), among the voltage vectors used within one period, if a voltage vector (V7) having a large number of positive-side semiconductor switching elements 4a, 4c, 4e turned on is used, V7) is arranged, and at both ends (or near the center) of one carrier period, among the voltage vectors used in the one period, the voltage vector in which the positive-side semiconductor switching elements 4a, 4c and 4e are turned off is large. (V0 is used if V0 is used), on the other hand, in the voltage vector switching in FIG. 18, the end of one cycle is positive among the voltage vectors used in one cycle. Side of the semiconductor switching elements 4a, 4c, 4e has not put the voltage vector large number of turned off (V0). When considering combination with other modulation methods, the pattern at the end of one cycle is different, which causes noise and vibration.

  Therefore, as described above, the duty divider 19 divides one of the zero vectors into two, and uses it to make the same shape as other modulation schemes. For example, in the case of FIG. 18, the duty dividing unit 19 divides the generation time ratio of the zero vector V7 into two. Subsequently, the duty placement determining unit 20 places one on the same location as in FIG. 18 and the other behind V2. In this case, it becomes as shown in FIG. At this time, the meaning of the zero vector is the same regardless of whether it is V7 or V0, so when it is arranged behind V5, it is arranged as V0 (the zero vector V0 is arranged in the first half and the second half in one cycle).

  Further, when the voltage vector is switched as shown in FIG. 19, switching always occurs at the center and both ends of one carrier cycle. That is, switching always occurs every carrier cycle (every half cycle), which causes noise.

  Therefore, the duty divider 19 divides the zero vector so that the center of the zero vector V7 is approximately the center of one cycle. For example, considering the case of FIG. 19, the duty divider 19 divides the duty of the zero vector V0 into two. At that time, in the first half of one cycle, the duty of the basic voltage vectors V1 and V5 and half of the duty of the zero vector V7 are subtracted from 1/2 of one carrier cycle, so that they are arranged in the first half of the zero vector V0. Find the duty. The latter half of the zero vector V0 remains. It is arranged as shown in FIG. 20 by the duty arrangement determining unit 20 so that the center of the zero vector V7 is approximately at the center of one cycle.

  By doing so, it is possible to extend the holding time of the switching pattern by a simple method without adding a new device, with few restrictions on the output voltage range. Further, it is possible to produce a PWM signal that prevents the noise and the efficiency from deteriorating drastically despite the fact that the current detectable time on the shunt resistor can be increased.

Note that the voltage command vector V ^* can be expressed in the same way even when there are five or six basic voltage vectors, but the processing by software becomes complicated, and the PWM waveform also leads to distortion noise and deterioration of vibration. Cannot be used because there are many problems in actual use.

It is a block diagram which shows the structure of the three-phase voltage type | mold inverter apparatus to which the three-phase PWM signal generator based on Embodiment 1 of this invention was applied. It is a figure which shows the relationship between a basic voltage vector, a switching pattern, and a detection phase current. It is a figure which shows the phase relationship of a basic voltage vector, and the relationship between an inverter rotation angle and a voltage command vector. 3 is a block diagram showing a configuration of a PWM signal generation unit of the three-phase PWM signal generation device according to Embodiment 1. FIG. It is a figure which decomposes | disassembles and shows voltage command vector V ^* in the direction of basic voltage vector V1, V3. FIG. 5 is a diagram showing the components of the basic voltage vector V1 exploded in the directions of basic voltage vectors V3 and V5 having a phase difference of 120 degrees. FIG. 6 is a diagram showing a part of the components of the basic voltage vector V1 in the direction of the basic voltage vectors V3 and V5 having a phase difference of 120 degrees. FIG. 6 is a diagram showing a part of the components of the basic voltage vector V1 in the direction of the basic voltage vectors V3 and V5 having a phase difference of 120 degrees. It is a time chart which shows the switching pattern based on FIG. FIG. 10 is a time chart of a switching pattern showing the generation time ratio of the basic voltage vector V1 in FIG. 10 is a time chart for explaining the latter half of the switching pattern in FIG. 9. 10 is a time chart showing the generation time ratio of the zero vector V7 divided into two in the switching pattern of FIG. 10 is a time chart showing a zero vector V7 arranged in the center of one carrier period in the switching pattern of FIG. 11 is a time chart showing the zero vector V7 in the center of one carrier period in the switching pattern of FIG. It is a block diagram which shows the structure of the PWM signal preparation part of the three-phase PWM signal generator which concerns on Embodiment 2 of this invention. FIG. 8 is a diagram showing a basic voltage vector V5 and a basic voltage vector V2 having a phase difference of 180 degrees with respect to the basic voltage vector V5 in FIG. FIG. 8 is a diagram showing a basic voltage vector V3 and a basic voltage vector V4 having a phase difference of 180 degrees with respect to the vector V3 by adding predetermined values in FIG. It is a time chart which shows the switching pattern based on FIG. FIG. 19 is a time chart showing the generation time ratio of the zero vector V7 divided into two in the switching pattern of FIG. 18. 20 is a time chart showing the zero vector V7 in the center of one carrier period in the switching pattern of FIG. It is a time chart which shows the switching pattern based on FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Inverter main circuit, 2 DC power supply, 3a, 3b DC bus, 4a-4f Semiconductor switching element, 5a-5f Flywheel diode, 6 Electric motor, 7 DC current detection part, 8 3 phase PWM signal generator, 9 phase current discrimination , 10 excitation current / torque current calculation unit, 11 voltage command vector calculation unit, 12 PWM signal generation unit, 13 PWM signal generation unit, 14 vector generation unit, 15 PWM signal duty redistribution setting unit, 16 three-phase modulation vector Production unit, 17 vector redistribution unit, 18 predetermined value determination unit, 19 duty division unit, 20 duty arrangement determination unit, 21 vector deformation unit.

Claims (15)

In the three-phase PWM signal generator for detecting the current flowing in the bus of the three-phase voltage type inverter device by driving the semiconductor switching element of the three-phase voltage type inverter device by the PWM signal,
Two types of basic voltage vectors having a phase difference of 60 degrees sandwiching the voltage command vector, and the two types of basic voltages having a phase difference of 60 degrees with a basic voltage vector close to the voltage command vector among the two types of basic voltage vectors. PWM signal generating means for generating a PWM signal using a third type of basic voltage vector different from the voltage vector is provided,
The PWM signal generating means is a minimum generation time that can detect a current, which is a value given as a generation time ratio to a basic voltage vector far from the voltage command vector out of two types of basic voltage vectors excluding the central basic voltage vector. A three-phase PWM signal generator comprising a value determining means for determining based on a ratio.   The value determining means is a minimum generation time ratio at which a current can be detected with a value given as an occurrence time ratio to a basic voltage vector close to the voltage command vector among two types of basic voltage vectors excluding the central basic voltage vector. The three-phase PWM signal generator according to claim 1, wherein the determination is based on: The PWM signal generating means includes:
An occurrence time ratio to be given to each of two types of basic voltage vectors having a phase difference of 60 degrees sandwiching the voltage command vector is assigned based on the voltage command vector, and two types of basic voltage vectors having a phase difference of 60 degrees are produced. Production means;
Among the two types of basic voltage vectors, two basic types having a basic voltage vector component close to the voltage command vector and a phase difference of 60 degrees on both sides centered on the basic voltage vector close to the voltage command vector. 3. The three-phase PWM signal generator according to claim 1, further comprising a redistribution unit that distributes the voltage vector. The PWM signal generating means includes:
A dividing means for dividing the generation time ratio of the central basic voltage vector into two;
The three-phase PWM according to any one of claims 1 to 3, further comprising arrangement determining means for arranging two divided generation time ratios in the first half and the second half within one carrier period of the PWM signal. Signal generator. The PWM signal generating means includes:
A dividing means for dividing a zero vector obtained by switching based on a generation time ratio of a basic voltage vector into two types of zero vectors, and dividing a generation period of one type of zero vector into two;
The three-phase PWM according to any one of claims 1 to 3, further comprising arrangement determining means for arranging two generation periods of the divided zero vectors in the first half and the second half in one carrier cycle, respectively. Signal generator. The PWM signal generating means includes:
The generation time ratio of the central basic voltage vector is divided into two, the zero vector obtained by switching based on the generation time ratio of the basic voltage vector is divided into two types of zero vectors, and the generation period of one type of zero vector is Dividing means to divide into two,
4. Arrangement determining means for arranging the generation time ratio of two divided basic voltage vectors and the generation period of two zero vectors in the first half and the second half in one carrier cycle, respectively. The three-phase PWM signal generator according to any one of the above. The PWM signal generating means includes:
A dividing unit that divides the zero vector obtained by switching based on the generation time ratio of the basic voltage vector into approximately two equal parts and divides the zero vector into two types of zero vectors, and divides the generation period of one type of zero vector into two;
Arrangement determining means for arranging two divided zero vector generation periods in the first half and second half in one carrier cycle, and arranging the other zero vector generation periods in the center of one carrier cycle. 4. The three-phase PWM signal generator according to claim 1, comprising: The PWM signal generating means includes:
The generation time ratio of the central basic voltage vector is divided into two, the zero vector obtained by switching based on the generation time ratio of the basic voltage vector is divided into almost two equal parts and divided into two types of zero vectors, and one kind of A dividing means for dividing the zero vector generation period into two;
The divided generation time ratios of two basic voltage vectors and the generation periods of two zero vectors are respectively arranged in the first half and the latter half of one carrier period, and the center of the generation period of another type of zero vector is the one carrier period. The three-phase PWM signal generator according to any one of claims 1 to 3, further comprising an arrangement determining unit arranged to be aligned with the center.   In a three-phase PWM signal generator for driving a semiconductor switching element of a three-phase voltage type inverter device by a PWM signal and detecting a current flowing in a bus of the three-phase voltage type inverter device, four types of basic voltage vectors and basic voltage vectors A three-phase PWM signal generation device comprising PWM signal generation means for generating a PWM signal by using a combination of zero vectors obtained by switching based on the generation time ratio. The PWM signal generating means includes:
Production of generating two types of basic voltage vectors having a phase difference of 60 degrees by assigning generation time ratios to two types of basic voltage vectors having a phase difference of 60 degrees across the voltage command vector based on the voltage command vectors Means,
Among the two types of basic voltage vectors, two basic types having a basic voltage vector component close to the voltage command vector and a phase difference of 60 degrees on both sides centered on the basic voltage vector close to the voltage command vector. Redistribution means for distributing to voltage vectors;
Deformation of a vector by adding the same value to one of the two basic voltage vectors excluding the central basic voltage vector and the basic voltage vector having a phase difference of 180 degrees from the basic voltage vector. 10. The three-phase PWM signal generator according to claim 9, further comprising: means. The PWM signal generating means includes:
Production of generating two types of basic voltage vectors having a phase difference of 60 degrees by assigning generation time ratios to two types of basic voltage vectors having a phase difference of 60 degrees across the voltage command vector based on the voltage command vectors Means,
Among the two types of basic voltage vectors, two basic types having a basic voltage vector component close to the voltage command vector and a phase difference of 60 degrees on both sides centered on the basic voltage vector close to the voltage command vector. Redistribution means for distributing to voltage vectors;
Deformation of a vector by adding the same value to one of the two basic voltage vectors excluding the central basic voltage vector and the basic voltage vector having a phase difference of 180 degrees from the basic voltage vector. Means,
The three-phase according to claim 9, further comprising switching means for switching a vector to which a value is given by the deformation means based on an inverter rotation angle range of an electric motor driven by the three-phase voltage type inverter device. PWM signal generator. The PWM signal generating means includes:
A dividing means for dividing the four types of basic vectors into two sets of basic vectors;
The three-phase PWM signal according to any one of claims 9 to 11, further comprising arrangement determining means for arranging two divided sets of basic voltage vectors in the first half and the second half in one carrier period, respectively. Generator. The PWM signal generating means includes:
The four basic vectors are divided into two basic vector sets, and the zero vector obtained by switching based on the generation time ratio of the basic voltage vector is divided into two types of zero vectors. A dividing means for dividing the generation period into two;
Arrangement determining means for arranging a set of two divided basic voltage vectors in the first half and the second half in one carrier cycle, and arranging a generation period of two divided zero vectors in the first half and the second half in one carrier cycle, respectively. The three-phase PWM signal generator according to claim 9, wherein the three-phase PWM signal generator is provided. The PWM signal generating means includes:
The four types of basic vectors are divided into two sets of basic vectors, the zero vector obtained by switching based on the generation time ratio of the basic voltage vector is divided into almost two equal parts and divided into two types of zero vectors, and 1 A dividing means for dividing the generation period of the zero vector of the type into two;
A set of two divided basic voltage vectors is arranged in the first half and the second half in one carrier cycle, and a generation period of two divided zero vectors is arranged in the first half and the second half in one carrier cycle, respectively. The three-phase PWM signal generation according to any one of claims 9 to 11, further comprising arrangement determining means for arranging the generation period of one kind of zero vector so as to be aligned with the center of one carrier cycle. apparatus.   15. A three-phase voltage type inverter apparatus comprising the three-phase PWM signal generation apparatus according to claim 1 and driven by a PWM signal from the three-phase PWM signal generation apparatus.

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