JP4225583B2 - ハードウェア・ロジック・エミュレーション・システムで使用するための分配ロジック・アナライザ - Google Patents

ハードウェア・ロジック・エミュレーション・システムで使用するための分配ロジック・アナライザ Download PDF

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Publication number
JP4225583B2
JP4225583B2 JP50076099A JP50076099A JP4225583B2 JP 4225583 B2 JP4225583 B2 JP 4225583B2 JP 50076099 A JP50076099 A JP 50076099A JP 50076099 A JP50076099 A JP 50076099A JP 4225583 B2 JP4225583 B2 JP 4225583B2
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logic
signal
analyzer
chip
chips
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Expired - Fee Related
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JP50076099A
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Japanese (ja)
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JP2002501646A (ja
JP2002501646A5 (enExample
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サンプル，ステファン・ピー
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Quickturn Design Systems Inc
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Quickturn Design Systems Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3177—Testing of logic operation, e.g. by logic analysers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/25—Testing of logic operation, e.g. by logic analysers

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Logic Circuits (AREA)
JP50076099A 1997-05-30 1998-05-18 ハードウェア・ロジック・エミュレーション・システムで使用するための分配ロジック・アナライザ Expired - Fee Related JP4225583B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/865,657 1997-05-30
US08/865,657 US5943490A (en) 1997-05-30 1997-05-30 Distributed logic analyzer for use in a hardware logic emulation system
PCT/US1998/010312 WO1998054649A1 (en) 1997-05-30 1998-05-18 Distributed logic analyzer for use in a hardware logic emulation system

Publications (3)

Publication Number Publication Date
JP2002501646A JP2002501646A (ja) 2002-01-15
JP2002501646A5 JP2002501646A5 (enExample) 2005-12-08
JP4225583B2 true JP4225583B2 (ja) 2009-02-18

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ID=25345974

Family Applications (1)

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JP50076099A Expired - Fee Related JP4225583B2 (ja) 1997-05-30 1998-05-18 ハードウェア・ロジック・エミュレーション・システムで使用するための分配ロジック・アナライザ

Country Status (10)

Country Link
US (2) US5943490A (enExample)
EP (1) EP0985175B1 (enExample)
JP (1) JP4225583B2 (enExample)
KR (1) KR20010013191A (enExample)
AT (1) ATE278986T1 (enExample)
CA (1) CA2291257A1 (enExample)
DE (1) DE69826859T2 (enExample)
IL (1) IL132984A0 (enExample)
TW (1) TW424199B (enExample)
WO (1) WO1998054649A1 (enExample)

Families Citing this family (110)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6687865B1 (en) * 1998-03-25 2004-02-03 On-Chip Technologies, Inc. On-chip service processor for test and debug of integrated circuits
US6289400B1 (en) * 1998-04-15 2001-09-11 Infineon Technologies Ag Electrical control device with configurable control modules
US6202042B1 (en) * 1998-11-09 2001-03-13 International Business Machines Corporation Hardware simulator instrumentation
US6195629B1 (en) * 1998-11-09 2001-02-27 International Business Machines Corporation Method and system for selectively disabling simulation model instrumentation
US7079490B1 (en) * 1998-12-03 2006-07-18 Intel Corporation Integrated circuit with trace analyzer
US6434733B1 (en) * 1999-03-24 2002-08-13 Synopsys, Inc. System and method for high-level test planning for layout
US6470478B1 (en) 1999-06-29 2002-10-22 International Business Machines Corporation Method and system for counting events within a simulation model
US6947882B1 (en) * 1999-09-24 2005-09-20 Mentor Graphics Corporation Regionally time multiplexed emulation system
US6263302B1 (en) * 1999-10-29 2001-07-17 Vast Systems Technology Corporation Hardware and software co-simulation including simulating the cache of a target processor
US6230114B1 (en) * 1999-10-29 2001-05-08 Vast Systems Technology Corporation Hardware and software co-simulation including executing an analyzed user program
US6262594B1 (en) * 1999-11-05 2001-07-17 Ati International, Srl Apparatus and method for configurable use of groups of pads of a system on chip
US6618839B1 (en) * 1999-11-30 2003-09-09 Synplicity, Inc. Method and system for providing an electronic system design with enhanced debugging capabilities
US6931572B1 (en) 1999-11-30 2005-08-16 Synplicity, Inc. Design instrumentation circuitry
US6823497B2 (en) 1999-11-30 2004-11-23 Synplicity, Inc. Method and user interface for debugging an electronic system
US7065481B2 (en) 1999-11-30 2006-06-20 Synplicity, Inc. Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer
US7356786B2 (en) * 1999-11-30 2008-04-08 Synplicity, Inc. Method and user interface for debugging an electronic system
US7072818B1 (en) 1999-11-30 2006-07-04 Synplicity, Inc. Method and system for debugging an electronic system
US7240303B1 (en) 1999-11-30 2007-07-03 Synplicity, Inc. Hardware/software co-debugging in a hardware description language
EP1139220B1 (en) * 2000-03-02 2017-10-25 Texas Instruments Incorporated Obtaining and exporting on-chip data processor trace and timing information
US7113902B2 (en) 2000-03-02 2006-09-26 Texas Instruments Incorporated Data processing condition detector with table lookup
US6961691B1 (en) * 2000-03-30 2005-11-01 Mentor Graphics Corporation Non-synchronized multiplex data transport across synchronous systems
US6697957B1 (en) * 2000-05-11 2004-02-24 Quickturn Design Systems, Inc. Emulation circuit with a hold time algorithm, logic analyzer and shadow memory
DE10196175T1 (de) * 2000-05-11 2003-04-17 Quickturn Design Systems Inc Emulations-Schaltkreis mit einem Haltezeit-Algorithmus, Logikanalysierer und Shadow-Speicher
US6437713B1 (en) * 2000-10-06 2002-08-20 Xilinx, Inc. Programmable logic device having amplitude and phase modulation communication
US7222315B2 (en) * 2000-11-28 2007-05-22 Synplicity, Inc. Hardware-based HDL code coverage and design analysis
US6978231B2 (en) 2000-12-05 2005-12-20 Derek Edward Williams Embedded hardware description language instrumentation
US7092864B2 (en) * 2000-12-29 2006-08-15 International Business Machines Corporation Signal override for simulation models
US7039574B1 (en) * 2000-12-29 2006-05-02 International Business Machines Corporation Naming and managing simulation model events
US6920418B2 (en) 2000-12-30 2005-07-19 International Business Machines Corporation Detecting events within simulation models
US6941257B2 (en) * 2000-12-30 2005-09-06 International Business Machines Corporation Hierarchical processing of simulation model events
US20020128809A1 (en) * 2000-12-30 2002-09-12 International Business Machines Corporation Randomized simulation model instrumentation
US7076595B1 (en) * 2001-05-18 2006-07-11 Xilinx, Inc. Programmable logic device including programmable interface core and central processing unit
KR100794916B1 (ko) * 2001-09-14 2008-01-14 양세양 에뮬레이션과 시뮬레이션을 혼용한 점진적 설계 검증을위한 설계검증 장치 및 이를 이용한 설계 검증 방법
EP1438662A2 (en) * 2001-10-11 2004-07-21 Altera Corporation Error detection on programmable logic resources
US7035787B2 (en) 2001-10-30 2006-04-25 Mentor Graphics Corporation Emulation components and system including distributed routing and configuration of emulation resources
WO2003038613A1 (en) * 2001-10-30 2003-05-08 Mentor Graphics Corporation Emulating components and system including distributed emulation methods
US7305633B2 (en) * 2001-10-30 2007-12-04 Mentor Graphics Corporation Distributed configuration of integrated circuits in an emulation system
US7130788B2 (en) 2001-10-30 2006-10-31 Mentor Graphics Corporation Emulation components and system including distributed event monitoring, and testing of an IC design under emulation
US7359847B2 (en) * 2001-11-30 2008-04-15 International Business Machines Corporation Tracking converage results in a batch simulation farm network
US7827510B1 (en) 2002-06-07 2010-11-02 Synopsys, Inc. Enhanced hardware debugging with embedded FPGAS in a hardware description language
JP3610978B2 (ja) * 2002-06-13 2005-01-19 株式会社村田製作所 モジュール試験装置
KR100423891B1 (ko) * 2002-06-21 2004-03-22 삼성전자주식회사 트레이스 모듈을 구비한 마이크로프로세서
US20040078656A1 (en) * 2002-06-26 2004-04-22 Mike Ryken Method of saving/restoring processor state after entering/exiting debug mode
US6973631B2 (en) * 2002-07-18 2005-12-06 Incentia Design Systems Corp. Scan insertion with bypass login in an IC design
US7127695B2 (en) * 2002-07-18 2006-10-24 Incentia Design Systems Corp. Timing based scan chain implementation in an IC design
US7235316B2 (en) * 2002-08-07 2007-06-26 Mti Microfuel Cells Inc. Integrated heat management of electronics and fuel cell power system
EP1403652A1 (de) * 2002-09-30 2004-03-31 Siemens Aktiengesellschaft Verfahren und Vorrichtung zur Prüfung der Abbildung/Implementierung eines Modells eines logischen Schaltkreises auf einen/in einem Hardware-Emulator
US7440884B2 (en) * 2003-01-23 2008-10-21 Quickturn Design Systems, Inc. Memory rewind and reconstruction for hardware emulator
JP2004234530A (ja) * 2003-01-31 2004-08-19 Fujitsu Ten Ltd マイクロコンピュータのロジック開発装置
US20040228411A1 (en) * 2003-05-12 2004-11-18 Sony Corporation Method and system for decoder clock control in presence of jitter
US8099273B2 (en) * 2003-06-05 2012-01-17 Mentor Graphics Corporation Compression of emulation trace data
US7184946B2 (en) * 2003-06-19 2007-02-27 Xilinx, Inc. Co-simulation via boundary scan interface
US6952813B1 (en) 2003-07-30 2005-10-04 Xilinx, Inc. Method and apparatus for selecting programmable interconnects to reduce clock skew
US20050086042A1 (en) * 2003-10-15 2005-04-21 Gupta Shiv K. Parallel instances of a plurality of systems on chip in hardware emulator verification
DE10355187B4 (de) * 2003-11-26 2006-05-24 Infineon Technologies Ag Verfahren und Vorrichtung zur Timinganalyse einer Schaltung
US7738399B2 (en) * 2004-06-01 2010-06-15 Quickturn Design Systems Inc. System and method for identifying target systems
US7739093B2 (en) * 2004-06-01 2010-06-15 Quickturn Design System, Inc. Method of visualization in processor based emulation system
US7412544B2 (en) 2004-06-18 2008-08-12 International Business Machines Corporation Reconfigurable USB I/O device persona
US7358765B2 (en) * 2005-02-23 2008-04-15 Cswitch Corporation Dedicated logic cells employing configurable logic and dedicated logic functions
US7368941B2 (en) * 2005-02-23 2008-05-06 Cswitch Corporation Dedicated logic cells employing sequential logic and control logic functions
US7353162B2 (en) * 2005-02-11 2008-04-01 S2C, Inc. Scalable reconfigurable prototyping system and method
US8205186B1 (en) 2005-04-11 2012-06-19 Synopsys, Inc. Incremental modification of instrumentation logic
US20060247909A1 (en) * 2005-04-27 2006-11-02 Desai Madhav P System and method for emulating a logic circuit design using programmable logic devices
US7751436B2 (en) * 2005-05-24 2010-07-06 Sony Corporation System and method for dynamically establishing PLL speed based on receive buffer data accumulation for streaming video
JP2007026170A (ja) * 2005-07-19 2007-02-01 Matsushita Electric Ind Co Ltd 半導体集積回路の自動レイアウト方法、自動レイアウトプログラム、および自動レイアウト装置
US7523297B1 (en) * 2005-09-16 2009-04-21 Sun Microsystems, Inc. Shadow scan decoder
US7600168B2 (en) * 2005-12-26 2009-10-06 Prolific Technology Inc. Apparatus with programmable scan chains for multiple chip modules and method for programming the same
US7739552B2 (en) * 2006-02-17 2010-06-15 Lanning Eric J Tapping a memory card
US8352242B2 (en) * 2006-02-21 2013-01-08 Mentor Graphics Corporation Communication scheme between programmable sub-cores in an emulation environment
US7555424B2 (en) 2006-03-16 2009-06-30 Quickturn Design Systems, Inc. Method and apparatus for rewinding emulated memory circuits
KR101282963B1 (ko) * 2006-05-12 2013-07-08 삼성전자주식회사 에뮬레이션 시스템 및 그 방법
US7725304B1 (en) * 2006-05-22 2010-05-25 Cadence Design Systems, Inc. Method and apparatus for coupling data between discrete processor based emulation integrated chips
CN100410887C (zh) * 2006-09-18 2008-08-13 中国航天时代电子公司第七七一研究所 基于信号类别的分布式仿真测试系统体系的构建方法
US7606698B1 (en) * 2006-09-26 2009-10-20 Cadence Design Systems, Inc. Method and apparatus for sharing data between discrete clusters of processors
US7904288B1 (en) * 2006-11-06 2011-03-08 Cadence Design Systems, Inc. Hardware emulator having a variable input emulation group
US20080148214A1 (en) * 2006-12-15 2008-06-19 Yancey Jerry W Method and system for configuring FPGAs from VHDL code with reduced delay from large multiplexers
US8234624B2 (en) 2007-01-25 2012-07-31 International Business Machines Corporation System and method for developing embedded software in-situ
US8296121B2 (en) * 2007-04-25 2012-10-23 Cadence Design Systems, Inc. Method and apparatus for controlling power in an emulation system
US7904859B2 (en) * 2007-05-09 2011-03-08 Synopsys, Inc. Method and apparatus for determining a phase relationship between asynchronous clock signals
US8756557B2 (en) * 2007-05-09 2014-06-17 Synopsys, Inc. Techniques for use with automated circuit design and simulations
US7930165B2 (en) * 2008-02-07 2011-04-19 Accemic Gmbh & Co. Kg Procedure and device for emulating a programmable unit providing system integrity control
US20090259457A1 (en) * 2008-04-14 2009-10-15 Mentor Graphics Corporaton Trace Routing Network
KR101524828B1 (ko) * 2008-04-23 2015-06-02 삼성전자주식회사 에뮬레이션 시스템 및 그 구동 방법
US8327198B2 (en) * 2009-08-14 2012-12-04 Intel Corporation On-die logic analyzer for semiconductor die
US8745447B2 (en) * 2009-08-18 2014-06-03 Lexmark International, Inc. System and method for analyzing an electronics device including a logic analyzer
US9170901B2 (en) 2009-08-18 2015-10-27 Lexmark International, Inc. System and method for analyzing an electronics device including a logic analyzer
US8473887B2 (en) * 2011-03-16 2013-06-25 Oracle America, Inc. Event scheduler for an electrical circuit design to account for hold time violations
CN102957424B (zh) * 2011-08-22 2016-08-24 上海华虹集成电路有限责任公司 用于ISO14443 TypeA协议的凹槽信号恢复电路
US8595683B1 (en) 2012-04-12 2013-11-26 Cadence Design Systems, Inc. Generating user clocks for a prototyping environment
FR2991476B1 (fr) * 2012-06-01 2022-04-22 Flexras Tech Prototypage multi-fpga d'un circuit asic
US9405877B1 (en) 2014-12-22 2016-08-02 Cadence Design Systems, Inc. System and method of fast phase aligned local generation of clocks on multiple FPGA system
US9495492B1 (en) 2015-01-05 2016-11-15 Cadence Design Systems, Inc. Implementing synchronous triggers for waveform capture in an FPGA prototyping system
US9294094B1 (en) 2015-01-08 2016-03-22 Cadence Design Systems, Inc. Method and apparatus for fast low skew phase generation for multiplexing signals on a multi-FPGA prototyping system
US10116557B2 (en) 2015-05-22 2018-10-30 Gray Research LLC Directional two-dimensional router and interconnection network for field programmable gate arrays, and other circuits and applications of the router and network
US10860763B1 (en) 2015-09-24 2020-12-08 Cadence Design Systems, Inc. Data routing and multiplexing architecture to support serial links and advanced relocation of emulation models
US9910810B1 (en) * 2015-10-23 2018-03-06 Cadence Design Systems, Inc. Multiphase I/O for processor-based emulation system
US10068041B2 (en) * 2016-02-01 2018-09-04 King Fahd University Of Petroleum And Minerals Multi-core compact executable trace processor
US10587534B2 (en) 2017-04-04 2020-03-10 Gray Research LLC Composing cores and FPGAS at massive scale with directional, two dimensional routers and interconnection networks
US10841246B2 (en) 2017-08-30 2020-11-17 Arista Networks, Inc. Distributed core switching with orthogonal fabric card and line cards
TWI665870B (zh) * 2018-02-01 2019-07-11 緯穎科技服務股份有限公司 電子系統及信號切換電路
US10922203B1 (en) * 2018-09-21 2021-02-16 Nvidia Corporation Fault injection architecture for resilient GPU computing
US11573883B1 (en) * 2018-12-13 2023-02-07 Cadence Design Systems, Inc. Systems and methods for enhanced compression of trace data in an emulation system
US20200195586A1 (en) * 2018-12-18 2020-06-18 Arista Networks, Inc. Network devices with multiple switch cards
US10986423B2 (en) 2019-04-11 2021-04-20 Arista Networks, Inc. Network device with compact chassis
TWI698088B (zh) * 2019-08-22 2020-07-01 瑞昱半導體股份有限公司 應用於多個操作模式的電路
US10902175B1 (en) 2019-09-11 2021-01-26 International Business Machines Corporation Cross-hierarchical block pin placement
US11266007B2 (en) 2019-09-18 2022-03-01 Arista Networks, Inc. Linecard system using riser printed circuit boards (PCBS)
KR102319160B1 (ko) * 2020-07-14 2021-11-01 주식회사 엑시콘 반도체 디바이스 테스트 시스템
KR102471771B1 (ko) * 2020-11-20 2022-11-29 주식회사 에스디에이 고속 신호 특성 검증을 위한 지능형 프로브 카드
KR102835577B1 (ko) * 2021-10-14 2025-07-16 삼성전자주식회사 테스트 장치, 테스트 장치의 동작 방법 및 반도체 장치 테스트 시스템

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3149460C2 (de) * 1981-12-14 1984-04-12 Rohde & Schwarz GmbH & Co KG, 8000 München Logikanalysator
US4924468A (en) * 1987-11-30 1990-05-08 Kontron Holding Ag Logic analyzer
EP1462964A3 (en) * 1988-10-05 2006-06-07 Quickturn Design Systems, Inc. Method for stimulating functional logic circuit with logical stimulus
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5109353A (en) * 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5377124A (en) * 1989-09-20 1994-12-27 Aptix Corporation Field programmable printed circuit board
US5352123A (en) * 1992-06-08 1994-10-04 Quickturn Systems, Incorporated Switching midplane and interconnection system for interconnecting large numbers of signals
WO1994003856A1 (en) * 1992-08-07 1994-02-17 Massachusetts Institute Of Technology Column-associative cache
US5425036A (en) * 1992-09-18 1995-06-13 Quickturn Design Systems, Inc. Method and apparatus for debugging reconfigurable emulation systems
US5483178A (en) * 1993-03-29 1996-01-09 Altera Corporation Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers
SE500988C2 (sv) * 1993-10-28 1994-10-17 Skf Ab Flerradigt sfäriskt rullager
TW253031B (enExample) * 1993-12-27 1995-08-01 At & T Corp
US5550843A (en) * 1994-04-01 1996-08-27 Xilinx, Inc. Programmable scan chain testing structure and method
US5630048A (en) * 1994-05-19 1997-05-13 La Joie; Leslie T. Diagnostic system for run-time monitoring of computer operations
WO1996013902A1 (en) * 1994-11-01 1996-05-09 Virtual Machine Works, Inc. Programmable multiplexing input/output port
US5659716A (en) * 1994-11-23 1997-08-19 Virtual Machine Works, Inc. Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation
US5649176A (en) * 1995-08-10 1997-07-15 Virtual Machine Works, Inc. Transition analysis and circuit resynthesis method and device for digital circuit modeling
US5754827A (en) * 1995-10-13 1998-05-19 Mentor Graphics Corporation Method and apparatus for performing fully visible tracing of an emulation
US5574388A (en) * 1995-10-13 1996-11-12 Mentor Graphics Corporation Emulation system having a scalable multi-level multi-stage programmable interconnect network
US5777489A (en) * 1995-10-13 1998-07-07 Mentor Graphics Corporation Field programmable gate array with integrated debugging facilities
US5790832A (en) * 1996-04-23 1998-08-04 Mentor Graphics Corporation Method and apparatus for tracing any node of an emulation
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation

Also Published As

Publication number Publication date
JP2002501646A (ja) 2002-01-15
IL132984A0 (en) 2001-03-19
TW424199B (en) 2001-03-01
ATE278986T1 (de) 2004-10-15
US5943490A (en) 1999-08-24
WO1998054649A1 (en) 1998-12-03
CA2291257A1 (en) 1998-12-03
US20020177990A1 (en) 2002-11-28
EP0985175B1 (en) 2004-10-06
DE69826859T2 (de) 2005-12-29
DE69826859D1 (de) 2004-11-11
EP0985175A1 (en) 2000-03-15
KR20010013191A (ko) 2001-02-26

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