JP4219647B2 - 適応的キャッシュフレームのロッキング及びアンロッキングのための方法及び装置 - Google Patents

適応的キャッシュフレームのロッキング及びアンロッキングのための方法及び装置 Download PDF

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JP4219647B2
JP4219647B2 JP2002295543A JP2002295543A JP4219647B2 JP 4219647 B2 JP4219647 B2 JP 4219647B2 JP 2002295543 A JP2002295543 A JP 2002295543A JP 2002295543 A JP2002295543 A JP 2002295543A JP 4219647 B2 JP4219647 B2 JP 4219647B2
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frame
frames
cache
task
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JP2003186743A5 (enExample
JP2003186743A (ja
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デワイヤー ハリー
スザンザ ファーナンド ジョン
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Agere Systems LLC
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Agere Systems LLC
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6042—Allocation of cache space to multiple users or processors

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2002295543A 2001-10-09 2002-10-09 適応的キャッシュフレームのロッキング及びアンロッキングのための方法及び装置 Expired - Fee Related JP4219647B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/975,764 US8261022B2 (en) 2001-10-09 2001-10-09 Method and apparatus for adaptive cache frame locking and unlocking
US09/975764 2001-10-09

Publications (3)

Publication Number Publication Date
JP2003186743A JP2003186743A (ja) 2003-07-04
JP2003186743A5 JP2003186743A5 (enExample) 2005-12-02
JP4219647B2 true JP4219647B2 (ja) 2009-02-04

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JP2002295543A Expired - Fee Related JP4219647B2 (ja) 2001-10-09 2002-10-09 適応的キャッシュフレームのロッキング及びアンロッキングのための方法及び装置

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US (2) US8261022B2 (enExample)
JP (1) JP4219647B2 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6904501B1 (en) * 2002-06-17 2005-06-07 Silicon Graphics, Inc. Cache memory for identifying locked and least recently used storage locations
US9098943B1 (en) * 2003-12-31 2015-08-04 Ziilabs Inc., Ltd. Multiple simultaneous bin sizes
US7590803B2 (en) * 2004-09-23 2009-09-15 Sap Ag Cache eviction
US20060143398A1 (en) * 2004-12-23 2006-06-29 Stefan Rau Method and apparatus for least recently used (LRU) software cache
US20060143389A1 (en) * 2004-12-28 2006-06-29 Frank Kilian Main concept for common cache management
US7539821B2 (en) * 2004-12-28 2009-05-26 Sap Ag First in first out eviction implementation
US20060143256A1 (en) 2004-12-28 2006-06-29 Galin Galchev Cache region concept
JP4617210B2 (ja) * 2005-07-13 2011-01-19 日立ビアメカニクス株式会社 描画装置及びそれを搭載した露光装置
US7877537B2 (en) * 2006-12-15 2011-01-25 Microchip Technology Incorporated Configurable cache for a microprocessor
US9208095B2 (en) * 2006-12-15 2015-12-08 Microchip Technology Incorporated Configurable cache for a microprocessor
US7966457B2 (en) 2006-12-15 2011-06-21 Microchip Technology Incorporated Configurable cache for a microprocessor
JP5083757B2 (ja) * 2007-04-19 2012-11-28 インターナショナル・ビジネス・マシーンズ・コーポレーション データをキャッシュする技術
EP2664993A1 (en) * 2011-01-12 2013-11-20 Fujitsu Limited Cache memory device, cache memory control device, information processing device, cache memory control method, and threshold value determination program for cache memory device
CN103885892A (zh) * 2012-12-20 2014-06-25 株式会社东芝 存储器控制器
US10460411B2 (en) * 2016-08-30 2019-10-29 Uber Technologies, Inc. Real-time resource management for on-demand services
US10509727B1 (en) * 2018-09-10 2019-12-17 Mediatek Inc. Method and apparatus for performing task-level cache management in electronic device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5715274A (en) 1980-06-30 1982-01-26 Fujitsu Ltd Buffer storage control system
JPH0266654A (ja) 1988-08-31 1990-03-06 Nec Corp キャッシュメモリ制御方式
US5353425A (en) * 1992-04-29 1994-10-04 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
JPH07334428A (ja) 1994-06-14 1995-12-22 Toshiba Corp キャッシュメモリ
GB2345987B (en) * 1999-01-19 2003-08-06 Advanced Risc Mach Ltd Memory control within data processing systems
JP3438650B2 (ja) * 1999-05-26 2003-08-18 日本電気株式会社 キャッシュメモリ
EP1182567B1 (en) * 2000-08-21 2012-03-07 Texas Instruments France Software controlled cache configuration

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Publication number Publication date
US20130024620A1 (en) 2013-01-24
US8478944B2 (en) 2013-07-02
US8261022B2 (en) 2012-09-04
US20030070047A1 (en) 2003-04-10
JP2003186743A (ja) 2003-07-04

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