JP4208237B2 - Manufacturing method of semiconductor substrate - Google Patents

Description

【００２８】
表１から分かるように、シリコン基板表面の窪みの密度を増加させることにより、ＥＰＤ、すなわち、歪Ｓｉ層の転位が抑制されることが認められた。
また、シリコン基板の窪み部分は、エピタキシャル成長させたＳｉＧｅ層表面においては窪みが残っておらず、表面全体が平坦に形成されていた。
【００２９】
【発明の効果】
本発明に係る製造方法によれば、ＳｉＧｅ層の薄層化、かつ、転位密度の低減化を図ることができ、しかも、ＳｉＧｅ層表面が平坦化された半導体基板が得られる。これにより、ＳｉＧｅ層を有する半導体基板の生産コストの削減、生産効率の向上を図ることも可能となる。
また、本発明に係る製造方法により得られたＳｉ層を有する半導体基板を用いれば、転位密度の低い高品質の歪Ｓｉ層が形成されているため、これをチャネル領域として用いることにより、キャリア移動度の高速化が図られることとなり、半導体素子のより一層の微細化、高性能化等に寄与することができる。
【図面の簡単な説明】
【図１】シリコン基板に形成される窪みを模式的に示したものであり、（ａ）は断面図、（ｂ）は上面図である。
【図２】シリコン基板表面に形成された窪みによる転位制御の様子を模式的に示した断面図である。
【図３】窪みが形成されたシリコン基板表面へのＳｉＧｅ層のエピタキシャル成長を段階的に示した断面図である。
【符号の説明】
１ シリコン基板
２ 窪み
３ ＳｉＧｅ層
４ 転位[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly to a method for manufacturing a semiconductor substrate having a SiGe layer.
[0002]
[Prior art]
In recent years, high-speed devices using a strained Si layer obtained by epitaxially growing Si on a silicon substrate via a SiGe layer as a channel region have been proposed.
This strained Si layer is strained by being pulled by SiGe, which has a larger lattice constant than Si, whereby the band structure of Si changes, the degeneracy is solved, and the carrier mobility increases.
Therefore, by using this strained Si layer for the channel region, the carrier movement speed can be increased by 1.5 times or more when bulk Si is used.
[0003]
In order to obtain the strained Si layer as described above without causing dislocation, it is necessary to epitaxially grow a SiGe layer having a low dislocation density on the silicon substrate.
However, since Si and SiGe have different lattice constants, dislocation occurs due to lattice mismatch, and the influence extends to the strained Si layer. As a result, dislocation occurs in the strained Si layer as the device active layer. was there.
[0004]
For this, conventionally, in the process of epitaxial growth, a method of preventing the occurrence of dislocation by forming a composition gradient layer that gradually increases the Ge concentration in the SiGe layer has been employed (for example, Patent Document 1).
[0005]
However, even with this method, it has been difficult to reduce dislocations to prevent malfunction of the transistor.
In addition, since the Ge concentration is increased stepwise, the thickness of the SiGe layer becomes very thick, about 3 μm, and the epitaxial growth of such a thick SiGe layer takes time, and also in terms of production efficiency and cost. It was inferior.
[0006]
In order to solve the above problem, a proposal has been made to further reduce the dislocation density in the SiGe layer by forming a V-shaped groove on the surface of the silicon substrate and then epitaxially growing the SiGe layer (Patent Document 2). reference).
[0007]
[Patent Document 1]
JP-A-6-252046 [Patent Document 2]
JP-A-2002-359189
[Problems to be solved by the invention]
The method for forming a groove on the surface of the silicon substrate described above is that dislocations generated during the formation of the SiGe layer can be eliminated by disappearing at the side surface of the groove, so that the dislocation density in the SiGe layer can be reduced. .
[0009]
However, in the above-described method, the thinner the SiGe layer formed by epitaxial growth, the easier it is to be formed in a state having grooves like the V-shaped groove formed on the surface of the SiC substrate. For this reason, the device region is limited to a portion other than the groove formed, the pattern design is restricted, and it is easy to waste when forming the device.
[0010]
Therefore, it is desirable that the entire substrate can be effectively used without being divided by the groove, that is, SiGe layer can be prevented from generating dislocations and free pattern design can be performed. The entire layer surface has been required to be formed flat.
[0011]
The present invention has been made to solve the above technical problem, and in the method of manufacturing a semiconductor substrate having a SiGe layer, the SiGe layer can be thinned and the dislocation density can be reduced. In addition, an object of the present invention is to provide a method for manufacturing a semiconductor substrate having a planarized SiGe layer surface.
[0012]
[Means for Solving the Problems]
The method for manufacturing a semiconductor substrate according to the present invention includes forming a recess having a plane orientation (001) on a silicon substrate surface having a crystal orientation <111> by alkaline etching , and then epitaxially growing a SiGe layer on the silicon substrate. Features.
According to the above method, since dislocations generated due to lattice mismatch can be terminated inside the recess, the SiGe layer can be thinned and the dislocation density on the surface of the SiGe layer can be reduced.
Further, according to the chemical polishing (chemical polishing) treatment with an alkaline solution, the depressions having the specific orientation as described above can be easily formed on the order of nm due to the characteristic anisotropy.
[0014]
The method for manufacturing a semiconductor substrate according to the present invention is characterized in that a Si layer is further formed on the SiGe layer.
The Si layer in the semiconductor substrate thus formed can be obtained as a strained Si layer with a low dislocation density, and the carrier mobility can be increased.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in more detail.
The method for manufacturing a semiconductor substrate according to the present invention is to form a recess having a plane orientation (001) on the surface of a silicon substrate having a crystal orientation <111> and epitaxially grow a SiGe layer on the surface.
According to the above manufacturing method, dislocations generated due to lattice mismatch between Si and SiGe can be terminated inside a recess formed on the surface of the silicon substrate, and the density of threading dislocations reaching the surface of the SiGe layer. Can be reduced.
Therefore, even when a strained Si layer is further formed on the SiGe layer, in order to suppress threading dislocations, a SiGe layer that has conventionally required a thickness of the order of μm by a composition gradient layer or the like is It can be made thin to order.
[0016]
In the manufacturing method according to the present invention, a silicon substrate having a crystal orientation <111> is used, and a recess having a plane orientation (001) is formed on the surface thereof.
In the manufacturing method according to the present invention, by specifying the plane orientation of the silicon substrate and the depression as described above, the difference between the plane orientation of the substrate and the depression appears in the epitaxial growth rate of the SiGe layer, and the SiGe layer is a thin film. Even if it exists, the surface shape is formed flat.
[0017]
FIG. 1 schematically shows a recess 2 formed in the silicon substrate 1. FIG. 1A is a cross-sectional view, and FIG. 1B is a top view.
FIG. 3 shows in a stepwise manner a case where the SiGe layer 3 is epitaxially grown on the surface of the silicon substrate 1 on which the depressions 2 as shown in FIG. 1 are formed.
As shown in FIG. 3, according to the present invention, even if the SiGe layer 3 is a thin film, the shape of the depression 2 formed in the silicon substrate 1 is not reflected on the surface of the SiGe layer 3 and is flat. A simple surface can be obtained easily.
Such flattening of the surface of the SiGe layer 3 is different from the surface of the recess 2 in that the epitaxial growth rate of the SiGe layer 3 is different in each plane direction, and the epitaxial growth rate of the (001) plane is that of the <111> plane. And the sagging (relaxation) of the shape due to lamination.
[0018]
FIG. 2 schematically shows a state of dislocation control by the depression 2 formed on the surface of the silicon substrate 1.
As shown in FIG. 2, in a normal flat silicon substrate, dislocations generated due to lattice mismatch between Si and SiGe penetrate to the surface of the SiGe layer 3.
On the other hand, when the depression 2 is formed on the surface of the silicon substrate 1, the dislocation generated in the depression 2 is terminated at the surface of the depression 2 and suppresses the dislocation penetrating to the surface of the SiGe layer 3. be able to.
[0019]
As described above, the dent serves to terminate dislocations in the inside thereof. Therefore, the size of the dent is preferably on the order of 1 to 10 nm.
[0020]
The depression on the surface of the silicon substrate is preferably formed by alkali etching.
According to such chemical polishing (chemical polishing) treatment using an alkaline solution, a recess having a plane orientation (001) is formed on the surface of a silicon substrate having a crystal orientation <111> due to anisotropy that is a feature thereof. It can be easily formed by order.
[0021]
The alkali etching treatment time is preferably 3 minutes or more, and more preferably 10 minutes or more in order to form the above-described depression.
In addition, the kind and density | concentration of the solution used for alkali etching, and etching processing time are suitably adjusted according to the size, density, etc. of the hollow formed in the silicon substrate surface.
[0022]
After the alkali etching process, as in the normal process, before the SiGe layer is epitaxially grown, a mirror surface processing (mirror lapping) process is performed. At this time, a process is performed so as to leave the previously formed depression.
[0023]
On the SiGe layer formed as described above, a strained Si layer having a low dislocation density can be formed by laminating an Si layer.
As described above, in a substrate on which a strained Si layer having a low dislocation density is formed, the strained Si layer can increase the speed of carrier movement and can be used as a suitable substrate for forming a high-speed device.
[0024]
【Example】
EXAMPLES Hereinafter, although this invention is demonstrated more concretely based on an Example, this invention is not restrict | limited by the following Example.
[Example 1]
After pulling up the crystal, the lapping-processed silicon substrate surface having the crystal orientation <111> was subjected to chemical polishing with a 10% sodium hydroxide solution for 3 minutes. By this alkali etching, a recess having a plane orientation (001) was formed on the surface of the silicon substrate.
This silicon substrate was subjected to mirror wrapping so as to leave the depressions, and the density of the depressions on the surface was measured.
A SiGe layer (Si: 70%, Ge: 30%; thickness: 200 nm) was epitaxially grown on the obtained silicon substrate, and a strained Si layer (thickness: 20 nm) was further epitaxially grown.
The surface of the strained Si layer was flat.
The substrate obtained as described above was subjected to Secco etching, and the etch pit density (EPD: Etch Pit Density) on the surface of the strained Si layer was evaluated.
These results are shown in Table 1.
[0025]
[Examples 2 to 4]
The concentration and etching time of the sodium hydroxide solution shown in Examples 2 to 4 in Table 1 were used. Otherwise, alkaline etching was performed in the same manner as in Example 1. As a result, the surface orientation (001 ) Was formed.
Each of these silicon substrates was subjected to mirror wrapping to such an extent that the depressions were left, and the density of the depressions on the surface was measured.
A SiGe layer and a strained Si layer were epitaxially grown on each of the obtained silicon substrates in the same manner as in Example 1.
All the surfaces of the strained Si layer were flat.
Each substrate obtained as described above was subjected to Secco etching, and EPD on the surface of the strained Si layer was evaluated.
These results are shown in Table 1.
[0026]
[Comparative Example 1]
After the crystal pulling, a SiGe layer and a strained Si layer were epitaxially grown in the same manner as in Example 1 on the lapped silicon substrate having the crystal orientation <111>.
The substrate obtained as described above was subjected to Secco etching, and EPD on the surface of the strained Si layer was evaluated.
The results are shown in Table 1.
[0027]
[Table 1]

[0028]
As can be seen from Table 1, it was confirmed that dislocation of the EPD, that is, the strained Si layer, was suppressed by increasing the density of the depressions on the surface of the silicon substrate.
In addition, the recess portion of the silicon substrate had no recess left on the surface of the epitaxially grown SiGe layer, and the entire surface was formed flat.
[0029]
【The invention's effect】
According to the manufacturing method of the present invention, the SiGe layer can be thinned and the dislocation density can be reduced, and a semiconductor substrate having a flat SiGe layer surface can be obtained. As a result, the production cost of the semiconductor substrate having the SiGe layer can be reduced and the production efficiency can be improved.
In addition, if a semiconductor substrate having a Si layer obtained by the manufacturing method according to the present invention is used, a high-quality strained Si layer having a low dislocation density is formed. Therefore, it is possible to contribute to further miniaturization and higher performance of the semiconductor element.
[Brief description of the drawings]
FIG. 1 schematically shows a depression formed in a silicon substrate, where (a) is a sectional view and (b) is a top view.
FIG. 2 is a cross-sectional view schematically showing a state of dislocation control by a depression formed on the surface of a silicon substrate.
FIG. 3 is a cross-sectional view showing stepwise the epitaxial growth of a SiGe layer on the surface of a silicon substrate in which depressions are formed.
[Explanation of symbols]
1 silicon substrate 2 dent 3 SiGe layer 4 dislocation

Claims (2)

A method of manufacturing a semiconductor substrate, comprising: forming a recess having a plane orientation (001) on a silicon substrate surface having a crystal orientation <111> by alkali etching , and then epitaxially growing a SiGe layer on the silicon substrate. Wherein on the SiGe layer, further, a method of manufacturing a semiconductor substrate according to claim 1, wherein the forming the Si layer.

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