JP2002359189A - SEMICONDUCTOR SUBSTRATE AND FIELD EFFECT TRANSISTOR, METHOD FOR FORMING SiGe LAYER, METHOD FOR FORMING STRAINED Si LAYER USING IT AND METHOD FOR MANUFACTURING FIELD EFFECT TRANSISTOR - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor substrate and a field effect transistor, a method for forming an SiGe layer, a method for forming a strained Si layer and a method for manufacturing a field effect transistor in which dislocation density of the SiGe layer is reduced by a method by which restriction on the process and on the degree of freedom in the placement of device design is suppressed. SOLUTION: The semiconductor substrate comprises an SiGe layer SG formed on an Si substrate 1 where grooves 1a are made on the surface of the Si substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high-speed MOSFET
The present invention relates to a method for forming a SiGe layer suitable for forming a semiconductor substrate, a field effect transistor, a strained Si layer, and the like used for the like, a method for forming a strained Si layer using the same, and a method for manufacturing a field effect transistor.

[0002]

2. Description of the Related Art In recent years, SiG (SiG)
High-speed M using a strained Si layer epitaxially grown through an e (silicon-germanium) layer for the channel region
OSFET, MODFET and HEMT have been proposed. In this strained Si-FET, tensile strain occurs in the Si layer due to SiGe having a larger lattice constant than Si,
For this reason, the band structure of Si is changed, the degeneracy is released, and the carrier mobility is increased. Therefore, by using this strained Si layer as a channel region, it is possible to increase the speed by about 1.5 to 8 times the normal speed. Further, a normal Si substrate by the CZ method can be used as a substrate as a process, and a high-speed CMOS can be realized by a conventional CMOS process.

However, in order to epitaxially grow the strained Si layer required as a channel region of the FET, it is necessary to epitaxially grow a high-quality SiGe layer on a Si substrate. However, due to the difference in lattice constant between Si and SiGe, There was a problem in crystallinity due to dislocations and the like. For this purpose, the following various proposals have conventionally been made.

For example, a method using a buffer layer in which the Ge composition ratio of SiGe is changed at a constant gentle slope, a method using a buffer layer in which the Ge (germanium) composition ratio is changed stepwise (stepwise), a Ge composition A method using a buffer layer whose ratio is changed in a superlattice shape, a method using a buffer layer whose Ge composition ratio is changed at a constant gradient using an off-cut wafer of Si, and the like have been proposed (USPate).
nt 5,442,205, USPatent 5,221,413, PCT WO98 / 0085
7, JP-A-6-252046).

[0005] US Patent 5,285,086, US Patent
No. 5,158,907 proposes a technique in which an SiO ₂ film or the like on a Si substrate is patterned to form a restricted region which is selectively removed, and a SiGe layer is selectively formed only in the restricted region. This technique reduces the dislocation density by making the SiGe layer in the restricted region have a certain relationship in thickness and area, thereby eliminating dislocations moving in the SiGe layer at the side of the restricted region.

[0006]

However, the above-mentioned conventional technique has the following problems. That is, in the above-described conventional technique, the threading dislocation density on the wafer surface is still high, and there is a further demand for a reduction in threading dislocation in order to prevent a malfunction of the transistor. In particular, in the technique of forming a SiGe layer only in the above-described restricted region, the SiGe layer is formed only in the restricted region having a thickness of about the SiGe film. As a technology, selective growth with a high film formation rate and a low film formation rate is required, so that there is an inconvenience that restrictions on processes are large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made to reduce the threading dislocation density of a SiGe layer, reduce process restrictions, and limit the degree of freedom in device design layout. It is an object of the present invention to provide an effect transistor, a method for forming a SiGe layer, a method for forming a strained Si layer using the same, and a method for manufacturing a field effect transistor.

[0008]

The present invention has the following features to attain the object mentioned above. That is, the semiconductor substrate of the present invention comprises a Si substrate and SiGe on the Si substrate.
Wherein the Si substrate has a groove on the surface. The method of forming a SiGe layer according to the present invention is a method of forming a SiGe layer on a Si substrate,
Forming a groove on the surface of the Si substrate; and epitaxially growing the SiGe layer on the Si substrate. Further, a semiconductor substrate of the present invention is a semiconductor substrate in which a SiGe layer is formed on a Si substrate, wherein the SiGe layer is formed by the above-described method of forming a SiGe layer of the present invention.

In the method of forming the semiconductor substrate and the SiGe layer, the SiGe layer is formed on the surface of the Si substrate on which the groove is formed, so that the dislocation generated during the formation of the SiGe layer moves and reaches the groove. , To escape on the groove side and disappear,
The dislocation density in the SiGe layer can be reduced. Further, since a groove may be formed in advance on the surface of the Si substrate and the SiGe layer may be uniformly formed on the surface, an advanced and low-speed film forming technique such as selective growth as in the related art is not required.

In the method of forming a semiconductor substrate and a SiGe layer according to the present invention, it is preferable to perform a heat treatment during or after the step of epitaxially growing. That is, in the method of forming the semiconductor substrate and the SiGe layer, heat treatment is performed during or after the step of epitaxial growth, so that the heat treatment can positively cause the dislocations to thermally move and reach the grooves, thereby further reducing threading dislocations. In addition, even when the distance between the grooves is large (that is, when the area of the flat region of the SiGe layer is large), the dislocation can reach the grooves.

[0011] In the semiconductor substrate of the present invention, the Si substrate may be:
It is preferable that the crystal surface is a {001} plane, and the groove has a V-shaped cross section in which the side surface is a {111} plane.
In the method of forming a SiGe layer according to the present invention, it is preferable that the Si substrate is a {001} plane of a crystal surface, and the groove is formed in a V-shaped cross section in which a side surface is a {111} plane. .

In the method of forming the semiconductor substrate and the SiGe layer, if the Si substrate has a {001} plane of the crystal surface and the groove has a V-shaped cross section having a {111} side surface, Since the {111} plane has a lower deposition rate than the {001} plane, it is possible to prevent the grooves from being filled with the SiGe layer after the SiGe layer is formed. Also, the SiGe layer is
Since smooth epitaxial growth is performed on the {111} plane, abnormal growth such as projections does not occur. Further, the V-shaped groove can be formed by controlling the shape such as the width thereof relatively easily and with high precision.

The method for forming a SiGe layer according to the present invention is a method for forming a SiGe layer on a Si substrate, comprising the steps of epitaxially growing the SiGe layer on the Si substrate, and forming the SiGe layer after the epitaxial growth step. The method includes a step of forming a groove and a step of performing a heat treatment after the step of forming the groove. Also,
The semiconductor substrate of the present invention is a semiconductor substrate in which a SiGe layer is formed on a Si substrate, wherein the SiGe layer is formed by the above-described method of forming a SiGe layer of the present invention.

In these methods of forming a semiconductor substrate and a SiGe layer, since a SiGe layer is epitaxially grown on a Si substrate, a groove is formed in the SiGe layer, and then a heat treatment is performed. The dislocations can be moved to reach the grooves, dislocations can be eliminated on the side surfaces of the grooves, and the dislocation density in the SiGe layer can be reduced.

In the semiconductor substrate according to the present invention, it is preferable that the SiGe layer has a gradient composition region in which the Ge composition ratio gradually increases toward the surface at least in part. In the method of forming a SiGe layer according to the present invention, it is preferable that a gradient composition region in which a Ge composition ratio is gradually increased toward a surface is formed in at least a part of the SiGe layer.

In the method of forming the semiconductor substrate and the SiGe layer, at least a part of the SiGe layer is formed as a gradient composition region in which the Ge composition ratio is gradually increased toward the surface. , The dislocation density can be suppressed particularly on the surface side in the SiGe layer, and the dislocations can easily extend in the direction along the SiGe layer, so that the dislocations can be eliminated more on the groove side surfaces.

In the semiconductor substrate of the present invention, it is preferable that the groove is adjacent to a device region where a semiconductor element is formed. In the method of forming a SiGe layer according to the present invention, it is preferable that the groove is formed adjacent to a device region where a semiconductor element is formed.

In the method of forming the semiconductor substrate and the SiGe layer, since the groove is provided at a position adjacent to the device region where the semiconductor element is formed, the SiGe in the device region is formed.
Dislocations generated in the layer can be efficiently eliminated on the groove side surfaces.

In the semiconductor substrate according to the present invention, it is preferable that the groove is provided at a cut-off portion for cutting and separating a semiconductor chip having the device region into a chip size. In the method of forming a SiGe layer according to the present invention, it is preferable that the groove is formed in a cut-off portion for cutting and separating a semiconductor chip having the device region into a chip size.

In the method of forming the semiconductor substrate and the SiGe layer, since the groove is arranged at a cut-off portion for cutting and separating the semiconductor chip having the device region into a chip size, the groove can be formed without any trouble in the device region. It can be formed, so that there is no waste in device fabrication and no restrictions are imposed on circuit design.

In the semiconductor substrate of the present invention, it is preferable that the grooves are formed in a lattice shape. In addition, the SiG of the present invention
In the method for forming the e-layer, the grooves are preferably formed in a lattice shape.

In the method of forming the semiconductor substrate and the SiGe layer, since the grooves are formed in a lattice, a square device region can be obtained, and no waste occurs in device fabrication.

The semiconductor substrate according to the present invention is characterized in that the semiconductor substrate according to the present invention has a strained Si layer disposed directly or via another SiGe layer on the SiGe layer. Alternatively, the method of forming a strained Si layer of the present invention is a method of forming a strained Si layer on a Si substrate via a SiGe layer, wherein the SiGe layer on the Si substrate is formed by forming the SiGe layer of the present invention. The film is formed by a method.

In the above-mentioned semiconductor substrate, the semiconductor substrate of the present invention comprises a strained Si layer disposed directly or via another SiGe layer on the SiGe layer. Since the upper SiGe layer is formed by the above-described method for forming a SiGe layer of the present invention, it is suitable as a strained Si layer or a semiconductor substrate for an integrated circuit using, for example, a MOSFET having a strained Si layer as a channel region. is there.

The field-effect transistor of the present invention has a
A field effect transistor having a channel region in a strained Si layer on a Ge layer, wherein the strained Si layer of the semiconductor substrate according to the present invention has the channel region. Further, the method of manufacturing a field effect transistor according to the present invention provides a method for manufacturing a strained S epitaxially grown on a SiGe layer.
A method for manufacturing a field-effect transistor in which a channel region is formed in an i-layer, wherein the strained Si layer is formed by the method for forming a strained Si layer according to the present invention. Further, the field-effect transistor of the present invention is formed of SiG
a field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on the e layer,
According to the method for forming a strained Si layer of the present invention, the strained Si
It is characterized in that a layer is formed.

The strained Si layer of the semiconductor substrate of the present invention has the channel region in the strained Si layer. In the method of manufacturing a field effect transistor, the strained Si layer is formed by the method of forming a strained Si layer of the present invention. Further, in the field effect transistor, since the strained Si layer is formed by the method for forming a strained Si layer of the present invention, a high quality field effect transistor can be obtained with a high yield by a high quality strained Si layer. Can be.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment according to the present invention will be described with reference to FIGS.

FIGS. 1 and 2 show the cross-sectional structures of a semiconductor wafer (semiconductor substrate) W0 and a semiconductor wafer (semiconductor substrate) W provided with a strained Si layer according to the present invention. The structure of a semiconductor wafer having a layer will be described together with its manufacturing process. First, as shown in FIG. 1A, the surface of the Si substrate 1 is patterned and etched with a mask or the like to form a lattice. A groove 1a is formed.

As shown in FIG. 3, the groove 1a is adjacent to a device region 1b in which a semiconductor element is formed, and is provided with a cut-off portion (so-called scribe) for cutting and separating a semiconductor chip having the device region 1b into a chip size. It is a line and is formed in a hatched area in FIG. That is, groove 1
The width of a is determined by, for example, the blade width of the dicing saw. The width of the device region 1b is determined in consideration of the chip size and an appropriate width at which the effects of the present invention can be obtained. When performing heat treatment, it is determined in consideration of the effect.

The surface of the Si substrate 1 is a {001} plane of the crystal surface, and the groove 1a is formed in a V-shaped cross section in which the side surface is a {111} plane. The etching at this time is anisotropic etching using a KOH / IPA / H ₂ O-based etchant at a liquid temperature of 80 ° C. for 75 minutes, for example.

The width of the groove 1a is 0.3 μm or more and 2 m or more.
m or less. The reason for this is that the strain Si
The thickness of the SiGe layer for forming the layer is 0.3 to 3 μm
This is because a groove having a width of 0.3 μm or more is preferable, and a width of 2 mm or less is preferable because a cutting margin at the time of device cutting should not be wasted. Groove 1
The depth a is preferably 0.3 μm or more and 200 μm or less. The reason is that SiGe for forming the strained Si layer is used.
Since the thickness of the layer is in the above range, the depth is 0.3 μm.
The above grooves are preferable, and if the groove depth is too deep, cracks tend to occur along the grooves during the device manufacturing process,
This is because the depth is preferably 200 μm or less.

Next, as shown in FIG. 1 (b), FIG. 2 and FIG. 4, on the Si substrate 1 on which the groove 1a is formed, the Ge composition ratio x is 0 to 0. The first SiGe layer 2, which is a gradient composition layer that gradually increases in the film-forming direction (toward the surface) up to 3, is epitaxially grown by a low pressure CVD method. Note that the film formation by the low-pressure CVD method uses H ₂ as a carrier gas and SiH ₄ and GeH ₄ as a source gas.

Next, on the first SiGe layer 2, the first S
At the final Ge composition ratio (0.3) of the iGe layer 2, the second SiGe layer 3 which is a constant composition layer and a relaxation layer is epitaxially grown. These first SiGe layer 2 and second SGe
The iGe layer 3 functions as a SiGe layer SG for forming a strained Si layer. Thus, the first S of the gradient composition layer
After the iGe layer 2 is formed, the second SiGe
Since the layer 3 is formed, the generation and growth of dislocations in the second SiGe layer 3 can be suppressed, and the final second SiG
The dislocation density on the surface of the e-layer 3 can be reduced.

Next, the wafer after the film formation is subjected to heat treatment (annealing) in a heat treatment furnace to produce a semiconductor wafer W0. At this time, the dislocation DL in the SiGe layer SG
As shown in FIG. 5, due to the thermal motion of the dislocations, reaches the groove 1a and disappears from the side surface of the groove 1a. As a result, the defect density of the device region 1b is reduced.

The conditions for the heat treatment temperature and the heat treatment time for the heat treatment are set, for example, at a Ge composition ratio of 0.1% for the SiGe layer.
In the case of 2, assuming that the thermal motion distance of the dislocation is 30 mm,
It looks like this: Therefore, when the chip size of the LSI chip is 30 mm on a side, annealing is performed using the following condition setting values as a guide. For chip sizes other than 30 mm, the heat treatment temperature and heat treatment time are calculated using the following condition setting values as a guide. Work such as decision is required.

<Annealing conditions> Heat treatment temperature T (° C.), thermal motion velocity of dislocation V (m / s), heat treatment time t (min) · 780 ° C., 2.50 × 10 ⁻⁶ m / s, 200 min · 800 3.80 × 10 ⁻⁶ m / s, 130 min., 900 ° C., 2.70 × 10 ⁻⁵ m / s, 19 min., 1000 ° C., 1.40 × 10 ⁻⁴ m / s, 3.6 min.

During the epitaxial growth of the first SiGe layer 2 and the second SiGe layer 3, the generated dislocations move and reach the groove 1a and disappear and disappear on the side surface of the groove. Therefore, many dislocations can be eliminated in the groove 1a by the motion of the dislocation at the time of film formation and the thermal motion by the heat treatment after the film formation.

Further, the Si substrate 1 has a crystal surface of $ 00
Since the groove 1a has a V-shaped cross section in which the side surface is a {111} plane, the groove 1a has a {11} plane with respect to the {001} plane.
Since the 1｝ plane has a low film formation rate, it is possible to prevent the groove 1a from being filled with the SiGe layer after the SiGe layer SG is formed. In addition, since the SiGe layer SG performs smooth epitaxial growth on the {111} plane, abnormal growth such as projections does not occur. Further, the V-shaped groove can be formed by controlling the shape such as the width thereof relatively easily and with high precision.

Thereafter, the semiconductor wafer W0
Is epitaxially grown on the second SiGe layer 3 to form a strained Si layer 4, and a semiconductor wafer W having the strained Si layer is manufactured. The thickness of each layer is, for example, 1.5 μm for the first SiGe layer 2, 0.75 μm for the second SiGe layer 3, and 15 to 22 nm for the strained Si layer 4.

As described above, in this embodiment, since the SiGe layer SG is formed on the surface of the Si substrate 1 on which the groove 1a is formed, the dislocation DL generated during the formation of the SiGe layer SG moves to move into the groove 1a. When it reaches, it disappears and disappears on the side surface of the groove 1a, so that the dislocation density in the SiGe film can be reduced. Further, since a groove 1a is formed in advance on the surface of the Si substrate 1 and the SiGe layer SG is formed uniformly on this surface, an advanced and low-speed film forming technique such as selective growth as in the prior art is unnecessary. Becomes

Further, since the heat treatment is performed after the step of epitaxial growth, the dislocation DL can be positively thermally moved by the heat treatment to reach the groove 1a, so that the dislocation density can be further reduced, and the dislocation density can be further reduced. Even when the distance from the groove 1a is large (that is, when the area of the flat region of the SiGe layer SG is large), the dislocation DL can reach the groove 1a.

Further, the first SiG which is a gradient composition region
Since the Ge composition ratio in the e layer 2 gradually increases, the density of dislocations in the second SiGe layer 3 can be suppressed, and the dislocations DL easily move in the direction along the first SiGe layer 2. Thus, the dislocation DL can be eliminated on the side surface of the groove 1a. In addition, if the groove 1a is arranged in a cut-off portion for cutting and separating a semiconductor chip having the device region 1b into a chip size, the groove 1a can be formed without any trouble in the device region 1b, which is wasteful in device fabrication. And no restrictions are imposed on the circuit design.

Next, a field effect transistor (MO) using a semiconductor wafer W having the above-mentioned strained Si layer of the present invention.
SFET) will be described together with its manufacturing process with reference to FIG.

FIG. 6 shows a schematic structure of a field-effect transistor of the present invention. In order to manufacture this field-effect transistor, a strained Si layer formed in the above-described manufacturing process was provided. A gate oxide film 5 of SiO ₂ and a gate polysilicon film 6 are sequentially deposited on the strained Si layer 4 on the surface of the semiconductor wafer W. Then, a gate electrode (not shown) is formed by patterning on the gate polysilicon film 6 on a portion to be a channel region.

Next, the gate oxide film 5 is also patterned to remove portions other than those below the gate electrode. Further, an n-type or p-type source region S and a drain region D are formed in the strained Si layer 4 and the second SiGe layer 3 in a self-aligned manner by ion implantation using the gate electrode as a mask. Thereafter, a source electrode and a drain electrode (not shown) are formed on the source region S and the drain region D, respectively.
n-type or p-type MOSF in which i-layer 4 becomes a channel region
An ET is manufactured.

In the MOSFET thus manufactured,
Since a channel region is formed in the strained Si layer 4 of the semiconductor wafer W having the strained Si layer manufactured by the above-described manufacturing method,
MOSFE with excellent operation characteristics due to high quality strained Si layer 4
T can be obtained with a high yield.

Next, a second embodiment according to the present invention will be described with reference to FIG.
This will be described with reference to FIG.

The difference between the second embodiment and the first embodiment is that, in the first embodiment, after the grooves 1a are formed on the surface of the Si substrate 1, the SiGe layer SG is formed, and the heat treatment is further performed. On the other hand, in the second embodiment, as shown in FIG. 7, no groove is formed in the Si substrate 1 and the groove G is formed in the SiGe layer SG.
Is formed.

That is, in the present embodiment, FIG.
As shown in FIG. 2, a SiGe layer SG in which a first SiGe layer 2 and a second SiGe layer 3 are successively formed on a flat Si substrate 1 is formed, and the surface of the SiGe layer SG is patterned by using a mask. As shown in FIG. 7B, a groove G is formed in a region to be a scribe line by etching. Further, the wafer in this state is heat-treated in a heat treatment furnace, and after the heat treatment, Si is epitaxially grown on the second SiGe layer 3 to form a strained Si layer, and a semiconductor wafer having the strained Si layer is manufactured.

In the present embodiment, the SiGe
After the layer SG is epitaxially grown, a groove G is formed in the SiGe layer SG, and then a heat treatment is performed. Can be eliminated by S
The dislocation density in the iGe layer can be reduced. Also,
In the present embodiment, as in the first embodiment, since the grooves are formed by etching, it is not necessary to use an advanced and slow growth technique such as selective growth. In the present embodiment, the effect of reducing the dislocation DL can be obtained even if the groove does not reach the surface of the Si substrate 1. However, it is preferable to form the deep groove G that reaches the surface of the Si substrate 1. A high dislocation reduction effect can be obtained.

The technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, in each of the above embodiments, the groove is formed by etching, but the groove may be formed by mechanical processing using a dicing technique or the like. Further, the heat treatment for thermally moving the dislocations is performed after the epitaxial growth step, but the heat treatment may be performed during the epitaxial growth step. Further, the present invention includes a semiconductor wafer further provided with a SiGe layer on the strained Si layer of the semiconductor wafer W provided with the strained Si layer of each of the above embodiments. Also, the second SiGe
Although the strained Si layer is formed directly on the layer, another SiGe layer may be formed on the second SiGe layer, and the strained Si layer may be epitaxially grown via the SiGe layer.

In each of the above embodiments, the MOSFET
A semiconductor wafer having a SiGe layer was manufactured as a substrate for use, but it may be a substrate applied to other uses.
For example, the method for forming a SiGe layer and the semiconductor substrate of the present invention may be applied to a substrate for a solar cell. That is, on the Si substrate of each of the above-described embodiments, the S composition of the gradient composition layer in which the Ge composition ratio is gradually increased so as to be 100% Ge at the outermost surface.
A solar cell substrate may be manufactured by forming an iGe layer and further forming GaAs (gallium arsenide) thereon. In this case, a high-performance solar cell substrate having a low dislocation density can be obtained.

[0053]

According to the present invention, the following effects can be obtained.
According to the method for forming a semiconductor substrate and a SiGe layer of the present invention, since a SiGe layer is formed on the surface of a Si substrate having a groove formed thereon, dislocations reach the groove and pass through, and disappear.
The dislocation density in the iGe layer can be reduced, and the defect density in the device region can be reduced. In addition, S
Since a groove may be formed on the surface of the i-substrate and the SiGe layer may be uniformly formed on the surface, an advanced and low-speed film forming technique such as selective growth as in the related art is not required. Therefore,
Since a relatively easy film-forming technique is used, restrictions on the process can be reduced, and dislocations can be eliminated by grooves formed outside the device region, so that restrictions on device design can be reduced.

According to the method of forming a semiconductor substrate and a SiGe layer of the present invention, a groove is formed in the SiGe layer after the SiGe layer is epitaxially grown on the Si substrate, and then a heat treatment is performed. The dislocations can be thermally moved to reach the grooves, and the dislocations can be eliminated by the grooves, and the dislocation density in the SiGe layer can be reduced.

According to the semiconductor substrate having the strained Si layer and the method of forming the strained Si layer of the present invention, the Si substrate having the SiGe layer is the semiconductor substrate of the present invention, and the SiGe layer on the Si substrate is provided. Is formed by the above-described method for forming a SiGe layer of the present invention, so that Si
A Si layer can be formed on the Ge layer, and a high-quality strained Si layer can be formed.

According to the field effect transistor and the method of manufacturing the field effect transistor of the present invention, a channel region is formed in the strained Si layer of the semiconductor substrate of the present invention, and the strained Si layer of the present invention is formed. Since the strained Si layer serving as the channel region is formed by the formation method described above, a high-performance MOSFET can be obtained with a high yield by using a high-quality strained Si layer.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a semiconductor substrate according to a first embodiment of the present invention in the order of manufacturing steps.

FIG. 2 shows strained Si according to the first embodiment of the present invention.
FIG. 3 is an enlarged sectional view of a main part showing a semiconductor substrate provided with layers.

FIG. 3 shows strained Si according to the first embodiment of the present invention.
FIG. 3 is a plan view of a main part showing a semiconductor substrate provided with layers.

FIG. 4 shows strained Si according to the first embodiment of the present invention.
4 is a graph showing a Ge composition ratio with respect to a film thickness of a semiconductor substrate having a layer.

FIG. 5 is a conceptual diagram in a main part cross section for explaining dislocations in the first embodiment according to the present invention.

FIG. 6 shows a MOSF according to the first embodiment of the present invention.
It is a schematic sectional drawing which shows ET.

FIG. 7 is a cross-sectional view showing a semiconductor substrate according to a second embodiment of the present invention in the order of manufacturing steps.

FIG. 8 is a conceptual diagram in a main part cross section for explaining dislocation in a second embodiment according to the present invention.

[Explanation of symbols]

1 Si substrate 1a, G the grooves 1b device region 2 first SiGe layer 3 and the second SiGe layer 4 strained Si layer 5 SiO ₂ gate oxide film 6 gate polysilicon film S source region D drain region DL dislocation SG SiGe layer W strain Semiconductor wafer with semiconductor layer (semiconductor substrate) W0 Semiconductor wafer (semiconductor substrate)

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kazuki Mizushima 1-297 Kitabukuro-cho, Saitama-shi, Saitama F-term in Mitsubishi Materials Research Institute 5F052 AA11 AA17 DA01 FA13 JA01 KA02 KA05 5F140 AA00 AA01 AC28 BA01 BA05 BA17 BA20 BC12 BC19 BF01 BF04 BK22

Claims (21)

[Claims] 1. A semiconductor substrate comprising: a Si substrate; and a SiGe layer on the Si substrate, wherein the Si substrate has a groove on a surface. 2. The semiconductor substrate according to claim 1, wherein the Si substrate has a {001} plane of a crystal surface, and the groove has a V-shaped cross section having a side surface of a {111} plane. A semiconductor substrate characterized by the above-mentioned. 3. The semiconductor substrate according to claim 1, wherein the groove is adjacent to a device region where a semiconductor element is formed. 4. The semiconductor substrate according to claim 3, wherein the groove is provided at a cut-off portion for cutting and separating a semiconductor chip having the device region into a chip size. . 5. The semiconductor substrate according to claim 1, wherein said grooves are formed in a lattice shape. 6. The semiconductor substrate according to claim 1, wherein the SiGe layer has, at least in part, a gradient composition region in which a Ge composition ratio gradually increases toward a surface. Semiconductor substrate. 7. A semiconductor substrate according to claim 1, further comprising a strained Si layer disposed directly or via another SiGe layer on the SiGe layer of the semiconductor substrate according to claim 1. . 8. A field effect transistor having a channel region in a strained Si layer on a SiGe layer, wherein the field region has the channel region in the strained Si layer of the semiconductor substrate according to claim 7. Effect type transistor. 9. A method for forming a SiGe layer on a Si substrate, comprising: forming a groove on the surface of the Si substrate; and epitaxially growing the SiGe layer on the Si substrate. Characteristic method of forming a SiGe layer. 10. The method for forming a SiGe layer according to claim 9, wherein a heat treatment is performed during or after the step of epitaxially growing. 11. The method for forming a SiGe layer according to claim 9, wherein the Si substrate has a {001} plane of a crystal surface, and the trench has a {111} plane. A method of forming a SiGe layer, wherein the SiGe layer is formed in a V-shaped cross section. 12. A method of forming a SiGe layer on a Si substrate, comprising: epitaxially growing the SiGe layer on the Si substrate; forming a groove in the SiGe layer after the epitaxial growing step; Performing a heat treatment after the step of forming the groove. 13. The method for forming a SiGe layer according to claim 9, wherein the groove is formed adjacent to a device region in which a semiconductor element is formed. Method. 14. The SiGe layer forming method according to claim 13, wherein the groove is formed in a cut-off portion for cutting and separating a semiconductor chip having the device region into a chip size. The method of forming the layer. 15. The method of forming a SiGe layer according to claim 9, wherein the grooves are formed in a lattice shape.
Method for forming iGe layer. 16. The method for forming a SiGe layer according to claim 9, wherein a gradient composition region in which a Ge composition ratio is gradually increased toward a surface is formed in at least a part of the SiGe layer. A method for forming a SiGe layer, comprising: 17. A method for forming a strained Si layer on a Si substrate via a SiGe layer, wherein the SiGe layer on the Si substrate is formed by the method according to claim 9. A method for forming a strained Si layer, characterized in that the film is formed by: 18. A method for manufacturing a field-effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer, wherein the strained Si layer is formed by the method for forming a strained Si layer according to claim 17. Forming a field effect transistor. 19. A semiconductor substrate having a SiGe layer formed on a Si substrate, wherein the SiGe layer is formed by the method for forming a SiGe layer according to claim 9. Description: Semiconductor substrate. 20. A semiconductor substrate having a strained Si layer formed on a Si substrate via a SiGe layer, wherein the strained Si layer is formed by the strained Si layer forming method according to claim 17. A semiconductor substrate characterized by the above-mentioned. 21. A field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer, wherein the strained Si layer is formed by the method for forming a strained Si layer according to claim 18. A field-effect transistor.