JP4345249B2

JP4345249B2 - Semiconductor substrate, field effect transistor, and manufacturing method thereof

Info

Publication number: JP4345249B2
Application number: JP2001238172A
Authority: JP
Inventors: 一郎塩野; 健志山口; 一樹水嶋
Original assignee: Sumco Corp
Current assignee: Sumco Corp
Priority date: 2001-08-06
Filing date: 2001-08-06
Publication date: 2009-10-14
Anticipated expiration: 2021-08-06
Also published as: JP2003051444A

Description

【０００１】
【発明の属する技術分野】
本発明は、高速ＭＯＳＦＥＴ等に用いられる半導体基板及び電界効果型トランジスタ並びにこれらの製造方法に関する。
【０００２】
【従来の技術】
近年、Ｓｉ（シリコン）基板上にＳｉＧｅ（シリコン・ゲルマニウム）層を介してエピタキシャル成長した歪みＳｉ層をチャネル領域に用いた高速のＭＯＳＦＥＴ、ＭＯＤＦＥＴ、ＨＥＭＴが提案されている。この歪みＳｉ−ＦＥＴでは、Ｓｉに比べて格子定数の大きいＳｉＧｅによりＳｉ層に引っ張り歪みが生じ、そのためＳｉのバンド構造が変化して縮退が解けてキャリア移動度が高まる。したがって、この歪みＳｉ層をチャネル領域として用いることにより通常の１．３〜８倍程度の高速化が可能になるものである。また、プロセスとしてＣＺ法による通常のＳｉ基板を基板として使用でき、従来のＣＭＯＳ工程で高速ＣＭＯＳを実現可能にするものである。
【０００３】
しかしながら、ＦＥＴのチャネル領域として要望される上記歪みＳｉ層をエピタキシャル成長するには、Ｓｉ基板上に良質なＳｉＧｅ層をエピタキシャル成長する必要があるが、ＳｉとＳｉＧｅとの格子定数の違いから、転位等により結晶性に問題があった。このために、従来、以下のような種々の提案が行われていた。
【０００４】
例えば、ＳｉＧｅのＧｅ組成比を一定の緩い傾斜で変化させたバッファ層を用いる方法、Ｇｅ（ゲルマニウム）組成比をステップ状（階段状）に変化させたバッファ層を用いる方法、Ｇｅ組成比を超格子状に変化させたバッファ層を用いる方法及びＳｉのオフカットウェーハを用いてＧｅ組成比を一定の傾斜で変化させたバッファ層を用いる方法等が提案されている（U.S.Patent 5,442,205、U.S.Patent 5,221,413、PCT WO98/00857、特開平6-252046号公報等）。
【０００５】
【発明が解決しようとする課題】
しかしながら、上記従来の技術では、以下のような課題が残されている。
すなわち、上記従来の技術を用いて成膜されたＳｉＧｅ層は、貫通転位密度や表面ラフネスがデバイス及び製造プロセスとして要望されるレベルには及ばない状態であった。
例えば、Ｇｅ組成比を傾斜させたバッファ層を用いる場合では、貫通転位密度を比較的低くすることができるが、表面ラフネスが悪化してしまう不都合があり、逆にＧｅ組成比を階段状にしたバッファ層を用いる場合では、表面ラフネスを比較的少なくすることができるが、貫通転位密度が大きくなってしまう不都合があった。また、オフカットウェーハを用いる場合では、転位が成膜方向ではなく横に抜け易くなるが、まだ十分な低転位化を図ることができていない。表面ラフネスについても、近年のＬＳＩ等におけるフォトリソグラフィ工程に要求されるレベルにはまだ至っていない。
【０００６】
本発明は、前述の課題に鑑みてなされたもので、貫通転位密度を低くかつ表面ラフネスも実用レベルまで小さくすることができる半導体基板及び電界効果型トランジスタ並びにこれらの製造方法を提供することを目的とする。
【０００７】
【課題を解決するための手段】
本発明は、前記課題を解決するために以下の構成を採用した。
すなわち、本発明の半導体基板は、Ｓｉ基板と、
該Ｓｉ基板上の第１のＳｉＧｅ層と、
該第１のＳｉＧｅ層上に直接配された第２のＳｉＧｅ層とを備え、
前記第１のＳｉＧｅ層は、膜厚の増加により転位を発生して格子緩和が生ずる膜厚である臨界膜厚の２倍より薄い膜厚であり、
前記第２のＳｉＧｅ層は、そのＧｅ組成比が前記第１のＳｉＧｅ層との接触面で第１のＳｉＧｅ層におけるＧｅ組成比の層中の最大値より低く０とされ、層全体がＧｅ組成比が０から表面に向けて漸次増加した傾斜組成層であることを特徴とする。
また、本発明の半導体基板の製造方法は、Ｓｉ基板上にＳｉＧｅ層をエピタキシャル成長させた半導体基板の製造方法であって、
前記Ｓｉ基板上に、第１のＳｉＧｅ層をエピタキシャル成長する第１の層形成工程と、
前記第１のＳｉＧｅ層上に直接第２のＳｉＧｅ層をエピタキシャル成長する第２の層形成工程とを有し、
前記第１の層形成工程は、膜厚の増加により転位を発生して格子緩和が生ずる膜厚である臨界膜厚の２倍より薄く前記第１のＳｉＧｅ層の膜厚を設定し、
前記第２の層形成工程は、前記第２のＳｉＧｅ層のＧｅ組成比を前記第１のＳｉＧｅ層との接触面で第１のＳｉＧｅ層におけるＧｅ組成比の層中の最大値より低く０とされ、かつ、層全体がＧｅ組成比が０から表面に向けて漸次増加した傾斜組成層を形成することを特徴とする。
また本発明の前記第２のＳｉＧｅ層は、層全体がＧｅ組成比が０から０．３まで表面に向けて漸次増加した傾斜組成層であることができる。
すなわち、本発明の半導体基板は、Ｓｉ基板と、該Ｓｉ基板上の第１のＳｉＧｅ層と、該第１のＳｉＧｅ層上に直接又はＳｉ層を介して配された第２のＳｉＧｅ層とを備え、前記第１のＳｉＧｅ層は、膜厚の増加により転位を発生して格子緩和が生ずる膜厚である臨界膜厚の２倍より薄い膜厚であり、前記第２のＳｉＧｅ層は、そのＧｅ組成比が少なくとも前記第１のＳｉＧｅ層あるいは前記Ｓｉ層との接触面で第１のＳｉＧｅ層におけるＧｅ組成比の層中の最大値より低く、かつ、少なくとも一部にＧｅ組成比が表面に向けて漸次増加した傾斜組成領域を有することを特徴とする。
また、本発明の半導体基板の製造方法は、Ｓｉ基板上にＳｉＧｅ層をエピタキシャル成長させた半導体基板の製造方法であって、前記Ｓｉ基板上に、第１のＳｉＧｅ層をエピタキシャル成長する第１の層形成工程と、前記第１のＳｉＧｅ層上に直接又はエピタキシャル成長したＳｉ層を介して第２のＳｉＧｅ層をエピタキシャル成長する第２の層形成工程とを有し、前記第１の層形成工程は、膜厚の増加により転位を発生して格子緩和が生ずる膜厚である臨界膜厚の２倍より薄く前記第１のＳｉＧｅ層の膜厚を設定し、前記第２の層形成工程は、前記第２のＳｉＧｅ層のＧｅ組成比を少なくとも前記第１のＳｉＧｅ層あるいは前記Ｓｉとの接触面で第１のＳｉＧｅ層におけるＧｅ組成比の層中の最大値より低く、かつ、少なくとも一部にＧｅ組成比が表面に向けて漸次増加した傾斜組成領域を形成することを特徴とする。
また、本発明の半導体基板は、Ｓｉ基板上にＳｉＧｅ層が形成された半導体基板であって、上記本発明の半導体基板の製造方法により作製されたことを特徴とする。
【０００８】
これらの半導体基板及び半導体基板の製造方法では、膜厚の増加により転位を発生して格子緩和が生ずる膜厚である臨界膜厚の２倍より薄く第１のＳｉＧｅ層の膜厚を設定し、第２のＳｉＧｅ層のＧｅ組成比を少なくとも第１のＳｉＧｅ層あるいは前記Ｓｉ層との接触面で第１のＳｉＧｅ層におけるＧｅ組成比の層中の最大値より低く、かつ、第２のＳｉＧｅ層は少なくとも一部にＧｅ組成比が表面に向けて漸次増加した傾斜組成領域を有するので、Ｓｉ基板と第１のＳｉＧｅ層との界面及び第１のＳｉＧｅ層と第２のＳｉＧｅ層との界面付近に効率的に転位を集中させることができ、第２のＳｉＧｅ層表面の貫通転位密度及び表面ラフネスを低減することができる。
【０００９】
すなわち、第１のＳｉＧｅ層が臨界膜厚の２倍より薄く成膜されるため、第１のＳｉＧｅ層成膜中では膜厚に応じて歪みエネルギーが大きくなるが転位はほとんど生成しない。次に、第２のＳｉＧｅ層のエピタキシャル成長を始めると、すでに第１のＳｉＧｅ層に歪みエネルギーが蓄積されているため、第２のＳｉＧｅ層の膜厚が薄い段階で、転位の生成と成長が、第１のＳｉＧｅ層両側の界面及び第２のＳｉＧｅ層内の第１のＳｉＧｅ層側からはじまり、第１のＳｉＧｅ層及び第２のＳｉＧｅ層の格子緩和が始まる。このとき、第２のＳｉＧｅ層のＧｅ組成比が第１のＳｉＧｅ層あるいは前記Ｓｉ層との接触面で第１のＳｉＧｅ層におけるＧｅ組成比の層中の最大値より低いため、転位は、第１のＳｉＧｅ層両側の界面に沿って集中し生成し、第１のＳｉＧｅ層両側の界面における転位の生成が、第２のＳｉＧｅ層の格子緩和を助け、第２のＳｉＧｅ層内での転位の生成や成長が抑制されると共に、第２のＳｉＧｅ層表面の表面ラフネスの悪化も抑制される。
【００１０】
さらに、第２のＳｉＧｅ層の傾斜組成領域では、転位が均等に生成し、転位同士の絡み合いが起こり、傾斜組成領域中の転位密度が減少するとともに、転位の成長が横方向に誘導されることにより表面領域における貫通転位密度が減少し、表面ラフネスの悪化も抑制される効果がある。
従来の第１のＳｉＧｅ層がない場合の傾斜組成領域では、傾斜組成領域の膜厚が所定の膜厚以上になり臨界膜厚を越えたときに転位の生成がはじまり、いったん転位密度の増加を経た後に、さらに傾斜組成祖領域を形成した場合に、前記の効果が得られる。すなわち、従来の構造では、傾斜組成領域の上側の一部の領域においてのみ前記の効果が得られる。
【００１１】
一方、第１のＳｉＧｅ層がある本発明の構造では、すでに第１のＳｉＧｅ層に歪みエネルギーが蓄積されているため、第２のＳｉＧｅ層の膜厚が薄い段階で、転位の生成が第２のＳｉＧｅ層内ではじまるため、第２のＳｉＧｅ層内の傾斜組成領域全体で前記の効果が得られ、第２のＳｉＧｅ層の表面領域における貫通転位密度が減少し、表面ラフネスの悪化も抑制される。
さらに、第１のＳｉＧｅ層は、Ｓｉ基板表面における水分や酸素成分あるいは炭素成分といった不純物を除去する層として機能し、Ｓｉ基板の表面汚染に起因した欠陥を抑制する効果がある。
【００１２】
なお、第１のＳｉＧｅ層の成膜中に転位が生成しはじめると、転位が多方向に成長し始めるため、転位の成長する方向を抑制することが困難になり、貫通転位や表面ラフネスを低減させることが難しい。そこで、第１のＳｉＧｅ層の膜厚は、臨界膜厚の２倍を越えない範囲で、実際に転位の生成や格子緩和が顕著にはじまる膜厚より薄い膜厚に設定する必要がある。同時に、第１のＳｉＧｅ層の膜厚は、実際に転位の生成や格子緩和が顕著にはじまる膜厚に近い膜厚であるほど効果的である。実際に転位の生成や格子緩和が顕著にはじまる膜厚は、成膜の温度条件等によって異なる。そこで、それぞれの成膜条件において、臨界膜厚の２倍を越えない範囲で、実際に転位の生成や格子緩和が顕著にはじまる膜厚付近で、本発明の効果が効果的に得られる膜厚を選べばよい。
【００１３】
また、本発明の半導体基板は、前記第１のＳｉＧｅ層が、Ｇｅ組成比ｘが一定であり、次の関係式；
ｔ_ｃ（ｎｍ）＝（１．９×１０^−３／ε（ｘ）^２）・ｌｎ（ｔ_ｃ／０．４）
ε（ｘ）＝（ａ_０＋０．２００３２６ｘ＋０．０２６１７４ｘ^２）／ａ_０）
ａ_０＝０．５４３ｎｍ（ａ_０は、Ｓｉの格子定数）
を満たす臨界膜厚ｔ_ｃの２倍未満の厚さである技術が採用される。
また、本発明の半導体基板の製造方法は、前記第１の層形成工程において、前記第１のＳｉＧｅ層のＧｅ組成比ｘが一定であり、第１のＳｉＧｅ層を、次の関係式；
ｔ_ｃ（ｎｍ）＝（１．９×１０^−３／ε（ｘ）^２）・ｌｎ（ｔ_ｃ／０．４）
ε（ｘ）＝（ａ_０＋０．２００３２６ｘ＋０．０２６１７４ｘ^２）／ａ_０）
ａ_０＝０．５４３ｎｍ（ａ_０は、Ｓｉの格子定数）
を満たす臨界膜厚ｔ_ｃの２倍未満の厚さにする技術が採用される。
また、本発明の半導体基板は、Ｓｉ基板上にＳｉＧｅ層が形成された半導体基板であって、上記本発明の半導体基板の製造方法により作製されたことを特徴とする。
【００１４】
これらの半導体基板及び半導体基板の製造方法では、第１のＳｉＧｅ層のＧｅ組成比が一定であるため、同じＧｅ組成比で実際に転位の生成や格子緩和が顕著にはじまる膜厚が最も薄くなり、最も薄い膜厚で本発明の効果が得られ、成膜に要する時間が短いという利点がある。また、これらの半導体基板及び半導体基板の製造方法では、第１のＳｉＧｅ層を上記関係式を満たす臨界膜厚（成膜温度にかかわらず、Ｇｅ組成比及び格子定数のみから算出される転位が発生して格子緩和が生ずる膜厚をいう）ｔ_ｃの２倍未満の厚さにすることにより、第１のＳｉＧｅ層の膜厚を容易に実際に転位の生成や格子緩和が顕著にはじまる膜厚内に設定することができる。
【００１５】
すなわち、上記実際に転位の生成や格子緩和が顕著にはじまる膜厚は成膜温度により変化するため、Ｇｅ組成比ｘ及び格子定数のみから理論的に求めた理想的な臨界膜厚ｔ_ｃの２倍未満とすれば、実際に転位の生成や格子緩和が顕著にはじまる膜厚より薄くなり、本発明の効果を得ることができる。なお、上記臨界膜厚は、平衡状態で成膜されることを前提にしているため、成膜温度にかかわらずＧｅ組成比及び格子定数のみで決定されるが、実際に転位の生成や格子緩和が顕著にはじまる膜厚は、平衡状態だけでなく低温成長などの非平衡状態で成膜された場合も含めたものであり、成膜温度に応じて決定される。
【００１６】
また、本発明の半導体基板は、前記第１のＳｉＧｅ層のＧｅ組成比ｘが０．０５以上かつ０．３以下であることが好ましい。
また、本発明の半導体基板の製造方法は、前記第１のＳｉＧｅ層のＧｅ組成比ｘが０．０５以上かつ０．３以下であることが好ましい。
また、本発明の半導体基板は、Ｓｉ基板上にＳｉＧｅ層が形成された半導体基板であって、上記本発明の半導体基板の製造方法により作製されたことを特徴とする。
【００１７】
これらの半導体基板及び半導体基板の製造方法では、前記第１のＳｉＧｅ層のＧｅ組成比ｘが０．０５以上かつ０．３以下であるため、実際に転位の生成や格子緩和が顕著にはじまる膜厚が薄すぎたり厚すぎたりすることがなく、適度な厚さの第１のＳｉＧｅ層で本発明の効果が効果的に得られる。
すなわち、第１のＳｉＧｅ層のＧｅ組成比ｘが０．０５より小さい場合は、実際に転位の生成や格子緩和が顕著にはじまる膜厚が厚くなりすぎるため、第１のＳｉＧｅ層の成膜に要する時間が長くなり、しかも、第１のＳｉＧｅ層の表面ラフネスが悪化してしまう。
【００１８】
一方、第１のＳｉＧｅ層のＧｅ組成比ｘが０．３より大きい場合は、ごく薄い膜厚で、実際に転位の生成や格子緩和が顕著にはじまってしまうため、第１のＳｉＧｅ層を制御性よく形成することが難しい。
また、前記第１のＳｉＧｅ層のＧｅ組成比ｘが０．０５以上かつ０．３以下であれば、実際に転位の生成や格子緩和が顕著にはじまる膜厚が適度な厚さとなり、第１のＳｉＧｅ層両側の界面に沿って転位が集中して生成し、第１のＳｉＧｅ層両側の界面における転位の生成が、第２のＳｉＧｅ層の格子緩和を助ける効果を効果的に得られる。
【００１９】
また、本発明の半導体基板は、前記第２のＳｉＧｅ層が前記第１のＳｉＧｅ層上に直接配され、かつ、層全体がＧｅ組成比が表面に向けて漸次増加して傾斜組成層である構造が採用される。
また、本発明の半導体基板の製造方法は、前記第２のＳｉＧｅ層が前記第１のＳｉＧｅ層上に直接配し、かつ、層全体がＧｅ組成比が表面に向けて漸次増加した傾斜組成層とする方法が採用される。
また、本発明の半導体基板は、Ｓｉ基板上にＳｉＧｅ層が形成された半導体基板であって、上記本発明の半導体基板の製造方法により作製されたことを特徴とする。
【００２０】
これらの半導体基板及び半導体基板の製造方法では、前記第２のＳｉＧｅ層が前記第１のＳｉＧｅ層上に直接配され、かつ、層全体がＧｅ組成比が表面に向けて漸次増加した傾斜組成層からなるため、本発明の効果を得るために必要な層が無駄なく配され、最も薄い膜厚で本発明の効果が得られ、成膜に要する時間が短いという利点がある。
【００２１】
本発明の半導体基板は、前記ＳｉＧｅ層上に直接又は他のＳｉＧｅ層を介して歪みＳｉ層をエピタキシャル成長することを特徴とする。
また、本発明の半導体基板の製造方法は、前記ＳｉＧｅ層上に直接又は他のＳｉＧｅ層を介して歪みＳｉ層をエピタキシャル成長することを特徴とする。
また、本発明の半導体基板は、Ｓｉ基板上にＳｉＧｅ層を介して歪みＳｉ層が形成された半導体基板であって、上記本発明の歪みＳｉ層を成長する半導体基板の製造方法により作製されたことを特徴とする。
【００２２】
これらの半導体基板及び半導体基板の製造方法では、前記ＳｉＧｅ層上に直接又は他のＳｉＧｅ層を介して歪みＳｉ層をエピタキシャル成長するので、欠陥が少なく、表面ラフネスの小さな良質な歪みＳｉ層が得られ、例えば歪みＳｉ層をチャネル領域とするＭＯＳＦＥＴ等を用いた集積回路用の半導体基板及びその製造方法として好適である。
【００２３】
本発明の電界効果型トランジスタは、ＳｉＧｅ層上の歪みＳｉ層にチャネル領域を有する電界効果型トランジスタであって、上記本発明の半導体基板の前記歪みＳｉ層に前記チャネル領域を有することを特徴とする。
また、本発明の電界効果型トランジスタの製造方法は、ＳｉＧｅ層上にエピタキシャル成長された歪みＳｉ層にチャネル領域が形成される電界効果型トランジスタの製造方法であって、上記本発明の半導体基板の製造方法により作製された半導体基板の前記歪みＳｉ層に前記チャネル領域を形成することを特徴とする。
また、本発明の電界効果型トランジスタは、ＳｉＧｅ層上にエピタキシャル成長された歪みＳｉ層にチャネル領域が形成される電界効果型トランジスタであって、上記本発明の電界効果型トランジスタの製造方法により作製されたことを特徴とする。
【００２４】
これらの電界効果型トランジスタ及び電界効果型トランジスタの製造方法では、上記本発明の半導体基板又は上記本発明の半導体基板の製造方法により作製された半導体基板の前記歪みＳｉ層に前記チャネル領域が形成されるので、良質な歪みＳｉ層により高特性な電界効果型トランジスタを高歩留まりで得ることができる。
【００２５】
【発明の実施の形態】
以下、本発明に係る第１実施形態を、図１から図３を参照しながら説明する。
【００２６】
図１は、本発明の半導体ウェーハ（半導体基板）Ｗの断面構造を示すものであり、この半導体ウェーハの構造をその製造プロセスと合わせて説明すると、まず、ＣＺ法等で引上成長して作製されたｐ型あるいはｎ型Ｓｉ基板１上に、図１及び図２に示すように、Ｇｅ組成比ｘが一定（例えばｘ＝０．１５）で上述した実際に転位の生成や格子緩和が顕著にはじまる膜厚よりも薄い厚さ（例えば３００ｎｍ）の第１のＳｉＧｅ層２を例えば減圧ＣＶＤ法によりエピタキシャル成長する。
【００２７】
この際、第１のＳｉＧｅ層２が実際に転位の生成や格子緩和が顕著にはじまる膜厚より薄く成膜されるため、第１のＳｉＧｅ層２成膜中では膜厚に応じて歪みエネルギーが大きくなるが転位や格子緩和はほとんど発生しない。
なお、第１のＳｉＧｅ層２の厚さは、次の関係式；
ｔ_ｃ（ｎｍ）＝（１．９×１０^−３／ε（ｘ）^２）・ｌｎ（ｔ_ｃ／０．４）
ε（ｘ）＝（ａ_０＋０．２００３２６ｘ＋０．０２６１７４ｘ^２）／ａ_０）
ａ_０＝０．５４３ｎｍ（ａ_０は、Ｓｉの格子定数）
を満たす臨界膜厚ｔ_ｃの２倍未満の厚さにする。
【００２８】
次に、第１のＳｉＧｅ層２上に第２のＳｉＧｅ層３をエピタキシャル成長する。この第２のＳｉＧｅ層３は、そのＧｅ組成比ｙが少なくとも第１のＳｉＧｅ層２との接触面で第１のＳｉＧｅ層２におけるＧｅ組成比ｘの層中の最大値より低く設定される。また、第２のＳｉＧｅ層３は、そのＧｅ組成比ｙが表面に向けて漸次増える傾斜組成層（例えば、Ｇｅ組成比ｙが０から０．３まで増加する層）（傾斜組成領域）であり、例えば１．１μｍの厚さまで成膜される。
【００２９】
第２のＳｉＧｅ層３のエピタキシャル成長を始めると、すでに第１のＳｉＧｅ層２に歪みエネルギーが蓄積されているため、第２のＳｉＧｅ層３の膜厚が薄い段階で、転位の生成と成長が、第１のＳｉＧｅ層２両側の界面及び第２のＳｉＧｅ層３内の第１のＳｉＧｅ層２側からはじまり、第１のＳｉＧｅ層２及び第２のＳｉＧｅ層３の格子緩和が始まる。このとき、第２のＳｉＧｅ層３のＧｅ組成比が第１のＳｉＧｅ層２の接触面で第１のＳｉＧｅ層２におけるＧｅ組成比の層中の最大値より低いため、転位は、第１のＳｉＧｅ層２両側の界面２ａ、２ｂに沿って集中し生成し、第１のＳｉＧｅ層２両側の界面２ａ、２ｂにおける転位の生成が、第２のＳｉＧｅ層３の格子緩和を助け、第２のＳｉＧｅ層３内での転位の生成や成長が抑制されると共に、第２のＳｉＧｅ層３表面の表面ラフネスの悪化も抑制される。
【００３０】
さらに、Ｇｅ組成比ｚが第２のＳｉＧｅ層３の最終的なＧｅ組成比と同じ（例えば、ｚが０．３）で一定組成比のＳｉＧｅ緩和層４を所定厚さ（例えば、０．４μｍ）だけエピタキシャル成長し、次に、該ＳｉＧｅ緩和層４上に単結晶Ｓｉをエピタキシャル成長して歪みＳｉ層５を所定厚さ（例えば、２０ｎｍ）だけ形成することにより、本実施形態の半導体ウェーハＷが作製される。
【００３１】
なお、上記減圧ＣＶＤ法による成膜は、キャリアガスとしてＨ_２を用い、ソースガスとしてＳｉＨ_４及びＧｅＨ_４を用いている。
【００３２】
このように本実施形態の半導体ウェーハＷでは、実際に転位の生成や格子緩和が顕著にはじまる膜厚より薄く第１のＳｉＧｅ層２の膜厚を設定し、第２のＳｉＧｅ層３のＧｅ組成比ｙを少なくとも第１のＳｉＧｅ層２との接触面で第１のＳｉＧｅ層２におけるＧｅ組成比ｘの層中の最大値より低くするので、Ｓｉ基板１と第１のＳｉＧｅ層２との界面２ａ及び第１のＳｉＧｅ層２と第２のＳｉＧｅ層３との界面２ｂに効率的に転位を集中させることができ、貫通転位密度及び表面ラフネスを低減すること等ができる。
【００３３】
また、第１のＳｉＧｅ層２のＧｅ組成比が一定であるため、同じＧｅ組成比で実際に転位の生成や格子緩和が顕著にはじまる膜厚が最も薄くなり、最も薄い膜厚で本発明の効果が得られ、成膜に要する時間が短いという利点がある。
また、第１のＳｉＧｅ層２を上記関係式を満たす臨界膜厚ｔ_ｃの２倍未満の厚さにすることにより、後述する実験結果に基づいて、第１のＳｉＧｅ層２の膜厚を容易に実際に転位の生成や格子緩和が顕著にはじまる膜厚内に設定することができる。
【００３４】
また、本実施形態では、第２のＳｉＧｅ層３がＧｅ組成比を漸次増加させた傾斜組成層（傾斜組成領域）とされることにより、転位が均等に生成し、転位同士の絡み合いが起こり、第２のＳｉＧｅ層３中の転位密度が減少するとともに、転位の成長が横方向に誘導されることにより表面領域における貫通転位密度が減少し、表面ラフネスの悪化も抑制される効果がある。
【００３５】
また、本実施形態では、第２のＳｉＧｅ層３の成膜前にすでに第１のＳｉＧｅ層２に歪みエネルギーが蓄積されているため、第２のＳｉＧｅ層３の膜厚が薄い段階で、転位の生成が第２のＳｉＧｅ層３内ではじまるため、第２のＳｉＧｅ層３内の傾斜組成領域全体で前記の効果が得られ、第２のＳｉＧｅ層３の表面領域における貫通転位密度が減少し、表面ラフネスの悪化も抑制される。
さらに、第１のＳｉＧｅ層２は、Ｓｉ基板１表面における水分や酸素成分あるいは炭素成分といった不純物を除去する層として機能し、Ｓｉ基板１の表面汚染に起因した欠陥を抑制する効果がある。
【００３６】
次に、本発明の上記半導体ウェーハＷを用いた電界効果型トランジスタ（ＭＯＳＦＥＴ）を、その製造プロセスと合わせて図３を参照して説明する。
【００３７】
図３は、本発明の電界効果型トランジスタの概略的な構造を示すものであって、この電界効果型トランジスタを製造するには、上記の製造工程で作製した半導体ウェーハＷ表面の歪みＳｉ層５上にＳｉＯ_２のゲート酸化膜６及びゲートポリシリコン膜７を順次堆積する。そして、チャネル領域となる部分上のゲートポリシリコン膜７上にゲート電極（図示略）をパターニングして形成する。
【００３８】
次に、ゲート酸化膜６もパターニングしてゲート電極下以外の部分を除去する。さらに、ゲート電極をマスクに用いたイオン注入により、歪みＳｉ層５及び緩和層４にｎ型あるいはｐ型のソース領域Ｓ及びドレイン領域Ｄを自己整合的に形成する。この後、ソース領域Ｓ及びドレイン領域Ｄ上にソース電極及びドレイン電極（図示略）をそれぞれ形成して、歪みＳｉ層５がチャネル領域となるｎ型あるいはｐ型ＭＯＳＦＥＴが製造される。
【００３９】
このように作製されたＭＯＳＦＥＴでは、上記製法で作製された半導体ウェーハＷ上の歪みＳｉ層５にチャネル領域が形成されるので、良質な歪みＳｉ層５により高特性なＭＯＳＦＥＴを高歩留まりで得ることができる。
【００４０】
次に、本発明に係る第２実施形態について、図４を参照して説明する。
【００４１】
第２実施形態と第１実施形態との異なる点は、第１実施形態における第１のＳｉＧｅ層２では、Ｇｅ組成比が一定に設定されているのに対し、第２実施形態では、図４に示すように、第１のＳｉＧｅ層１２のＧｅ組成比ｘをＳｉ基板１との接触面で層中の最大値とし、Ｇｅ組成比ｘを漸次減少させている点である。
【００４２】
すなわち、本実施形態では、第１のＳｉＧｅ層１２の形成工程において、成膜開始時ではＧｅ組成比ｘを０．３とし、その後徐々に減少させて最終的にはＧｅ組成比ｘをほぼ０まで変化させ、実際に転位の生成や格子緩和が顕著にはじまる膜厚より薄い所定厚さ（例えば、３５０ｎｍ）だけ成長させた傾斜組成層とする。
【００４３】
本実施形態では、第１のＳｉＧｅ層１２のＧｅ組成比ｘをＳｉ基板１との接触面で層中の最大値とすることにより、成膜時の歪みエネルギーがＳｉ基板１との界面側に集中することになり、第２のＳｉＧｅ層３成膜開始時に生じる格子緩和の際に、第２のＳｉＧｅ層３との界面よりもＳｉ基板１との界面に多くの転位を発生させることができる。これにより、第２のＳｉＧｅ層３表面側から離れた位置に転位を集中させることができ、第１実施形態と同様に、貫通転位や表面ラフネスを低減させることが可能になる。
【００４４】
次に、本発明に係る第３実施形態について、図５を参照して説明する。
【００４５】
第３実施形態と第２実施形態との異なる点は、第２実施形態の第２のＳｉＧｅ層１２が、Ｇｅ組成比を漸次減少させた傾斜組成層であるのに対し、第３実施形態では、図５に示すように、第１のＳｉＧｅ層２２の形成工程において、成膜開始時ではＧｅ組成比ｘを０．３とし、その後徐々に減少させてＧｅ組成比ｘをほぼ０まで変化させて所定厚さ（例えば、３５０ｎｍ）成膜した後、さらに再びＧｅ組成比ｘを徐々に増加させて最終的に０．３まで所定厚さ（例えば、３５０ｎｍ）成膜した組成変化層とした点で異なっている。
【００４６】
なお、この第１のＳｉＧｅ層２２の厚さも、実際に転位の生成や格子緩和が顕著にはじまる膜厚より薄く設定する。
この第３実施形態においても、第１のＳｉＧｅ層２２のＧｅ組成比ｘがＳｉ基板１及び第２のＳｉＧｅ層３との接触面で層中の最大値となるので、第１実施形態と同様に、Ｓｉ基板１及び第２のＳｉＧｅ層３との界面に多くの転位を発生させることができる。
【００４７】
次に、本発明に係る第４実施形態及び第５実施形態について、図６及び図７を参照して説明する。
【００４８】
第４実施形態と第１実施形態との異なる点は、第１実施形態における第１のＳｉＧｅ層２では、Ｇｅ組成比が一定に設定されているのに対し、第４実施形態では、図６に示すように、第１のＳｉＧｅ層３２のＧｅ組成比ｘをほぼ０から徐々に増加させて最終的に０．３まで実際に転位の生成や格子緩和が顕著にはじまる膜厚より薄い所定厚さ（例えば、３５０ｎｍ）成膜している点である。
【００４９】
また、第５実施形態と第１実施形態との異なる点は、第１実施形態における第１のＳｉＧｅ層２では、Ｇｅ組成比が一定に設定されているのに対し、第５実施形態では、図７に示すように、第１のＳｉＧｅ層４２のＧｅ組成比ｘをほぼ０から徐々に増加させて０．３まで所定厚さ（例えば、３５０ｎｍ）成膜し、さらにその後Ｇｅ組成比ｘを０．３から徐々に減少させてほぼ０まで所定厚さ（例えば、３５０ｎｍ）成膜している点である。なお、第１のＳｉＧｅ層４２の厚さは、実際に転位の生成や格子緩和が顕著にはじまる膜厚より薄く設定される。
【００５０】
これらの第４及び第５実施形態では、いずれも第１のＳｉＧｅ層３２、４２が実際に転位の生成や格子緩和が顕著にはじまる膜厚より薄い膜厚で形成されるので、第２のＳｉＧｅ層３の成膜時に第１のＳｉＧｅ層３２、４２の両側の界面に転位が集中的に発生し、貫通転位や表面ラフネスを低減することができる。なお、第４及び第５実施形態では、第１のＳｉＧｅ層３２、４２の層中におけるＧｅ組成比の最大値がＳｉ基板１との界面側にないため、第１及び第２実施形態の方が、より貫通転位及び表面ラフネスの改善効果を得ることができる。
【００５１】
なお、本発明の技術範囲は上記実施の形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲において種々の変更を加えることが可能である。
【００５２】
例えば、上記各実施形態では、第１のＳｉＧｅ層中において膜厚に対するＧｅ組成比の分布として５通りの分布としたが、他の分布としても構わない。例えば、第１のＳｉＧｅ層をＧｅ組成比が異なる複数のＳｉＧｅ層からなる多層膜としても構わない。また、前記多層膜でＳｉ層を含む多層膜としても構わない。
また、上記各実施形態では、第１のＳｉＧｅ層内でＧｅ組成比を変化させる場合、膜厚に対して一定割合で蘇生を変化させたが、その割合を一定でなくした構造としても構わない。
さらに、第１のＳｉＧｅ層は、Ｇｅを含む層であり、歪みエネルギーを蓄積できればよく、これら以外のいかなるＧｅ組成比の分布であっても構わない。
【００５３】
また、上記各実施形態では、第２のＳｉＧｅ層全体をＧｅ組成比が漸次増加する傾斜組成層としたが、傾斜組成層と均一組成層とからなる多層構造の層としても構わない。また、Ｓｉ層を含む多層膜としても構わない。
また、上記各実施形態では、第２のＳｉＧｅ層内でＧｅ組成比を表面に向けて漸次増加させた傾斜組成領域を、膜厚に対して一定割合で組成を変化させたが、その割合を一定でなくした構造としても構わない。また、その組成傾斜を階段状のＧｅ組成比の変化としても構わない。
また、上記各実施形態では、第１のＳｉＧｅ層上に直接第２のＳｉＧｅ層を配したが、Ｓｉ層を介して第２のＳｉＧｅ層を配しても構わない。
また、上記各実施形態の半導体ウェーハＷの歪みＳｉ層上に、さらにＳｉＧｅ層を成膜しても構わない。
【００５４】
また、上記各実施形態では、ＭＯＳＦＥＴ用の基板としてＳｉＧｅ層を有する半導体ウェーハを作製したが、他の用途に適用する基板としても構わない。例えば、本発明の半導体基板の製造方法及び半導体基板を太陽電池用の基板に適用してもよい。すなわち、上述した各実施形態のＳｉ基板上に最表面で１００％ＧｅとなるようにＧｅ組成比を漸次増加させた傾斜組成層のＳｉＧｅ層を成膜し、さらにこの上にＧａＡｓ（ガリウムヒ素）を成膜することで、太陽電池用基板を作製してもよい。この場合、低転位密度で高特性の太陽電池用基板が得られる。
【００５５】
【実施例】
次に、本発明に係る半導体基板を実際に作製した際のＳＩＭＳ(Secondary Ion Mass Spectrometry)による分析結果、貫通転位密度、表面ラフネス及び表面光学顕微鏡写真の観察結果を説明する。
【００５６】
作製した半導体基板は、上記第１実施形態に対応するものであって、第１のＳｉＧｅ層２のＧｅ組成比を０．１，０．１５、０．２とし、膜厚を変えて複数作製したものである。なお、比較のために従来技術、すなわち第１のＳｉＧｅ層がないものも作製した。
【００５７】
これらの半導体基板のうち、第１のＳｉＧｅ層の膜厚を３００ｎｍとした基板について、膜厚に対するＧｅ組成比の分布をＳＩＭＳにより分析した結果を図８に示す。
これらの半導体基板の貫通転位密度及び表面ラフネスの測定結果を、それぞれ図９及び図１０に示す。なお、貫通転位密度は、エッチピット密度で示し、表面ラフネスは、ＲＭＳ（Root Mean Square）で示している。
これらの図からもわかるように、従来技術（第１のＳｉＧｅ層の厚さ０）の場合に比べて、第１のＳｉＧｅ層の膜厚が少なくとも臨界膜厚ｔ_ｃの２倍未満である場合、貫通転位密度及び表面ラフネスのいずれも低減されている。
【００５８】
また、従来技術（第１のＳｉＧｅ層の厚さ０）の場合及び上記実施例のうち第１のＳｉＧｅ層のＧｅ組成比が０．２で第１のＳｉＧｅ層の厚さが５０ｎｍの場合とについて、表面の光学顕微鏡写真をそれぞれ図１１及び図１２に示す。
これらの図からもわかるように、従来技術の場合に比べて本実施例の場合は、エッチピットの暗点が非常に少なくなっている。
なお、これらの本発明の実施例について、ＴＥＭ像を観察した結果、第１のＳｉＧｅ層とＳｉ基板との界面及び第１のＳｉＧｅ層と第２のＳｉＧｅ層との界面に多くの転位が発生し、第２のＳｉＧｅ層の表面側には転位が非常に少ないことが確認できた。
【００５９】
また、上記第２〜第５実施形態に対応する半導体基板を実際に作製し、上記と同様に、表面ラフネスを測定した結果を、図１３の表に示す。なお、いずれも第１のＳｉＧｅ層の最大Ｇｅ組成比は０．２とし、膜厚を３５０ｎｍとしている。図１３からわかるように、これらの実施例において、第２実施形態及び第３実施形態に対応する実施例が、他の実施例よりも良好な結果を得ている。第２実施形態に対応する実施例について、第１のＳｉＧｅ層の膜厚に対する貫通転位密度及び表面ラフネスの測定結果を、それぞれ図１４及び図１５に示す。第１実施形態の場合と同様に、従来技術（第１のＳｉＧｅ層の厚さ０）の場合に比べて、第１のＳｉＧｅ層の膜厚が少なくとも臨界膜厚ｔ_ｃの２倍未満である場合、貫通転位密度及び表面ラフネスのいずれも低減されている。
【００６０】
【発明の効果】
本発明によれば、以下の効果を奏する。
本発明の半導体基板及び半導体基板の製造方法によれば、膜厚の増加により転位を発生して格子緩和が生ずる膜厚である臨界膜厚の２倍より薄く第１のＳｉＧｅ層の膜厚を設定し、第２のＳｉＧｅ層のＧｅ組成比を少なくとも第１のＳｉＧｅ層あるいは前記Ｓｉ層との接触面で第１のＳｉＧｅ層におけるＧｅ組成比の層中の最大値より低く、かつ、第２のＳｉＧｅ層は少なくとも一部にＧｅ組成比が表面に向けて漸次増加した傾斜組成領域を有するので、Ｓｉ基板と第１のＳｉＧｅ層との界面及び第１のＳｉＧｅ層と第２のＳｉＧｅ層との界面付近に効率的に転位を集中させることができ、第２のＳｉＧｅ層表面の貫通転位密度及び表面ラフネスを低減することができる。
【００６１】
また、本発明の歪みＳｉ層を備えた半導体基板及びその製造方法によれば、前記ＳｉＧｅ層上に直接又は他のＳｉＧｅ層を介して歪みＳｉ層をエピタキシャル成長するので、表面状態が良好なＳｉＧｅ層上にＳｉ層を成膜でき、欠陥が少なく、表面ラフネスの小さな良質な歪みＳｉ層を形成することができる。
【００６２】
また、本発明の電界効果型トランジスタ及び電界効果型トランジスタの製造方法によれば、上記本発明の半導体基板又は上記本発明の半導体基板の製造方法により作製された半導体基板の前記歪みＳｉ層に前記チャネル領域が形成されるので、良質な歪みＳｉ層により高特性なＭＯＳＦＥＴを高歩留まりで得ることができる。
【図面の簡単な説明】
【図１】本発明に係る第１実施形態における半導体基板を示す断面図である。
【図２】本発明に係る第１実施形態における半導体基板の膜厚に対するＧｅ組成比を示すグラフである。
【図３】本発明に係る第１実施形態におけるＭＯＳＦＥＴを示す概略的な断面図である。
【図４】本発明に係る第２実施形態における半導体基板の膜厚に対するＧｅ組成比を示すグラフである。
【図５】本発明に係る第３実施形態における半導体基板の膜厚に対するＧｅ組成比を示すグラフである。
【図６】本発明に係る第４実施形態における半導体基板の膜厚に対するＧｅ組成比を示すグラフである。
【図７】本発明に係る第５実施形態における半導体基板の膜厚に対するＧｅ組成比を示すグラフである。
【図８】本発明に係る第１実施形態に対応する実施例における半導体基板のうち、第１のＳｉＧｅ層の膜厚を３００ｎｍとした基板について、膜厚に対するＧｅ組成比の分布をＳＩＭＳにより分析した結果を示すグラフである。
【図９】本発明に係る第１実施形態に対応する実施例における第１のＳｉＧｅ層の膜厚に対する貫通転位密度を示すグラフである。
【図１０】本発明に係る第１実施形態に対応する実施例における第１のＳｉＧｅ層の膜厚に対する表面ラフネスを示すグラフである。
【図１１】本発明に係る従来例における表面の光学顕微鏡写真である。
【図１２】本発明に係る第１実施形態に対応する実施例における表面の光学顕微鏡写真である。
【図１３】本発明に係る第２〜５実施形態に対応する実施例におけるそれぞれの表面ラフネスを示す表である。
【図１４】本発明に係る第２実施形態に対応する実施例における第１のＳｉＧｅ層の膜厚に対する貫通転位密度の測定結果を示すグラフである。
【図１５】本発明に係る第２実施形態に対応する実施例における第１のＳｉＧｅ層の膜厚に対する表面ラフネスの測定結果を示すグラフである。
【符号の説明】
１Ｓｉ基板
２、１２、２２、３２、４２第１のＳｉＧｅ層
３第２のＳｉＧｅ層（傾斜組成領域）
４ＳｉＧｅ緩和層
５歪みＳｉ層
６ＳｉＯ_２ゲート酸化膜
７ゲートポリシリコン膜
Ｓソース領域
Ｄドレイン領域
Ｗ半導体ウェーハ（半導体基板）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor substrate and a field effect transistor used for a high-speed MOSFET and the like, and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, high-speed MOSFETs, MODFETs, and HEMTs using a strained Si layer epitaxially grown on a Si (silicon) substrate via a SiGe (silicon-germanium) layer as a channel region have been proposed. In this strained Si-FET, tensile strain is generated in the Si layer due to SiGe having a larger lattice constant than Si, so that the band structure of Si is changed, the degeneracy is solved, and the carrier mobility is increased. Therefore, by using this strained Si layer as the channel region, the speed can be increased by about 1.3 to 8 times the normal speed. Further, a normal Si substrate by the CZ method can be used as a substrate as a process, and a high-speed CMOS can be realized by a conventional CMOS process.
[0003]
However, in order to epitaxially grow the strained Si layer required as the channel region of the FET, it is necessary to epitaxially grow a high-quality SiGe layer on the Si substrate, but due to the difference in lattice constant between Si and SiGe, There was a problem with crystallinity. For this purpose, various proposals have been made in the past.
[0004]
For example, a method using a buffer layer in which the Ge composition ratio of SiGe is changed with a constant gentle slope, a method using a buffer layer in which the Ge (germanium) composition ratio is changed stepwise (stepped), and a Ge composition ratio exceeding There have been proposed a method using a buffer layer changed into a lattice shape and a method using a buffer layer in which the Ge composition ratio is changed at a constant gradient using a Si off-cut wafer (US Patent 5,442,205, US Patent 5,221,413, PCT). WO98 / 00857, JP-A-62-252046, etc.).
[0005]
[Problems to be solved by the invention]
However, the following problems remain in the conventional technology.
That is, the SiGe layer formed by using the above-described conventional technique is in a state where the threading dislocation density and the surface roughness do not reach the level required for the device and the manufacturing process.
For example, in the case of using a buffer layer in which the Ge composition ratio is inclined, the threading dislocation density can be made relatively low, but there is a disadvantage that the surface roughness is deteriorated, and conversely, the Ge composition ratio is stepped. When the buffer layer is used, the surface roughness can be relatively reduced, but there is a disadvantage that the threading dislocation density increases. Further, in the case of using an off-cut wafer, dislocations easily escape laterally rather than in the film forming direction, but a sufficiently low dislocation has not yet been achieved. The surface roughness has not yet reached the level required for the photolithography process in recent LSI or the like.
[0006]
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor substrate, a field effect transistor, and a manufacturing method thereof, which can reduce threading dislocation density and surface roughness to a practical level. And
[0007]
[Means for Solving the Problems]
The present invention employs the following configuration in order to solve the above problems.
That is, the semiconductor substrate of the present invention includes a Si substrate,
A first SiGe layer on the Si substrate;
A second SiGe layer disposed directly on the first SiGe layer;
The first SiGe layer is thinner than twice the critical film thickness, which is a film thickness in which dislocation occurs due to an increase in film thickness and lattice relaxation occurs.
The Ge composition ratio of the second SiGe layer is 0 lower than the maximum value of the Ge composition ratio in the first SiGe layer at the contact surface with the first SiGe layer, and the entire layer has a Ge composition. The gradient composition layer has a ratio that gradually increases from 0 toward the surface.
The method for manufacturing a semiconductor substrate of the present invention is a method for manufacturing a semiconductor substrate in which a SiGe layer is epitaxially grown on a Si substrate,
A first layer forming step of epitaxially growing a first SiGe layer on the Si substrate;
A second layer forming step of epitaxially growing a second SiGe layer directly on the first SiGe layer,
In the first layer forming step, the thickness of the first SiGe layer is set to be less than twice the critical thickness, which is a thickness at which dislocation occurs due to an increase in thickness and lattice relaxation occurs.
In the second layer forming step, the Ge composition ratio of the second SiGe layer is set to 0 lower than the maximum value in the layer of the Ge composition ratio of the first SiGe layer at the contact surface with the first SiGe layer. In addition, the entire layer forms a gradient composition layer in which the Ge composition ratio gradually increases from 0 toward the surface.
Further, the second SiGe layer of the present invention may be a gradient composition layer in which the entire layer gradually increases from the Ge composition ratio toward the surface from 0 to 0.3.
That is, the semiconductor substrate of the present invention includes a Si substrate, a first SiGe layer on the Si substrate, and a second SiGe layer disposed on the first SiGe layer directly or via the Si layer. The first SiGe layer is thinner than twice the critical thickness, which is a thickness at which dislocation occurs due to an increase in thickness and lattice relaxation occurs, and the second SiGe layer The Ge composition ratio is lower than the maximum value of the Ge composition ratio in the first SiGe layer at least at the contact surface with the first SiGe layer or the Si layer, and at least partly the Ge composition ratio is on the surface. It has the gradient composition area | region which increased gradually toward the direction.
The method for manufacturing a semiconductor substrate according to the present invention is a method for manufacturing a semiconductor substrate in which a SiGe layer is epitaxially grown on a Si substrate, wherein the first layer is formed by epitaxially growing a first SiGe layer on the Si substrate. And a second layer forming step of epitaxially growing a second SiGe layer directly or via an epitaxially grown Si layer on the first SiGe layer, the first layer forming step comprising: The film thickness of the first SiGe layer is set to be less than twice the critical film thickness, which is a film thickness that causes dislocation due to the increase in the lattice relaxation, and the second layer forming step includes the second layer forming step. The Ge composition ratio of the SiGe layer is lower than the maximum value in the layer of the Ge composition ratio of the first SiGe layer at least at the contact surface with the first SiGe layer or the Si, and at least partly Ge. Formation ratio and forming a graded composition region gradually increased toward the surface.
The semiconductor substrate of the present invention is a semiconductor substrate in which a SiGe layer is formed on a Si substrate, and is manufactured by the method for manufacturing a semiconductor substrate of the present invention.
[0008]
In these semiconductor substrates and semiconductor substrate manufacturing methods, the thickness of the first SiGe layer is set to be less than twice the critical thickness, which is the thickness at which dislocation occurs due to the increase in thickness and lattice relaxation occurs. The Ge composition ratio of the second SiGe layer is lower than the maximum value in the layer of the Ge composition ratio of the first SiGe layer at least in contact with the first SiGe layer or the Si layer, and the second SiGe layer Has a gradient composition region in which the Ge composition ratio gradually increases toward the surface at least partially, so that the interface between the Si substrate and the first SiGe layer and the vicinity of the interface between the first SiGe layer and the second SiGe layer Thus, dislocations can be efficiently concentrated, and threading dislocation density and surface roughness on the surface of the second SiGe layer can be reduced.
[0009]
That is, since the first SiGe layer is formed to be thinner than twice the critical film thickness, strain energy increases in accordance with the film thickness during the first SiGe layer film formation, but almost no dislocation is generated. Next, when the epitaxial growth of the second SiGe layer is started, strain energy has already been accumulated in the first SiGe layer, and therefore, the generation and growth of dislocations occurs when the thickness of the second SiGe layer is thin. Starting from the interfaces on both sides of the first SiGe layer and the first SiGe layer side in the second SiGe layer, lattice relaxation of the first SiGe layer and the second SiGe layer starts. At this time, since the Ge composition ratio of the second SiGe layer is lower than the maximum value in the layer of the Ge composition ratio in the first SiGe layer at the contact surface with the first SiGe layer or the Si layer, the dislocation is The formation of dislocations at the interfaces on both sides of the first SiGe layer helps the lattice relaxation of the second SiGe layer, and the generation of dislocations in the second SiGe layer. Generation and growth are suppressed, and deterioration of the surface roughness of the second SiGe layer surface is also suppressed.
[0010]
Furthermore, in the graded composition region of the second SiGe layer, dislocations are generated uniformly, entanglement between the dislocations occurs, the dislocation density in the graded composition region decreases, and the growth of dislocations is induced in the lateral direction. As a result, the threading dislocation density in the surface region is reduced, and the deterioration of the surface roughness is suppressed.
In the gradient composition region without the conventional first SiGe layer, dislocation generation starts when the thickness of the gradient composition region exceeds a predetermined thickness and exceeds the critical film thickness , and once the dislocation density is increased. After the elapse of time, the above-described effect can be obtained when a gradient composition ancestor region is further formed. That is, in the conventional structure, the above-described effect can be obtained only in a partial region above the gradient composition region.
[0011]
On the other hand, in the structure of the present invention having the first SiGe layer, since the strain energy is already accumulated in the first SiGe layer, the generation of dislocation is second when the second SiGe layer is thin. Therefore, the above effect is obtained in the entire gradient composition region in the second SiGe layer, the threading dislocation density in the surface region of the second SiGe layer is reduced, and the deterioration of the surface roughness is suppressed. The
Furthermore, the first SiGe layer functions as a layer that removes impurities such as moisture, oxygen components, and carbon components on the surface of the Si substrate, and has an effect of suppressing defects due to surface contamination of the Si substrate.
[0012]
If dislocations begin to form during the formation of the first SiGe layer, dislocations begin to grow in multiple directions, making it difficult to suppress the direction of dislocation growth and reducing threading dislocations and surface roughness. It is difficult to let Therefore, the thickness of the first SiGe layer needs to be set to a thickness smaller than the thickness at which dislocation generation or lattice relaxation starts to be noticeable within a range not exceeding twice the critical thickness. At the same time, the film thickness of the first SiGe layer is more effective as the film thickness is closer to the film thickness at which dislocation generation and lattice relaxation are actually noticeable. The film thickness at which dislocation generation and lattice relaxation are actually noticeable varies depending on the temperature condition of the film formation. Therefore, in each film forming condition, a film thickness in which the effects of the present invention can be effectively obtained in the vicinity of the film thickness where the generation of dislocations and lattice relaxation starts remarkably within a range not exceeding twice the critical film thickness. You can choose.
[0013]
In the semiconductor substrate of the present invention, the first SiGe layer has a constant Ge composition ratio x, and the following relational expression:
t _c (nm) = (1.9 × 10 ⁻³ / ε (x) ² ) · ln (t _c /0.4)
ε (x) = (a ₀ + 0.200326x + 0.026174x ² ) / a ₀ )
a ₀ = 0.543 nm (a ₀ is the lattice constant of Si)
A technique that is less than twice the critical film thickness t _c that satisfies the above is adopted.
In the method for manufacturing a semiconductor substrate of the present invention, the Ge composition ratio x of the first SiGe layer is constant in the first layer forming step, and the first SiGe layer is expressed by the following relational expression:
t _c (nm) = (1.9 × 10 ⁻³ / ε (x) ² ) · ln (t _c /0.4)
ε (x) = (a ₀ + 0.200326x + 0.026174x ² ) / a ₀ )
a ₀ = 0.543 nm (a ₀ is the lattice constant of Si)
Technique to a thickness of less than twice the critical thickness t _c that satisfies is employed.
The semiconductor substrate of the present invention is a semiconductor substrate in which a SiGe layer is formed on a Si substrate, and is manufactured by the method for manufacturing a semiconductor substrate of the present invention.
[0014]
In these semiconductor substrates and semiconductor substrate manufacturing methods, since the Ge composition ratio of the first SiGe layer is constant, the film thickness at which dislocation generation or lattice relaxation starts to be noticeable at the same Ge composition ratio is the thinnest. The effects of the present invention can be obtained with the thinnest film thickness, and there are advantages that the time required for film formation is short. Further, in these semiconductor substrates and semiconductor substrate manufacturing methods, the critical thickness of the first SiGe layer satisfying the above relational expression (dislocations calculated only from the Ge composition ratio and the lattice constant occur regardless of the deposition temperature). and refers to a film thickness lattice relaxation occurs in) by the less than twice the thickness of t _c, the thickness of the film thickness of the first SiGe layer is readily actual dislocation generation and lattice relaxation begins to significantly Can be set within.
[0015]
That is, since the thickness starting remarkable generation and lattice relaxation of the actual dislocation varies with deposition temperature, 2 of only the Ge composition ratio x and the lattice constant of the theoretically obtained ideal critical thickness t _c If it is less than double, the film thickness becomes smaller than the film thickness at which dislocation generation and lattice relaxation actually start remarkably, and the effects of the present invention can be obtained. Since the critical film thickness is assumed to be formed in an equilibrium state, it is determined only by the Ge composition ratio and the lattice constant regardless of the film formation temperature. The film thickness at which the film starts remarkably includes not only the equilibrium state but also the case where the film is formed in a non-equilibrium state such as low-temperature growth, and is determined according to the deposition temperature.
[0016]
In the semiconductor substrate of the present invention, the Ge composition ratio x of the first SiGe layer is preferably 0.05 or more and 0.3 or less.
In the method for manufacturing a semiconductor substrate according to the present invention, the Ge composition ratio x of the first SiGe layer is preferably 0.05 or more and 0.3 or less.
The semiconductor substrate of the present invention is a semiconductor substrate in which a SiGe layer is formed on a Si substrate, and is manufactured by the method for manufacturing a semiconductor substrate of the present invention.
[0017]
In these semiconductor substrates and semiconductor substrate manufacturing methods, since the Ge composition ratio x of the first SiGe layer is 0.05 or more and 0.3 or less, a film in which dislocation generation and lattice relaxation are actually remarkably started. The effect of the present invention can be effectively obtained with the first SiGe layer having an appropriate thickness without being too thin or too thick.
That is, when the Ge composition ratio x of the first SiGe layer is smaller than 0.05, the film thickness at which dislocation generation or lattice relaxation actually starts remarkably becomes too thick, so that the first SiGe layer is formed. The time required is increased, and the surface roughness of the first SiGe layer is deteriorated.
[0018]
On the other hand, when the Ge composition ratio x of the first SiGe layer is larger than 0.3, the generation of dislocations and lattice relaxation actually starts remarkably with a very thin film thickness, so the first SiGe layer is controlled. It is difficult to form well.
In addition, when the Ge composition ratio x of the first SiGe layer is 0.05 or more and 0.3 or less, the film thickness at which dislocation generation and lattice relaxation are actually noticeable becomes an appropriate thickness. Dislocations are concentrated and formed along the interfaces on both sides of the SiGe layer, and the generation of dislocations at the interfaces on both sides of the first SiGe layer effectively provides an effect of assisting lattice relaxation of the second SiGe layer.
[0019]
In the semiconductor substrate of the present invention, the second SiGe layer is directly disposed on the first SiGe layer, and the entire layer is a graded composition layer in which the Ge composition ratio gradually increases toward the surface. Structure is adopted.
Further, in the method of manufacturing a semiconductor substrate according to the present invention, the second SiGe layer is directly disposed on the first SiGe layer, and the entire layer has a gradient composition layer in which the Ge composition ratio gradually increases toward the surface. The method is adopted.
The semiconductor substrate of the present invention is a semiconductor substrate in which a SiGe layer is formed on a Si substrate, and is manufactured by the method for manufacturing a semiconductor substrate of the present invention.
[0020]
In these semiconductor substrates and semiconductor substrate manufacturing methods, the second SiGe layer is directly disposed on the first SiGe layer, and the entire layer has a graded composition layer in which the Ge composition ratio gradually increases toward the surface. Therefore, the layers necessary for obtaining the effects of the present invention are disposed without waste, and the effects of the present invention can be obtained with the thinnest film thickness, and the time required for film formation is short.
[0021]
The semiconductor substrate of the present invention is characterized in that a strained Si layer is epitaxially grown directly on the SiGe layer or via another SiGe layer.
The semiconductor substrate manufacturing method of the present invention is characterized in that a strained Si layer is epitaxially grown directly on the SiGe layer or via another SiGe layer.
The semiconductor substrate of the present invention is a semiconductor substrate in which a strained Si layer is formed on a Si substrate via a SiGe layer, and is produced by the semiconductor substrate manufacturing method for growing the strained Si layer of the present invention. It is characterized by that.
[0022]
In these semiconductor substrates and semiconductor substrate manufacturing methods, a strained Si layer is epitaxially grown directly on the SiGe layer or via another SiGe layer, so that a high-quality strained Si layer with few defects and small surface roughness can be obtained. For example, it is suitable as a semiconductor substrate for an integrated circuit using a MOSFET or the like having a strained Si layer as a channel region and a manufacturing method thereof.
[0023]
The field effect transistor of the present invention is a field effect transistor having a channel region in a strained Si layer on a SiGe layer, wherein the strained Si layer of the semiconductor substrate of the present invention has the channel region. To do.
The field effect transistor manufacturing method of the present invention is a method of manufacturing a field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer, wherein the semiconductor substrate of the present invention is manufactured. The channel region is formed in the strained Si layer of the semiconductor substrate manufactured by the method.
The field effect transistor of the present invention is a field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer, and is manufactured by the method for manufacturing a field effect transistor of the present invention. It is characterized by that.
[0024]
In the field effect transistor and the method of manufacturing the field effect transistor, the channel region is formed in the semiconductor substrate of the present invention or the strained Si layer of the semiconductor substrate manufactured by the method of manufacturing the semiconductor substrate of the present invention. Therefore, a high-performance field effect transistor can be obtained with a high yield by using a high-quality strained Si layer.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
A first embodiment according to the present invention will be described below with reference to FIGS.
[0026]
FIG. 1 shows a cross-sectional structure of a semiconductor wafer (semiconductor substrate) W of the present invention. The structure of this semiconductor wafer will be described together with its manufacturing process. On the p-type or n-type Si substrate 1, as shown in FIGS. 1 and 2, the above-described actual generation of dislocations and lattice relaxation are remarkable with the Ge composition ratio x being constant (eg, x = 0.15). The first SiGe layer 2 having a thickness (for example, 300 nm) thinner than the starting film thickness is epitaxially grown by, for example, a low pressure CVD method.
[0027]
At this time, since the first SiGe layer 2 is formed to be thinner than the film thickness at which dislocation generation and lattice relaxation start to be noticeable, strain energy depends on the film thickness during the first SiGe layer 2 film formation. Although it becomes large, dislocation and lattice relaxation hardly occur.
Note that the thickness of the first SiGe layer 2 is expressed by the following relational expression:
t _c (nm) = (1.9 × 10 ⁻³ / ε (x) ² ) · ln (t _c /0.4)
ε (x) = (a ₀ + 0.200326x + 0.026174x ² ) / a ₀ )
a ₀ = 0.543 nm (a ₀ is the lattice constant of Si)
The thickness is less than twice the critical film thickness t _c that satisfies the above condition.
[0028]
Next, the second SiGe layer 3 is epitaxially grown on the first SiGe layer 2. The Ge composition ratio y of the second SiGe layer 3 is set lower than the maximum value in the layer of the Ge composition ratio x in the first SiGe layer 2 at least at the contact surface with the first SiGe layer 2. The second SiGe layer 3 is a gradient composition layer (for example, a layer in which the Ge composition ratio y increases from 0 to 0.3) (gradient composition region) whose Ge composition ratio y gradually increases toward the surface. For example, the film is formed to a thickness of 1.1 μm.
[0029]
When the epitaxial growth of the second SiGe layer 3 is started, strain energy is already accumulated in the first SiGe layer 2, so that dislocation generation and growth occurs at a stage where the thickness of the second SiGe layer 3 is thin. Lattice relaxation of the first SiGe layer 2 and the second SiGe layer 3 starts from the interfaces on both sides of the first SiGe layer 2 and the first SiGe layer 2 side in the second SiGe layer 3. At this time, since the Ge composition ratio of the second SiGe layer 3 is lower than the maximum value in the layer of the Ge composition ratio in the first SiGe layer 2 at the contact surface of the first SiGe layer 2, the dislocation is The generation of dislocations at the interfaces 2a and 2b on both sides of the first SiGe layer 2 helps the lattice relaxation of the second SiGe layer 3 by being concentrated and generated along the interfaces 2a and 2b on both sides of the SiGe layer 2. Generation and growth of dislocations in the SiGe layer 3 are suppressed, and deterioration of the surface roughness on the surface of the second SiGe layer 3 is also suppressed.
[0030]
Further, the SiGe relaxation layer 4 having the same composition ratio z as the final Ge composition ratio of the second SiGe layer 3 (for example, z is 0.3) and a constant composition ratio has a predetermined thickness (for example, 0.4 μm). ) And then epitaxial growth of single crystal Si on the SiGe relaxation layer 4 to form the strained Si layer 5 by a predetermined thickness (for example, 20 nm), thereby producing the semiconductor wafer W of the present embodiment. Is done.
[0031]
The film formation by the low pressure CVD method uses H ₂ as a carrier gas and SiH ₄ and GeH ₄ as source gases.
[0032]
As described above, in the semiconductor wafer W of the present embodiment, the film thickness of the first SiGe layer 2 is set to be thinner than the film thickness at which dislocation generation and lattice relaxation actually start, and the Ge composition of the second SiGe layer 3 is set. Since the ratio y is lower than the maximum value in the layer of the Ge composition ratio x in the first SiGe layer 2 at least at the contact surface with the first SiGe layer 2, the interface between the Si substrate 1 and the first SiGe layer 2 Dislocations can be efficiently concentrated on the interface 2b between 2a and the first SiGe layer 2 and the second SiGe layer 3, and threading dislocation density and surface roughness can be reduced.
[0033]
In addition, since the Ge composition ratio of the first SiGe layer 2 is constant, the film thickness at which dislocation generation and lattice relaxation start remarkably at the same Ge composition ratio is the thinnest, and the film thickness of the present invention is the smallest. The effect is obtained, and there is an advantage that the time required for film formation is short.
In addition, by setting the thickness of the first SiGe layer 2 to less than twice the critical thickness t _c satisfying the above relational expression, the thickness of the first SiGe layer 2 can be easily set based on the experimental results described later. In fact, the film thickness can be set within a film thickness at which dislocation generation and lattice relaxation are remarkably started.
[0034]
In the present embodiment, the second SiGe layer 3 is a graded composition layer (gradient composition region) in which the Ge composition ratio is gradually increased, so that dislocations are uniformly generated and entanglement between the dislocations occurs. The dislocation density in the second SiGe layer 3 is reduced, and the growth of dislocations is induced in the lateral direction, whereby the threading dislocation density in the surface region is reduced and the deterioration of the surface roughness is suppressed.
[0035]
In the present embodiment, since the strain energy has already been accumulated in the first SiGe layer 2 before the second SiGe layer 3 is formed, the dislocation is performed when the second SiGe layer 3 is thin. Is generated in the second SiGe layer 3, the above effect is obtained in the entire gradient composition region in the second SiGe layer 3, and the threading dislocation density in the surface region of the second SiGe layer 3 is reduced. Also, deterioration of the surface roughness is suppressed.
Further, the first SiGe layer 2 functions as a layer that removes impurities such as moisture, oxygen components, and carbon components on the surface of the Si substrate 1, and has an effect of suppressing defects due to surface contamination of the Si substrate 1.
[0036]
Next, a field effect transistor (MOSFET) using the semiconductor wafer W of the present invention will be described with reference to FIG.
[0037]
FIG. 3 shows a schematic structure of the field effect transistor of the present invention. In order to manufacture this field effect transistor, the strained Si layer 5 on the surface of the semiconductor wafer W manufactured in the above manufacturing process is shown. A SiO ₂ gate oxide film 6 and a gate polysilicon film 7 are sequentially deposited thereon. Then, a gate electrode (not shown) is formed by patterning on the gate polysilicon film 7 on the portion to become the channel region.
[0038]
Next, the gate oxide film 6 is also patterned to remove portions other than those under the gate electrode. Further, an n-type or p-type source region S and drain region D are formed in a self-aligned manner in the strained Si layer 5 and the relaxation layer 4 by ion implantation using the gate electrode as a mask. Thereafter, a source electrode and a drain electrode (not shown) are formed on the source region S and the drain region D, respectively, and an n-type or p-type MOSFET in which the strained Si layer 5 serves as a channel region is manufactured.
[0039]
In the MOSFET manufactured in this way, a channel region is formed in the strained Si layer 5 on the semiconductor wafer W manufactured by the above-described manufacturing method, so that a high-quality MOSFET can be obtained with a high yield with a high-quality strained Si layer 5. Can do.
[0040]
Next, a second embodiment according to the present invention will be described with reference to FIG.
[0041]
The difference between the second embodiment and the first embodiment is that, in the first SiGe layer 2 in the first embodiment, the Ge composition ratio is set constant, whereas in the second embodiment, FIG. As shown in FIG. 4, the Ge composition ratio x of the first SiGe layer 12 is set to the maximum value in the layer at the contact surface with the Si substrate 1, and the Ge composition ratio x is gradually decreased.
[0042]
That is, in the present embodiment, in the process of forming the first SiGe layer 12, the Ge composition ratio x is set to 0.3 at the start of film formation, and then gradually decreased, and finally the Ge composition ratio x is substantially 0. The graded composition layer is grown by a predetermined thickness (for example, 350 nm) thinner than the thickness at which dislocation generation and lattice relaxation are actually noticeable.
[0043]
In this embodiment, by setting the Ge composition ratio x of the first SiGe layer 12 to the maximum value in the layer at the contact surface with the Si substrate 1, the strain energy at the time of film formation is on the interface side with the Si substrate 1. At the time of lattice relaxation occurring at the start of film formation of the second SiGe layer 3, more dislocations can be generated at the interface with the Si substrate 1 than at the interface with the second SiGe layer 3. . Thereby, dislocations can be concentrated at a position away from the surface side of the second SiGe layer 3, and threading dislocations and surface roughness can be reduced as in the first embodiment.
[0044]
Next, a third embodiment according to the present invention will be described with reference to FIG.
[0045]
The difference between the third embodiment and the second embodiment is that the second SiGe layer 12 of the second embodiment is a gradient composition layer in which the Ge composition ratio is gradually reduced, whereas in the third embodiment, As shown in FIG. 5, in the process of forming the first SiGe layer 22, the Ge composition ratio x is set to 0.3 at the start of film formation, and then gradually decreased to change the Ge composition ratio x to almost zero. After the film is formed to a predetermined thickness (for example, 350 nm), the Ge composition ratio x is gradually increased again to finally form a composition change layer having a predetermined thickness (for example, 350 nm) formed to 0.3. Is different.
[0046]
Note that the thickness of the first SiGe layer 22 is also set to be thinner than the film thickness at which dislocation generation and lattice relaxation are actually remarkably started.
Also in the third embodiment, the Ge composition ratio x of the first SiGe layer 22 becomes the maximum value in the layer at the contact surface between the Si substrate 1 and the second SiGe layer 3, so that it is the same as in the first embodiment. In addition, many dislocations can be generated at the interface between the Si substrate 1 and the second SiGe layer 3.
[0047]
Next, 4th Embodiment and 5th Embodiment which concern on this invention are described with reference to FIG.6 and FIG.7.
[0048]
The difference between the fourth embodiment and the first embodiment is that the Ge composition ratio is set constant in the first SiGe layer 2 in the first embodiment, whereas in the fourth embodiment, FIG. As shown in FIG. 4, the Ge composition ratio x of the first SiGe layer 32 is gradually increased from approximately 0 to finally reach a predetermined thickness that is thinner than 0.3 so that the generation of dislocations and lattice relaxation starts to be noticeable. (For example, 350 nm).
[0049]
Further, the difference between the fifth embodiment and the first embodiment is that the Ge composition ratio is set constant in the first SiGe layer 2 in the first embodiment, whereas in the fifth embodiment, As shown in FIG. 7, the Ge composition ratio x of the first SiGe layer 42 is gradually increased from approximately 0 to a predetermined thickness (for example, 350 nm) up to 0.3, and then the Ge composition ratio x is set. The film thickness is gradually decreased from 0.3 to almost 0 to a predetermined thickness (for example, 350 nm). Note that the thickness of the first SiGe layer 42 is set to be thinner than the film thickness at which dislocation generation and lattice relaxation are actually noticeable.
[0050]
In each of the fourth and fifth embodiments, the first SiGe layers 32 and 42 are formed with a thickness smaller than the thickness at which dislocation generation and lattice relaxation are actually noticeable. When the layer 3 is formed, dislocations are intensively generated at the interfaces on both sides of the first SiGe layers 32 and 42, and threading dislocations and surface roughness can be reduced. In the fourth and fifth embodiments, since the maximum value of the Ge composition ratio in the first SiGe layers 32 and 42 is not on the interface side with the Si substrate 1, the first and second embodiments are the same. However, the effect of improving threading dislocations and surface roughness can be obtained.
[0051]
The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.
[0052]
For example, in each of the above embodiments, the five distributions of the Ge composition ratio with respect to the film thickness are set in the first SiGe layer, but other distributions may be used. For example, the first SiGe layer may be a multilayer film composed of a plurality of SiGe layers having different Ge composition ratios. The multilayer film may be a multilayer film including a Si layer.
In each of the above embodiments, when the Ge composition ratio is changed in the first SiGe layer, the resuscitation is changed at a constant rate with respect to the film thickness. However, the ratio may not be constant. .
Furthermore, the first SiGe layer is a layer containing Ge as long as strain energy can be accumulated, and any other Ge composition ratio distribution may be used.
[0053]
In each of the above embodiments, the entire second SiGe layer is a graded composition layer in which the Ge composition ratio gradually increases. However, the second SiGe layer may have a multilayer structure including a graded composition layer and a uniform composition layer. Further, a multilayer film including a Si layer may be used.
Further, in each of the above embodiments, the composition ratio of the gradient composition region in which the Ge composition ratio is gradually increased toward the surface in the second SiGe layer is changed at a constant ratio with respect to the film thickness. It does not matter if the structure is not constant. Further, the composition gradient may be a stepwise change in the Ge composition ratio.
In each of the above embodiments, the second SiGe layer is disposed directly on the first SiGe layer. However, the second SiGe layer may be disposed via the Si layer.
Further, a SiGe layer may be further formed on the strained Si layer of the semiconductor wafer W in each of the above embodiments.
[0054]
In each of the above embodiments, a semiconductor wafer having a SiGe layer is manufactured as a substrate for MOSFET. However, the substrate may be applied to other applications. For example, you may apply the manufacturing method and semiconductor substrate of the semiconductor substrate of this invention to the board | substrate for solar cells. That is, a SiGe layer having a graded composition layer in which the Ge composition ratio is gradually increased so as to be 100% Ge on the outermost surface is formed on the Si substrate of each of the embodiments described above, and GaAs (gallium arsenide) is further formed thereon. A solar cell substrate may be produced by forming a film. In this case, a solar cell substrate having low dislocation density and high characteristics can be obtained.
[0055]
【Example】
Next, an analysis result by SIMS (Secondary Ion Mass Spectrometry), an observation result of a threading dislocation density, a surface roughness, and a surface optical micrograph when the semiconductor substrate according to the present invention is actually manufactured will be described.
[0056]
The manufactured semiconductor substrate corresponds to the first embodiment described above, and a plurality of semiconductor substrates are manufactured by changing the film thickness by changing the Ge composition ratio of the first SiGe layer 2 to 0.1, 0.15, and 0.2. It is a thing. For comparison, a prior art, that is, a device without the first SiGe layer was also produced.
[0057]
Among these semiconductor substrates, FIG. 8 shows the results of analyzing the distribution of the Ge composition ratio with respect to the film thickness by SIMS for a substrate in which the film thickness of the first SiGe layer is 300 nm.
The measurement results of threading dislocation density and surface roughness of these semiconductor substrates are shown in FIGS. 9 and 10, respectively. The threading dislocation density is indicated by etch pit density, and the surface roughness is indicated by RMS (Root Mean Square).
As can be seen from these figures, the thickness of the first SiGe layer is at least less than twice the critical thickness t _c as compared with the case of the prior art (the thickness of the first SiGe layer is 0). Both threading dislocation density and surface roughness are reduced.
[0058]
Further, the prior art when the thickness of the (first SiGe layer thickness zero) in the case and the embodiment sac Chi first Ge composition ratio of the SiGe layer is first SiGe layer 0.2 is 50nm for preparative shows an optical micrograph of the surface in FIG. 11 and FIG. 12 respectively.
As can be seen from these figures, the dark spots of the etch pits are much less in the case of the present embodiment than in the case of the prior art.
In addition, as a result of observing TEM images of these embodiments of the present invention, many dislocations occurred at the interface between the first SiGe layer and the Si substrate and at the interface between the first SiGe layer and the second SiGe layer. It was confirmed that there were very few dislocations on the surface side of the second SiGe layer.
[0059]
Moreover, the table | surface of FIG. 13 shows the result of actually producing the semiconductor substrate corresponding to the said 2nd-5th embodiment, and measuring surface roughness similarly to the above. In either case, the maximum Ge composition ratio of the first SiGe layer is 0.2, and the film thickness is 350 nm. As can be seen from FIG. 13, in these examples, the examples corresponding to the second embodiment and the third embodiment obtain better results than the other examples. In the example corresponding to the second embodiment, the measurement results of the threading dislocation density and the surface roughness with respect to the film thickness of the first SiGe layer are shown in FIGS. 14 and 15, respectively. As in the case of the first embodiment, the thickness of the first SiGe layer is at least less than twice the critical thickness t _c as compared with the case of the conventional technique (the thickness of the first SiGe layer is 0). In this case, both the threading dislocation density and the surface roughness are reduced.
[0060]
【The invention's effect】
The present invention has the following effects.
According to the semiconductor substrate and the method of manufacturing a semiconductor substrate of the present invention, the thickness of the first SiGe layer is less than twice the critical thickness, which is the thickness at which dislocation occurs due to the increase in thickness and lattice relaxation occurs. The Ge composition ratio of the second SiGe layer is lower than the maximum value of the Ge composition ratio in the first SiGe layer at least at the contact surface with the first SiGe layer or the Si layer, and The SiGe layer at least partially has a graded composition region in which the Ge composition ratio gradually increases toward the surface, so that the interface between the Si substrate and the first SiGe layer, the first SiGe layer and the second SiGe layer, Dislocations can be efficiently concentrated in the vicinity of the interface, and threading dislocation density and surface roughness on the surface of the second SiGe layer can be reduced.
[0061]
In addition, according to the semiconductor substrate having the strained Si layer of the present invention and the manufacturing method thereof, the strained Si layer is epitaxially grown on the SiGe layer directly or via another SiGe layer, so that the SiGe layer having a good surface state A Si layer can be formed thereon, and a high-quality strained Si layer with few defects and small surface roughness can be formed.
[0062]
Further, according to the field effect transistor and the method of manufacturing a field effect transistor of the present invention, the strained Si layer of the semiconductor substrate of the present invention or the semiconductor substrate manufactured by the method of manufacturing the semiconductor substrate of the present invention is Since the channel region is formed, a high-quality MOSFET can be obtained with a high yield by a high-quality strained Si layer.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a semiconductor substrate according to a first embodiment of the present invention.
FIG. 2 is a graph showing the Ge composition ratio with respect to the film thickness of the semiconductor substrate according to the first embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view showing the MOSFET in the first embodiment according to the invention.
FIG. 4 is a graph showing a Ge composition ratio with respect to a film thickness of a semiconductor substrate in a second embodiment according to the present invention.
FIG. 5 is a graph showing a Ge composition ratio with respect to a film thickness of a semiconductor substrate according to a third embodiment of the present invention.
FIG. 6 is a graph showing a Ge composition ratio with respect to a film thickness of a semiconductor substrate according to a fourth embodiment of the present invention.
FIG. 7 is a graph showing a Ge composition ratio with respect to a film thickness of a semiconductor substrate according to a fifth embodiment of the present invention.
FIG. 8 shows the distribution of the Ge composition ratio with respect to the film thickness of the semiconductor substrate in the example corresponding to the first embodiment according to the present invention in which the film thickness of the first SiGe layer is 300 nm. It is a graph which shows the result.
FIG. 9 is a graph showing threading dislocation density with respect to film thickness of a first SiGe layer in an example corresponding to the first embodiment according to the present invention.
FIG. 10 is a graph showing the surface roughness with respect to the film thickness of the first SiGe layer in an example corresponding to the first embodiment according to the present invention.
FIG. 11 is an optical micrograph of a surface in a conventional example according to the present invention.
FIG. 12 is an optical micrograph of a surface in an example corresponding to the first embodiment according to the present invention.
FIG. 13 is a table showing surface roughness in examples corresponding to the second to fifth embodiments according to the present invention.
FIG. 14 is a graph showing the measurement results of threading dislocation density with respect to the film thickness of the first SiGe layer in an example corresponding to the second embodiment according to the present invention.
FIG. 15 is a graph showing a measurement result of surface roughness with respect to a film thickness of a first SiGe layer in an example corresponding to the second embodiment according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Si substrate 2, 12, 22, 32, 42 1st SiGe layer 3 2nd SiGe layer (gradient composition area)
4 SiGe relaxation layer 5 Strained Si layer 6 SiO ₂ gate oxide film 7 Gate polysilicon film S Source region D Drain region W Semiconductor wafer (semiconductor substrate)

Claims

A Si substrate;
A first SiGe layer on the Si substrate;
A second SiGe layer disposed directly on the first SiGe layer;
The first SiGe layer is thinner than twice the critical film thickness, which is a film thickness in which dislocation occurs due to an increase in film thickness and lattice relaxation occurs.
The Ge composition ratio of the second SiGe layer is 0 lower than the maximum value of the Ge composition ratio in the first SiGe layer at the contact surface with the first SiGe layer, and the entire layer has a Ge composition. A semiconductor substrate characterized by being a graded composition layer whose ratio gradually increases from 0 toward the surface.

2. The semiconductor substrate according to claim 1, wherein the first SiGe layer has a constant Ge composition ratio x.

In the semiconductor substrate according to claim 1 or 2,
The semiconductor substrate according to claim 1, wherein the first SiGe layer has a Ge composition ratio x of 0.05 to 0.3.

In the semiconductor substrate according to any one of claims 1 to 3,
The semiconductor substrate according to claim 2, wherein the second SiGe layer is a graded composition layer in which the entire layer has a Ge composition ratio that gradually increases from 0 to 0.3 toward the surface.

5. A semiconductor substrate comprising a strained Si layer disposed directly or via another SiGe layer on the second SiGe layer of the semiconductor substrate according to claim 1.

A field effect transistor having a channel region in a strained Si layer on a SiGe layer,
Field effect transistor, wherein a call with the channel region in the strained Si layer of the semiconductor substrate according to claim 5.

A method of manufacturing a semiconductor substrate in which a SiGe layer is epitaxially grown on a Si substrate,
A first layer forming step of epitaxially growing a first SiGe layer on the Si substrate;
A second layer forming step of epitaxially growing a second SiGe layer directly on the first SiGe layer,
In the first layer forming step, the thickness of the first SiGe layer is set to be less than twice the critical thickness, which is a thickness at which dislocation occurs due to an increase in thickness and lattice relaxation occurs.
In the second layer forming step, the Ge composition ratio of the second SiGe layer is set to 0 lower than the maximum value in the layer of the Ge composition ratio of the first SiGe layer at the contact surface with the first SiGe layer. And forming a graded composition layer in which the entire layer has a Ge composition ratio that gradually increases from 0 toward the surface.

In the manufacturing method of the semiconductor substrate according to claim 7,
In the first layer forming step, the Ge composition ratio x of the first SiGe layer is made constant.

In the manufacturing method of the semiconductor substrate according to claim 7 or 8,
The method of manufacturing a semiconductor substrate, wherein the first SiGe layer has a Ge composition ratio x of 0.05 to 0.3.

In the manufacturing method of the semiconductor substrate in any one of Claim 7 to 9,
The method of manufacturing a semiconductor substrate, wherein the second SiGe layer is a gradient composition layer in which the entire layer has a Ge composition ratio that gradually increases from 0 to 0.3 toward the surface.

A method of manufacturing a semiconductor substrate in which a strained Si layer is formed on a Si substrate via a SiGe layer,
11. The strained Si layer is epitaxially grown directly or via another SiGe layer on the second SiGe layer of the semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 7. A method for manufacturing a semiconductor substrate.

A method of manufacturing a field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer,
A method for manufacturing a field effect transistor, comprising forming the channel region in the strained Si layer of a semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 11.