JP4277467B2 - Semiconductor substrate, field effect transistor, and manufacturing method thereof - Google Patents

Semiconductor substrate, field effect transistor, and manufacturing method thereof Download PDF

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JP4277467B2
JP4277467B2 JP2001331289A JP2001331289A JP4277467B2 JP 4277467 B2 JP4277467 B2 JP 4277467B2 JP 2001331289 A JP2001331289 A JP 2001331289A JP 2001331289 A JP2001331289 A JP 2001331289A JP 4277467 B2 JP4277467 B2 JP 4277467B2
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semiconductor substrate
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JP2003133548A (en
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一郎 塩野
一樹 水嶋
健志 山口
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Sumco Corp
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Description

【０００１】
【発明の属する技術分野】
本発明は、高速ＭＯＳＦＥＴ等に用いられる半導体基板及び電界効果型トランジスタ並びにこれらの製造方法に関する。
【０００２】
【従来の技術】
近年、Ｓｉ（シリコン）基板上にＳｉＧｅ（シリコン・ゲルマニウム）層を介してエピタキシャル成長した歪みＳｉ層をチャネル領域に用いた高速のＭＯＳＦＥＴ、ＭＯＤＦＥＴ、ＨＥＭＴが提案されている。この歪みＳｉ−ＦＥＴでは、Ｓｉに比べて格子定数の大きいＳｉＧｅによりＳｉ層に引っ張り歪みが生じ、そのためＳｉのバンド構造が変化して縮退が解けてキャリア移動度が高まる。したがって、この歪みＳｉ層をチャネル領域として用いることにより通常の１．３〜８倍程度の高速化が可能になるものである。また、プロセスとしてＣＺ法による通常のＳｉ基板を基板として使用でき、従来のＣＭＯＳ工程で高速ＣＭＯＳを実現可能にするものである。
【０００３】
しかしながら、ＦＥＴのチャネル領域として要望される上記歪みＳｉ層をエピタキシャル成長するには、Ｓｉ基板上に良質なＳｉＧｅ層をエピタキシャル成長する必要があるが、ＳｉとＳｉＧｅとの格子定数の違いから、転位等により結晶性に問題があった。このために、従来、以下のような種々の提案が行われていた。
【０００４】
例えば、ＳｉＧｅのＧｅ組成比を一定の緩い傾斜で増加させたバッファ層を用いる方法、Ｇｅ（ゲルマニウム）組成比をステップ状（階段状）に変化させたバッファ層を用いる方法、Ｇｅ組成比を超格子状に変化させたバッファ層を用いる方法及びＳｉのオフカットウェーハを用いてＧｅ組成比を一定の傾斜で変化させたバッファ層を用いる方法等が提案されている（U.S.Patent 5,442,205、U.S.Patent 5,221,413、PCT WO98/00857、特開平6-252046号公報等）。
【０００５】
【発明が解決しようとする課題】
しかしながら、上記従来の技術では、以下のような課題が残されている。
すなわち、上記従来の技術を用いて成膜されたＳｉＧｅ層は、貫通転位密度や表面ラフネスがデバイス及び製造プロセスとして要望されるレベルには及ばない状態であった。
例えば、Ｇｅ組成比を一定の緩い傾斜で増加させたバッファ層を用いる場合、Ｇｅ組成比の傾斜構造中で発生する転位は、ＳｉＧｅ層に沿った方向にのび易くなって、ＳｉＧｅ層の特に表面側で転位の密度を抑制することができる。しかし、まだ十分な低転位化を図ることができていない。
また、Ｇｅ組成比を階段状にしたバッファ層を用いる場合では、表面ラフネスを比較的少なくすることができるが、貫通転位密度が大きくなってしまう不都合があった。また、オフカットウェーハを用いる場合では、転位が成膜方向ではなく横に抜け易くなるが、まだ十分な低転位化を図ることができていない。
【０００６】
本発明は、前述の課題に鑑みてなされたもので、貫通転位密度をより低くすることができる半導体基板及び電界効果型トランジスタ並びにこれらの製造方法を提供することを目的とする。
【０００７】
【課題を解決するための手段】
本発明は、前記課題を解決するために以下の構成を採用した。
すなわち、本発明の半導体基板は、Ｓｉ基板と、該Ｓｉ基板上のＳｉＧｅ層とを備え、該ＳｉＧｅ層は、表面に向けて層内のＧｅ組成比が漸次減少するＳｉＧｅの傾斜組成層を複数層積層状態にして構成され、これらの傾斜組成層は、各上面のＧｅ組成比が表面に向けて順次増加しており、各傾斜組成層内で表面に向けてＧｅが減量した状態で前記ＳｉＧｅのＧｅ組成比を表面に向けて増加するよう変化させたことを特徴とする。
本発明の半導体基板の製造方法、Ｓｉ基板上にＳｉＧｅ層をエピタキシャル成長させた半導体基板の製造方法であって、前記Ｓｉ基板上に、ＳｉＧｅ層をエピタキシャル成長するＳｉＧｅ層形成工程を備え、該ＳｉＧｅ層形成工程は、表面に向けて層内のＧｅ組成比を漸次減少させたＳｉＧｅの傾斜組成層を複数層積層状態にすると共に、これらの傾斜組成層の各上面のＧｅ組成比を表面に向けて順次増加させて、各傾斜組成層内では表面に向けてＧｅが減量した状態としてＧｅ組成比が表面に向けて増加するよう変化させて前記ＳｉＧｅ層を形成することを特徴とする。
本発明の半導体基板は、Ｓｉ基板と、該Ｓｉ基板上のＳｉＧｅ層とを備え、該ＳｉＧｅ層は、表面に向けて層内のＧｅ組成比が漸次減少するＳｉＧｅの傾斜組成層を複数層積層状態にして構成され、これらの傾斜組成層は、各上面のＧｅ組成比が表面に向けて順次増加していることができる。
【０００８】
また、本発明の半導体基板の製造方法は、Ｓｉ基板上にＳｉＧｅ層をエピタキシャル成長させた半導体基板の製造方法であって、前記Ｓｉ基板上に、ＳｉＧｅ層をエピタキシャル成長するＳｉＧｅ層形成工程を備え、該ＳｉＧｅ層形成工程は、表面に向けて層内のＧｅ組成比を漸次減少させたＳｉＧｅの傾斜組成層を複数層積層状態にすると共に、これらの傾斜組成層の各上面のＧｅ組成比を表面に向けて順次増加させて前記ＳｉＧｅ層を形成することを特徴とする。
【０００９】
これらの半導体基板及び半導体基板の製造方法では、Ｓｉ基板上のＳｉＧｅ層を、表面に向けて層内のＧｅ組成比を漸次減少させたＳｉＧｅの傾斜組成層を複数層積層状態にして形成し、これらの傾斜組成層の各上面のＧｅ組成比を表面に向けて順次増加させているので、各傾斜組成層内で表面に向けてＧｅが減量しているため、転位は主に各層の界面付近で発生し、しかも、その界面付近に閉じ込められる傾向がある。その結果、表面に貫通する転位が低減される。
【００１０】
本発明の半導体基板は、Ｓｉ基板上にＳｉＧｅ層が形成された半導体基板であって、上記本発明の半導体基板の製造方法により作製されたことを特徴とする。すなわち、この半導体基板は、上記本発明の半導体基板の製造方法により作製されているので、表面の貫通転位が少なく、良好な表面ラフネスを有している。
【００１１】
本発明の半導体基板の製造方法は、研磨された前記ＳｉＧｅ層上に直接又は他のＳｉＧｅ層を介して歪みＳｉ層をエピタキシャル成長する工程を有することを特徴とする。
また、本発明の半導体基板は、Ｓｉ基板上にＳｉＧｅ層を介して歪みＳｉ層が形成された半導体基板であって、上記本発明の半導体基板の製造方法により作製されたことを特徴とする。
【００１２】
これらの半導体基板の製造方法及び半導体基板では、研磨された前記ＳｉＧｅ層上に直接又は他のＳｉＧｅ層を介して歪みＳｉ層がエピタキシャル成長されるので、欠陥が少なく、表面ラフネスの小さな良質な歪みＳｉ層が得られ、例えば歪みＳｉ層をチャネル領域とするＭＯＳＦＥＴ等を用いた集積回路用として好適な半導体基板を得ることができる。
【００１３】
本発明の電界効果型トランジスタの製造方法は、ＳｉＧｅ層上にエピタキシャル成長された歪みＳｉ層にチャネル領域が形成される電界効果型トランジスタの製造方法であって、上記本発明の歪みＳｉ層を有する半導体基板の製造方法により作製された半導体基板の前記歪みＳｉ層に前記チャネル領域を形成することを特徴とする。
また、本発明の電界効果型トランジスタは、ＳｉＧｅ層上にエピタキシャル成長された歪みＳｉ層にチャネル領域が形成される電界効果型トランジスタであって、上記本発明の電界効果型トランジスタの製造方法により作製されたことを特徴とする。
【００１４】
これらの電界効果型トランジスタの製造方法及び電界効果型トランジスタは、上記本発明の歪みＳｉ層を有する半導体基板の製造方法により作製された半導体基板の歪みＳｉ層にチャネル領域を形成するので、良質な歪みＳｉ層により高特性な電界効果型トランジスタを高歩留まりで得ることができる。
【００１５】
【発明の実施の形態】
以下、本発明に係る第１実施形態を、図１から図４を参照しながら説明する。
【００１６】
図１は、本発明の半導体ウェーハ（半導体基板）Ｗの断面構造を示すものであり、この半導体ウェーハの構造をその製造プロセスと合わせて説明すると、まず、ＣＺ法等で引上成長して作製されたｐ型あるいはｎ型Ｓｉ基板１上に、図１及び図２に示すように、第１のＳｉＧｅ層２を例えば減圧ＣＶＤ法によりエピタキシャル成長する。
【００１７】
この際、図２及び図３に示すように、表面に向けて層内のＧｅ組成比を漸次減少させたＳｉＧｅの傾斜組成層２ａを６層積層状態にして、第１のＳｉＧｅ層２を形成する。また、これらの傾斜組成層２ａの各上面のＧｅ組成比を、表面に向けて順次増加するように設定する。すなわち、本実施形態では、各傾斜組成層２ａの膜厚を０．２５μｍにし、減少するＧｅ組成比の傾斜率（表面に向けて減少するＧｅ組成比の変化率）を０．２／μｍとしていると共に、各上面でのＧｅ組成比を０から０．２５まで０．０５毎に順次増加させている。
【００１８】
次に、第１のＳｉＧｅ層２上に、Ｇｅ組成比が０．２５で一定組成比の第２のＳｉＧｅ層３を、緩和層としてエピタキシャル成長する。さらに、第２のＳｉＧｅ層３上にＳｉをエピタキシャル成長して歪みＳｉ層４を形成することにより、本実施形態の歪みＳｉ層を備えた半導体ウェーハＷが作製される。なお、各層の膜厚は、例えば、第１のＳｉＧｅ層２が１．５μｍ、第２のＳｉＧｅ層３が０．７〜０．８μｍ、歪みＳｉ層４が１５〜２２ｎｍである。
なお、上記減圧ＣＶＤ法による成膜は、例えばキャリアガスとしてＨ2を用い、ソースガスとしてＳｉＨ4及びＧｅＨ4を用いている。
【００１９】
このように本実施形態の半導体ウェーハＷでは、Ｓｉ基板１上の第１のＳｉＧｅ層２を、表面に向けて層内のＧｅ組成比を漸次減少させたＳｉＧｅの傾斜組成層２ａを複数層積層状態にして形成し、これらの傾斜組成層２ａの各上面のＧｅ組成比を表面に向けて順次増加させているので、各傾斜組成層２ａ内で表面に向けてＧｅが減量しているため、転位は主に各層の界面付近で発生し、しかも、その界面付近に閉じ込められる傾向がある。その結果、表面に貫通する転位が低減される。
【００２０】
次に、本発明の上記半導体ウェーハＷを用いた電界効果型トランジスタ（ＭＯＳＦＥＴ）を、その製造プロセスと合わせて図４を参照して説明する。
【００２１】
図４は、本発明の電界効果型トランジスタの概略的な構造を示すものであって、この電界効果型トランジスタを製造するには、上記の製造工程で作製した半導体ウェーハＷ表面の歪みＳｉ層４上にＳｉＯ2のゲート酸化膜５及びゲートポリシリコン膜６を順次堆積する。そして、チャネル領域となる部分上のゲートポリシリコン膜６上にゲート電極（図示略）をパターニングして形成する。
【００２２】
次に、ゲート酸化膜５もパターニングしてゲート電極下以外の部分を除去する。さらに、ゲート電極をマスクに用いたイオン注入により、歪みＳｉ層４及び第２のＳｉＧｅ層３にｎ型あるいはｐ型のソース領域Ｓ及びドレイン領域Ｄを自己整合的に形成する。この後、ソース領域Ｓ及びドレイン領域Ｄ上にソース電極及びドレイン電極（図示略）をそれぞれ形成して、歪みＳｉ層４がチャネル領域となるｎ型あるいはｐ型ＭＯＳＦＥＴが製造される。
【００２３】
このように作製されたＭＯＳＦＥＴでは、上記製法で作製された半導体ウェーハＷ上の歪みＳｉ層４にチャネル領域が形成されるので、良質な歪みＳｉ層４により高特性なＭＯＳＦＥＴを高歩留まりで得ることができる。
【００２４】
次に、本発明に係る第２〜第６実施形態について、図５から図９を参照して説明する。
【００２５】
第２実施形態と第１実施形態との異なる点は、第１実施形態では、傾斜組成層２ａを６層積層状態にして第１のＳｉＧｅ層２を形成しているのに対し、第２実施形態では、図５に示すように、傾斜組成層１２ａを７層積層状態にして第１のＳｉＧｅ層１２を形成している点である。
また、第３及び第４実施形態と第１実施形態との異なる点は、第１実施形態では、Ｇｅ組成比の傾斜率を０．２／μｍとした傾斜組成層２ａを６層積層状態にして第１のＳｉＧｅ層２を形成しているのに対し、第３及び第４実施形態では、図６及び図７に示すように、Ｇｅ組成比の傾斜率を０．４／μｍとした傾斜組成層２２ａ、３２ａを３層及び４層の積層状態にして第１のＳｉＧｅ層２２、３２をそれぞれ形成している点である。
【００２６】
さらに、第５及び第６実施形態と第３及び第４実施形態との異なる点は、第３及び第４実施形態では、傾斜組成層２２ａ、３２ａの各膜厚が０．２５μｍであるのに対し、第５及び第６実施形態では、図８及び図９に示すように、傾斜組成層４２ａｍ５２ａの各膜厚が０．５μｍであり、Ｇｅ組成比の傾斜率も０．２／μｍとされている点である。なお、第５実施形態では、傾斜組成層４２ａを３層積層状態にして第１のＳｉＧｅ層４２が形成され、第６実施形態では、傾斜組成層５２ａを４層積層状態にして第１のＳｉＧｅ層５２が形成されている。
【００２７】
これらの第２〜第６実施形態は、いずれも上記第１実施形態と同様に、第１のＳｉＧｅ層１２、２２、３２、４２、５２を、表面に向けて層内のＧｅ組成比を漸次減少させたＳｉＧｅの傾斜組成層１２ａ、２２ａ、３２ａ、４２ａ、５２ａを複数層積層状態にして形成し、これらの傾斜組成層の各上面のＧｅ組成比を表面に向けて順次増加させているので、転位は主に各層の界面付近で発生し、しかも、その界面付近に閉じ込められる傾向がある。その結果、表面に貫通する転位が低減される。
【００２８】
なお、本発明の技術範囲は上記実施の形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲において種々の変更を加えることが可能である。
【００２９】
例えば、上記各実施形態では、傾斜組成層の各膜厚は一定に設定したが、異なる膜厚の傾斜組成層を積層して第１のＳｉＧｅ層を構成しても構わない。例えば、Ｇｅ組成比が増加するほど傾斜組成層の膜厚を厚く設定してもよい。
また、上記各実施形態では、傾斜組成層内で膜厚に対して一定割合で組成を変化させたが、その割合を一定でなくした構造としても構わない。
また、上記各実施形態の半導体ウェーハの歪みＳｉ層上に、さらにＳｉＧｅ層を成膜しても構わない。
【００３０】
また、上記各実施形態では、ＭＯＳＦＥＴ用の基板としてＳｉＧｅ層を有する半導体ウェーハを作製したが、他の用途に適用する基板としても構わない。例えば、本発明の半導体基板の製造方法及び半導体基板を太陽電池や光素子用の基板に適用してもよい。すなわち、上述した各実施形態のＳｉ基板上に最表面で６５％から１００％Ｇｅあるいは、１００％Ｇｅとなるように第１のＳｉＧｅ層及び第２のＳｉＧｅ層を成膜し、さらにこの上にＩｎＧａＰ（インジウムガリウムリン）あるいはＧａＡｓ（ガリウムヒ素）やＡｌＧａＡｓ（アルミニウムガリウムヒ素）を成膜することで、太陽電池や光素子用基板を作製してもよい。この場合、低転位密度で高特性の太陽電池用基板が得られる。
【００３１】
【発明の効果】
本発明によれば、以下の効果を奏する。
本発明の半導体基板及び半導体基板の製造方法によれば、Ｓｉ基板上のＳｉＧｅ層を、表面に向けて層内のＧｅ組成比を漸次減少させたＳｉＧｅの傾斜組成層を複数層積層状態にして形成し、これらの傾斜組成層の各上面のＧｅ組成比を表面に向けて順次増加させているので、転位は主に各層の界面付近で発生し、しかも、その界面付近に閉じ込められる傾向がある。その結果、表面に貫通する転位が低減される。しかも、良好な表面ラフネスも得ることができる。
【００３２】
また、本発明の電界効果型トランジスタ及び電界効果型トランジスタの製造方法によれば、上記本発明の半導体基板又は上記本発明の半導体基板の製造方法により作製された半導体基板の前記歪みＳｉ層に前記チャネル領域が形成されるので、良質な歪みＳｉ層により高特性なＭＯＳＦＥＴを高歩留まりで得ることができる。
【図面の簡単な説明】
【図１】 本発明に係る第１実施形態における半導体基板を示す断面図である。
【図２】 本発明に係る第１実施形態における第１のＳｉＧｅ層を示す断面図である。
【図３】 本発明に係る第１実施形態における第１のＳｉＧｅ層及び第２のＳｉＧｅ層の膜厚に対するＧｅ組成比を示すグラフである。
【図４】 本発明に係る第１実施形態におけるＭＯＳＦＥＴを示す概略的な断面図である。
【図５】 本発明に係る第２実施形態における第１のＳｉＧｅ層及び第２のＳｉＧｅ層の膜厚に対するＧｅ組成比を示すグラフである。
【図６】 本発明に係る第３実施形態における第１のＳｉＧｅ層及び第２のＳｉＧｅ層の膜厚に対するＧｅ組成比を示すグラフである。
【図７】 本発明に係る第４実施形態における第１のＳｉＧｅ層及び第２のＳｉＧｅ層の膜厚に対するＧｅ組成比を示すグラフである。
【図８】 本発明に係る第５実施形態における第１のＳｉＧｅ層及び第２のＳｉＧｅ層の膜厚に対するＧｅ組成比を示すグラフである。
【図９】 本発明に係る第６実施形態における第１のＳｉＧｅ層及び第２のＳｉＧｅ層の膜厚に対するＧｅ組成比を示すグラフである。
【符号の説明】
１ Ｓｉ基板
２、１２、２２、３２、４２、５２ 第１のＳｉＧｅ層
２ａ、１２ａ、２２ａ、３２ａ、４２ａ、５２ａ 傾斜組成層
３ 第２のＳｉＧｅ層
４ 歪みＳｉ層
５ ＳｉＯ2ゲート酸化膜
６ ゲートポリシリコン膜
Ｓ ソース領域
Ｄ ドレイン領域
Ｗ 半導体ウェーハ（半導体基板）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor substrate and a field effect transistor used for a high-speed MOSFET and the like, and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, high-speed MOSFETs, MODFETs, and HEMTs using a strained Si layer epitaxially grown on a Si (silicon) substrate via a SiGe (silicon-germanium) layer as a channel region have been proposed. In this strained Si-FET, tensile strain is generated in the Si layer due to SiGe having a larger lattice constant than Si, so that the band structure of Si is changed, the degeneracy is solved, and the carrier mobility is increased. Therefore, by using this strained Si layer as the channel region, the speed can be increased by about 1.3 to 8 times the normal speed. Further, a normal Si substrate by the CZ method can be used as a substrate as a process, and a high-speed CMOS can be realized by a conventional CMOS process.
[0003]
However, in order to epitaxially grow the strained Si layer required as the channel region of the FET, it is necessary to epitaxially grow a high-quality SiGe layer on the Si substrate, but due to the difference in lattice constant between Si and SiGe, There was a problem with crystallinity. For this purpose, various proposals have been made in the past.
[0004]
For example, a method using a buffer layer in which the Ge composition ratio of SiGe is increased at a constant gentle slope, a method using a buffer layer in which the Ge (germanium) composition ratio is changed stepwise (stepped), and a Ge composition ratio exceeding There have been proposed a method using a buffer layer changed into a lattice shape and a method using a buffer layer in which the Ge composition ratio is changed at a constant gradient using a Si off-cut wafer (US Patent 5,442,205, US Patent 5,221,413, PCT). WO98 / 00857, JP-A-62-252046, etc.).
[0005]
[Problems to be solved by the invention]
However, the following problems remain in the conventional technology.
That is, the SiGe layer formed by using the above-described conventional technique is in a state where the threading dislocation density and the surface roughness do not reach the level required for the device and the manufacturing process.
For example, when using a buffer layer whose Ge composition ratio is increased at a constant gentle slope, dislocations that occur in the slope structure of the Ge composition ratio are likely to extend in the direction along the SiGe layer, and particularly the surface of the SiGe layer. The density of dislocations can be suppressed on the side. However, a sufficient reduction in dislocation has not been achieved yet.
In addition, when a buffer layer having a Ge composition ratio in a step shape is used, the surface roughness can be relatively reduced, but there is a disadvantage that the threading dislocation density is increased. Further, in the case of using an off-cut wafer, dislocations easily escape laterally rather than in the film forming direction, but a sufficiently low dislocation has not yet been achieved.
[0006]
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor substrate, a field effect transistor, and a manufacturing method thereof that can further reduce threading dislocation density.
[0007]
[Means for Solving the Problems]
The present invention employs the following configuration in order to solve the above problems.
That is, the semiconductor substrate of the present invention includes a Si substrate and a SiGe layer on the Si substrate, and the SiGe layer includes a plurality of SiGe graded composition layers in which the Ge composition ratio in the layer gradually decreases toward the surface. These graded composition layers are composed of layered layers, and the Ge composition ratio of each upper surface sequentially increases toward the surface, and the SiGe is reduced in a state where Ge is reduced toward the surface in each graded composition layer. The Ge composition ratio is changed so as to increase toward the surface.
A method of manufacturing a semiconductor substrate according to the present invention, a method of manufacturing a semiconductor substrate in which a SiGe layer is epitaxially grown on a Si substrate, comprising a SiGe layer forming step of epitaxially growing a SiGe layer on the Si substrate, and forming the SiGe layer In the process, a gradient composition layer of SiGe in which the Ge composition ratio in the layer is gradually decreased toward the surface is made into a multilayered state, and the Ge composition ratio of each upper surface of these gradient composition layers is sequentially directed to the surface. The SiGe layer is formed by changing the Ge composition ratio so that the Ge composition ratio increases toward the surface in a state where Ge is decreased toward the surface in each graded composition layer.
The semiconductor substrate of the present invention includes a Si substrate and a SiGe layer on the Si substrate, and the SiGe layer is formed by laminating a plurality of graded composition layers of SiGe in which the Ge composition ratio in the layer gradually decreases toward the surface. is constructed in the state, these gradient composition layer, Ru can Ge composition ratio of the upper surface is sequentially increased toward the surface.
[0008]
The semiconductor substrate manufacturing method of the present invention is a semiconductor substrate manufacturing method in which a SiGe layer is epitaxially grown on a Si substrate, comprising a SiGe layer forming step of epitaxially growing a SiGe layer on the Si substrate, In the SiGe layer forming step, a plurality of SiGe graded composition layers in which the Ge composition ratio in the layer is gradually reduced toward the surface are made into a laminated state, and the Ge composition ratio of each upper surface of these graded composition layers is set on the surface. The SiGe layer is formed by sequentially increasing the thickness.
[0009]
In these semiconductor substrates and semiconductor substrate manufacturing methods, the SiGe layer on the Si substrate is formed in a multi-layered state with a SiGe gradient composition layer in which the Ge composition ratio in the layer is gradually reduced toward the surface, Since the Ge composition ratio of each upper surface of these graded composition layers is sequentially increased toward the surface, the amount of Ge is reduced toward the surface in each graded composition layer, so the dislocation is mainly near the interface of each layer. And tends to be trapped near the interface. As a result, dislocations penetrating the surface are reduced.
[0010]
The semiconductor substrate of the present invention is a semiconductor substrate in which a SiGe layer is formed on a Si substrate, and is manufactured by the method for manufacturing a semiconductor substrate of the present invention. That is, since this semiconductor substrate is manufactured by the method for manufacturing a semiconductor substrate of the present invention, the surface has few threading dislocations and has a good surface roughness.
[0011]
The method for producing a semiconductor substrate according to the present invention includes a step of epitaxially growing a strained Si layer directly on the polished SiGe layer or via another SiGe layer.
The semiconductor substrate of the present invention is a semiconductor substrate in which a strained Si layer is formed on a Si substrate via a SiGe layer, and is produced by the semiconductor substrate manufacturing method of the present invention.
[0012]
In these semiconductor substrate manufacturing methods and semiconductor substrates, since the strained Si layer is epitaxially grown directly on the polished SiGe layer or via another SiGe layer, a high-quality strained Si with few defects and small surface roughness. For example, a semiconductor substrate suitable for an integrated circuit using a MOSFET or the like having a strained Si layer as a channel region can be obtained.
[0013]
The method for producing a field effect transistor of the present invention is a method for producing a field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer, the semiconductor having the strained Si layer of the present invention. The channel region is formed in the strained Si layer of a semiconductor substrate manufactured by a substrate manufacturing method.
The field effect transistor of the present invention is a field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer, and is manufactured by the method for manufacturing a field effect transistor of the present invention. It is characterized by that.
[0014]
These field effect transistor manufacturing methods and field effect transistors have good quality because the channel region is formed in the strained Si layer of the semiconductor substrate manufactured by the semiconductor substrate manufacturing method having the strained Si layer of the present invention. A high-performance field effect transistor can be obtained with a high yield by the strained Si layer.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
A first embodiment according to the present invention will be described below with reference to FIGS.
[0016]
FIG. 1 shows a cross-sectional structure of a semiconductor wafer (semiconductor substrate) W of the present invention. The structure of this semiconductor wafer will be described together with its manufacturing process. As shown in FIGS. 1 and 2, the first SiGe layer 2 is epitaxially grown on the p-type or n-type Si substrate 1 by, for example, a low pressure CVD method.
[0017]
At this time, as shown in FIGS. 2 and 3, the SiGe gradient composition layer 2a in which the Ge composition ratio in the layer is gradually decreased toward the surface is made into a six-layered state, and the first SiGe layer 2 is formed. To do. Further, the Ge composition ratio of each upper surface of the gradient composition layer 2a is set so as to increase sequentially toward the surface. That is, in this embodiment, the thickness of each gradient composition layer 2a is set to 0.25 μm, and the decreasing rate of the Ge composition ratio (the rate of change of the Ge composition ratio decreasing toward the surface) is set to 0.2 / μm. In addition, the Ge composition ratio on each upper surface is sequentially increased from 0 to 0.25 every 0.05.
[0018]
Next, a second SiGe layer 3 having a Ge composition ratio of 0.25 and a constant composition ratio is epitaxially grown on the first SiGe layer 2 as a relaxation layer. Further, by epitaxially growing Si on the second SiGe layer 3 to form the strained Si layer 4, the semiconductor wafer W provided with the strained Si layer of this embodiment is manufactured. The thickness of each layer is, for example, 1.5 μm for the first SiGe layer 2, 0.7 to 0.8 μm for the second SiGe layer 3, and 15 to 22 nm for the strained Si layer 4.
The film formation by the low pressure CVD method uses, for example, H 2 as a carrier gas and SiH 4 and GeH 4 as source gases.
[0019]
As described above, in the semiconductor wafer W of the present embodiment, the first SiGe layer 2 on the Si substrate 1 is laminated with a plurality of SiGe graded composition layers 2a in which the Ge composition ratio in the layer is gradually decreased toward the surface. Since the Ge composition ratio of each upper surface of these graded composition layers 2a is sequentially increased toward the surface, Ge is decreased toward the surface in each graded composition layer 2a. Dislocations mainly occur near the interface of each layer and tend to be confined near the interface. As a result, dislocations penetrating the surface are reduced.
[0020]
Next, a field effect transistor (MOSFET) using the semiconductor wafer W of the present invention will be described with reference to FIG. 4 together with its manufacturing process.
[0021]
FIG. 4 shows a schematic structure of the field effect transistor of the present invention. In order to manufacture this field effect transistor, the strained Si layer 4 on the surface of the semiconductor wafer W manufactured in the above manufacturing process is shown. An SiO 2 gate oxide film 5 and a gate polysilicon film 6 are sequentially deposited thereon. Then, a gate electrode (not shown) is formed by patterning on the gate polysilicon film 6 on the portion to become the channel region.
[0022]
Next, the gate oxide film 5 is also patterned to remove portions other than those under the gate electrode. Further, an n-type or p-type source region S and drain region D are formed in a self-aligned manner in the strained Si layer 4 and the second SiGe layer 3 by ion implantation using the gate electrode as a mask. Thereafter, a source electrode and a drain electrode (not shown) are formed on the source region S and the drain region D, respectively, and an n-type or p-type MOSFET in which the strained Si layer 4 serves as a channel region is manufactured.
[0023]
In the MOSFET manufactured in this way, a channel region is formed in the strained Si layer 4 on the semiconductor wafer W manufactured by the above-described manufacturing method, so that a high-quality MOSFET can be obtained with a high yield by using the high-quality strained Si layer 4. Can do.
[0024]
Next, 2nd-6th embodiment which concerns on this invention is described with reference to FIGS.
[0025]
The difference between the second embodiment and the first embodiment is that, in the first embodiment, the first SiGe layer 2 is formed with six graded composition layers 2a stacked, whereas the second embodiment is different from the first embodiment. In the embodiment, as shown in FIG. 5, the first SiGe layer 12 is formed with seven graded composition layers 12a laminated.
Further, the difference between the third and fourth embodiments and the first embodiment is that, in the first embodiment, the gradient composition layer 2a having a Ge composition ratio gradient of 0.2 / μm is made into a six-layer laminated state. The first SiGe layer 2 is formed, whereas in the third and fourth embodiments, as shown in FIGS. 6 and 7, the gradient of the Ge composition ratio is 0.4 / μm. The first and second SiGe layers 22 and 32 are formed by stacking the composition layers 22a and 32a into three and four layers, respectively.
[0026]
Furthermore, the fifth and sixth embodiments are different from the third and fourth embodiments in that the thicknesses of the gradient composition layers 22a and 32a are 0.25 μm in the third and fourth embodiments. On the other hand, in the fifth and sixth embodiments, as shown in FIGS. 8 and 9, each thickness of the gradient composition layer 42am52a is 0.5 μm, and the gradient ratio of the Ge composition ratio is 0.2 / μm. It is a point. In the fifth embodiment, the first SiGe layer 42 is formed by stacking the graded composition layer 42a in three layers, and in the sixth embodiment, the first SiGe layer 42 is formed by stacking the graded composition layer 52a in four layers. A layer 52 is formed.
[0027]
In these second to sixth embodiments, as in the first embodiment, the first SiGe layers 12, 22, 32, 42, 52 are directed toward the surface, and the Ge composition ratio in the layers is gradually increased. The reduced SiGe graded composition layers 12a, 22a, 32a, 42a, 52a are formed in a laminated state, and the Ge composition ratio of each upper surface of these graded composition layers is sequentially increased toward the surface. Dislocations mainly occur near the interface of each layer and tend to be confined near the interface. As a result, dislocations penetrating the surface are reduced.
[0028]
The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.
[0029]
For example, in each of the embodiments described above, each thickness of the gradient composition layer is set to be constant, but the first SiGe layer may be configured by stacking gradient composition layers having different thicknesses. For example, the thickness of the gradient composition layer may be set larger as the Ge composition ratio increases.
In each of the above embodiments, the composition is changed at a constant ratio with respect to the film thickness in the gradient composition layer, but a structure in which the ratio is not constant may be used.
Further, a SiGe layer may be further formed on the strained Si layer of the semiconductor wafer of each of the above embodiments.
[0030]
In each of the above embodiments, a semiconductor wafer having a SiGe layer is manufactured as a substrate for MOSFET. However, the substrate may be applied to other applications. For example, you may apply the manufacturing method and semiconductor substrate of the semiconductor substrate of this invention to the board | substrate for solar cells or an optical element. That is, the first SiGe layer and the second SiGe layer are formed on the Si substrate of each of the above-described embodiments so that the outermost surface has 65% to 100% Ge or 100% Ge, and further on this. A substrate for a solar cell or an optical element may be manufactured by depositing InGaP (indium gallium phosphide), GaAs (gallium arsenide), or AlGaAs (aluminum gallium arsenide). In this case, a solar cell substrate having low dislocation density and high characteristics can be obtained.
[0031]
【The invention's effect】
The present invention has the following effects.
According to the semiconductor substrate and the method of manufacturing a semiconductor substrate of the present invention, the SiGe layer on the Si substrate is turned into a multi-layer laminated state with a SiGe graded composition layer in which the Ge composition ratio in the layer is gradually decreased toward the surface. Since the Ge composition ratio of each upper surface of these graded composition layers is sequentially increased toward the surface, dislocations mainly occur near the interface of each layer and tend to be confined near that interface. . As a result, dislocations penetrating the surface are reduced. In addition, good surface roughness can be obtained.
[0032]
Further, according to the field effect transistor and the method of manufacturing a field effect transistor of the present invention, the strained Si layer of the semiconductor substrate of the present invention or the semiconductor substrate manufactured by the method of manufacturing the semiconductor substrate of the present invention is Since the channel region is formed, a high-quality MOSFET can be obtained with a high yield by a high-quality strained Si layer.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a semiconductor substrate according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a first SiGe layer in the first embodiment according to the present invention.
FIG. 3 is a graph showing a Ge composition ratio with respect to film thicknesses of a first SiGe layer and a second SiGe layer in the first embodiment according to the present invention.
FIG. 4 is a schematic cross-sectional view showing a MOSFET according to the first embodiment of the invention.
FIG. 5 is a graph showing the Ge composition ratio with respect to the film thickness of the first SiGe layer and the second SiGe layer in the second embodiment according to the present invention.
FIG. 6 is a graph showing a Ge composition ratio with respect to film thicknesses of a first SiGe layer and a second SiGe layer in a third embodiment according to the present invention.
FIG. 7 is a graph showing a Ge composition ratio with respect to film thicknesses of a first SiGe layer and a second SiGe layer in a fourth embodiment according to the present invention.
FIG. 8 is a graph showing a Ge composition ratio with respect to film thicknesses of a first SiGe layer and a second SiGe layer in a fifth embodiment according to the present invention.
FIG. 9 is a graph showing a Ge composition ratio with respect to film thicknesses of a first SiGe layer and a second SiGe layer in a sixth embodiment according to the present invention.
[Explanation of symbols]
1 Si substrate 2,12,22,32,42,52 first SiGe layer 2a, 12a, 22a, 32a, 42a, 52a gradient composition layer 3 and the second SiGe layer 4 strained Si layer 5 SiO 2 gate oxide film 6 Gate polysilicon film S Source region D Drain region W Semiconductor wafer (semiconductor substrate)

Claims (9)

Ｓｉ基板と、
該Ｓｉ基板上のＳｉＧｅ層とを備え、
該ＳｉＧｅ層は、表面に向けて層内のＧｅ組成比が漸次減少するＳｉＧｅの傾斜組成層を複数層積層状態にして構成され、これらの傾斜組成層は、各上面のＧｅ組成比が表面に向けて順次増加しており、各傾斜組成層内で表面に向けてＧｅが減量した状態で前記ＳｉＧｅのＧｅ組成比を表面に向けて増加するよう変化させたことを特徴とする半導体基板。A Si substrate;
A SiGe layer on the Si substrate;
The SiGe layer is formed by laminating a plurality of SiGe graded composition layers in which the Ge composition ratio in the layer gradually decreases toward the surface, and the graded composition layer has a Ge composition ratio of each upper surface on the surface. A semiconductor substrate , wherein the Ge composition ratio of the SiGe is changed to increase toward the surface in a state where Ge is gradually decreased toward the surface in each graded composition layer . 請求項１に記載の半導体基板の前記ＳｉＧｅ層上に直接又は他のＳｉＧｅ層を介して配された歪みＳｉ層を備えていることを特徴とする半導体基板。  A semiconductor substrate comprising a strained Si layer disposed directly or via another SiGe layer on the SiGe layer of the semiconductor substrate according to claim 1. ＳｉＧｅ層上の歪みＳｉ層にチャネル領域を有する電界効果型トランジスタであって、
請求項２に記載の半導体基板の前記歪みＳｉ層に前記チャネル領域を有することを特徴とする電界効果型トランジスタ。A field effect transistor having a channel region in a strained Si layer on a SiGe layer,
A field effect transistor comprising the channel region in the strained Si layer of the semiconductor substrate according to claim 2. Ｓｉ基板上にＳｉＧｅ層をエピタキシャル成長させた半導体基板の製造方法であって、
前記Ｓｉ基板上に、ＳｉＧｅ層をエピタキシャル成長するＳｉＧｅ層形成工程を備え、
該ＳｉＧｅ層形成工程は、表面に向けて層内のＧｅ組成比を漸次減少させたＳｉＧｅの傾斜組成層を複数層積層状態にすると共に、これらの傾斜組成層の各上面のＧｅ組成比を表面に向けて順次増加させて、各傾斜組成層内では表面に向けてＧｅが減量した状態としてＧｅ組成比が表面に向けて増加するよう変化させて前記ＳｉＧｅ層を形成することを特徴とする半導体基板の製造方法。A method of manufacturing a semiconductor substrate in which a SiGe layer is epitaxially grown on a Si substrate,
A SiGe layer forming step of epitaxially growing a SiGe layer on the Si substrate;
In the SiGe layer forming step, a SiGe graded composition layer in which the Ge composition ratio in the layer is gradually reduced toward the surface is made into a multilayered state, and the Ge composition ratio of each upper surface of these graded composition layers is changed to the surface. The SiGe layer is formed by changing the Ge composition ratio so that the Ge composition ratio increases toward the surface as the Ge is decreased toward the surface in each graded composition layer. A method for manufacturing a substrate. Ｓｉ基板上にＳｉＧｅ層を介して歪みＳｉ層が形成された半導体基板の製造方法であって、
請求項４に記載の半導体基板の製造方法により作製された半導体基板の前記ＳｉＧｅ層上に直接又は他のＳｉＧｅ層を介して前記歪みＳｉ層をエピタキシャル成長することを特徴とする半導体基板の製造方法。A method of manufacturing a semiconductor substrate in which a strained Si layer is formed on a Si substrate via a SiGe layer,
A method for producing a semiconductor substrate, comprising: epitaxially growing the strained Si layer directly on the SiGe layer of the semiconductor substrate produced by the method for producing a semiconductor substrate according to claim 4 or via another SiGe layer. ＳｉＧｅ層上にエピタキシャル成長された歪みＳｉ層にチャネル領域が形成される電界効果型トランジスタの製造方法であって、
請求項５に記載の半導体基板の製造方法により作製された半導体基板の前記歪みＳｉ層に前記チャネル領域を形成することを特徴とする電界効果型トランジスタの製造方法。A method of manufacturing a field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer,
A method for manufacturing a field effect transistor, comprising forming the channel region in the strained Si layer of a semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 5. Ｓｉ基板上にＳｉＧｅ層が形成された半導体基板であって、
請求項４に記載の半導体基板の製造方法により作製されたことを特徴とする半導体基板。A semiconductor substrate having a SiGe layer formed on a Si substrate,
A semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 4. Ｓｉ基板上にＳｉＧｅ層を介して歪みＳｉ層が形成された半導体基板であって、
請求項５に記載の半導体基板の製造方法により作製されたことを特徴とする半導体基板。A semiconductor substrate in which a strained Si layer is formed on a Si substrate via a SiGe layer,
A semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 5. ＳｉＧｅ層上にエピタキシャル成長された歪みＳｉ層にチャネル領域が形成される電界効果型トランジスタであって、
請求項６に記載の電界効果型トランジスタの製造方法により作製されたことを特徴とする電界効果型トランジスタ。A field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer,
A field effect transistor manufactured by the method for manufacturing a field effect transistor according to claim 6.
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