JP2002359188A - METHOD FOR FORMING STRAINED Si LAYER, METHOD FOR MANUFACTURING FIELD EFFECT TRANSISTOR, SEMICONDUCTOR SUBSTRATE AND FIELD EFFECT TRANSISTOR - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming a strained Si layer, a method for manufacturing a field effect transistor, a semiconductor substrate and a field effect transistor in which a strained Si layer of good quality can be formed thicker than a conventional one. SOLUTION: The method for forming a strained Si layer 4 on an Si substrate through an SiGe buffer layer 3 comprises a step for forming the SiGe buffer layer on the Si substrate, a step for polishing the surface of the SiGe buffer layer to planarize at least cross-hatch like irregularities on the surface, and a step for epitaxially growing the strained Si layer on the planarized SiGe buffer layer directly or through other SiGe layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high-speed MOSFET
The present invention relates to a method for forming a strained Si layer and a method for manufacturing a field-effect transistor, and a semiconductor substrate and a field-effect transistor.

[0002]

2. Description of the Related Art In recent years, S (silicon) wafers have
High-speed MOSFETs, MODFETs, and HEMTs using a strained Si layer epitaxially grown via an iGe (silicon-germanium) layer as a channel region have been proposed. In this strained Si-FET, tensile strain occurs in the Si layer due to SiGe having a larger lattice constant than that of Si, so that the band structure of Si changes and the degeneracy is released, thereby increasing the carrier mobility. Therefore, by using this strained Si layer as a channel region, the normal 1.5 to
The speed can be increased about eight times. Further, a normal Si substrate by the CZ method can be used as a substrate as a process, and a high-speed CMOS can be realized by a conventional CMOS process.

[0003]

However, the above-mentioned conventional technique has the following problems. That is, when the strained Si layer desired as a channel region of the FET is epitaxially grown on the SiGe layer,
High quality films could only be obtained up to a certain film thickness regardless of the film formation conditions. For example, when the Ge composition ratio on the surface of the SiGe layer was 0.3, a high-quality strained Si layer with few defects could be formed only up to a thickness of about 30 nm. Although it depends on the MOSFET design, it is generally said that carriers in the inversion layer penetrate from the surface to about 400 nm ("Silicon Processing for the VLSIEra").
Volume 3: The Submicron MOSFET ", by Stanley Wolf (L
attice Press, 1995, California), it is believed that if the interface with the SiGe layer is as shallow as 30 nm, the interface will affect the operating characteristics of the device. Therefore, in order to improve the operating characteristics of the MOSFET,
There is a need for a strained Si layer with better quality interfaces. However, in a substrate having a conventional strained Si layer, Si
Since cross-hatched irregularities called cross-hatches on the surface of the Ge layer exist, the same level of roughness is present on the interface and surface of the strained Si layer, which has been a problem. Further, in order to leave a high-quality strained Si layer having a sufficient thickness even after cleaning of a wafer, formation of an oxide film, or heat treatment in a device process, a thicker high-quality strained Si layer is required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and is intended to form a strained Si layer capable of forming a high-quality strained Si layer having a small interface and a small surface roughness and having few defects. It is an object to provide a method and a method for manufacturing a field-effect transistor, and a semiconductor substrate and a field-effect transistor.

[0005]

Means for Solving the Problems The present inventors have proposed SiGe.
As a result of research on the technology of epitaxially growing a strained Si layer on a layer, when the strained Si layer is lattice-relaxed, first, dislocations are formed in the strained Si layer above the cross hatch on the surface of the underlying SiGe layer. It turned out to be focused. As a result of lattice relaxation, it has been found that a distorted Si layer having a thickness greater than about 30 nm has a low quality. The present invention has been obtained from the above findings, and has the following configurations to solve the above-mentioned problems.

That is, the method for forming a strained Si layer according to the present invention comprises the steps of: forming a strained Si layer on a Si substrate via a SiGe buffer layer;
A method for forming a layer, comprising:
Forming a Ge buffer layer, polishing the surface of the SiGe buffer layer to flatten at least cross-hatched irregularities on the surface, and directly or other SiGe on the flattened SiGe buffer layer. Strained Si through the layer
Epitaxially growing a layer.

In this method for forming a strained Si layer, SiGe
By polishing the surface of the buffer layer to flatten at least the cross-hatch irregularities on the surface, a strained Si layer can be formed on the SiGe buffer layer from which irregularities where dislocations are concentrated can be removed, so that a thicker and higher quality A good film can be obtained.

The method for forming a strained Si layer according to the present invention comprises the steps of:
The step of forming the SiGe buffer layer includes epitaxially growing a first SiGe layer at least partially including a graded composition layer having a Ge composition ratio gradually increased on the Si substrate; and forming the first SiGe layer on the Si substrate. Epitaxial growth of a second SiGe layer at a constant Ge composition ratio on the layer.

That is, in the method of forming the strained Si layer, the second SiGe layer having a constant composition layer is formed after forming the first SiGe layer including the gradient composition layer. Generation and growth of dislocations can be suppressed, and the dislocation density on the surface of the final SiGe layer can be reduced.

[0010] The semiconductor substrate of the present invention comprises a Si substrate
A semiconductor substrate on which a strained Si layer is formed via a Ge layer, wherein the strained Si layer is formed by the strained Si layer forming method of the present invention. In this semiconductor substrate, since the strained Si layer is formed by the above-described method for forming a strained Si layer of the present invention, it is suitable as, for example, a Si substrate for an integrated circuit using a MOSFET or the like having the strained Si layer as a channel region. .

The method of manufacturing a field-effect transistor according to the present invention is characterized in that the strain S
A method for manufacturing a field-effect transistor in which a channel region is formed in an i-layer, wherein the strained Si layer is formed by the method for forming a strained Si layer according to the present invention. Further, the field-effect transistor of the present invention is formed of SiG
a field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on the e layer,
According to the method for forming a strained Si layer of the present invention, the strained Si
It is characterized in that a layer is formed.

In the method for manufacturing a field-effect transistor and the field-effect transistor, the strained Si layer in which the channel region is formed is formed by the above-described method for forming the strained Si layer of the present invention. A high-quality strained Si layer having a small roughness and a small number of defects makes it possible to obtain a field-effect transistor excellent in operation characteristics at a high yield.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to FIGS.

FIG. 1 shows a cross-sectional structure of a semiconductor wafer (semiconductor substrate) W of the present invention. The structure of this semiconductor wafer will be described together with its manufacturing process.
First, as shown in FIG. 1 and FIG. 2, on a Si substrate 1 manufactured by pulling-up by the CZ method, a gradient in which the Ge composition ratio x gradually increases with a gradient in the film forming direction from 0 to 0.3. The first SiGe layer 2 which is a composition layer is epitaxially grown by a low pressure CVD method. Note that the film formation by the low pressure CVD method uses H ₂ as a carrier gas and SiH ₄ and GeH ₄ as a source gas.

Next, the first SGe layer is formed on the first SiGe layer 2.
At the final Ge composition ratio (0.3) of the iGe layer 2, the second SiGe layer 3 which is a constant composition layer and a relaxation layer is epitaxially grown. These first SiGe layer 2 and second SGe
The iGe layer 3 functions as a SiGe buffer layer for forming a strained Si layer. Thus, the first of the graded composition layers
After the formation of the SiGe layer 2 of the second composition, the second Si
Since the Ge layer 3 is formed, the generation and growth of dislocations in the second SiGe layer 3 can be suppressed, and the final second S
The dislocation density on the surface of the iGe layer 3 can be reduced.

On the wafer surface in the above state, as shown in FIG. 3A, lattice-like (cross-hatch-like) irregularities caused by lattice relaxation of SiGe, so-called cross-hatch C, occur. For this reason, next, the wafer in the above state is taken out of the low pressure CVD furnace, and the second SiGe
The surface of the layer 3 is polished to remove at least a cross hatch on the surface and flattened. For example, since the groove in the unevenness of the cross hatch C has a depth of about 20 to 30 nm, it is polished at least about 30 nm, and desirably, the surface roughness is reduced to 1 nm or less, which is a normal wafer level.

After the polishing, the low pressure CVD method is again applied to the substrate shown in FIG.
As shown in FIG. 3B, the strained Si layer 4 is formed by epitaxially growing Si on the flattened second SiGe layer 3, whereby the semiconductor wafer W of the present embodiment is manufactured. In the present embodiment, for example, the first Si
Ge layer 2 is 1.5 μm, second SiGe layer 3 is 0.7 μm
It is 0.8 μm.

In this embodiment, the surface of the first SiGe layer 3 is polished to flatten at least the cross-hatched irregularities on the surface, so that the irregularities on which dislocations are concentrated are removed from the second SiGe layer 3. Since the strained Si layer 4 can be formed on the substrate, a thicker and higher quality film can be obtained than before.

Next, a field effect transistor (MOSFET) using the semiconductor wafer W of the present invention will be described with reference to FIGS.

FIG. 4 shows a schematic structure of the field-effect transistor of the present invention. In order to manufacture this field-effect transistor, the surface of the semiconductor wafer W manufactured in the above-described manufacturing process is deformed. On the Si layer 4, a gate oxide film 5 of SiO ₂ and a gate polysilicon film 6 are sequentially deposited. Then, a gate electrode (not shown) is formed by patterning on the gate polysilicon film 6 on a portion to be a channel region.

Next, the gate oxide film 5 is also patterned to remove portions other than those below the gate electrode. Further, an n-type or p-type source region S and a drain region D are formed in the strained Si layer 4 and the relaxation layer 3 in a self-aligned manner by ion implantation using the gate electrode as a mask. Thereafter, a source electrode and a drain electrode (not shown) are respectively formed on the source region S and the drain region D, and an n-type or p-type MOSFET in which the strained Si layer 4 becomes a channel region is manufactured.

In the MOSFET thus manufactured,
The strained Si layer 4 of the semiconductor wafer W manufactured by the above manufacturing method
Since a channel region is formed in the high-quality strained Si layer 4
As a result, a MOSFET having excellent operation characteristics can be obtained with a high yield.

The technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, the strained Si layer 4 of the semiconductor wafer W of the above embodiment
A SiGe layer may be further formed thereon. Also,
Although the strained Si layer was formed directly on the planarized second SiGe layer, another SiGe layer was further formed on the planarized second SiGe layer, and the strained Si layer was formed through the SiGe layer.
The layers may be grown epitaxially.

[0024]

According to the present invention, the following effects can be obtained.
According to the method for forming a strained Si layer of the present invention and a semiconductor substrate manufactured using the same, dislocations are concentrated by polishing the surface of the SiGe buffer layer to flatten at least cross-hatched irregularities on the surface. Si with no irregularities
Since the strained Si layer can be formed on the Ge buffer layer, a thicker and higher quality film can be obtained.

According to the method of manufacturing a field-effect transistor of the present invention and the field-effect transistor of the present invention, a strained Si layer serving as a channel region is formed by the method of forming a strained Si layer of the present invention. Since the channel region is formed in the strained Si layer of the semiconductor substrate of the present invention, a high-speed MOS having excellent operation characteristics due to a high-quality strained Si layer having small interface and surface roughness and having few defects.
FETs can be obtained with a high yield.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor substrate according to an embodiment of the present invention.

FIG. 2 is a graph showing a Ge composition ratio with respect to a film thickness in one embodiment according to the present invention.

FIG. 3 is a schematic cross-sectional view of a principal part showing a state of forming a strained Si layer before polishing and after polishing in one embodiment according to the present invention.

FIG. 4 shows a MOSFET according to an embodiment of the present invention.
It is a schematic sectional drawing which shows T.

[Explanation of symbols]

Reference Signs List 1 Si substrate 2 First SiGe layer (SiGe buffer layer) 3 Second SiGe layer (SiGe buffer layer) 4 Strained Si layer 5 SiO ₂ gate oxide film 6 Gate polysilicon film C Cross hatch S Source region D Drain region W Semiconductor wafer (semiconductor substrate)

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kazuki Mizushima 1-297 Kitabukurocho, Saitama City, Saitama Prefecture Inside the Mitsubishi Materials Research Institute (72) Inventor Ichiro Shiono 1-297 Kitabukurocho, Saitama City, Saitama Prefecture Mitsubishi Materials F-term in the Research Institute, Inc. (reference) 5F045 AB01 AB02 AC01 AF02 BB12 CA05 DA53 DA58 GH06 5F052 DA01 DA03 EA15 JA01 KA01 KA05 5F140 AA01 AA15 AB01 AC28 BA01 BA05 BA17 BC12 BC19 BF01 BF04 BK13 CD01 CD06 CE05

Claims (5)

[Claims] 1. A method for forming a strained Si layer on a Si substrate via a SiGe buffer layer, comprising: forming the SiGe buffer layer on the Si substrate; and polishing the surface of the SiGe buffer layer. Flattening at least the cross-hatch irregularities on the surface, and epitaxially growing a strained Si layer on the flattened SiGe buffer layer directly or via another SiGe layer. Forming a strained Si layer. 2. The method for forming a strained Si layer according to claim 1, wherein the step of forming the SiGe buffer layer comprises the step of forming a gradient composition in which a Ge composition ratio is gradually increased at least partially on the Si substrate. Epitaxially growing a first SiGe layer including a layer, and forming a second S on the first SiGe layer at a constant Ge composition ratio.
epitaxially growing an iGe layer. 3. A method for manufacturing a field-effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer, wherein the strain is generated by the method for forming a strained Si layer according to claim 1 or 2. A method for manufacturing a field effect transistor, comprising forming an Si layer. 4. A semiconductor substrate having a strained Si layer formed on a Si substrate via a SiGe buffer layer, wherein the strained Si layer is formed by the method of forming a strained Si layer according to claim 1 or 2. A semiconductor substrate, comprising: 5. A field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer, wherein the strained Si layer is formed by the method of forming a strained Si layer according to claim 1 or 2. A field-effect transistor, which is formed.