JP2004342815A - Method of producing semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for producing a semiconductor substrate having an SiGe layer in which the SiGe layer can be made thin, dislocation density can be reduced and the surface of the SiGe layer is flattened. <P>SOLUTION: The method of producing a semiconductor substrate characterised in that a recess having a face orientation (001) is formed in the surface of a silicon substrate having a crystal orientation <111> by alkali etching, and then an SiGe layer is grown epitaxially on the silicon substrate, is used. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【００２８】
表１から分かるように、シリコン基板表面の窪みの密度を増加させることにより、ＥＰＤ、すなわち、歪Ｓｉ層の転位が抑制されることが認められた。
また、シリコン基板の窪み部分は、エピタキシャル成長させたＳｉＧｅ層表面においては窪みが残っておらず、表面全体が平坦に形成されていた。
【００２９】
【発明の効果】
本発明に係る製造方法によれば、ＳｉＧｅ層の薄層化、かつ、転位密度の低減化を図ることができ、しかも、ＳｉＧｅ層表面が平坦化された半導体基板が得られる。これにより、ＳｉＧｅ層を有する半導体基板の生産コストの削減、生産効率の向上を図ることも可能となる。
また、本発明に係る製造方法により得られたＳｉ層を有する半導体基板を用いれば、転位密度の低い高品質の歪Ｓｉ層が形成されているため、これをチャネル領域として用いることにより、キャリア移動度の高速化が図られることとなり、半導体素子のより一層の微細化、高性能化等に寄与することができる。
【図面の簡単な説明】
【図１】シリコン基板に形成される窪みを模式的に示したものであり、（ａ）は断面図、（ｂ）は上面図である。
【図２】シリコン基板表面に形成された窪みによる転位制御の様子を模式的に示した断面図である。
【図３】窪みが形成されたシリコン基板表面へのＳｉＧｅ層のエピタキシャル成長を段階的に示した断面図である。
【符号の説明】
１ シリコン基板
２ 窪み
３ ＳｉＧｅ層
４ 転位[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly, to a method for manufacturing a semiconductor substrate having a SiGe layer.
[0002]
[Prior art]
In recent years, a high-speed device using a strained Si layer obtained by epitaxially growing Si on a silicon substrate via a SiGe layer as a channel region has been proposed.
This strained Si layer is strained by being pulled by SiGe having a larger lattice constant than Si, whereby the band structure of Si is changed, degeneracy is released, and carrier mobility is increased.
Therefore, by using this strained Si layer for the channel region, the speed of carrier movement can be 1.5 times or more as high as that when bulk Si is used.
[0003]
In order to obtain such a strained Si layer without dislocations, it is necessary to epitaxially grow a SiGe layer having a low dislocation density on a silicon substrate.
However, since Si and SiGe have different lattice constants, dislocations are generated due to lattice mismatch, which affects the strained Si layer, and as a result, dislocations occur in the strained Si layer which is a device active layer. was there.
[0004]
On the other hand, conventionally, a method of preventing the occurrence of dislocation by forming a composition gradient layer that gradually increases the Ge concentration in the SiGe layer in the process of epitaxial growth has been adopted (for example, Patent Document 1).
[0005]
However, even with this method, it has been difficult to reduce the number of dislocations so as to prevent a malfunction of the transistor.
In addition, since the Ge concentration is increased stepwise, the thickness of the SiGe layer becomes very thick, about 3 μm, and it takes time for the epitaxial growth of such a thick SiGe layer, and also in terms of production efficiency and cost. Was inferior.
[0006]
In order to solve the above problem, it has been proposed to reduce the dislocation density in the SiGe layer by forming a V-shaped groove on the surface of the silicon substrate and then epitaxially growing the SiGe layer (Patent Document 2). reference).
[0007]
[Patent Document 1]
JP-A-6-252046 [Patent Document 2]
JP-A-2002-359189
[Problems to be solved by the invention]
The above-described method of forming a groove on the surface of a silicon substrate is capable of reducing the dislocation density in the SiGe layer because the dislocation generated during the film formation of the SiGe layer escapes on the side surface of the groove and disappears. .
[0009]
However, in the above method, as the SiGe layer formed by epitaxial growth is thinner, it is more likely to be formed with a groove, like the V-shaped groove formed on the surface of the SiC substrate. For this reason, the device region is limited to a portion other than the portion where the groove is formed, and the pattern design is also restricted.
[0010]
Therefore, it is desirable that the substrate can be effectively utilized without being divided by the groove. That is, the SiGe layer is formed so as to suppress the occurrence of dislocations in the SiGe layer and to enable a free pattern design. It has been required that the entire layer surface be formed flat.
[0011]
The present invention has been made to solve the above technical problem, and in a method for manufacturing a semiconductor substrate having a SiGe layer, a SiGe layer can be made thinner and a dislocation density can be reduced, Moreover, it is another object of the present invention to provide a method of manufacturing a semiconductor substrate having a planarized SiGe layer surface.
[0012]
[Means for Solving the Problems]
The method of manufacturing a semiconductor substrate according to the present invention is characterized in that a depression having a plane orientation (001) is formed on the surface of a silicon substrate having a crystal orientation <111>, and then a SiGe layer is epitaxially grown on the silicon substrate. .
According to the above method, dislocations generated due to lattice mismatch can be terminated inside the depressions, so that the thickness of the SiGe layer can be reduced and the dislocation density on the surface of the SiGe layer can be reduced.
[0013]
Preferably, the depression is formed by alkali etching.
According to the chemical polishing (chemical polishing) treatment using an alkali solution, the above-mentioned depression in a specific direction can be easily formed on the order of nm due to the anisotropy characteristic of the treatment.
[0014]
Further, the method of manufacturing a semiconductor substrate according to the present invention is characterized in that a Si layer is further formed on the SiGe layer.
The Si layer in the semiconductor substrate formed in this manner can be obtained as a strained Si layer having a low dislocation density, and the carrier mobility can be increased.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in more detail.
In the method for manufacturing a semiconductor substrate according to the present invention, a depression having a plane orientation (001) is formed on the surface of a silicon substrate having a crystal orientation <111>, and a SiGe layer is epitaxially grown on the surface.
According to the above manufacturing method, the dislocation generated by the lattice mismatch between Si and SiGe can be terminated inside the depression formed on the surface of the silicon substrate, and the density of threading dislocation extending to the surface of the SiGe layer can be reduced. Can be reduced.
Therefore, even when a strained Si layer is further formed on the SiGe layer, in order to suppress threading dislocations, the SiGe layer, which conventionally required a thickness of μm order by a composition gradient layer or the like, is changed to nm. It can be thinned to the order.
[0016]
In the manufacturing method according to the present invention, a depression having a plane orientation (001) is formed on the surface of a silicon substrate having a crystal orientation <111>.
In the manufacturing method according to the present invention, by specifying the plane orientation of the silicon substrate and the recess as described above, the difference between the plane orientation of the substrate and the recess appears in the epitaxial growth rate of the SiGe layer, and the SiGe layer is formed as a thin film. Even if there is, the surface shape is formed flat.
[0017]
FIG. 1 schematically shows a depression 2 formed in the silicon substrate 1. FIG. 1A is a cross-sectional view, and FIG. 1B is a top view.
FIG. 3 shows, in a stepwise manner, the case where the SiGe layer 3 is epitaxially grown on the surface of the silicon substrate 1 in which the depression 2 as shown in FIG. 1 is formed.
As shown in FIG. 3, according to the present invention, even if the SiGe layer 3 is a thin film, the shape of the depression 2 formed in the silicon substrate 1 is not reflected on the surface of the SiGe layer 3 and is flat. Surface can be easily obtained.
Such planarization of the surface of the SiGe layer 3 is achieved by differentiating the epitaxial growth rate of the SiGe layer 3 with respect to the surface of the depression 2 in each direction, and the epitaxial growth rate of the (001) plane is the same as that of the <111> plane. And the shape is sagged (relaxed) due to the lamination.
[0018]
FIG. 2 schematically shows a state of dislocation control by the depression 2 formed on the surface of the silicon substrate 1.
As shown in FIG. 2, in a normal flat silicon substrate, dislocations generated due to lattice mismatch between Si and SiGe penetrate to the surface of the SiGe layer 3.
On the other hand, when the depression 2 is formed on the surface of the silicon substrate 1, the dislocation generated in the depression 2 ends at the surface of the depression 2 and suppresses the dislocation penetrating to the surface of the SiGe layer 3. be able to.
[0019]
As described above, the depression plays a role of terminating the dislocation inside the dislocation, and therefore, the size of the depression is preferably on the order of 1 to 10 nm.
[0020]
Preferably, the depression on the surface of the silicon substrate is formed by alkali etching.
According to such chemical polishing (chemical polishing) using an alkaline solution, a depression having a plane orientation (001) is formed on the surface of a silicon substrate having a crystal orientation <111> by nm due to the anisotropy characteristic of the treatment. It can be easily formed in order.
[0021]
The processing time of the alkali etching is preferably at least 3 minutes, more preferably at least 10 minutes, in order to form the above-mentioned depression.
Note that the type and concentration of the solution used for the alkaline etching and the etching time are appropriately adjusted according to the size and density of the dents formed on the silicon substrate surface.
[0022]
After the alkali etching treatment, a mirror finishing (mirror lapping) treatment is performed before epitaxial growth of the SiGe layer, as in a normal treatment. At this time, the treatment is performed so as to leave the previously formed depression.
[0023]
By stacking a Si layer on the SiGe layer formed as described above, a strained Si layer having a low dislocation density can be formed.
As described above, in a substrate on which a strained Si layer having a low dislocation density is formed, the strained Si layer achieves high-speed carrier movement, and can be used as a substrate suitable for forming a high-speed device.
[0024]
【Example】
Hereinafter, the present invention will be described more specifically based on examples, but the present invention is not limited to the following examples.
[Example 1]
After the crystal was pulled, the lapping-processed silicon substrate surface having the crystal orientation <111> was subjected to a chemical polishing treatment with a 10% sodium hydroxide solution for 3 minutes. By this alkali etching, a depression having a plane orientation (001) was formed on the surface of the silicon substrate.
This silicon substrate was subjected to a mirror lapping treatment so as to leave the depression, and the density of the depression on the surface was measured.
On the obtained silicon substrate, a SiGe layer (Si: 70%, Ge: 30%; thickness: 200 nm) was epitaxially grown, and further, a strained Si layer (thickness: 20 nm) was epitaxially grown.
The surface of the strained Si layer was flat.
The substrate obtained as described above was subjected to Secco etching, and the etch pit density (EPD: Etch Pit Density) on the surface of the strained Si layer was evaluated.
Table 1 shows the results.
[0025]
[Examples 2 to 4]
The alkali etching was performed in the same manner as in Example 1 except that the concentration of the sodium hydroxide solution and the etching time shown in Examples 2 to 4 in Table 1 were used. ) Was formed.
Each of these silicon substrates was subjected to a mirror lapping treatment so as to leave the above-mentioned depression, and the density of the depression on the surface was measured.
On each of the obtained silicon substrates, a SiGe layer and a strained Si layer were epitaxially grown in the same manner as in Example 1.
The surface of each of the strained Si layers was flat.
Each substrate obtained as described above was subjected to Secco etching, and the EPD on the surface of the strained Si layer was evaluated.
Table 1 shows the results.
[0026]
[Comparative Example 1]
After pulling the crystal, a SiGe layer and a strained Si layer were epitaxially grown on a lapping-processed silicon substrate having a crystal orientation <111> in the same manner as in Example 1.
The substrate obtained as described above was subjected to Secco etching, and the EPD on the surface of the strained Si layer was evaluated.
Table 1 shows the results.
[0027]
[Table 1]

[0028]
As can be seen from Table 1, it was recognized that the EPD, that is, the dislocation of the strained Si layer was suppressed by increasing the density of the depressions on the silicon substrate surface.
Further, in the dent portion of the silicon substrate, no dent remained on the surface of the epitaxially grown SiGe layer, and the entire surface was formed flat.
[0029]
【The invention's effect】
According to the manufacturing method of the present invention, the thickness of the SiGe layer can be reduced and the dislocation density can be reduced, and a semiconductor substrate having a planarized SiGe layer surface can be obtained. This makes it possible to reduce the production cost and improve the production efficiency of the semiconductor substrate having the SiGe layer.
When a semiconductor substrate having a Si layer obtained by the manufacturing method according to the present invention is used, a high-quality strained Si layer having a low dislocation density is formed. As a result, it is possible to contribute to further miniaturization and higher performance of the semiconductor element.
[Brief description of the drawings]
FIG. 1 schematically shows a depression formed in a silicon substrate, wherein (a) is a cross-sectional view and (b) is a top view.
FIG. 2 is a cross-sectional view schematically showing a state of dislocation control by a depression formed on the surface of a silicon substrate.
FIG. 3 is a sectional view showing stepwise epitaxial growth of a SiGe layer on a surface of a silicon substrate in which a depression is formed.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Depression 3 SiGe layer 4 Dislocation

Claims (3)

A method for manufacturing a semiconductor substrate, comprising: forming a depression having a plane orientation (001) on the surface of a silicon substrate having a crystal orientation <111>, and then epitaxially growing a SiGe layer on the silicon substrate. The method according to claim 1, wherein the depression is formed by alkali etching. 3. The method according to claim 1, further comprising forming an Si layer on the SiGe layer.

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