JP4202194B2 - Power semiconductor device and manufacturing method thereof - Google Patents

Power semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP4202194B2
JP4202194B2 JP2003162866A JP2003162866A JP4202194B2 JP 4202194 B2 JP4202194 B2 JP 4202194B2 JP 2003162866 A JP2003162866 A JP 2003162866A JP 2003162866 A JP2003162866 A JP 2003162866A JP 4202194 B2 JP4202194 B2 JP 4202194B2
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layer
semiconductor device
drift layer
silicon oxide
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JP2004363498A (en
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秀史 高谷
公守 濱田
康嗣 大倉
晃 黒柳
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Denso Corp
Toyota Motor Corp
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Denso Corp
Toyota Motor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Description

【０００１】
【発明の属する技術分野】
本発明は、電力用半導体装置およびその製造方法、特に、トレンチゲート型ＭＯＳゲートデバイスに関するものである。
【０００２】
【従来の技術】
大電流を制御する電力用半導体装置は家庭用電化製品から産業用装置の分野まで広く普及している。特に自動車用エレクトロニクスを支える半導体装置として、ＡＢＳ等の油圧バルブ制御、パワーウインドウ等のモータ制御、さらに電気自動車のバッテリ直流電圧を交流に変換するインバータシステム等多くの部分に使用されている。
【０００３】
インバータの高周波化と小型化の要求により、電力用半導体装置のなかでも、高速スイッチングが可能で、しかも電圧駆動であるため駆動回路を低損失にできるという特徴を有するＭＯＳ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）ゲートデバイスが注目されている。ＭＯＳゲートデバイスは、電子または正孔どちらか一方がキャリアとして動作するユニポーラデバイスであるＭＯＳＦＥＴ（Field Effect Transistor）と、電子と正孔がともにキャリアとして動作するバイポーラデバイスであるＩＧＢＴ（Insulated Gate Bipolor Transistor）とに大別できる。ＭＯＳ ＦＥＴは少数キャリアの蓄積がないため、特に高速性に優れている。
【０００４】
電力用半導体装置に要求されている課題として、無効電力削減のためのオン抵抗の低減と、信頼性向上のための耐圧の向上がある。オン抵抗とはＭＯＳ ＦＥＴの最も重要な特性の一つで、ドレインからソースまで、ドレイン電流が流れる素子内のすべての経路を通じた抵抗値を言い、主にチャネル領域の抵抗（チャネル抵抗）に支配されている。一方、耐圧とはドレイン−ソース間の耐圧を言い、オン抵抗とはトレードオフの関係にあることが知られている。
【０００５】
チャネル抵抗を下げるために、半導体表面に狭く、深い溝（トレンチ）を掘って、その側面にゲートを形成するトレンチゲート構造が開発された。これにより電流経路がトレンチ側壁に３次元的に拡大したことで、飛躍的な低オン抵抗が実現できた。
【０００６】
一方、耐圧を向上させるために、ボディ−ｐ領域の下のｎ−ドリフト領域に、積層したｐ浮遊層を埋め込むことにより電界集中を緩和する構造が提案された（例えば非特許文献１参照）。
【０００７】
また、トレンチゲートをドリフト領域深くまで形成し、トレンチ底部のゲート酸化膜を厚くして耐圧を向上させる構造も提案された（例えば非特許文献２参照。）。ゲート絶縁膜が薄い部分を深くするほど、オン抵抗が低減でき、耐圧とのトレードオフ関係を改善できる。
【０００８】
【非特許文献１】
エヌ．チェザック（Ｎ．Ｃｅｚａｃ）他、「A New Generation of Power Unipolar Devices: the Concept of the FLoating Islands MOS Transistor」、ISPSD'2000、フランス、IEEE、２０００年、ｐ．69−72
【非特許文献２】
ワイ．馬場 他、「A STUDY ON A HIGH BLOCKING VOLTAGE UMOS-FET WITH A DOUBLE GATE STRUCTURE」、ISPSD'1992、日本、IEEE、１９９２年、ｐ．300−302
【０００９】
【発明が解決しようとする課題】
上述の積層したｐ浮遊層を埋め込むことによるオン抵抗の低減は、ドリフト抵抗の低減が主である。したがって、オン抵抗にドリフト抵抗の占める割合の小さい低耐圧ＭＯＳ ＦＥＴでは、低減効果が小さく、複雑な積層構造を実現するための製造コストの増大を考慮すると、有効な構造ではない。
【００１０】
また、トレンチゲートの微細化による、オン抵抗と耐圧のトレードオフの改善にもプロセス上の制約から限界がある。
【００１１】
本発明はＭＯＳ ＦＥＴにおいて、オン抵抗の低減と耐圧の向上を簡易なプロセスにより実現できる構造の提供を目的とする。
【００１２】
【課題を解決するための手段】
本発明の電力用トレンチゲート型半導体装置の特徴は、ｎ（ｐ）型半導体基板に形成された第一のｎ（ｐ）型ドリフト層と、この第一のｎ（ｐ）型ドリフト層の表面に形成されたｐ（ｎ）型空乏領域拡張層と、このｐ（ｎ）型空乏領域拡張層の表面に形成された第二のｎ（ｐ）型ドリフト層と、この第二のｎ（ｐ）型ドリフト層の表面に形成されたｐ（ｎ）型ボディ層と、このｐ（ｎ）型ボディ層の表面に形成されたｎ（ｐ）型ソース領域と、を備え、前記溝は前記ｎ（ｐ）型ソース領域、前記ｐ（ｎ）型ボディ層、前記第二のｎ（ｐ）ドリフト層、前記ｐ（ｎ）型空乏領域拡張層を貫き前記第一のｎ（ｐ）型ドリフト層に達するように形成され、前記ｐ（ｎ）型空乏領域拡張層の前記溝の側壁近傍に、ｎ（ｐ）型に転換させたｎ（ｐ）型転換領域を備えることである。
【００１３】
この構造によれば、キャリアはｎ（ｐ）型転換領域を流れることができ、オフ動作時にｐ／ｎ界面にて空乏層が広がるため耐圧が高くなり、オン抵抗と耐圧とのトレードオフ関係を改善できる。
【００１４】
本発明の電力用トレンチゲート型半導体装置の他の特徴は、前記ｐ（ｎ）型ボディ層に接する前記ゲート絶縁膜の厚さは、前記ｐ（ｎ）型空乏領域拡張層および前記第一のｎ（ｐ）型ドリフト層に接する前記ゲート絶縁膜の厚さに比べて薄いことである。
【００１５】
この構成によれば、ゲートしきい値電圧を増大させること無く、ゲート絶縁膜の厚みの変化点近傍での電界集中を緩和でき、耐圧を向上することができる。
【００１６】
本発明の電力用トレンチゲート型半導体装置の他の特徴は、前記第一ｎ（ｐ）型ドリフト層の不純物濃度は第二ｎ（ｐ）型ドリフト層よりも低濃度であることである。
【００１７】
この構成によれば、トレンチ底部近傍での電界集中が緩和できるとともに、ｐ型空乏領域拡張層からの空乏層がより広がるため、耐圧をさらに向上することができる。
【００１８】
本発明の電力用トレンチゲート型半導体装置の他の特徴は、基板を第一のｎ（ｐ）型ドリフト層とは反対の極性を持つ半導体基板としたことである。
【００１９】
この構造によれば、基板の極性が第一のｎ（ｐ）型ドリフト層と反対の極性をであっても、オン抵抗と耐圧とのトレードオフ関係を改善できる構造が実現できる。
【００２０】
本発明の電力用トレンチゲート型半導体装置の他の特徴は、前記ｐ（ｎ）型ボディ層上部に接する前記ゲート絶縁膜の厚さは、前記ｐ（ｎ）型ボディ層下部、第二ｎ（ｐ）型ドリフト層、ｐ（ｎ）型空乏領域拡張層および第一ｎ（ｐ）型ドリフト層に接する前記ゲート絶縁膜の厚さに比べて薄いことである。
【００２１】
この構造によれば、トレンチの上部であるゲート絶縁膜の膜厚はｐ型ボディ層に接する領域で変化することになるので、その近傍で生じる電界集中をさらに緩和できる。
【００２２】
本発明の電力用トレンチゲート型半導体装置の製造方法の特徴は、ｎ（ｐ）型半導体基板に第一のｎ（ｐ）型ドリフト層と、ｐ（ｎ）型空乏領域拡張層と、第二のｎ（ｐ）型ドリフト層と、を順にエピタキシャル成長する工程と、前記ｎ（ｐ）型ソース領域、前記ｐ（ｎ）型ボディ層、前記ｐ（ｎ）型空乏領域拡張層を貫き前記第一のｎ（ｐ）型ドリフト層に達する溝を形成する工程と、前記ｐ（ｎ）型空乏領域拡張層の前記溝の側壁近傍に、ｎ（ｐ）型に転換させたｎ（ｐ）型転換領域を形成する工程と、を含むことである。
【００２３】
この方法によれば、キャリアの通路を確保した、空乏領域拡張層を形成することができる。
【００２４】
本発明の電力用トレンチゲート型半導体装置の製造方法の他の特徴は、前記溝を埋めるように第一のシリコン酸化膜を堆積さする工程と、前記第一のシリコン酸化膜を異方性ドライエッチング法により、所定の深さまでエッチングする工程と、前記溝の第一のシリコン酸化膜がエッチングされた内壁に、前記第一のシリコン酸化膜の厚みより薄い第二のシリコン酸化膜を形成する工程と、を含むことである。
【００２５】
この方法によれば、トレンチ内に厚みの異なるゲート絶縁膜を形成することができる。
【００２６】
本発明の電力用トレンチゲート型半導体装置の製造方法の他の特徴は、前記溝の内壁に第一のシリコン酸化膜を形成する工程と、前記第一のシリコン酸化膜が形成された前記溝にレジストを充填させる工程と、前記レジストを所定の所定の深さまでエッチバックする工程と、前記エッチバックされたレジストをエッチングマスクとして前記第一のシリコン酸化膜をエッチングする工程と、前記溝の第一のシリコン酸化膜がエッチングされた内壁に、前記第一のシリコン酸化膜の厚みより薄い第二のシリコン酸化膜を形成する工程と、を含むことである。
【００２７】
この方法によっても、トレンチ内に厚みの異なるゲート絶縁膜を形成することができる。
【００２８】
【発明の実施の形態】
実施形態１．
［デバイスの構造］
図１は実施形態１にかかるＭＯＳ ＦＥＴ１の断面図である。シリコンからなるｎ+型基板２に第一ｎ型ドリフト層３、ｐ型空乏領域拡張層４、第二ｎ型ドリフト層５、ｐ型ボディ層８が順に積層されており、ｐ型ボディ層８の表面にはｎ+型ソース領域９が形成されている。ｎ+型ソース領域９表面からｐ型ボディ層８、第二ｎ型層ドリフト層５および空乏領域拡張層４を貫き、第一ｎ型ドリフト層３に達する溝６が形成されており、溝内にはゲート絶縁膜１０を介して埋め込み電極（ゲート電極）１１が設けられている。ｎ+半導体基板２の裏面にはドレイン電極１４が形成されており、ｐ型ボディ層８の表面には、層間絶縁膜１２によって埋め込み電極（ゲート電極）１１と絶縁され、ソース領域９と電気的に接続されてソース電極１３が形成されている。本発明において特徴的な構造は、第一ｎ型ドリフト層３と第二ｎ型ドリフト層５の間にｐ型空乏領域拡張層４が挟まれ、ｐ型空乏領域拡張層４の前記溝６の側壁近傍領域は、ｐ型からｎ型に転換された転換領域７が形成されていることである。
【００２９】
実施形態１のＭＯＳ ＦＥＴ１はｎ型基板であって、キャリアが電子であるｎチャネル型であるが、半導体各層、領域の導電型はそれぞれ逆の導電型とし、ホールをキャリアとしたｐチャネル型でも良い。例えば、基板、およびソース領域等がｐ型であり、ボディ領域がｎ型でもよい。また、基板は第一のｎ（ｐ）型ドリフト層とは反対の極性を持つ半導体基板であってもよい。さらに本実施例では半導体としてシリコンを用いたが、化合物半導体を用いることも可能である。
【００３０】
［デバイスの動作］
図２を用いて、ＭＯＳ ＦＥＴ１のオン動作を説明する。まず、ドレイン電極１４に正電圧、例えば、２Ｖを印加し、ソース電極１３を接地させる。この状態において、ゲート電極１１に正電圧、例えば、５Ｖを印加すると、ｐ型ボディ層８中の電子は、埋め込み電極１１に引き寄せられ、溝６の近傍領域にｎ型のチャネルが形成される。これにより、ソース電極１３から供給された電子は、ｎ+型ソース領域９から第二ｎ型ドリフト層５、ｎ型転換領域７、第一ｎ型ドリフト層３、ｎ+型基板２を通り、ドレイン電極１４に到達する。この電子の流れを矢印で示す。
【００３１】
次に、図３を用いて、ＭＯＳ ＦＥＴ１のオフ動作を説明する。ゲート電極１１を正電圧から負電圧もしくは接地にすると、ｐ型ボディ層７中のｎ型のチャネルが無くなり、電流は流れることはできない。ＭＯＳ ＦＥＴ１がオフ動作の時、第二ｎ型ドリフト層５とｐ型ボディ層８の界面、ｐ型空乏領域拡張層４と第二ｎ型層ドリフト５および第一ｎ型ドリフト層３とｐ型空乏領域拡張層４の界面にあるｐ／ｎ接合部から空乏層が広がり、ソース電極１３からドレイン電極１４に電子が流れるのを阻止する。
【００３２】
実施形態１のＭＯＳ ＦＥＴ１によれば、オン抵抗を低減し、耐圧を向上することができる。チャネル抵抗およびドリフト抵抗はｐ型ボディ層８および第一ｎ型ドリフト層３の不純物濃度が高くなるほど、抵抗は下がるが、空乏層が狭くなるため、耐圧が下がり、不純物濃度が小さくなるほど、抵抗は上がるが、空乏層が広がるため、耐圧が上がる。実施形態１のＭＯＳ ＦＥＴ１ではｐ型空乏領域拡張層４により、従来構造と比べて、空乏領域が広がるため、耐圧が高くなる。したがって、オン抵抗を下げるため、第二ｎ型ドリフト層５および第一ｎ型ドリフト層３の不純物濃度を上げても、従来構造に比べ高い耐圧を持たせることができる。
【００３３】
さらに、第一ｎ型ドリフト層の不純物濃度を第二ｎ型ドリフト層よりも低濃度にすることも好ましい。この構成によれば、トレンチ底部近傍での電界集中が緩和できるとともに、ｐ型空乏領域拡張層からの空乏層がより広がるため、耐圧をさらに向上することができる。
【００３４】
また、ｐ型ボディ層上部に接する前記ゲート絶縁膜の厚さは、ｐ型ボディ層下部、第二ｎ型ドリフト層、ｐ型空乏領域拡張層および第一ｎ型ドリフト層に接する前記ゲート絶縁膜の厚さに比べて薄いことも好ましい。この構造によれば、トレンチの上部であるゲート絶縁膜の膜厚はｐ型ボディ層に接する領域で変化することになるので、その近傍で生じる電界集中をさらに緩和できる。この構造の場合、ゲートしきい値電圧に対する影響を考慮し、デバイスの要求される特性に応じた構造の最適化が重要である。
【００３５】
実施形態２．
［デバイスの構造］
図４は実施形態２にかかるＭＯＳ ＦＥＴ１００の断面図である。実施形態２のＭＯＳ ＦＥＴ１００は実施形態１のＭＯＳ ＦＥＴ１の構造に加え、前記ｐ型ボディ層領域における前記ゲート絶縁膜の厚みは、前記ｐ型空乏領域拡張層および前記第一のｎ型ドリフト層領域における厚みに比べて薄いことを特徴とする。
【００３６】
溝６の底部でゲート絶縁膜１０を厚くすることにより、埋め込み電極１１先端部の電界の集中が緩和され、ドレイン−ソース間の耐圧を向上することができるが、ｎ型チャネルを形成するｐ型ボディ層８領域においては、ゲートしきい値電圧を上げないようにゲート絶縁膜１０は薄いことが望ましい。上記の領域別にゲート絶縁膜１０の厚みを最適化させるためにゲート絶縁膜の厚みが変る厚み境界１０ａが存在する。
【００３７】
実施形態２の構造によれば、ゲート絶縁膜の厚み境界１０ａの近傍のドリフト層領域において、起こる電界集中を緩和することができ、耐圧を向上することができる。
【００３８】
［電界分布のシミュレーション］
実施形態２のＭＯＳ ＦＥＴ１００の構造における、電界分布をシミュレートし、耐圧とオン抵抗を求めた。図５（A）は実施形態２のＭＯＳ ＦＥＴ１００のトレンチ溝６近傍の断面構造とブレークダウン時の電界分布を示し、図５（B）は比較例として実施形態２のＭＯＳ ＦＥＴ１００の構造からｐ型空乏領域拡張層４を無くした構造の、トレンチ溝６近傍の断面構造とブレークダウン時の電界分布を示す。
【００３９】
ｐ型空乏領域拡張層４のない構造では、溝の底６ａの近傍および、ゲート絶縁膜の厚み境界１０ａの近傍で電界が集中していることがわかる。この電界集中を詳細に検討するため、図５（B）のＡ−Ａ断面での電界強度分布を図６（B）に示す。この分布より、厚み境界１０ａ近傍での電界強度が最も高く、この領域でこのＭＯＳ ＦＥＴの耐圧が決定されることがわかる。
【００４０】
一方、実施形態２のＭＯＳ ＦＥＴ１００の構造では、比較例と同様に溝の底６ａの近傍および、ゲート絶縁膜の厚み境界１０ａの近傍で電界が集中しているが、分布はより下方へ広がっていることがわかる。さらに、図５（A）のＡ−Ａ断面での電界強度分布は図６（A）に示すように、相対的に溝の底６ａ近傍の電界強度が増し、電界が分散していることがわかる。
【００４１】
この電界強度分布の結果、耐圧は比較例では約４６Ｖであるが、実施形態２のＭＯＳ ＦＥＴ１００の構造では約６５Ｖと向上した。
【００４２】
耐圧とオン抵抗のトレードオフ関係の改善効果をみるため、耐圧に対して、規格化オン抵抗（Ω・ｍｍ2）をプロットした結果を図７に示す。ｐ型空乏領域拡張層４のない構造の特性を黒丸、実施形態２のＭＯＳ ＦＥＴ１００の構造の特性を黒三角でプロットした。本実施形態２のＭＯＳ ＦＥＴ１００によれば、規格化オン抵抗（Ω・ｍｍ2）が１０％低減でき、耐圧とオン抵抗のトレードオフ関係が改善したことがわかる。
【００４３】
実施形態３．
［デバイスの構造］
図２１は実施形態３に係るＩＧＢＴ２００の断面図である。このＩＧＢＴ２００は、実施形態１または実施形態２の構造におけるｎ+型基板２に代えてｐ+型基板３３を適用したものである。
【００４４】
実施形態３の構造によれば、ｐ型空乏領域拡張層４にコレクタから注入されるホールが蓄積し、表面近傍のキャリア濃度が上昇することにより、従来のＩＧＢＴよりも低抵抗化することができる。
【００４５】
さらに実施形態３の構造によれば、従来のＩＧＢＴの電動度変調効果が損なわれにくい。また、ｐ型空乏層拡散層４があるため、負荷短絡時にJFET効果により短絡電流が低減し、負荷短絡耐量が向上する。
【００４６】
［デバイスの製造方法］
ＭＯＳ ＦＥＴ１００の製造工程を図を用いて説明する。図８から図１０はこれを説明するための工程図である。
【００４７】
図８に示すように、ｎ+型シリコン基板２に第一ｎ型ドリフト層３、ｐ型層（空乏領域拡張層）４、第二ｎ型ドリフト層５を順にエピタキシャル成長により積層させる。
【００４８】
次に図９に示すように、第二ｎ型ドリフト層５および空乏領域拡張層４を貫通し第一ｎ型ドリフト層３まで到達する溝（トレンチ）６を形成する。まず、エピタキシャル成長を行った第二ｎ型ドリフト層５の表面の全面にＨＴＯＣＶＤ（高温酸化膜化学気相堆積）法によりＨＴＯ（高温酸化）膜を形成した後、この表面にトレンチ開口パターンのフォトリソグラフィーおよびＨＴＯ膜エッチングを行い、ＨＴＯ膜にトレンチ溝開口パターンを形成する。次に、パターニングしたＨＴＯ膜をエッチングマスク３０として、ＣＦ系およびＨＢｒ系ガス等を用いたＲＩＥ（反応性イオンエッチング装置）などの異方性ドライエッチングにより第二ｎ型ドリフト層５およびｐ型空乏領域拡張層４を貫通し第一ｎ型ドリフト層３まで到達するトレンチ６を形成する。
【００４９】
次に、図１０に示すように、トレンチ６の側壁に斜めイオン注入技術を用いてｎ型転換領域７を形成する。このイオン注入工程により、ｐ型空乏領域拡張層４のトレンチ側壁もｎ型領域となり、トレンチ側壁は全てｎ型領域となる。
【００５０】
次にトレンチ内壁にゲート絶縁膜１０を形成する。図１１に示すように、基板全面に第一のシリコン酸化膜２０をＣＶＤ法により、溝を埋めるように堆積させる。第一のシリコン酸化膜２０は、トレンチ側壁近傍では高い密度で堆積し、中央部は疎な密度で堆積する。
【００５１】
さらに、ＨＴＯ膜によるエッチングマスクを形成し、ＲＩＥ（反応性イオンエッチング装置）などの異方性ドライエッチングにより、図１２に示すように、第一のシリコン酸化膜２０をトレンチ側壁近傍において、厚み境界１０ａの位置まで、エッチングする。トレンチを埋める第一のシリコン酸化膜２０は、トレンチ側壁近傍は密度が高いため、エッチングレートが低く、中央部は密度が疎であるため、エッチングレートが高い。したがって、トレンチ中央部では第一のシリコン酸化膜２０はトレンチ側壁近傍より、深くエッチングされる。
【００５２】
次に、図１３に示すように、トレンチ側壁の第一のシリコン酸化膜２０の上の部分に第二のシリコン酸化膜を形成する。基板全面に熱酸化を行うと、トレンチ側壁のシリコン露出部は第二のシリコン酸化膜２１となり、第一のシリコン酸化膜２０と合わせてトレンチ底部にて厚みの厚いゲート絶縁膜１０を形成することができる。第二のシリコン酸化膜の形成はＣＶＤ法による堆積によってもよい。
【００５３】
次に、図１４に示すように、トレンチに埋め込み電極１１を形成する。ＣＶＤ法により、全面にポリシリコン層を溝を埋めるように堆積させ、リンを高濃度に注入・拡散して高導電率化を図り、埋め込み電極１１とする。
【００５４】
次に、図１５に示すように、第二ｎ型ドリフト層５表面に、拡散により、ｐ型ボディ層８を形成し、ｐ型ボディ層８表面のトレンチ開口近傍領域にｎ+型ソース領域９を形成する。
【００５５】
以降は一般的なＭＯＳ ＦＥＴの作製プロセスと同様に、層間絶縁膜、コンタクト、ソース電極１３およびｎ+半導体基板２の裏面にはドレイン電極１４を形成し、ＭＯＳ ＦＥＴ１００が完成する。
【００５６】
なお、ｐ型ボディ層８の拡散による形成は、溝６のエッチング前に行うこともできる。
【００５７】
また、トレンチ内にて厚みの異なるゲート絶縁膜１０を形成するもう一つの方法がある。まず、トレンチ６形成後、図１７に示すように、第一のシリコン酸化膜２０をトレンチ６を完全に充填しない厚みで形成する。第一のシリコン酸化膜２０の形成は、熱酸化によるものでもよいし、ＣＶＤ法によるシリコン酸化膜の堆積によるものでもよい。
【００５８】
次に、図１８に示すように、基板の全面に有機系のレジストを塗布し、トレンチ６内に充填させる。
【００５９】
次に、レジストを所定の深さまでエッチバックし、このエッチバックしたレジストをエッチングマスクとして、図１９に示すように第一のシリコン酸化膜２０のエッチングを行う。
【００６０】
次に、レジストを除去した後、図２０に示すように、第一のシリコン酸化膜２０の上の部分に第二のシリコン酸化膜２１を形成する。基板全面を熱酸化を行うと、トレンチ側壁のシリコン露出部はシリコン酸化膜２１となり、シリコン酸化膜２０と合わせて、トレンチ底部にて厚みの厚いゲート絶縁膜１０を形成することができる。第二のシリコン酸化膜の形成はＣＶＤ法による堆積のよってもよい。
【００６１】
以上はＭＯＳ ＦＥＴの作製プロセスを例に説明したが、トレンチ構造のＭＯＳゲートを有するデバイス、例えば、ＩＧＢＴ（Insulated Gate Bipolor Transistor）などにも用いることができる。
【００６２】
以上、本発明の実施の形態について実施例を用いて説明したが、本発明はこうした実施例に何等限定されるものではなく、本発明の要旨を逸脱しない範囲内において、種々な形態で実施することができる。
【図面の簡単な説明】
【図１】 本発明の実施形態にかかるＭＯＳ ＦＥＴ１の断面構造である。
【図２】 本発明の実施形態にかかるＭＯＳ ＦＥＴ１オン動作時の電子の経路を示す図である。
【図３】 本発明の実施形態にかかるＭＯＳ ＦＥＴ１オフ動作時の空乏層の形成されるｐ／ｎ接合部を示す図である。
【図４】 本発明の実施形態２にかかるＭＯＳ ＦＥＴ１００の断面構造を示す図である。
【図５】 本発明の実施形態２にかかるＭＯＳ ＦＥＴ１００のブレークダウン時の電界分布を示す図である。
【図６】 本発明の実施形態２にかかるＭＯＳ ＦＥＴ１００のブレークダウン時の電界分布におけるＡ−Ａ断面での電界強度分布を示す図である。
【図７】 本発明の実施形態２にかかるＭＯＳ ＦＥＴ１００の耐圧とオン抵抗のトレードオフ関係の改善効果をみるため、耐圧に対して、規格化オン抵抗（Ω・ｍｍ2）をプロットした図である。
【図８】 本発明の実施形態２にかかるＭＯＳ ＦＥＴ１００の製造工程を説明するための工程図であって、エピタキシャル成長後の積層を示す図である。
【図９】 本発明の実施形態２にかかるＭＯＳ ＦＥＴ１００の製造工程を説明するための工程図であって、溝の断面形状を示す図である。
【図１０】 本発明の実施形態２にかかるＭＯＳ ＦＥＴ１００の製造工程を説明するための工程図であって、ｎ型転換領域の形成を示す図である。
【図１１】 本発明の実施形態２にかかるＭＯＳ ＦＥＴ１００の製造工程を説明するための工程図であって、溝に第一のシリコン酸化膜を堆積させる工程を示す図である。
【図１２】 本発明の実施形態２にかかるＭＯＳ ＦＥＴ１００の製造工程を説明するための工程図であって、第一のシリコン酸化膜のエッチング形状を示す断面図である。
【図１３】 本発明の実施形態２にかかるＭＯＳ ＦＥＴ１００の製造工程を説明するための工程図であって、トレンチ側壁の厚み境界から上の部分にゲート絶縁膜を形成する工程を示す図である。
【図１４】 本発明の実施形態２にかかるＭＯＳ ＦＥＴ１００の製造工程を説明するための工程図であって、埋め込み電極を形成する工程を示す図である。
【図１５】 本発明の実施形態２にかかるＭＯＳ ＦＥＴ１００の製造工程を説明するための工程図であって、ｐ型ボディ層８およびｎ+型ソース領域９の形成を示す図である。
【図１６】 本発明の実施形態２にかかるＭＯＳ ＦＥＴ１００の製造工程を説明するための工程図であって、ソース電極およびドレイン電極１４の形成を示す図である。
【図１７】 厚みの異なるゲート絶縁膜を形成するためのもう一つの方法を説明するための工程図であって、溝に第一のシリコン酸化膜を形成させる工程を示す図である。
【図１８】 厚みの異なるゲート絶縁膜を形成するためのもう一つの方法を説明するための工程図であって、溝にレジストを充填させる工程を示す図である。
【図１９】 厚みの異なるゲート絶縁膜を形成するためのもう一つの方法を説明するための工程図であって、エッチバックしたレジストをエッチングマスクとして第一のシリコン酸化膜をエッチングする工程を示す図である。
【図２０】 厚みの異なるゲート絶縁膜を形成するためのもう一つの方法を説明するための工程図であって、第二のシリコン酸化膜を形成する工程を示す図である。
【図２１】 本発明の実施形態３に係るＩＧＢＴ２００の断面図である。
【符号の説明】
１，１００ ＭＯＳ ＦＥＴ、２ ｎ+型基板、３ 第一ｎ型ドリフト層、４ｐ型空乏領域拡張層、５ 第二ｎ型ドリフト層、６ 溝、７ ｎ型転換領域、８ ｐ型ボディ層、９ ｎ+型ソース領域、１０ ゲート絶縁膜、１１ 埋め込み電極（ゲート電極）、１２ 層間絶縁膜、１３ ソース電極、１４ ドレイン電極、２０ 第一のシリコン酸化膜、２１ 第二のシリコン酸化膜、３０ エッチングマスク、３２ レジスト、３３ ｐ+型基板、 ２００ ＩＧＢＴ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power semiconductor device and a manufacturing method thereof, and more particularly to a trench gate type MOS gate device.
[0002]
[Prior art]
Power semiconductor devices that control large currents are widely used from household appliances to industrial devices. In particular, semiconductor devices that support automobile electronics are used in many parts such as hydraulic valve controls such as ABS, motor controls such as power windows, and inverter systems that convert battery DC voltage of electric vehicles into alternating current.
[0003]
A MOS (Metal Oxide Semiconductor) gate device having the characteristics that high-speed switching is possible among power semiconductor devices due to demands for high frequency and miniaturization of the inverter, and the drive circuit can be reduced in loss because of voltage drive. Is attracting attention. MOS gate devices are MOSFET (Field Effect Transistor), which is a unipolar device in which either electrons or holes operate as carriers, and IGBT (Insulated Gate Bipolor Transistor), which is a bipolar device in which both electrons and holes operate as carriers. And can be broadly divided. Since MOS FETs do not accumulate minority carriers, they are particularly excellent in high speed performance.
[0004]
Problems required for power semiconductor devices include a reduction in on-resistance for reducing reactive power and an increase in breakdown voltage for improving reliability. On-resistance is one of the most important characteristics of MOS FETs. It refers to the resistance value from the drain to the source through all the paths in the element where the drain current flows, and is mainly governed by the resistance of the channel region (channel resistance). Has been. On the other hand, the breakdown voltage refers to the breakdown voltage between the drain and the source, and it is known that the ON resistance is in a trade-off relationship.
[0005]
In order to lower the channel resistance, a trench gate structure has been developed in which a narrow and deep groove (trench) is dug in the semiconductor surface and a gate is formed on the side surface. As a result, the current path is three-dimensionally expanded on the trench side wall, thereby realizing a dramatic low on-resistance.
[0006]
On the other hand, in order to improve the breakdown voltage, a structure has been proposed in which electric field concentration is mitigated by embedding a stacked p floating layer in an n-drift region below the body-p region (see Non-Patent Document 1, for example).
[0007]
In addition, a structure has been proposed in which the trench gate is formed deep into the drift region and the gate oxide film at the bottom of the trench is thickened to improve the breakdown voltage (see, for example, Non-Patent Document 2). As the gate insulating film becomes deeper, the on-resistance can be reduced and the trade-off relationship with the breakdown voltage can be improved.
[0008]
[Non-Patent Document 1]
N. N. Cezac et al., “A New Generation of Power Unipolar Devices: The Concept of the Floating Islands MOS Transistor”, ISPSD '2000, France, IEEE, 2000, p. 69−72
[Non-Patent Document 2]
Wy. Baba et al. “A STUDY ON A HIGH BLOCKING VOLTAGE UMOS-FET WITH A DOUBLE GATE STRUCTURE”, ISPSD '1992, Japan, IEEE, 1992, p. 300−302
[0009]
[Problems to be solved by the invention]
The reduction of the on-resistance by embedding the laminated p floating layer described above is mainly the reduction of the drift resistance. Therefore, the low breakdown voltage MOS FET in which the ratio of the drift resistance to the on-resistance is small, the reduction effect is small, and it is not an effective structure in consideration of an increase in manufacturing cost for realizing a complicated stacked structure.
[0010]
In addition, improvement in the trade-off between on-resistance and breakdown voltage due to miniaturization of the trench gate is limited due to process limitations.
[0011]
It is an object of the present invention to provide a structure capable of realizing a reduction in on-resistance and an improvement in breakdown voltage by a simple process in a MOS FET.
[0012]
[Means for Solving the Problems]
The power trench gate type semiconductor device of the present invention is characterized by the first n (p) type drift layer formed on the n (p) type semiconductor substrate and the surface of the first n (p) type drift layer. P (n) type depletion region extension layer formed on the surface, a second n (p) type drift layer formed on the surface of the p (n) type depletion region extension layer, and the second n (p ) Type p-type body layer formed on the surface of the drift layer and an n (p) -type source region formed on the surface of the p (n) -type body layer. (P) type source region, said p (n) type body layer, said second n (p) drift layer, said first n (p) type drift layer penetrating through said p (n) type depletion region extension layer N (p) type conversion that is converted to n (p) type in the vicinity of the side wall of the groove of the p (n) type depletion region expansion layer. It is to comprise a region.
[0013]
According to this structure, carriers can flow through the n (p) type conversion region, and the depletion layer spreads at the p / n interface during the off operation, so that the breakdown voltage increases, and the trade-off relationship between on-resistance and breakdown voltage is obtained. Can improve.
[0014]
Another feature of the power trench gate type semiconductor device of the present invention is that the thickness of the gate insulating film in contact with the p (n) type body layer is different from that of the p (n) type depletion region extension layer and the first type. The thickness is smaller than the thickness of the gate insulating film in contact with the n (p) type drift layer.
[0015]
According to this configuration, the electric field concentration in the vicinity of the change point of the thickness of the gate insulating film can be alleviated without increasing the gate threshold voltage, and the breakdown voltage can be improved.
[0016]
Another feature of the power trench gate type semiconductor device of the present invention is that the impurity concentration of the first n (p) type drift layer is lower than that of the second n (p) type drift layer.
[0017]
According to this configuration, the electric field concentration in the vicinity of the bottom of the trench can be alleviated and the depletion layer from the p-type depletion region expansion layer can be further expanded, so that the breakdown voltage can be further improved.
[0018]
Another feature of the power trench gate type semiconductor device of the present invention is that the substrate is a semiconductor substrate having a polarity opposite to that of the first n (p) type drift layer.
[0019]
According to this structure, even if the polarity of the substrate is opposite to that of the first n (p) type drift layer, a structure that can improve the trade-off relationship between the on-resistance and the breakdown voltage can be realized.
[0020]
Another feature of the power trench gate type semiconductor device of the present invention is that the thickness of the gate insulating film in contact with the upper part of the p (n) type body layer is lower than the lower part of the p (n) type body layer. The thickness is smaller than the thickness of the gate insulating film in contact with the p) type drift layer, the p (n) type depletion region extension layer, and the first n (p) type drift layer.
[0021]
According to this structure, since the film thickness of the gate insulating film, which is the upper part of the trench, changes in the region in contact with the p-type body layer, the electric field concentration occurring in the vicinity thereof can be further relaxed.
[0022]
The manufacturing method of the power trench gate type semiconductor device of the present invention is characterized in that an n (p) type semiconductor substrate has a first n (p) type drift layer, a p (n) type depletion region expansion layer, and a second type. The n (p) -type drift layer of the first epitaxial layer, the n (p) -type source region, the p (n) -type body layer, and the p (n) -type depletion region extension layer. Forming a trench reaching the n (p) type drift layer of the n (p) type, and converting the n (p) type to the n (p) type in the vicinity of the sidewall of the trench of the p (n) type depletion region expansion layer Forming a region.
[0023]
According to this method, it is possible to form a depletion region expansion layer that secures a carrier path.
[0024]
Another feature of the method for manufacturing a power trench gate type semiconductor device according to the present invention is that a step of depositing a first silicon oxide film so as to fill the trench, and an anisotropic dry process of the first silicon oxide film are performed. Etching to a predetermined depth by an etching method, and forming a second silicon oxide film thinner than the thickness of the first silicon oxide film on the inner wall of the groove where the first silicon oxide film is etched And including.
[0025]
According to this method, gate insulating films having different thicknesses can be formed in the trench.
[0026]
Another feature of the method for manufacturing a power trench gate type semiconductor device of the present invention is that a step of forming a first silicon oxide film on the inner wall of the groove, and a step of forming the first silicon oxide film in the groove A step of filling the resist, a step of etching back the resist to a predetermined depth, a step of etching the first silicon oxide film using the etched back resist as an etching mask, and a first of the grooves Forming a second silicon oxide film thinner than the thickness of the first silicon oxide film on the inner wall where the silicon oxide film is etched.
[0027]
Also by this method, gate insulating films having different thicknesses can be formed in the trench.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1. FIG.
[Device structure]
FIG. 1 is a cross-sectional view of a MOS FET 1 according to the first embodiment. A first n-type drift layer 3, a p-type depletion region expansion layer 4, a second n-type drift layer 5, and a p-type body layer 8 are sequentially stacked on an n + -type substrate 2 made of silicon. An n + type source region 9 is formed on the surface. A groove 6 is formed from the surface of the n + -type source region 9 through the p-type body layer 8, the second n-type layer drift layer 5 and the depletion region extension layer 4 to reach the first n-type drift layer 3. Are provided with a buried electrode (gate electrode) 11 through a gate insulating film 10. A drain electrode 14 is formed on the back surface of the n + semiconductor substrate 2, and the surface of the p-type body layer 8 is insulated from the embedded electrode (gate electrode) 11 by the interlayer insulating film 12 and electrically connected to the source region 9. A source electrode 13 is formed so as to be connected to. A characteristic structure in the present invention is that a p-type depletion region extension layer 4 is sandwiched between a first n-type drift layer 3 and a second n-type drift layer 5, and the groove 6 of the p-type depletion region extension layer 4 is formed. The side wall vicinity region is that a conversion region 7 converted from p-type to n-type is formed.
[0029]
The MOS FET 1 of Embodiment 1 is an n-type substrate and is an n-channel type in which carriers are electrons, but the conductivity type of each semiconductor layer and region is the opposite conductivity type, and the p-channel type in which holes are carriers is also used. good. For example, the substrate and the source region may be p-type and the body region may be n-type. The substrate may be a semiconductor substrate having a polarity opposite to that of the first n (p) type drift layer. Further, although silicon is used as a semiconductor in this embodiment, a compound semiconductor can also be used.
[0030]
[Device operation]
The ON operation of the MOS FET 1 will be described with reference to FIG. First, a positive voltage, for example, 2V, is applied to the drain electrode 14, and the source electrode 13 is grounded. In this state, when a positive voltage, for example, 5 V is applied to the gate electrode 11, electrons in the p-type body layer 8 are attracted to the buried electrode 11, and an n-type channel is formed in the region near the groove 6. Thereby, electrons supplied from the source electrode 13 pass from the n + type source region 9 to the second n type drift layer 5, the n type conversion region 7, the first n type drift layer 3, and the n + type substrate 2. It reaches the drain electrode 14. This electron flow is indicated by arrows.
[0031]
Next, the off operation of the MOS FET 1 will be described with reference to FIG. When the gate electrode 11 is changed from a positive voltage to a negative voltage or ground, the n-type channel in the p-type body layer 7 is lost and no current can flow. When the MOSFET 1 is turned off, the interface between the second n-type drift layer 5 and the p-type body layer 8, the p-type depletion region expansion layer 4 and the second n-type layer drift 5, and the first n-type drift layer 3 and the p-type The depletion layer spreads from the p / n junction located at the interface of the depletion region expansion layer 4 and prevents electrons from flowing from the source electrode 13 to the drain electrode 14.
[0032]
According to the MOS FET 1 of the first embodiment, the on-resistance can be reduced and the breakdown voltage can be improved. The channel resistance and drift resistance decrease as the impurity concentration of the p-type body layer 8 and the first n-type drift layer 3 increases. However, since the depletion layer becomes narrower, the breakdown voltage decreases and the resistance decreases as the impurity concentration decreases. Although the depletion layer spreads, the breakdown voltage increases. In the MOS FET 1 of the first embodiment, the p-type depletion region expansion layer 4 expands the depletion region as compared with the conventional structure, so that the breakdown voltage is increased. Therefore, even if the impurity concentrations of the second n-type drift layer 5 and the first n-type drift layer 3 are increased in order to reduce the on-resistance, a higher breakdown voltage can be provided compared to the conventional structure.
[0033]
Furthermore, it is also preferable that the impurity concentration of the first n-type drift layer is lower than that of the second n-type drift layer. According to this configuration, the electric field concentration in the vicinity of the bottom of the trench can be alleviated and the depletion layer from the p-type depletion region expansion layer can be further expanded, so that the breakdown voltage can be further improved.
[0034]
The thickness of the gate insulating film in contact with the upper part of the p-type body layer is such that the gate insulating film in contact with the lower part of the p-type body layer, the second n-type drift layer, the p-type depletion region extension layer, and the first n-type drift layer. It is also preferable that the thickness is smaller than the thickness of. According to this structure, since the film thickness of the gate insulating film, which is the upper part of the trench, changes in the region in contact with the p-type body layer, the electric field concentration occurring in the vicinity thereof can be further relaxed. In the case of this structure, considering the influence on the gate threshold voltage, it is important to optimize the structure in accordance with the required characteristics of the device.
[0035]
Embodiment 2. FIG.
[Device structure]
FIG. 4 is a cross-sectional view of the MOS FET 100 according to the second embodiment. In addition to the structure of the MOS FET 1 according to the first embodiment, the MOS FET 100 according to the second embodiment has a thickness of the gate insulating film in the p-type body layer region that includes the p-type depletion region extension layer and the first n-type drift layer region. It is characterized by being thinner than the thickness at.
[0036]
By thickening the gate insulating film 10 at the bottom of the trench 6, the concentration of the electric field at the tip of the embedded electrode 11 can be relaxed and the breakdown voltage between the drain and the source can be improved, but p-type forming an n-type channel. In the body layer 8 region, the gate insulating film 10 is desirably thin so as not to raise the gate threshold voltage. In order to optimize the thickness of the gate insulating film 10 for each region, there is a thickness boundary 10a where the thickness of the gate insulating film changes.
[0037]
According to the structure of the second embodiment, the electric field concentration occurring in the drift layer region near the thickness boundary 10a of the gate insulating film can be relaxed, and the breakdown voltage can be improved.
[0038]
[Simulation of electric field distribution]
The electric field distribution in the structure of the MOS FET 100 of the second embodiment was simulated, and the breakdown voltage and the on-resistance were obtained. FIG. 5A shows a cross-sectional structure in the vicinity of the trench groove 6 of the MOS FET 100 of the second embodiment and an electric field distribution at the time of breakdown, and FIG. 5B shows a p-type structure from the structure of the MOS FET 100 of the second embodiment as a comparative example. The cross-sectional structure near the trench groove 6 and the electric field distribution at the time of breakdown of the structure without the depletion region expansion layer 4 are shown.
[0039]
It can be seen that in the structure without the p-type depletion region expansion layer 4, the electric field is concentrated in the vicinity of the trench bottom 6a and in the vicinity of the thickness boundary 10a of the gate insulating film. In order to examine this electric field concentration in detail, FIG. 6B shows the electric field strength distribution along the section AA in FIG. This distribution shows that the electric field strength in the vicinity of the thickness boundary 10a is the highest, and the breakdown voltage of this MOS FET is determined in this region.
[0040]
On the other hand, in the structure of the MOS FET 100 of the second embodiment, the electric field is concentrated in the vicinity of the groove bottom 6a and in the vicinity of the thickness boundary 10a of the gate insulating film as in the comparative example, but the distribution spreads further downward. I understand that. Furthermore, as shown in FIG. 6 (A), the electric field strength distribution in the AA cross section of FIG. 5 (A) shows that the electric field strength near the bottom 6a of the groove is relatively increased and the electric field is dispersed. Recognize.
[0041]
As a result of this electric field strength distribution, the breakdown voltage was about 46 V in the comparative example, but improved to about 65 V in the structure of the MOS FET 100 of the second embodiment.
[0042]
FIG. 7 shows the result of plotting the normalized on-resistance (Ω · mm 2 ) against the breakdown voltage in order to see the improvement effect of the trade-off relationship between the breakdown voltage and the on-resistance. The characteristics of the structure without the p-type depletion region expansion layer 4 are plotted with black circles, and the characteristics of the structure of the MOS FET 100 of Embodiment 2 are plotted with black triangles. According to the MOS FET 100 of the second embodiment, it can be seen that the normalized on-resistance (Ω · mm 2 ) can be reduced by 10%, and the trade-off relationship between breakdown voltage and on-resistance is improved.
[0043]
Embodiment 3. FIG.
[Device structure]
FIG. 21 is a cross-sectional view of an IGBT 200 according to the third embodiment. The IGBT 200 is obtained by applying a p + type substrate 33 in place of the n + type substrate 2 in the structure of the first or second embodiment.
[0044]
According to the structure of the third embodiment, holes injected from the collector are accumulated in the p-type depletion region expansion layer 4 and the carrier concentration in the vicinity of the surface is increased, so that the resistance can be reduced as compared with the conventional IGBT. .
[0045]
Furthermore, according to the structure of the third embodiment, the power modulation effect of the conventional IGBT is not easily impaired. Further, since the p-type depletion layer diffusion layer 4 is present, the short-circuit current is reduced by the JFET effect when the load is short-circuited, and the load short-circuit tolerance is improved.
[0046]
[Device manufacturing method]
A manufacturing process of the MOS FET 100 will be described with reference to the drawings. 8 to 10 are process diagrams for explaining this.
[0047]
As shown in FIG. 8, a first n-type drift layer 3, a p-type layer (depletion region expansion layer) 4, and a second n-type drift layer 5 are sequentially stacked on an n + -type silicon substrate 2 by epitaxial growth.
[0048]
Next, as shown in FIG. 9, a groove (trench) 6 that penetrates the second n-type drift layer 5 and the depletion region extension layer 4 and reaches the first n-type drift layer 3 is formed. First, an HTO (high temperature oxide) film is formed on the entire surface of the epitaxially grown second n-type drift layer 5 by the HTOCVD (high temperature oxide chemical vapor deposition) method, and then a trench opening pattern photolithography is formed on this surface. Then, the HTO film is etched to form a trench groove opening pattern in the HTO film. Next, using the patterned HTO film as an etching mask 30, the second n-type drift layer 5 and the p-type depletion are performed by anisotropic dry etching such as RIE (reactive ion etching apparatus) using CF-based gas, HBr-based gas, or the like. A trench 6 that penetrates the region expansion layer 4 and reaches the first n-type drift layer 3 is formed.
[0049]
Next, as shown in FIG. 10, an n-type conversion region 7 is formed on the sidewall of the trench 6 by using an oblique ion implantation technique. By this ion implantation process, the trench sidewall of the p-type depletion region expansion layer 4 also becomes an n-type region, and all the trench sidewalls become an n-type region.
[0050]
Next, the gate insulating film 10 is formed on the inner wall of the trench. As shown in FIG. 11, a first silicon oxide film 20 is deposited on the entire surface of the substrate by CVD to fill the trench. The first silicon oxide film 20 is deposited at a high density in the vicinity of the trench sidewall, and is deposited at a sparse density in the center.
[0051]
Further, an etching mask is formed by an HTO film, and anisotropic dry etching such as RIE (reactive ion etching apparatus) is used to form the first silicon oxide film 20 in the vicinity of the trench side wall, as shown in FIG. Etching is performed up to the position of 10a. The first silicon oxide film 20 filling the trench has a high etching rate because the density is high in the vicinity of the trench side wall, and the etching rate is high because the density is sparse in the central part. Therefore, the first silicon oxide film 20 is etched deeper in the center of the trench than in the vicinity of the trench sidewall.
[0052]
Next, as shown in FIG. 13, a second silicon oxide film is formed on the trench sidewall on the first silicon oxide film 20. When thermal oxidation is performed on the entire surface of the substrate, the silicon exposed portion on the side wall of the trench becomes the second silicon oxide film 21, and the thick gate insulating film 10 is formed at the bottom of the trench together with the first silicon oxide film 20. Can do. The second silicon oxide film may be formed by deposition using a CVD method.
[0053]
Next, as shown in FIG. 14, the buried electrode 11 is formed in the trench. A polysilicon layer is deposited over the entire surface by CVD to fill the trench, and phosphorus is implanted and diffused at a high concentration to increase the conductivity, thereby forming the buried electrode 11.
[0054]
Next, as shown in FIG. 15, a p-type body layer 8 is formed on the surface of the second n-type drift layer 5 by diffusion, and an n + -type source region 9 is formed in the region near the trench opening on the surface of the p-type body layer 8. Form.
[0055]
Thereafter, the drain electrode 14 is formed on the back surface of the interlayer insulating film, the contact, the source electrode 13 and the n + semiconductor substrate 2 in the same manner as a general MOS FET manufacturing process, and the MOS FET 100 is completed.
[0056]
The formation of the p-type body layer 8 by diffusion can also be performed before the trench 6 is etched.
[0057]
There is another method for forming the gate insulating films 10 having different thicknesses in the trench. First, after the trench 6 is formed, as shown in FIG. 17, the first silicon oxide film 20 is formed with a thickness that does not completely fill the trench 6. The first silicon oxide film 20 may be formed by thermal oxidation or by deposition of a silicon oxide film by a CVD method.
[0058]
Next, as shown in FIG. 18, an organic resist is applied to the entire surface of the substrate and filled in the trench 6.
[0059]
Next, the resist is etched back to a predetermined depth, and the first silicon oxide film 20 is etched as shown in FIG. 19 using the etched back resist as an etching mask.
[0060]
Next, after removing the resist, a second silicon oxide film 21 is formed on the first silicon oxide film 20 as shown in FIG. When the entire surface of the substrate is thermally oxidized, the silicon exposed portion on the trench side wall becomes the silicon oxide film 21, and the thick gate insulating film 10 can be formed at the bottom of the trench together with the silicon oxide film 20. The formation of the second silicon oxide film may be performed by deposition by a CVD method.
[0061]
The above description has been made by taking the manufacturing process of the MOS FET as an example, but it can also be used for a device having a MOS gate having a trench structure, for example, an IGBT (Insulated Gate Bipolor Transistor).
[0062]
The embodiments of the present invention have been described using the embodiments. However, the present invention is not limited to these embodiments, and can be implemented in various forms without departing from the gist of the present invention. be able to.
[Brief description of the drawings]
FIG. 1 is a cross-sectional structure of a MOS FET 1 according to an embodiment of the present invention.
FIG. 2 is a diagram showing an electron path when the MOS FET 1 is turned on according to the embodiment of the present invention.
FIG. 3 is a diagram showing a p / n junction where a depletion layer is formed when the MOS FET 1 is turned off according to an embodiment of the present invention.
FIG. 4 is a diagram showing a cross-sectional structure of a MOS FET 100 according to a second embodiment of the present invention.
FIG. 5 is a diagram showing an electric field distribution at the time of breakdown of the MOS FET 100 according to the second embodiment of the present invention.
FIG. 6 is a diagram showing an electric field strength distribution along an AA section in an electric field distribution at the time of breakdown of the MOS FET 100 according to the second embodiment of the present invention.
FIG. 7 is a graph plotting normalized on-resistance (Ω · mm 2 ) against breakdown voltage in order to see the effect of improving the trade-off relationship between breakdown voltage and on-resistance of the MOS FET 100 according to the second embodiment of the present invention. is there.
FIG. 8 is a process diagram for explaining a manufacturing process of the MOS FET 100 according to the second embodiment of the present invention and is a diagram showing a stack after epitaxial growth.
FIG. 9 is a process diagram for explaining a manufacturing process of the MOS FET 100 according to the second embodiment of the present invention, and is a diagram showing a cross-sectional shape of a groove.
FIG. 10 is a process diagram for explaining a manufacturing process of the MOS FET 100 according to the second embodiment of the present invention and is a diagram showing formation of an n-type conversion region.
FIG. 11 is a process diagram for explaining a manufacturing process of the MOS FET 100 according to the second embodiment of the present invention and a process for depositing a first silicon oxide film in a groove;
FIG. 12 is a process diagram for explaining a manufacturing process of the MOS FET 100 according to the second embodiment of the present invention, and a sectional view showing an etching shape of the first silicon oxide film.
FIG. 13 is a process diagram for explaining a manufacturing process of the MOS FET 100 according to the second embodiment of the present invention, and showing a process of forming a gate insulating film on the upper portion from the thickness boundary of the trench side wall. .
FIG. 14 is a process diagram for explaining a manufacturing process of the MOS FET 100 according to the second embodiment of the present invention and a process for forming a buried electrode;
FIG. 15 is a process diagram for explaining a manufacturing process of the MOS FET 100 according to the second embodiment of the present invention, and is a diagram showing formation of a p-type body layer 8 and an n + -type source region 9;
FIG. 16 is a process diagram for explaining the manufacturing process of the MOS FET 100 according to the second embodiment of the present invention, and is a diagram showing the formation of the source electrode and the drain electrode 14;
FIG. 17 is a process diagram for explaining another method for forming gate insulating films having different thicknesses, and showing a process of forming a first silicon oxide film in a groove;
FIG. 18 is a process diagram for explaining another method for forming gate insulating films having different thicknesses, and showing a process of filling a groove with a resist.
FIG. 19 is a process diagram for explaining another method for forming gate insulating films having different thicknesses, and showing a process of etching the first silicon oxide film using the etched back resist as an etching mask; FIG.
FIG. 20 is a process diagram for explaining another method for forming gate insulating films having different thicknesses, and showing a process of forming a second silicon oxide film.
FIG. 21 is a cross-sectional view of an IGBT 200 according to Embodiment 3 of the present invention.
[Explanation of symbols]
1,100 MOS FET, 2 n + type substrate, 3 first n type drift layer, 4 p type depletion region expansion layer, 5 second n type drift layer, 6 groove, 7 n type conversion region, 8 p type body layer, 9 n + -type source region, 10 gate insulating film, 11 buried electrode (gate electrode), 12 interlayer insulating film, 13 source electrode, 14 drain electrode, 20 first silicon oxide film, 21 second silicon oxide film, 30 Etching mask, 32 resist, 33 p + type substrate, 200 IGBT.

Claims (8)

溝の中にゲート絶縁膜を介して埋め込まれたゲート電極を備えた電力用トレンチゲート型半導体装置において、
ｎ（ｐ）型半導体基板に形成された第一のｎ（ｐ）型ドリフト層と、
この第一のｎ（ｐ）型ドリフト層の表面に形成されたｐ（ｎ）型空乏領域拡張層と、
このｐ（ｎ）型空乏領域拡張層の表面に形成された第二のｎ（ｐ）型ドリフト層と、
この第二のｎ（ｐ）型ドリフト層の表面に形成されたｐ（ｎ）型ボディ層と、
このｐ（ｎ）型ボディ層の表面に形成されたｎ（ｐ）型ソース領域と、
を備え、
前記溝は前記ｎ（ｐ）型ソース領域、前記ｐ（ｎ）型ボディ層、前記第二のｎ（ｐ）ドリフト層、前記ｐ（ｎ）型空乏領域拡張層を貫き前記第一のｎ（ｐ）型ドリフト層に達するように形成され、
前記ｐ（ｎ）型空乏領域拡張層の前記溝の側壁近傍に、ｎ（ｐ）型に転換させたｎ（ｐ）型転換領域を備えることを特徴とする電力用トレンチゲート型半導体装置。In a power trench gate type semiconductor device comprising a gate electrode embedded in a trench through a gate insulating film,
a first n (p) type drift layer formed on an n (p) type semiconductor substrate;
A p (n) type depletion region extension layer formed on the surface of the first n (p) type drift layer;
A second n (p) type drift layer formed on the surface of the p (n) type depletion region expansion layer;
A p (n) type body layer formed on the surface of the second n (p) type drift layer;
An n (p) type source region formed on the surface of the p (n) type body layer;
With
The trench penetrates the first n (p) source region, the p (n) body layer, the second n (p) drift layer, and the p (n) depletion region extension layer. p) formed to reach the drift layer,
A power trench gate type semiconductor device comprising an n (p) type conversion region converted into an n (p) type in the vicinity of the side wall of the groove of the p (n) type depletion region expansion layer. 請求項１に記載の電力用トレンチゲート型半導体装置であって、
前記ｐ（ｎ）型ボディ層に接する前記ゲート絶縁膜の厚さは、前記ｐ（ｎ）型空乏領域拡張層および前記第一のｎ（ｐ）型ドリフト層に接する前記ゲート絶縁膜の厚さと比べて薄いことを特徴とする電力用トレンチゲート型半導体装置。The power trench gate type semiconductor device according to claim 1,
The thickness of the gate insulating film in contact with the p (n) type body layer is equal to the thickness of the gate insulating film in contact with the p (n) type depletion region extension layer and the first n (p) type drift layer. A power trench gate type semiconductor device characterized by being thinner. 請求項１または２に記載の電力用トレンチゲート型半導体装置であって、
前記第一のｎ（ｐ）型ドリフト層の不純物濃度は第二のｎ（ｐ）型ドリフト層よりも低濃度であることを特徴とする電力用トレンチゲート型半導体装置。It is a power trench gate type semiconductor device according to claim 1 or 2,
A power trench gate type semiconductor device, wherein the impurity concentration of the first n (p) type drift layer is lower than that of the second n (p) type drift layer. 請求項１または３に記載の電力用トレンチゲート型半導体装置であって、
基板を第一のｎ（ｐ）型ドリフト層とは反対の極性を持つ半導体基板としたことを特徴とする電力用トレンチ型半導体装置。It is a power trench gate type semiconductor device according to claim 1 or 3,
A power trench type semiconductor device, wherein the substrate is a semiconductor substrate having a polarity opposite to that of the first n (p) type drift layer. 請求項１または３に記載の電力用トレンチゲート型半導体装置であって、
前記ｐ（ｎ）型ボディ層上部に接する前記ゲート絶縁膜の厚さは、前記ｐ（ｎ）型ボディ層下部、第二のｎ（ｐ）型ドリフト層、ｐ（ｎ）型空乏領域拡張層および第一のｎ（ｐ）型ドリフト層に接する前記ゲート絶縁膜の厚さに比べて薄いことを特徴とする電力用トレンチゲート型半導体装置。It is a power trench gate type semiconductor device according to claim 1 or 3,
The thickness of the gate insulating film in contact with the upper part of the p (n) type body layer is as follows: the lower part of the p (n) type body layer, the second n (p) type drift layer, and the p (n) type depletion region extension layer. And a power trench gate type semiconductor device characterized by being thinner than a thickness of the gate insulating film in contact with the first n (p) type drift layer. 溝の中にゲート絶縁膜を介して埋め込まれたゲート電極を備えた電力用トレンチゲート型半導体装置の製造方法であって、
ｎ（ｐ）型半導体基板に第一のｎ（ｐ）型ドリフト層と、ｐ（ｎ）型空乏領域拡張層と、第二のｎ（ｐ）型ドリフト層と、を順にエピタキシャル成長する工程と、
前記ｎ（ｐ）型ソース領域、前記ｐ（ｎ）型ボディ層、前記第二のｎ（ｐ）型ドリフト層、前記ｐ（ｎ）型空乏領域拡張層を貫き前記第一のｎ（ｐ）型ドリフト層に達する溝を形成する工程と、
前記ｐ（ｎ）型空乏領域拡張層の前記溝の側壁近傍に、ｎ（ｐ）型に転換させたｎ（ｐ）型転換領域を形成する工程と、
を含むことを特徴とする電力用トレンチゲート型半導体装置の製造方法。A method of manufacturing a power trench gate type semiconductor device comprising a gate electrode embedded in a trench through a gate insulating film,
a step of epitaxially growing a first n (p) type drift layer, a p (n) type depletion region extension layer, and a second n (p) type drift layer in order on an n (p) type semiconductor substrate;
The first n (p) through the n (p) type source region, the p (n) type body layer, the second n (p) type drift layer, and the p (n) type depletion region extension layer. Forming a groove reaching the mold drift layer;
Forming an n (p) type conversion region converted into an n (p) type in the vicinity of the sidewall of the groove of the p (n) type depletion region expansion layer;
A method for manufacturing a power trench gate type semiconductor device. 請求項６に記載の電力用トレンチゲート型半導体装置の製造方法であって、
前記溝を埋めるように第一のシリコン酸化膜を堆積させる工程と、
前記第一のシリコン酸化膜を異方性ドライエッチング法により、所定の深さまでエッチングする工程と、
前記溝の第一のシリコン酸化膜がエッチングされた内壁に、前記第一のシリコン酸化膜の厚みより薄い第二のシリコン酸化膜を形成する工程と、
を含むことを特徴とする電力用トレンチゲート型半導体装置の製造方法。A method of manufacturing a power trench gate type semiconductor device according to claim 6,
Depositing a first silicon oxide film to fill the trench;
Etching the first silicon oxide film to a predetermined depth by anisotropic dry etching;
Forming a second silicon oxide film thinner than the thickness of the first silicon oxide film on the inner wall of the groove where the first silicon oxide film is etched;
A method for manufacturing a power trench gate type semiconductor device. 請求項６に記載の電力用トレンチゲート型半導体装置の製造方法であって、
前記溝の内壁に第一のシリコン酸化膜を形成する工程と、
前記第一のシリコン酸化膜が形成された前記溝にレジストを充填させる工程と、
前記レジストを所定の深さまでエッチバックする工程と、
前記エッチバックされたレジストをエッチングマスクとして前記第一のシリコン酸化膜をエッチングする工程と、
前記溝の第一のシリコン酸化膜がエッチングされた内壁に、前記第一のシリコン酸化膜の厚みより薄い第二のシリコン酸化膜を形成する工程と、
を含むことを特徴とする電力用トレンチゲート型半導体装置の製造方法。A method of manufacturing a power trench gate type semiconductor device according to claim 6,
Forming a first silicon oxide film on the inner wall of the groove;
Filling the groove in which the first silicon oxide film is formed with a resist;
Etching back the resist to a predetermined depth;
Etching the first silicon oxide film using the etched back resist as an etching mask;
Forming a second silicon oxide film thinner than the thickness of the first silicon oxide film on the inner wall of the groove where the first silicon oxide film is etched;
A method for manufacturing a power trench gate type semiconductor device.
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