JP4383820B2 - Trench gate type semiconductor device - Google Patents

Description

  The present invention relates to a trench gate type semiconductor device, and more particularly to a trench gate type MOS gate device including a source trench.

  Semiconductor devices that control current are widely used from household appliances to industrial devices. In particular, semiconductor devices that support automobile electronics are used in many parts such as hydraulic valve controls such as ABS, motor controls such as power windows, and inverter systems that convert battery DC voltage of electric vehicles into alternating current.

  A MOS (Metal Oxide Semiconductor) gate device having characteristics that a high-speed switching is possible among current control semiconductor devices and a drive circuit can be reduced in loss due to a demand for high frequency and miniaturization of an inverter. Is attracting attention. The MOS gate device includes a MOSFET (Field Effect Transistor) that is a unipolar device in which either an electron or a hole operates as a carrier, and an IGBT (Insulated Gate Bipolar Transistor) that is a bipolar device in which both an electron and a hole operate as a carrier. And can be broadly divided. Since MOSFETs do not accumulate minority carriers, they are particularly excellent in high speed performance.

  Problems required for the current control semiconductor device include a reduction in on-resistance for reducing reactive power and an increase in breakdown voltage for improving reliability. On-resistance is one of the most important characteristics of a MOSFET. It refers to the resistance value through all the paths in the element through which drain current flows from the drain to the source. The lower the breakdown voltage, the more generally the resistance of the channel region ( The contribution of the channel resistance is large, accounting for about 70% in the 20V class. On the other hand, the breakdown voltage is about 30% in the 100V class. On the other hand, the breakdown voltage refers to the breakdown voltage between the drain and the source, and it is known that the ON resistance is in a trade-off relationship.

  In order to lower the channel resistance, a trench gate structure has been developed in which a narrow and deep trench is formed from the semiconductor surface and a gate is formed on the side surface. As a result, the current path is three-dimensionally expanded on the trench sidewall, and the on-resistance can be drastically reduced. Further, in order to lower the on-resistance, a structure is adopted in which the trench gate interval is narrowed to increase the cell density to increase the effective current path density.

  On the other hand, when an excessive voltage is applied between the drain and the source, breakdown occurs at the bottom of the gate trench where the electric field is most concentrated. Therefore, in order to alleviate electric field concentration at the bottom of the gate trench, a source trench having the same depth as the gate trench is provided between the gate trenches, a source insulating film is formed so as to cover the inner surface of the source trench, and doping is performed. A structure has been proposed in which a source trench electrode made of depolysilicon or the like is formed so as to fill the source trench (see, for example, Patent Document 1).

  According to this configuration, the electrons in the drift layer are attracted to the surface of the source insulating film in the drift layer to form negative space charges, and the concentration of the electric field near the corner of the bottom of the gate trench in the drift layer is alleviated. improves.

JP-A-9-331063

  The invention of Patent Document 1 is effective for power semiconductor products having a relatively high breakdown voltage, such as an IGBT, in which the drift layer from the bottom of the source (emitter) trench to the substrate has a sufficient thickness (50 μm or more). Since the structure has a breakdown voltage with the thickness of the drift layer, the thickness of the drift layer from the bottom of the source (emitter) trench to the substrate is sufficient, and the buried source is used to ensure the breakdown voltage in the source (emitter) trench. This is because it is not necessary to increase the thickness of the insulating film that insulates the electrodes.

  However, in the low breakdown voltage MOSEFT having a breakdown voltage of about 100 V or less, the drift layer is as thin as about a dozen μm in order to reduce the on-resistance. Therefore, in order to alleviate the electric field concentration at the bottom corner of the gate trench, when the bottom height of the source trench electrode penetrating the drift layer is arranged below the bottom height of the gate insulating layer, the inside of the source trench is covered. Most of the breakdown voltage between the drain and source must be maintained only by the source trench insulating film. Therefore, in order to improve the breakdown voltage, it is necessary to increase the thickness of the source trench insulating film. For example, a MOSFET with a withstand voltage of 100 V requires a film thickness of at least 100 nm even when the source trench insulating film is formed of a high-quality oxide film, and the film thickness of 500 nm or more is required in consideration of variations in film quality and ensuring reliability. Necessary.

  When the source trench insulating film is formed on the bottom of the source trench by an oxide film by CVD or the like, a thick oxide film is also formed on the side wall of the source trench. Considering the electrode embedding property in a later step, the opening width of the source trench needs to be large to some extent. In general, since the source trench insulating film (interlayer insulating film) needs to be thicker than the gate insulating film, in general, the width of the source trench needs to be wider than the width of the gate trench.

  On the other hand, in order to reduce the on-resistance, it is necessary to narrow the gate trench interval and reduce the cell pitch. However, disposing a wide source trench between the gate trenches limits the reduction of the gate trench interval.

  For example, it is compared with the case where the width of the gate trench is 0.5 μm, the source trench is not formed, the cell pitch is 2 μm rule, that is, the trench interval is 1.5 μm. When the width of the source trench is 1.5 μm and the gate trench and the source trench are arranged in parallel in the unit cell, the cell pitch is 5 μm (= 0 if the same 1.5 μm trench spacing is secured. .5 + 1.5 + 1.5 + 1.5).

  In a low breakdown voltage MOSFET having a large ratio of on-resistance to channel resistance, the on-resistance is greatly increased due to the expansion of the cell pitch, and there is a case where the effect of improving the breakdown voltage is hardly exhibited.

  Accordingly, the present invention has been made in view of the above problems, and provides a trench gate type semiconductor device that realizes a high breakdown voltage and a low on-resistance.

  The trench gate type semiconductor device of the present invention includes an n (p) type drift region formed on the upper surface of an n (p) type semiconductor substrate, and a p (n) formed on the upper surface of the n (p) type drift region. Type channel region, an n (p) type source region formed on the upper surface of the p (n) type channel region, and the n (p) type drift region penetrating the source region and the p (n) type channel region A gate trench embedded in the gate trench through a gate insulating film, a source trench reaching at least the n (p) -type drift region, and an interlayer insulating film in the source trench A source electrode embedded in the gate trench, and the gate trench and the source trench are arranged to cross each other.

  In another aspect of the present invention, the bottom surface of the source electrode is located below the bottom surface of the gate insulating film.

  In another aspect of the present invention, a part of the source electrode is electrically connected to the source region on the side wall of the source trench from which the interlayer insulating film is removed.

  In another aspect of the present invention, the interlayer insulating film is characterized in that the thickness at the bottom of the trench is thicker than the thickness at the edge of the trench opening.

  In another aspect of the present invention, a floating p (n) region is provided in the n (p) type drift region below the gate trench between the source trenches.

  In another aspect of the present invention, at least two or more of the gate trenches and gate electrodes and at least two or more of the source trenches and source electrodes are provided, and the gate electrodes are connected to each other by wiring electrodes. It is characterized by being.

  In another aspect of the present invention, the wiring electrode includes a wiring trench that penetrates the source region and the p (n) type channel region and reaches the n (p) type drift region, and a wiring in the wiring trench. And a wiring electrode embedded through a trench insulating film.

  According to the present invention, it is possible to realize a structure that relaxes the electric field concentrated on the bottom corner portion of the gate trench of the drift layer and improves the breakdown voltage without greatly sacrificing the on-resistance.

  The effect of the present invention will be described in comparison with the conventional structure in which the source trench is disposed between the gate trenches in parallel with the gate trench in terms of breakdown voltage and on-resistance.

  FIG. 1 is a diagram schematically showing the arrangement of a gate trench and a source trench of a trench gate type semiconductor device according to an embodiment of the present invention, and the arrangement of a gate trench and a source trench having a conventional structure.

  With respect to the breakdown voltage, the same improvement can be realized by arranging the source trenches at a predetermined depth and interval.

  Next, the on-resistance is compared. When only the arrangement of the gate trench and the source trench is different, the on-resistance is inversely proportional to the channel width per effective area unit area of the MOSFET. Therefore, the channel widths of both are compared.

  Here, a channel width in an effective area of a 1 mm × 1 mm semiconductor device is considered. The width of the gate trench and the source trench and the trench interval are respectively common to 0.5 μm, 1.5 μm and 1.5 μm.

  In the case of the conventional structure in which the source trench is arranged in parallel with the gate trench between the gate trenches, as shown in FIG. 2A, the cell pitch, which is the distance between the gate trench and the gate trench, is 5 μm. The channel width in the area is (1 mm / 5 μm) × 2 × 1 mm = 400 mm.

  On the other hand, in the case of the trench gate type semiconductor device according to the embodiment of the present invention, as shown in FIG. 2B, when the pitch of the source trench is 5 μm as in the conventional structure, the gate trench pitch is related to the width of the source trench. From the process rule, it can be set to 2 μm. Therefore, the channel width in the effective area is (1 mm / 2 μm) × 2 × (1 mm−1.5 μm × 1 mm / 5 μm) = 700 mm.

  Therefore, according to the present invention, the same breakdown voltage improvement as the conventional structure can be obtained, the channel width can be increased by 75%, and the on-resistance can be reduced.

  Hereinafter, the best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described with reference to the drawings.

[Embodiment 1]
(Construction)
FIG. 2 is a diagram schematically showing a cross-sectional structure of the MOSFET 100 according to the first embodiment. An n ⁻ type drift region 2 and a p type channel p region 3 in which a channel as an electron path is formed are sequentially stacked on an n ⁺ type substrate 1 made of silicon, and electrons are conducted on the upper surface of the channel p region 3. An n ⁺ type source region 4 is formed. The gate trench 5 is a groove that penetrates the n ⁺ type source region 4 and the channel p region 3 and reaches the n ⁻ type drift region 2, and the gate trench 5 is made of polycrystalline silicon via the gate insulating film 6. A gate electrode 7 is embedded.

The source trench 8 is a groove that penetrates the source region 4, the p-type channel region 3, and the n ⁻ -type drift region 2 and reaches the n ⁺ -type substrate 1, and is orthogonal to the gate trench. Further, a buried source electrode 10 is buried in the source trench 8 via an interlayer insulating film 9.

Since the gate electrode 7 is divided by the source trench 8, the gate electrode 7 is made of polycrystalline Si embedded in the gate connection groove 20 provided in parallel to the source trench 8 in order to apply a voltage to the gate electrode 7. Are connected to each other and connected to the outside from the end of the MOSFET 100. In the MOSFET 100 of the first embodiment, as an example, the connection wiring is arranged in a direction parallel to the source trench 8. A source surface electrode 13 is formed on the upper surface of the buried source electrode 10, and a drain electrode 14 is formed on the back surface of the n ⁺ type substrate 1.

The interlayer insulating film 9 is removed from a region in contact with the n ⁺ -type source region 4 between the gate trench 5 and the gate trench 5, and the buried source electrode 10 extends to the removed region, and the side wall of the source trench 8 is formed. Source region 4 and channel region 3 are electrically connected to buried source electrode 10. According to the structure in which the n ⁺ -type source region 4 and the channel p region 3 and the buried source electrode 10 are electrically connected on the side wall of the source trench, it is necessary to secure a contact area for electrical connection on the surface of the semiconductor device. Therefore, the gate pitch can be reduced and the on-resistance can be reduced.

Here, the position of the bottom surface of the buried source electrode 10 (height), n ^- the position of the ^- (bottom of the interface between the type drift region 2 gate insulating film 6 and n) a bottom of the gate trench 5 in the type drift region 2 It is preferably below (height).

With this configuration, it is possible to reduce the concentration of the electric field at the bottom corner of the gate that determines the breakdown voltage of the trench MOSFET, and to improve the breakdown voltage. To alleviate this electric field concentration, a source potential is applied via the interlayer insulating film 9 to the n ⁻ type drift region 2 existing at the bottom of the gate by the buried source electrode 10, and the depletion layer in the n ⁻ type drift region 2 is By expanding.

If the height of the bottom surface of the buried source electrode 10 is substantially the same as the position of the bottom surface of the gate trench 5, the n ⁻ -type drift region 2, and the interface, there is an effect of reducing the electric field concentration at the bottom of the gate trench, If the gate trench 5 and the n ⁻ -type drift region 2 are below the bottom of the interface, the electric field distribution is expanded on the drain side, and a greater breakdown voltage improvement effect can be obtained.

  Here, in the MOSFET 100 according to the first embodiment, the source trench 8 is an example orthogonal to the gate trench 5, but the source trench 8 and the gate trench 5 do not have to be orthogonal but only need to intersect. As long as they intersect, the withstand voltage can be improved by the buried source electrode 10 and the gate pitch can be reduced regardless of the source trench width and the source trench shape, and the on-resistance can be reduced. However, it is preferable that the source trench 8 and the gate trench 5 be orthogonal to each other under the condition that the distance between the trench and the trench is constant due to the gate trench width, the source trench width, and the process restrictions. This is because the volume at which the source trench 8 and the gate trench 5 intersect can be made smallest and the channel width becomes the longest, so that the on-resistance can be made smaller.

Further, in MOSFET100 according to the first embodiment of the present invention, the source trenches 8 has been a structure reaching the n ⁺ -type substrate 1, not reach the n ⁺ -type substrate 1, bottom the n ^- -type drift region 2 You may stay. This is because the effect of improving the breakdown voltage is not directly determined by the depth of the source trench 8 but is determined by the height of the bottom surface of the buried source electrode 10 and the height of the interface between the gate trench 5 and the n ⁻ -type drift region 2. . The difference between the height of the bottom surface of the source trench 8 and the height of the bottom surface of the buried source electrode 10 is determined by the thickness of the bottom portion of the interlayer insulating film 9. Source trenches 8, when a structure reaching the n ⁺ -type substrate 1, the source - the breakdown voltage between the drain (n ⁺ -type substrate 1), must be held only in the interlayer insulating film 9, the source trenches 8, n ^- case of the structure that remains on the type drift region 2, the source - the breakdown voltage of the drain (n ⁺ -type substrate 1), n ^- the source trenches 8 type drift region 2 and the portion and the interlayer insulating film 9 under Need to hold in. In any case, the withstand voltage of the interlayer insulating film 9 depends on the insulating film quality. Therefore, whether the source trench 8 has a structure that penetrates the n-type drift layer or a structure in which the bottom surface of the source trench 8 remains in the n-type drift layer depends on the height of the bottom surface of the buried source electrode 10. This is determined by the effect and the quality and thickness of the interlayer insulating film 9.

Further, in MOSFET100 according to the first embodiment, and the source electrode 10 buried n ⁺ -type source region 4 and the channel p region 3, an example has been described taking the electrical connections and contacts in the source trench sidewall, n ⁺ -type source The buried source electrode 10 may be in contact with the n ⁺ -type source region 4 and the channel p region 3 on the upper surface of the region 4 to establish electrical connection.

In order to electrically contact the buried source electrode 10 with the n ⁺ -type source region 4 and the channel p region 3 at the side wall of the source trench 8, an interlayer insulating film 9 is formed between the gate trench 5 and the gate trench 5. ^It is necessary to perform etching to remove a region in contact with the ⁺ type source region 4. The etching depth needs to penetrate the n ⁺ type source region 4 and remain in the channel p region 3, so that high accuracy is required. For this reason, the buried source electrode 10 and the n ⁺ -type source region 4 and the channel p region 3 are not electrically contacted by the side wall of the source trench, but are electrically connected by the n ⁺ -type source region 4 and the channel p region 3 on the upper surface of the wafer. With the contact structure, an etching process that requires high accuracy can be eliminated, and a stable contact resistance can be realized.

The interlayer insulating film 9 in the source trench 8 is preferably thicker at the bottom of the trench than at the opening edge of the source trench. The interlayer insulating film 9 at the bottom of the source trench 8 needs to have a certain thickness or more in order to obtain a withstand voltage between the buried source electrode 10 and the n ⁺ type substrate 1. On the other hand, it is not necessary to increase the thickness of the interlayer insulating film 9 at the edge of the source trench in order to obtain a withstand voltage. Conversely, the thinner the interlayer insulating film 9, the narrower the source trench 8 and the wider the channel width. Therefore, the on-resistance can be reduced. The opening width of the source trench 8 on the wafer upper surface (edge) is determined to be an opening width that allows the interlayer insulating film 9 having a predetermined thickness to be deposited on the bottom of the source trench 8. This is because when the interlayer insulating film 9 is deposited by the CVD method or the like, if the opening width is narrow, the insulating film material does not reach the bottom of the trench sufficiently, and an insulating film having a required thickness cannot be deposited. Therefore, according to this structure, a high breakdown voltage and a low on-resistance can be realized.

  In the MOSFET 100 according to the first embodiment of the present invention, the structure in which the substrate is an n-type is taken as an example. However, the conductivity types of the semiconductor layers and regions may be opposite to each other. For example, the substrate, drift region and source region may be p-type and the channel region may be n-type. In that case, the same operation as the MOSFET 100 according to the first embodiment is performed using holes as carriers. Furthermore, although silicon is used as a semiconductor in this embodiment, a compound semiconductor can also be used.

Further, as a structure for reducing the concentration of the electric field at the bottom corner of the gate, the buried electrode is electrically connected to the source electrode. However, the buried electrode and the source electrode are not electrically connected, and the buried electrode is not electrically connected. A potential different from the source potential may be applied to the capacitor. Even if the potential of the buried electrode is not the ground potential which is the source potential, the depletion layer of the n ⁻ type drift region 2 can be expanded in the depth direction.

(Simulation of device performance)
Next, the improvement of the drain-source breakdown voltage of the MOSFET 100 according to the first embodiment of the present invention will be described.

  FIG. 3 is a cross-sectional view of the gate trench at the time of breakdown near the gate trench bottom 5B of a trench gate type semiconductor device provided with a source trench and a trench gate type semiconductor device having a conventional structure without a source trench obtained by simulation. It is the figure which showed electric field distribution. FIG. 4 is a diagram showing the distribution of the electric field strength in the depth direction in the AA cross section of FIG.

In the conventional structure in which the source trench shown in FIGS. 3A and 4A is not provided, the electric field concentrates in the vicinity of the gate trench bottom 5B in the n ⁻ type drift region 2 and breakdown occurs. On the other hand, in the trench gate type semiconductor device provided with the source trench shown in FIG. 3B and FIG. 4B, the buried source electrode 10 that is at the ground potential extends the depletion layer of the n ⁻ type drift region 2 in the depth direction. Therefore, the electric field distribution is relaxed compared with the conventional structure, and the peak of the electric field strength is lowered. As shown in FIG. 4B, in the trench gate type semiconductor device provided with the source trench, it can be seen that the electric field concentration is relaxed and the breakdown voltage is improved by the area indicated by the hatched region.

Specifically, when the n-type doping concentration of the n ⁻ -type drift region 2 is 1 × 10 ¹⁶ cm ⁻³ and the thickness is 6 μm, the breakdown voltage, which is about 50 V in the conventional structure without the source trench, is The source trench structure can improve the voltage to about 80V.

  On the other hand, when the electric field distribution is considered in terms of a plane parallel to the substrate (a plane perpendicular to the gate trench), in the MOSFET 100 of Embodiment 1 of the present invention, the electric field is adjacent to the bottom of the gate trench farthest from the source trench, that is, adjacent. Concentrate at the bottom of the gate trench located at the midpoint of the source trench. Therefore, the breakdown voltage between the drain and the source depends on the source trench pitch.

FIG. 5 is a diagram showing the relationship between the source trench pitch and the breakdown voltage of the MOSFET 100 according to the first embodiment of the present invention, obtained by simulation. The thick line indicates the breakdown voltage when there is no source trench structure. In the simulation, for example, the doping concentration of the n ⁻ type drift region 2 is 1 × 10 ¹⁶ cm ⁻³ , the source trench width is 1.5 μm, the thickness of the interlayer insulating film 9 of the source trench is 0.5 μm, The depth was set to 2.0 μm, and the thickness of the gate insulating film 6 was set to 0.1 μm.

  As shown in FIG. 5, it can be seen that the breakdown voltage increases as the source trench pitch decreases. Under these conditions, the effect of improving the breakdown voltage becomes significant when the source trench pitch is about 5 μm or less. If the conditions such as the doping concentration of the drift layer and the thickness of the interlayer insulating film 9 of the source trench are different, the source trench pitch at which the effect of improving the withstand voltage becomes remarkable varies depending on the conditions.

  On the other hand, the on-resistance increases as the source trench pitch decreases. This is because the volume where the source trench 8 and the gate trench 5 intersect increases and the channel width becomes narrow.

  Accordingly, the source trench pitch is appropriately determined within a range that is as small as possible to obtain the drain-source breakdown voltage improvement effect required for the trench gate type semiconductor device and a large value so that a desired on-resistance can be obtained. .

  Further, as described above, the breakdown voltage is determined by the source trench pitch if the source trench width is constant. That is, the breakdown voltage is determined by the distance between the side walls of adjacent source trenches. Therefore, by narrowing the source trench width while maintaining the distance between the side walls of adjacent source trenches, the channel width can be increased and the on-resistance can be reduced without reducing the drain-source breakdown voltage. .

(Production method)
A manufacturing process of MOSFET 100 according to the first embodiment of the present invention will be described with reference to the drawings. 6 to 8 are process diagrams for explaining the manufacturing process.

First, as shown in FIG. 6A, a stripe-shaped gate trench 5 and a channel p region are formed on a wafer obtained by epitaxially growing an n ⁻ type drift region 2 on an n type substrate 1 using a widely known semiconductor process. 3 and n ⁺ type source regions 4 are formed.

Next, as shown in FIG. 6B, a SiO 2 film deposited on the entire surface of the wafer by a CVD method is formed in a source trench mask pattern by using a photolithography method. Using this SiO 2 film as a mask, the source trench 8 is formed by a dry etching method such as RIE. In the example shown in FIG. 6B, the source trench 8 has a depth reaching the n-type substrate 1 through the n ⁻ -type drift region 2. Here, in order to form the source trench 8 deeper than the gate trench 5, the etching is performed under a condition with a low Si / SiO2 selection ratio.

  Next, as shown in FIG. 7C, an interlayer insulating film 9 having a predetermined thickness is deposited in the source trench 8 by the CVD method.

  Next, as shown in FIG. 7D, polysilicon doped with impurities is deposited on the entire surface of the wafer so as to fill the source trench 8 covered with the interlayer insulating film 9. Then, the polysilicon on the wafer surface other than in the source trench 8 is removed by etch back. The remaining doped polysilicon in the source trench 8 becomes the buried source electrode 10.

Next, as shown in FIG. 8 (e), the n ⁺ -type source region 4 and the channel p region 3 of the buried source electrode 10 are removed by an anisotropic etching method such as RIE. To do. This etching is performed until the height of the surface of the buried source electrode 10 to be etched reaches a height at which the channel p region 3 is located. Further, the interlayer insulating film 9 is etched by a wet etching method to form a contact groove 12 to expose the contact surfaces of the n ⁺ type source region 4 and the channel p region 3 on the side wall of the source trench.

Next, as shown in FIG. 8F, a source surface electrode 13 for embedding the contact groove 12 with a metal such as a gold alloy and polysilicon is formed. Thereafter, the drain electrode 14 is formed on the back surface of the n ⁺ type substrate 1.

[Embodiment 2]
(Construction)
FIG. 9 is a diagram schematically showing a cross-sectional structure of the MOSFET 101 according to the second embodiment of the present invention. The MOSFET 101 includes a floating p region 15 below the gate trench 5 between the source trenches 8 in addition to the configuration of the MOSFET 100 according to the first embodiment.

  As can be seen from the simulation results of the device performance of the MOSFET 100 of the first embodiment shown in FIG. 5, the smaller the source trench pitch, the higher the breakdown voltage, but the on-resistance also increases. Therefore, in the MOSFET 101 according to the second embodiment, as shown in FIG. 9, a floating p region 15 is provided below the gate trench 5 between the source trenches 8, and an electric field from the source trench 8 is applied to the floating p region 15. The floating p region 15 has the same function as that of the source trench 8.

  Therefore, according to the structure of the MOSFET 101 according to the second embodiment, substantially the same breakdown voltage can be maintained even when the source trench pitch is increased by the width of the floating p region 15 as compared with the structure without the floating p region 15. On the other hand, since the source trench pitch is widened, the volume at which the gate trench and the source trench intersect with each other is reduced, and the channel width is widened, so that the on-resistance can be lowered.

(Production method)
In the manufacturing process of the MOSFET 101 according to the second embodiment, the manufacturing process of the floating p region 15 is inserted into the manufacturing process of the MOSFET 100 according to the first embodiment.

There are two methods for manufacturing the floating p region 15. In the first method, the floating p region 15 is selected by patterning the n ⁺ type substrate 1 before epitaxially growing the n ⁻ type drift region 2 on the n ⁺ type substrate 1 shown in FIG. In this method, the n ⁻ type drift region 2 is epitaxially grown on the entire surface by epitaxial growth and then removing the patterning mask. The second method is a method of performing p-type doping such as B on the n ⁻ -type drift region 2 at the bottom of the gate trench 5 by high-speed ion implantation after the gate trench 5 is etched. In the high-speed ion implantation method, since the ion implantation depth can be controlled according to the acceleration energy condition, a region having a predetermined depth in the n ⁻ -type drift region 2 at the bottom of the gate trench can be used as the floating p region 15.

[Embodiment 3]
FIG. 10 is a diagram schematically showing a cross-sectional structure of the MOSFET 102 according to the third embodiment. In the MOSFET 100 according to the first embodiment, the gate connection groove 20 for connecting the gate electrodes 7 to each other and electrically connecting to the outside has the same structure as the gate. However, the MOSFET 102 includes the gate connection groove 20 in the source trench. It has the same structure.

The gate connection groove 20 of the MOSFET 102 according to the third embodiment is a groove that penetrates the source region 4, the p-type channel region 3, and the n ⁻ -type drift region 2, reaches the n ⁺ -type substrate 1, and is orthogonal to the gate trench. The doped polysilicon is buried in the gate connection trench 20 through the interlayer insulating film 9. Further, the gate electrodes 7 are electrically connected to each other in the same manner as the contact between the buried source electrode 10 and the source region 4 and the p-type channel region 3.

  According to this structure, since it is not necessary to form a source trench pattern between the already formed fine gate connection groove 20 patterns, a highly accurate mask alignment process in photolithography can be eliminated.

It is a figure which shows typically arrangement | positioning of the gate trench of a trench gate type semiconductor device of the Example of this invention, and a source trench, and arrangement | positioning of the gate trench of a conventional structure, and a source trench. It is a figure which shows typically the cross-section of MOSFET100 which concerns on Embodiment 1 of this invention. It is the figure which showed the electric field distribution at the time of the breakdown of gate trench bottom 5B vicinity with the trench gate type semiconductor device which provided the source trench, and the trench gate type semiconductor device of the conventional structure which does not provide a source trench. It is a figure which shows the distribution to the depth direction of the electric field strength in the AA cross section of FIG. It is a figure which shows the relationship between the source trench pitch of the trench gate type semiconductor device 100 of Embodiment 1 of this invention, and a proof pressure. It is a figure explaining the manufacturing process of MOSFET100 concerning Embodiment 1 of this invention. It is a figure explaining the manufacturing process of MOSFET100 concerning Embodiment 1 of this invention. It is a figure explaining the manufacturing process of MOSFET100 concerning Embodiment 1 of this invention. It is a figure which shows typically the cross-section of MOSFET101 which concerns on Embodiment 2 of this invention. It is a figure which shows typically the cross-section of MOSFET102 which concerns on Embodiment 3 of this invention.

Explanation of symbols

  1 substrate, 2 drift region, 3 channel p region, 4 source region, 5 gate trench, 6 gate insulating film, 7 gate electrode, 8 source trench, 9 interlayer insulating film, 10 source electrode, 11 source trench mask, 12 contact trench , 13 source surface electrode, 14 drain electrode, 15 floating p region, 20 gate connection groove, 100, 101, 102 MOSFET.

Claims (7)

An n (p) type drift region formed on the upper surface of an n (p) type semiconductor substrate having a drain electrode on the lower surface;
A p (n) type channel region formed on the upper surface of the n (p) type drift region;
An n (p) type source region formed on the upper surface of the p (n) type channel region;
A gate trench that penetrates the source region and the p (n) type channel region and reaches the n (p) type drift region;
A gate electrode embedded in the gate trench through a gate insulating film;
A source trench reaching at least the n (p) -type drift region;
A source electrode embedded in the source trench through an interlayer insulating film;
With
The trench gate type semiconductor device, wherein the source trenches are arranged to intersect with the gate trench. The trench gate type semiconductor device according to claim 1,
The trench gate type semiconductor device, wherein a bottom surface of the source electrode is located below a bottom surface of the gate insulating film. A trench gate type semiconductor device according to claim 1 or 2,
A part of the source electrode is electrically connected to the source region and the p (n) type channel region on the side wall of the source trench from which the interlayer insulating film is removed. A trench gate type semiconductor device according to any one of claims 1 to 3,
The trench gate type semiconductor device, wherein the interlayer insulating film is thicker at the bottom of the trench than at the edge of the trench opening. A trench gate type semiconductor device according to any one of claims 1 to 4,
A trench gate type semiconductor device comprising a floating p (n) region in the n (p) type drift region below the gate trench between the source trenches. A trench gate type semiconductor device according to any one of claims 1 to 5,
At least two or more of said gate trenches and gate electrodes;
At least two or more of the source trenches and source electrodes;
With
The trench gate type semiconductor device, wherein the gate electrodes are connected to each other by wiring electrodes. The trench gate type semiconductor device according to claim 6,
The wiring electrode includes a wiring trench that passes through the source region and the p (n) channel region and reaches the n (p) drift region, and a wiring embedded in the wiring trench via a wiring trench insulating film A trench gate type semiconductor device comprising an electrode.

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