JP4195520B2 - Phase measuring device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a phase measurement device that measures a phase difference between two signals.
[0002]
[Prior art]
Conventionally, as a method for measuring a phase difference between signals, an exclusive OR circuit method and a flip-flop method are used. The exclusive OR method includes two waveform shaping circuits that respectively receive two signals for measuring a phase difference, an exclusive OR gate that receives these two waveform shaped signals at two inputs, An integrating circuit that receives the output and a meter that receives the integrated output. In this circuit system, in order to obtain an exclusive OR of two waveform shaping outputs, a value proportional to the length of a period during which only one waveform is high is displayed as a phase difference as a meter.
[0003]
On the other hand, in the flip-flop method, similarly, two waveform shaping circuits each receiving two signals whose phase difference is to be measured, and an RS flip-flop that receives one output of the waveform shaping circuit at the set terminal and the other output at the reset terminal And an integration circuit that receives the Q output of the flip-flop, and a meter that receives the integration output. In this flip-flop method, a value related to the length of a period from one leading edge (or trailing edge) to the other leading edge (or trailing edge) of two waveform shaping outputs is displayed as a phase difference by a meter. .
[0004]
[Problems to be solved by the invention]
The above-mentioned conventional exclusive OR circuit system has an advantage that the circuit is simple and resistant to noise, but a phase difference measurement error occurs due to a change in the waveform shape of the measurement signal, that is, the duty ratio of the waveform shaping signal. There is a drawback. Further, since the output of the exclusive OR gate is related only to the absolute value of the phase difference, it is not possible to determine the phase delay advance.
[0005]
On the other hand, the conventional flip-flop system has advantages that the circuit is simple, is not affected by the duty ratio of the waveform, and the measurement edge (leading edge or trailing edge) can be selected. However, the RS flip-flop set / reset timing may fluctuate due to the influence of noise, so that there is a drawback that it is necessary to consider noise. Also, since the set timing and reset timing are reversed back and forth between the phase lag and advance, the flip-flop output changes greatly, and therefore the meter output becomes unstable near a phase difference of 0 degrees. There are drawbacks.
[0006]
Accordingly, an object of the present invention is to provide a phase measuring apparatus capable of detecting the lag advance, that is, the polarity of the phase difference in addition to the absolute value of the phase difference with a simple circuit.
[0007]
Another object of the present invention is to provide a phase measuring device that is less susceptible to noise.
[0008]
Another object of the present invention is to provide a phase measurement device capable of generating a phase difference measurement output that continuously changes with respect to a continuous change in phase difference.
[0009]
[Means for Solving the Problems]
To achieve the above object, the phase measuring apparatus according to the present invention is connected to the first and second input signals to be measured for phase difference, and the first and second waveforms obtained by shaping the waveforms of these signals are provided. A waveform shaping means for generating a second shaping signal; b) an absolute value of a phase difference between the first and second shaping signals, connected to receive the first and second shaping signals; A phase difference absolute value detecting means for generating a first logic signal including a pulse having a pulse width related to (c), and c) receiving the first and second shaping signals, and connecting the first and second shaping signals. Phase difference polarity detection means for generating a second logic signal indicating the polarity of the phase difference between the shaping signals of the first and second signals; and d) coupling logic means connected to receive the first logic signal and the second logic signal. And the second logic signal indicates one of positive and negative polarity. Only when the first logic signal is generated as the first output logic signal and the second logic signal indicates the other of the positive and negative polarities, the first logic signal is generated as the second output logic signal. The coupling logic means generated as a signal; and e) connected to receive the first output logic signal from the coupling logic means, integrating the first output logic signal and obtaining the result as a first A first integrating means for generating an integrated signal; and f) connected to receive the second output logic signal from the coupling logic means, and integrating the second output logic signal to obtain a second result. A second integrating means for generating an integrated signal; and g) a first input connected to receive the first integrated signal, and a second input connected to receive the second integrated signal. , Representing the difference between the first integral signal and the second integral signal Coupling means for generating a signal, h) connected to receive said difference signal, and display means for generating an indication of the phase difference in response to said difference signal consists.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of the present invention will be described in detail with reference to the drawings.
[0011]
FIG. 1 shows a phase measuring apparatus according to the present invention, which is roughly divided into a waveform shaping unit 1, a phase difference absolute value / polarity detection unit 2, a coupling logic unit 3, an integration circuit unit 4, and a coupling unit. The unit 5 and the display unit 6 are included. Specifically, the waveform shaping unit 1 includes two waveform shaping circuits 10 and 12, and each of the shaping circuits may have any known circuit configuration. Each of these circuits 10 and 12 has an input for receiving two inputs A _in and B _in for which a phase difference is to be measured, and each output thereof is a shaped output obtained by binarizing the waveform and shaping the waveform. A _s and B _s are generated.
[0012]
The next phase difference absolute value / polarity detection unit 2 includes an exclusive OR gate 20 and a D-type flip-flop 22. Exclusive OR gate 20 connects one input to the output of the waveform shaping circuit 10 receives the output A _s, also connected another input to the output of the waveform shaping circuit 12 receives the output A _s. The gate 20, the output, these two inputs, i.e., the output A _s, for generating an output P _a representative of the phase difference absolute value is the result of an XOR operation of B _s. That is, the output P _a is only one of the output A _s and the output B _s becomes high at the high, is otherwise low, their output by the length of the high period of the phase shift magnitude of Form a signal to represent. D-type flip-flop 22, D input is connected to the output of the shaping circuit 10 receives the output A _s, CLK input connected to the output of the shaping circuit 12 receives the output B _s, and the Q output position An output P _p representing the polarity of the phase difference is generated. That is, the output P _p becomes high when the output A _s is high at the leading edge or the rising edge of the output B _s , for example, and the input B _in is delayed _in phase from the reference input A _in (that is, Conversely, the phase difference polarity is negative), and conversely, when the output A _s is low at the leading edge or rising edge of the output B _s , the output B _s is low, and the phase of the input B _in advances from the reference input A _in (That is, the phase difference polarity is positive).
[0013]
Next, the combination logic unit 3 is configured by a logic circuit including two AND gates 30 and 32 and one inverter. AND gates 30 and 32 receives the phase difference absolute value output P _a respective one of the inputs of are connected to the output of the exclusive OR gate 20, and the other input of the gate 30 is connected to the output of the inverter 34 ing. The other input of the gate 32 is connected to the Q output of the flip-flop 22 together with the input of the inverter 34 to receive the phase difference polarity output P _p . AND gate 30, by the phase difference polarity output P _p is passing only the phase difference absolute value output P _a time indicating the That advance phase state at a low, generating a phase advance amount output P _lead. On the other hand, the AND gate 32, by the phase difference polarity output P _p is passing only the phase difference absolute value output P _a time indicating ie slow state when high, generating a slow amount output P _lag.
[0014]
Next, the integrating circuit unit 4 is composed of two integrating circuits 40 and 42, and each integrating circuit may have any known circuit configuration. Integrator circuit 40 has an input receiving a connection to the phase advance amount output P _lead to the output of an AND gate 30, and generates a integrating the phase advance amount integrated output I _lead it to its output. On the other hand, the integrating circuit 42 has an input connected to the output of the AND gate 32 to receive the delay amount output P _lag , and generates a delay amount integration output I _lag obtained by integrating it at its output.
[0015]
Next, the coupling unit 5 for receiving these outputs is composed of a differential amplifier, which is composed of an operational amplifier 50 and a group of resistors R1, R2, R3, and R4. Specifically, the inverting input of the operational amplifier 50 is connected to the output of the integrating circuit 42 via the resistor R1 to receive the output I _lag , and the non-inverting input is integrated via the resistor R3. It is connected to the output of the circuit 40 to receive the output I _lead . Resistor R2 is connected between the inverting input and output of the operational amplifier, and resistor R4 is connected between the non-inverting input and ground. In this differential amplifier, the gains of the inverting input and the non-inverting input are made equal by setting the values of R1-R4. Thus, the differential amplifier determines the difference between the two received inputs, ie, (I _lead −I _lag ), and generates a phase difference output P _d proportional to this difference.
[0016]
Finally, the display unit 6 includes an analog-type meter 60 that indicates a phase difference, and this meter has an input for receiving the phase difference output P _d from the coupling unit 5.
[0017]
Next, the operation of the phase measuring apparatus according to the present invention will be described with reference to FIG. For explanation, it is assumed that a sine wave input B _in having the same period as the input A _in is delayed by an angle θ with respect to the reference sine wave input A _in . In this case, the waveform shaping unit 1 performs waveform shaping by binarizing at a predetermined threshold value, 0 volt which is an intermediate value of a sine wave in this example. Therefore, the duty ratio of these shaping waveforms A _s and B _s is 50%. As a result, in the next exclusive OR gate 20, when on the basis of the period of the input A _in, for generating an output P _a to be high for 0 ° ~θ degree and 180 degrees ~ (180 + θ) degrees. The flip-flop 22, since the molding input A _s to the front edge, that is, when the rising edge of the shaped output B _s of the CLK terminal is positive, the phase difference polarity output P _p becomes high indicating a phase lag. When the output P _p is high, the AND gate 30 is closed, while the phase advance amount output P _lead is low, gate 32 is opened, the phase difference absolute value output P _a becomes slow amount output P _lag. Thereby, the integral output I _lead becomes zero, and the integral output I _lag takes a positive value. At this time, the output P _{d of the} differential amplifier becomes a value proportional to the integral output I _lag and instructs the meter 60 to express the positive phase difference.
[0018]
On the other hand, when the phase of the input B _in is advanced with respect to the input A _in , the output P _p is low, the AND gate 32 is closed, and the delay amount output P _lag is low, contrary to the above case. On the other hand, the phase difference absolute value output P _a phase advancing amount output P _lead next to gate 30 is opened also, the integration output I _lag zero, the integrated output I _lead is a positive of a value. Thereby, the output P _d of the differential amplifier has a value proportional to the integrated output I _lead, the meter 60 directs the negative retardation represented by that value.
[0019]
When the input A _in and the input B _in are in phase, the output P _p becomes either low or high due to a slight difference in timing, so that either the AND gate 30 or 32 opens. However, in the case of in-phase, the phase difference absolute value outputs P _a , P _lead and P _lag remain completely low or almost low, so that the integral outputs I _lead and I _lag are zero or almost zero. As a result, the output P _{d of the} differential amplifier, and hence the phase difference indicated by the meter 60, is also zero or almost zero.
[0020]
As a result, as shown in FIG. 3, even when the phase difference continuously changes from negative to positive or from positive to negative across zero, the output P _{d of the} differential amplifier continuously changes. Even during continuous changes crossing zero, there is no discontinuity in the differential amplifier output P _d . As described above, according to the phase measuring device of the present invention, an indication without discontinuity is provided for the absolute value and polarity of the phase difference with a simple circuit configuration.
[0021]
In the embodiment of the present invention described above, the following modifications are possible. First, the exclusive OR gate 20 and the D-type flip-flop 22 may be realized by any other circuit configuration as long as they perform an equivalent function. Further, although the coupling logic unit is also configured by two AND gates and one inverter, it can also be realized by any other circuit configuration that performs an equivalent function. Secondly, the meter 60 may be a digital indicator instead of an analog type.
[0022]
【The invention's effect】
As described above, according to the phase measurement apparatus of the present invention, a continuous phase difference measurement output can be generated by combining the combination logic unit and the combination unit. In addition, by detecting the absolute value of the phase difference and detecting the polarity, it is possible to detect the lag advance of the phase difference. In addition, the use of an exclusive OR gate realizes a circuit configuration that is less susceptible to noise.
[Brief description of the drawings]
FIG. 1 is a block circuit diagram showing a phase measuring apparatus according to the present invention.
FIG. 2 is a timing chart showing an output waveform appearing in the phase measuring apparatus of FIG. 1;
3 is a graph showing the relationship between the differential amplifier output and the phase difference represented by it in the phase measurement device of FIG. 1;
[Explanation of symbols]
1: Waveform shaping unit 2: Phase difference absolute value / polarity detection unit 3: Coupling logic unit 4: Integration circuit unit 5: Coupling unit 6: Display unit

Claims (5)

A phase measuring device comprising:
A) Waveform shaping means connected to receive the first and second input signals whose phase difference is to be measured, and which generates first and second shaping signals obtained by shaping the waveforms of these signals;
B) a first logic signal connected to receive the first and second shaped signals and including a pulse having a pulse width related to an absolute value of a phase difference between the first and second shaped signals; Phase difference absolute value detecting means for generating
C) Phase difference polarity detection means connected to receive the first and second shaping signals and generating a second logic signal indicating the polarity of the phase difference between the first and second shaping signals. When,
D) coupled logic means connected to receive the first logic signal and the second logic signal, and only when the second logic signal indicates one of positive and negative polarity; Generating one logic signal as a first output logic signal and generating the first logic signal as a second output logic signal only when the second logic signal indicates the other of the positive and negative polarities; A combination logic means of
E) first integrating means connected to receive the first output logic signal from the coupling logic means, integrating the first output logic signal and generating the result as a first integration signal;
F) second integration means connected to receive the second output logic signal from the coupling logic means, integrating the second output logic signal and generating the result as a second integration signal;
G) having a first input connected to receive the first integrated signal and a second input connected to receive the second integrated signal, the first integrated signal and the second integrated signal; Coupling means for generating a difference signal representative of the difference between
H) display means connected to receive the difference signal and generating an indication of the phase difference in response to the difference signal;
A phase measuring device. The phase measuring device according to claim 1,
The coupling means comprises differential amplifier means having a non-inverting input connected to the first input and an inverting input connected to the second input;
A phase measuring device characterized by the above. The phase measuring device according to claim 1 or 2,
The phase difference absolute value detecting means obtains an exclusive OR of a first input for receiving the first shaping signal, a second input for receiving the second shaping signal, and the first and second shaping signals. An exclusive OR gate having an output that generates an exclusive OR signal representing the first logic signal;
A phase measuring device characterized by the above. The phase measuring device according to any one of claims 1 to 3,
The phase difference polarity detection means includes a D-type flip-flop having a D input for receiving the first shaping signal, a CLK input for receiving the second shaping signal, and a Q output for generating the second logic signal. Was it,
A phase measuring device characterized by the above. The phase measuring device according to any one of claims 1 to 4,
The combination logic means includes:
A) a first AND gate having a first input connected to receive the first logic signal, a second input, and an output;
B) a second AND gate having a first input connected to receive the first logic signal, a second input connected to receive the second logic signal, and an output;
C) an inverter having an input connected to receive the second logic signal and an output connected to the second input of the first AND gate;
A phase measuring device characterized by comprising:

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