JPS614972A - Frequency discriminating circuit - Google Patents

Abstract

PURPOSE:To improve the accuracy of frequency measurement through simple constitution by detecting the most significant digit bits and bits of other digits of the output of an (n)-bit binary counter and discriminating whether the frequency of input pulses is larger than a specific value and the range of the frequency. CONSTITUTION:The frequency discriminating circuit consists of the (n)-bit binary counter 1 which has an input terminal 2, reset terminal 3, and output terminals 40-4n. Then, input pulses whose frequency is to be detected are applied to the input terminal 2 and a reset pulse is applied to the reset terminal 3 at every tsec. Then, outputs of the output terminals 40-4n are detected to discriminate whether the frequency of the input pulses is >=2<h>/t Hz or not on the basis of an H or L level output appearing at the output terminal 4n for the most significant digit bit and also measures accurately the frequency range of the input pulses on the basis of H or L level outputs appearing at the output terminals 40-4n for respective digit bits.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a frequency discrimination circuit for input pulse frequencies to a digital circuit or a pulse circuit.

<Prior Art> Conventionally, this type of frequency discrimination circuit, as shown in FIG. The output pulse width of the mono multivibrator 5 is determined by its time constant OR.The external part of the retriggerable mower multivibrator 5 is composed of a component capacitor C and a resistor R, and the output pulse of the retriggerable mower multivibrator 5 is used as a latch signal. The signal was output to a latch circuit 6, and the output of the latch circuit 6 was used to perform frequency discrimination.

This frequency discrimination circuit compares the output pulse width of the retriggerable mower multivibrator 5, which is determined by the time constant CR of the external component capacitor C and the resistor R, with the input pulse width, and calculates the triggerable mono multivibrator based on the input pulse width. 5, the input pulse is latched by the latch circuit 6, so the output of the latch circuit 6 becomes H (high level), and the frequency of the input pulse is 1/C.
R or less and the input pulse width is smaller than the output pulse width of the retriggerable mower multivibrator 5, the input pulse is not latched by the latch circuit 6, the output of the latch circuit 6 becomes L (low level), and the input It can be determined that the frequency of the pulse is 1/CR or more.

<Problems to be Solved by the Invention> However, in such a conventional frequency discrimination circuit, the time constant of charging and discharging the capacitor C changes due to variations in the capacitance value and resistance value of the capacitor C and the resistor R, and therefore the output pulse width This has the drawback that the accuracy of frequency detection deteriorates. In addition, if the frequency of the input pulse is more than twice the discrimination frequency set by CR, the input pulse will become H or L while the latch signal of more than one cycle is output, resulting in incorrect input pulse frequency. The disadvantage of detection is that it is H when the duty ratio is not 50%.
Since the interval between and the interval between L and L are not the same, the input pulse frequency has a drawback that there are many erroneous detections of the input pulse frequency.

The present invention aims to solve these problems.

<Means for Solving the Problems> In order to achieve the above object, the present invention provides an n-bit binary counter to which a reset signal is input every second, and the output of the n-bit binary counter is By detecting the most significant bit every second, the frequency of the input pulse is reduced to 2n/t.
It is configured to discriminate whether the frequency is above Hz or below 21''/lHz, and at the same time to discriminate the frequency range of the input pulse by detecting each output bit every second.

<Embodiment> FIG. 1 is a circuit diagram of a frequency discrimination circuit according to an embodiment of the present invention. The frequency discrimination circuit of this embodiment includes an n-bit binary counter 1. An input pulse whose frequency is to be detected is applied to an input terminal 2 of the binary counter 1, and the n-bit 2
A reset pulse is applied to the reset terminal 3 of the forward counter 1 every second. The frequency detection result is output to each of the output terminals 40, 41, . . . , 4n of the n-pinto binary counter 1.

That is, the output level I" (high level) or L (low level) appearing at the output terminal 4n of the most significant bit indicates whether the frequency (period of the large-power pulse) is 2n/tHz or more, and the output terminal of each bit The output level H or L appearing at 40, 41...4n indicates the frequency range of the input pulse depending on the combination thereof.

<Effects of the Invention> As described above, the frequency discrimination circuit of the present invention has two
Add a frequency-discriminating input pulse to the input of the counter, count it sequentially, check whether the output state of the most significant bit is 14 after one second, and calculate the frequency of the input pulse. Since it is designed to detect whether it is greater than or equal to 2'/t] (z or less than 2''/lHz, the time setting of 1 second can be achieved by inputting a reset signal every 1 second. At the same time, 2°, 21.2
The pulse frequency can be discriminated by checking whether the output state of each of the parts 2, . Furthermore, since the circuit is constructed without using external parts as in the prior art, there is no reduction in accuracy due to variations in component constants.

Furthermore, on the pulse transmission side, the frequency division ratio of the divider connected to the pulse oscillator can be discriminated by the frequency discrimination circuit of the present invention, and the effect of transmitting several types of information through one set of transmission lines can be expected.

In this way, the present invention has the effect that it is possible to discriminate the frequency of pulse waves with a very simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a frequency discrimination circuit diagram of a conventional example, and FIG. 2 is a frequency discrimination circuit diagram of an embodiment of the present invention. 1 is an n-bit binary count, 5 is a retriggerable mono multi-byte break, and 6 is a latch circuit.

Claims (1)

[Claims] (1) An n-bit binary counter to which a reset signal is input every t seconds, and by detecting the most significant bit of the output of this n-bit binary counter every t seconds, the frequency of the input pulse is 2^ Is it higher than n/tHz or 2^n/t
A frequency discrimination circuit that discriminates the frequency range of an input pulse by discriminating whether the input pulse is below Hz and simultaneously detecting each output bit every t seconds.