JP4195439B2 - 集積回路及び携帯電子機器 - Google Patents
集積回路及び携帯電子機器 Download PDFInfo
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- JP4195439B2 JP4195439B2 JP2004353482A JP2004353482A JP4195439B2 JP 4195439 B2 JP4195439 B2 JP 4195439B2 JP 2004353482 A JP2004353482 A JP 2004353482A JP 2004353482 A JP2004353482 A JP 2004353482A JP 4195439 B2 JP4195439 B2 JP 4195439B2
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- transistor
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- integrated circuit
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- field effect
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- 239000004065 semiconductor Substances 0.000 claims description 17
- 230000005669 field effect Effects 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 12
- 239000012212 insulator Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 230000000295 complement effect Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 22
- 238000013461 design Methods 0.000 description 9
- 239000007943 implant Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 230000010354 integration Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000007667 floating Methods 0.000 description 6
- 230000001965 increasing effect Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 125000001475 halogen functional group Chemical group 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000036039 immunity Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008450 motivation Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/783—Field effect transistors with field effect produced by an insulated gate comprising a gate to body connection, i.e. bulk dynamic threshold voltage MOSFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
1)このトランジスタでは、オフの状態で閾値を高くし、オンの状態で閾値を低くすることができ、それによって、Ionが大きく、Ioffが小さくなり、on/off電流比が改善される。
2)オンの状態で閾値が低いために電源電圧をスケール・ダウンすることができ、電力消費/損失を小さくすることができる。
3)「ゲート」20により、トランジスタ部分のチャネルがpウェル接点から切り離されても、トランジスタ内で浮動本体による影響はない。(オンの状態では、トランジスタのpウェルは浮動状態になり、トランジスタ本体は、ソース電圧と同じ電位に上昇し得る。部分的に空乏化されたSOI MOSFETでは、この浮動本体の電位は、トランジスタがその高衝撃イオン化条件により、最後にスイッチングされたのがいつか、どのくらいの頻度でスイッチングされたかによって決まる。しかし、本発明によるトランジスタ構造では、オフの状態でpウェルがpウェル接点に接続され、pウェルに蓄積された電荷が容易に除去される。)
4)図1の従来型DTMOSFETと異なり、トランジスタ部分のゲートはpウェル接点に直接接続されず、そのため、順方向p−n接合部の漏れがなく、また電源電圧が、漏れを大きくし得る決定的な影響を与えることはない。
12 ハンドリング基板
14 絶縁体、BOX層
16 シリコン本体
18 pウェル接点
20 N+領域、コントロール・コンタクト
22 空乏領域
24 ゲート接続部
100 DTMOSFETの輪郭
110 ゲート構造
120 レジスト層
125 コントロール・コンタクトの位置
130 コントロール・コンタクトの位置
140 レジスト層
145 ハロー・インプラント
150 レジスト層
155 コントロール・コンタクト領域の位置
160 レジスト
165 ウェル接点領域の位置
170 接点
171 接点
180 シリサイド
200 電源
300 携帯電子機器
Claims (8)
- 基板上の絶縁体上に設けられた第1導電タイプの半導体層中に形成されたソース、ドレイン、およびゲートを有する電界効果トランジスタが設けられた部分と、
前記半導体層へのボディ・コンタクトと、
前記ゲートと前記ボディ・コンタクトの間に設けられ、前記ゲートに接続された前記第1導電タイプと反対の導電タイプのコントロール・コンタクトとを備え、
前記電界効果トランジスタがオン状態の時に、前記コントロール・コンタクトから延びた空乏領域が前記絶縁体に結合する、電界効果トランジスタを有する集積回路。 - 前記半導体層への前記ボディ・コンタクトが、前記第1導電タイプの領域である、請求項1に記載の集積回路。
- 前記半導体層への前記ボディ・コンタクトが、接地に接続される、請求項1に記載の集積回路。
- 前記半導体層がシリコン・オン・インシュレータ基板のシリコン層である、請求項1に記載の集積回路。
- 前記半導体層の厚さが800Åであり、前記コントロール・コンタクトが、前記半導体層中を300Å〜350Å延びる、請求項1に記載の集積回路。
- 前記電界効果トランジスタが設けられた部分が相補型トランジスタ対を含む、請求項1に記載の集積回路。
- 電源と、
電界効果トランジスタを有する集積回路とを備え、
前記集積回路が、
基板上の絶縁体上に設けられた第1導電タイプの半導体層中に形成されたソース、ドレイン、およびゲートを有する電界効果トランジスタが設けられた部分と、
前記半導体層へのボディ・コンタクトと、
前記ゲートと前記ボディ・コンタクトの間に設けられ、前記ゲートに接続された前記第1導電タイプと反対の導電タイプのコントロール・コンタクトとを備え、
前記電界効果トランジスタがオン状態の時に、前記コントロール・コンタクトから延びた空乏領域が前記絶縁体に結合する、携帯電子機器。 - 前記電界効果トランジスタが設けられた部分が相補型トランジスタ対を含む、請求項7に記載の携帯電子機器。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/728,750 US7045873B2 (en) | 2003-12-08 | 2003-12-08 | Dynamic threshold voltage MOSFET on SOI |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005175478A JP2005175478A (ja) | 2005-06-30 |
JP4195439B2 true JP4195439B2 (ja) | 2008-12-10 |
Family
ID=34633790
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004353482A Expired - Fee Related JP4195439B2 (ja) | 2003-12-08 | 2004-12-07 | 集積回路及び携帯電子機器 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7045873B2 (ja) |
JP (1) | JP4195439B2 (ja) |
CN (1) | CN100375296C (ja) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6804502B2 (en) | 2001-10-10 | 2004-10-12 | Peregrine Semiconductor Corporation | Switch circuit and method of switching radio frequency signals |
US7719343B2 (en) | 2003-09-08 | 2010-05-18 | Peregrine Semiconductor Corporation | Low noise charge pump method and apparatus |
EP3570374B1 (en) | 2004-06-23 | 2022-04-20 | pSemi Corporation | Integrated rf front end |
US7890891B2 (en) | 2005-07-11 | 2011-02-15 | Peregrine Semiconductor Corporation | Method and apparatus improving gate oxide reliability by controlling accumulated charge |
USRE48965E1 (en) | 2005-07-11 | 2022-03-08 | Psemi Corporation | Method and apparatus improving gate oxide reliability by controlling accumulated charge |
US7910993B2 (en) | 2005-07-11 | 2011-03-22 | Peregrine Semiconductor Corporation | Method and apparatus for use in improving linearity of MOSFET's using an accumulated charge sink |
US9653601B2 (en) | 2005-07-11 | 2017-05-16 | Peregrine Semiconductor Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction |
US8742502B2 (en) | 2005-07-11 | 2014-06-03 | Peregrine Semiconductor Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction |
US20080076371A1 (en) | 2005-07-11 | 2008-03-27 | Alexander Dribinsky | Circuit and method for controlling charge injection in radio frequency switches |
US20080191788A1 (en) * | 2007-02-08 | 2008-08-14 | International Business Machines Corporation | Soi mosfet device with adjustable threshold voltage |
US7960772B2 (en) | 2007-04-26 | 2011-06-14 | Peregrine Semiconductor Corporation | Tuning capacitance to enhance FET stack voltage withstand |
EP3958468B1 (en) | 2008-02-28 | 2024-01-31 | pSemi Corporation | Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device |
US9030248B2 (en) * | 2008-07-18 | 2015-05-12 | Peregrine Semiconductor Corporation | Level shifter with output spike reduction |
JP2011528870A (ja) | 2008-07-18 | 2011-11-24 | ペレグリン セミコンダクター コーポレーション | 低ノイズ高効率バイアス生成回路及び方法 |
US9660590B2 (en) | 2008-07-18 | 2017-05-23 | Peregrine Semiconductor Corporation | Low-noise high efficiency bias generation circuits and method |
US8723260B1 (en) | 2009-03-12 | 2014-05-13 | Rf Micro Devices, Inc. | Semiconductor radio frequency switch with body contact |
US9264053B2 (en) | 2011-01-18 | 2016-02-16 | Peregrine Semiconductor Corporation | Variable frequency charge pump |
US9590674B2 (en) | 2012-12-14 | 2017-03-07 | Peregrine Semiconductor Corporation | Semiconductor devices with switchable ground-body connection |
US20150236798A1 (en) | 2013-03-14 | 2015-08-20 | Peregrine Semiconductor Corporation | Methods for Increasing RF Throughput Via Usage of Tunable Filters |
US9406695B2 (en) | 2013-11-20 | 2016-08-02 | Peregrine Semiconductor Corporation | Circuit and method for improving ESD tolerance and switching speed |
US9831857B2 (en) | 2015-03-11 | 2017-11-28 | Peregrine Semiconductor Corporation | Power splitter with programmable output phase shift |
US9948281B2 (en) | 2016-09-02 | 2018-04-17 | Peregrine Semiconductor Corporation | Positive logic digitally tunable capacitor |
US10236872B1 (en) | 2018-03-28 | 2019-03-19 | Psemi Corporation | AC coupling modules for bias ladders |
US10886911B2 (en) | 2018-03-28 | 2021-01-05 | Psemi Corporation | Stacked FET switch bias ladders |
US10505530B2 (en) | 2018-03-28 | 2019-12-10 | Psemi Corporation | Positive logic switch with selectable DC blocking circuit |
US11476849B2 (en) | 2020-01-06 | 2022-10-18 | Psemi Corporation | High power positive logic switch |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5008723A (en) * | 1989-12-29 | 1991-04-16 | Kopin Corporation | MOS thin film transistor |
JPH06260640A (ja) * | 1993-03-03 | 1994-09-16 | Casio Comput Co Ltd | 可変しきい値電圧トランジスタ |
US5559368A (en) * | 1994-08-30 | 1996-09-24 | The Regents Of The University Of California | Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation |
US5689144A (en) * | 1996-05-15 | 1997-11-18 | Siliconix Incorporated | Four-terminal power MOSFET switch having reduced threshold voltage and on-resistance |
US6020222A (en) * | 1997-12-16 | 2000-02-01 | Advanced Micro Devices, Inc. | Silicon oxide insulator (SOI) semiconductor having selectively linked body |
CN1238532A (zh) * | 1998-02-06 | 1999-12-15 | 国际商业机器公司 | 具有动态阈值电压的晶体管电路 |
US6297686B1 (en) * | 1999-05-28 | 2001-10-02 | Winbond Electronics Corporation | Semiconductor integrated circuit for low-voltage high-speed operation |
KR100343288B1 (ko) * | 1999-10-25 | 2002-07-15 | 윤종용 | 에스오아이 모스 트랜지스터의 플로팅 바디 효과를제거하기 위한 에스오아이 반도체 집적회로 및 그 제조방법 |
DE60036594T2 (de) * | 1999-11-15 | 2008-01-31 | Matsushita Electric Industrial Co., Ltd., Kadoma | Feldeffekt-Halbleiterbauelement |
JP5001494B2 (ja) * | 2001-08-28 | 2012-08-15 | セイコーインスツル株式会社 | 絶縁性基板上に形成された電界効果トランジスタ |
US6504226B1 (en) * | 2001-12-20 | 2003-01-07 | Stmicroelectronics, Inc. | Thin-film transistor used as heating element for microreaction chamber |
-
2003
- 2003-12-08 US US10/728,750 patent/US7045873B2/en not_active Expired - Lifetime
-
2004
- 2004-11-17 CN CNB2004100912259A patent/CN100375296C/zh active Active
- 2004-12-07 JP JP2004353482A patent/JP4195439B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN100375296C (zh) | 2008-03-12 |
CN1627533A (zh) | 2005-06-15 |
US20050121699A1 (en) | 2005-06-09 |
US7045873B2 (en) | 2006-05-16 |
JP2005175478A (ja) | 2005-06-30 |
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