JP4188556B2 - クロック信号をデスキューする方法および装置 - Google Patents

クロック信号をデスキューする方法および装置 Download PDF

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Publication number
JP4188556B2
JP4188556B2 JP2000515330A JP2000515330A JP4188556B2 JP 4188556 B2 JP4188556 B2 JP 4188556B2 JP 2000515330 A JP2000515330 A JP 2000515330A JP 2000515330 A JP2000515330 A JP 2000515330A JP 4188556 B2 JP4188556 B2 JP 4188556B2
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Japan
Prior art keywords
delay
clock
clock signal
phase
clock signals
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Expired - Fee Related
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JP2000515330A
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English (en)
Japanese (ja)
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JP2001519577A (ja
JP2001519577A5 (enExample
Inventor
ジァンノパウロス，ジョージ
ウォン，ケン・エル
テイラー，グレッグ・エフ
ダイ，シャ
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Intel Corp
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Intel Corp
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Publication of JP2001519577A5 publication Critical patent/JP2001519577A5/ja
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2000515330A 1997-10-07 1998-08-20 クロック信号をデスキューする方法および装置 Expired - Fee Related JP4188556B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/946,671 1997-10-07
US08/946,671 US6075832A (en) 1997-10-07 1997-10-07 Method and apparatus for deskewing clock signals
PCT/US1998/017399 WO1999018660A1 (en) 1997-10-07 1998-08-20 Method and apparatus for deskewing clock signals

Publications (3)

Publication Number Publication Date
JP2001519577A JP2001519577A (ja) 2001-10-23
JP2001519577A5 JP2001519577A5 (enExample) 2006-01-05
JP4188556B2 true JP4188556B2 (ja) 2008-11-26

Family

ID=25484790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000515330A Expired - Fee Related JP4188556B2 (ja) 1997-10-07 1998-08-20 クロック信号をデスキューする方法および装置

Country Status (6)

Country Link
US (1) US6075832A (enExample)
JP (1) JP4188556B2 (enExample)
KR (1) KR100388950B1 (enExample)
AU (1) AU9113598A (enExample)
TW (1) TW412706B (enExample)
WO (1) WO1999018660A1 (enExample)

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US6480548B1 (en) * 1997-11-17 2002-11-12 Silicon Graphics, Inc. Spacial derivative bus encoder and decoder
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US6294937B1 (en) * 1999-05-25 2001-09-25 Lsi Logic Corporation Method and apparatus for self correcting parallel I/O circuitry
US6816561B1 (en) * 1999-08-06 2004-11-09 3Dlabs, Inc., Ltd Phase correction for multiple processors
US7031420B1 (en) * 1999-12-30 2006-04-18 Silicon Graphics, Inc. System and method for adaptively deskewing parallel data signals relative to a clock
US7035269B2 (en) * 2000-02-02 2006-04-25 Mcgill University Method and apparatus for distributed synchronous clocking
TW463080B (en) * 2000-03-24 2001-11-11 Winbond Electronics Corp Clock generating device which can adjust clock skew and method
KR100416695B1 (ko) * 2000-06-30 2004-02-05 주식회사 하이닉스반도체 노이즈 제어가 가능한 지연고정루프
US6622255B1 (en) * 2000-09-13 2003-09-16 Intel Corporation Digital clock skew detection and phase alignment
US6690209B1 (en) * 2000-09-28 2004-02-10 Infineon Technologies North America Corp. Phase detecting with parallel discharge paths
US6326830B1 (en) * 2000-12-29 2001-12-04 Intel Corporation Automatic clock calibration circuit
US6630855B2 (en) * 2001-03-29 2003-10-07 Intel Corporation Clock distribution phase alignment technique
US6925555B2 (en) 2001-07-27 2005-08-02 Hewlett-Packard Development Company, L.P. System and method for determining a plurality of clock delay values using an optimization algorithm
US6934872B2 (en) * 2001-12-19 2005-08-23 Intel Corporation Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise
US7120838B2 (en) * 2002-03-26 2006-10-10 Intel Corporation Method and unit for deskewing signals
US7194650B2 (en) * 2003-05-09 2007-03-20 Hewlett-Packard Development Company, L.P. System and method for synchronizing multiple synchronizer controllers
US7100065B2 (en) * 2003-05-09 2006-08-29 Hewlett-Packard Development Company, L.P. Controller arrangement for synchronizer data transfer between a core clock domain and bus clock domain each having its own individual synchronizing controller
US7245684B2 (en) * 2003-05-09 2007-07-17 Hewlett-Packard Development Company, L.P. System and method for compensating for skew between a first clock signal and a second clock signal
US7219251B2 (en) * 2003-05-09 2007-05-15 Hewlett-Packard Development Company, L.P. Programmable clock synchronizer
US6842055B1 (en) * 2003-08-13 2005-01-11 Hewlett-Packard Development Company, L.P. Clock adjustment
JP3869406B2 (ja) * 2003-11-10 2007-01-17 株式会社東芝 クロック位相差検出回路、クロック分配回路、及び大規模集積回路
US7002358B2 (en) * 2003-12-10 2006-02-21 Hewlett-Packard Development Company, L.P. Method and apparatus for measuring jitter
US7103492B2 (en) * 2004-06-18 2006-09-05 Macronix International Co., Ltd. Process independent delay chain
US7218161B2 (en) * 2004-08-20 2007-05-15 Macronix International Co., Ltd. Substantially temperature independent delay chain
US7023252B2 (en) * 2004-05-19 2006-04-04 Lsi Logic Corporation Chip level clock tree deskew circuit
US7464283B2 (en) * 2004-06-28 2008-12-09 Texas Instruments Incorporated System and method for producing precision timing signals by controlling register banks to provide a phase difference between two signal paths
US7119582B2 (en) * 2004-07-23 2006-10-10 Hewlett-Packard Development Company, Lp. Phase detection in a sync pulse generator
US7382847B2 (en) * 2004-07-23 2008-06-03 Hewlett-Packard Development Company, L.P. Programmable sync pulse generator
US7340631B2 (en) * 2004-07-23 2008-03-04 Hewlett-Packard Development Company, L.P. Drift-tolerant sync pulse circuit in a sync pulse generator
US7436917B2 (en) * 2004-07-29 2008-10-14 Hewlett-Packard Development Company, L.P. Controller for clock synchronizer
US20060023819A1 (en) * 2004-07-29 2006-02-02 Adkisson Richard W Clock synchronizer
US7266744B2 (en) * 2004-12-14 2007-09-04 Hewlett-Packard Development Company, L.P. Application specific integrated circuit with internal testing
KR101206503B1 (ko) * 2006-06-30 2012-11-29 삼성전자주식회사 스큐 제거 회로 및 그에 의한 스큐 제거 방법
KR100838376B1 (ko) * 2006-08-24 2008-06-13 주식회사 하이닉스반도체 전원전압 변동에 대비한 디엘엘장치.
US8205182B1 (en) 2007-08-22 2012-06-19 Cadence Design Systems, Inc. Automatic synthesis of clock distribution networks
WO2009134223A1 (en) * 2008-04-30 2009-11-05 Hewlett-Packard Development Company, L.P. Intentionally skewed optical clock signal distribution
US20130300458A1 (en) * 2012-05-11 2013-11-14 Stmicroelectronics Sa Clock Signal Synchronization Circuit
US8937491B2 (en) * 2012-11-15 2015-01-20 Xilinx, Inc. Clock network architecture
TWI561958B (en) * 2014-05-22 2016-12-11 Global Unichip Corp Integrated circuit
US10218360B2 (en) * 2016-08-02 2019-02-26 Altera Corporation Dynamic clock-data phase alignment in a source synchronous interface circuit
US10333535B1 (en) 2016-09-28 2019-06-25 Altera Corporation Techniques for signal skew compensation
US12360550B2 (en) * 2021-09-07 2025-07-15 Intel Corporation Apparatus and method for global to local clock compensation

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US4789996A (en) * 1988-01-28 1988-12-06 Siemens Transmission Systems, Inc. Center frequency high resolution digital phase-lock loop circuit
US5101117A (en) * 1988-02-17 1992-03-31 Mips Computer Systems Variable delay line phase-locked loop circuit synchronization system
US5087829A (en) * 1988-12-07 1992-02-11 Hitachi, Ltd. High speed clock distribution system
US5307381A (en) * 1991-12-27 1994-04-26 Intel Corporation Skew-free clock signal distribution network in a microprocessor
US5675273A (en) * 1995-09-08 1997-10-07 International Business Machines Corporation Clock regulator with precision midcycle edge timing
US5692165A (en) * 1995-09-12 1997-11-25 Micron Electronics Inc. Memory controller with low skew control signal

Also Published As

Publication number Publication date
KR20010015712A (ko) 2001-02-26
US6075832A (en) 2000-06-13
AU9113598A (en) 1999-04-27
JP2001519577A (ja) 2001-10-23
KR100388950B1 (ko) 2003-06-25
TW412706B (en) 2000-11-21
WO1999018660A1 (en) 1999-04-15

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