JP4182065B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4182065B2 JP4182065B2 JP2005026171A JP2005026171A JP4182065B2 JP 4182065 B2 JP4182065 B2 JP 4182065B2 JP 2005026171 A JP2005026171 A JP 2005026171A JP 2005026171 A JP2005026171 A JP 2005026171A JP 4182065 B2 JP4182065 B2 JP 4182065B2
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- JP
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- Prior art keywords
- circuit
- input terminal
- mode
- semiconductor device
- external input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 239000004065 semiconductor Substances 0.000 title claims description 56
- 239000003990 capacitor Substances 0.000 claims description 43
- 230000009467 reduction Effects 0.000 claims description 30
- 230000015556 catabolic process Effects 0.000 claims description 14
- 230000002265 prevention Effects 0.000 claims description 10
- 230000000903 blocking effect Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 10
- 230000015654 memory Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/225—Clock input buffers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
- H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2227—Standby or low power modes
Landscapes
- Electronic Switches (AREA)
- Dram (AREA)
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Description
11 モード判定回路
12 入力容量調整用コンデンサ
13 外部入力端子
14 初段入力回路
15 フローティング防止回路
17、18、19、20 半導体素子
21、25 抵抗素子
22 NMOSトランジスタ
23 PMOSトランジスタ
24 インバータ
Claims (9)
- 外部入力端子と、
前記外部入力端子に対して容量を付加する入力容量調整用コンデンサと、
半導体装置の動作が消費電力低減モードであるか通常動作モードであるかを表すモード信号を出力するモード判定回路と、
前記外部入力端子と前記入力容量調整用コンデンサとの間に挿入され、前記モード信号を入力し、前記モード信号が、前記消費電力低減モードを示す場合に非導通状態となり、前記通常動作モードを示す場合に導通状態となる遮断回路と、
少なくとも前記通常動作モードの場合には前記外部入力端子に接続される初段入力回路と、
を備えることを特徴とする半導体装置。 - 前記遮断回路の一端には、前記外部入力端子が接続され、前記遮断回路の他端には、前記入力容量調整用コンデンサと前記初段入力回路とが接続され、
前記モード信号が前記消費電力低減モードを示す場合に、前記外部入力端子と前記入力容量調整用コンデンサおよび前記初段入力回路とが前記遮断回路によって遮断され、
前記モード信号が前記通常動作モードを示す場合に、前記外部入力端子と前記入力容量調整用コンデンサおよび前記初段入力回路とが前記遮断回路によって導通されることを特徴とする請求項1記載の半導体装置。 - 前記消費電力低減モードの場合に前記初段入力回路の入力端を所定の電圧レベルに固定するフローティング防止回路をさらに備えることを特徴とする請求項2記載の半導体装置。
- 前記遮断回路の一端と前記外部入力端子との間に静電破壊防止用抵抗素子を含むことを特徴とする請求項1記載の半導体装置。
- 前記遮断回路の一端には、前記外部入力端子と前記初段入力回路とが接続され、前記遮断回路の他端には、前記入力容量調整用コンデンサが接続され、
前記モード信号が前記消費電力低減モードを示す場合に、前記外部入力端子と前記入力容量調整用コンデンサとが前記遮断回路によって遮断され、
前記モード信号が前記通常動作モードを示す場合に、前記外部入力端子と前記入力容量調整用コンデンサとが前記遮断回路によって導通されることを特徴とする請求項1記載の半導体装置。 - 前記遮断回路が接続される前記外部入力端子は、前記消費電力低減モードから前記通常動作モードへの復帰動作に必要な情報を入力する入力端子を除く他の入力端子であることを特徴とする請求項1記載の半導体装置。
- 前記遮断回路は、導通状態において1KΩ以下の抵抗値を有することを特徴とする請求項1記載の半導体装置。
- 前記遮断回路は、MOSトランジスタからなるスイッチ回路であり、前記モード信号が前記MOSトランジスタの制御端子に供給されることを特徴とする請求項1または7記載の半導体装置。
- 前記遮断回路は、トランスファゲートからなるスイッチ回路であり、前記モード信号が前記トランスファゲートの制御端子に供給されることを特徴とする請求項1または7記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005026171A JP4182065B2 (ja) | 2005-02-02 | 2005-02-02 | 半導体装置 |
US11/339,799 US7330067B2 (en) | 2005-02-02 | 2006-01-26 | Semiconductor apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005026171A JP4182065B2 (ja) | 2005-02-02 | 2005-02-02 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006217138A JP2006217138A (ja) | 2006-08-17 |
JP4182065B2 true JP4182065B2 (ja) | 2008-11-19 |
Family
ID=36979997
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005026171A Expired - Fee Related JP4182065B2 (ja) | 2005-02-02 | 2005-02-02 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7330067B2 (ja) |
JP (1) | JP4182065B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7577053B2 (en) * | 2006-11-13 | 2009-08-18 | Qimonda North America Corp. | Memory including deep power down mode |
FI20075269A0 (fi) * | 2007-04-19 | 2007-04-19 | Pulse Finland Oy | Menetelmä ja järjestely antennin sovittamiseksi |
CN101365087B (zh) * | 2007-08-08 | 2012-07-04 | 三洋电机株式会社 | 摄像装置 |
JP6298353B2 (ja) * | 2013-05-17 | 2018-03-20 | 株式会社半導体エネルギー研究所 | 半導体装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100401507B1 (ko) * | 2001-05-10 | 2003-10-17 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 입력 캐패시턴스의 미세조정 회로및 그 제조방법 |
JP3850264B2 (ja) | 2001-10-29 | 2006-11-29 | 株式会社ルネサステクノロジ | 半導体装置 |
US20030123299A1 (en) * | 2002-01-02 | 2003-07-03 | Annavajjhala Ravi P. | Protection circuit |
US6757147B1 (en) * | 2002-05-03 | 2004-06-29 | Pericom Semiconductor Corp. | Pin-to-pin ESD-protection structure having cross-pin activation |
KR100426443B1 (ko) | 2002-06-29 | 2004-04-13 | 주식회사 하이닉스반도체 | 딥 파워다운 제어 회로 |
-
2005
- 2005-02-02 JP JP2005026171A patent/JP4182065B2/ja not_active Expired - Fee Related
-
2006
- 2006-01-26 US US11/339,799 patent/US7330067B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7330067B2 (en) | 2008-02-12 |
US20060238236A1 (en) | 2006-10-26 |
JP2006217138A (ja) | 2006-08-17 |
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