JP4166615B2 - データ処理装置におけるマルチアクセス命令を処理するデータ処理装置及び方法並びにその方法によるコンピュータ・プログラム製品 - Google Patents

データ処理装置におけるマルチアクセス命令を処理するデータ処理装置及び方法並びにその方法によるコンピュータ・プログラム製品 Download PDF

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JP4166615B2
JP4166615B2 JP2003115385A JP2003115385A JP4166615B2 JP 4166615 B2 JP4166615 B2 JP 4166615B2 JP 2003115385 A JP2003115385 A JP 2003115385A JP 2003115385 A JP2003115385 A JP 2003115385A JP 4166615 B2 JP4166615 B2 JP 4166615B2
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logic unit
master logic
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JP2003345648A5 (enExample
JP2003345648A (ja
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ジョン グウィルト デイヴィッド
マシューソン ブルース
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エイアールエム リミテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
JP2003115385A 2002-05-23 2003-04-21 データ処理装置におけるマルチアクセス命令を処理するデータ処理装置及び方法並びにその方法によるコンピュータ・プログラム製品 Expired - Lifetime JP4166615B2 (ja)

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Application Number Priority Date Filing Date Title
GB0211950A GB2388929B (en) 2002-05-23 2002-05-23 Handling of a multi-access instruction in a data processing apparatus
GB0211950.1 2002-05-23

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JP2003345648A JP2003345648A (ja) 2003-12-05
JP2003345648A5 JP2003345648A5 (enExample) 2005-10-06
JP4166615B2 true JP4166615B2 (ja) 2008-10-15

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JP2003115385A Expired - Lifetime JP4166615B2 (ja) 2002-05-23 2003-04-21 データ処理装置におけるマルチアクセス命令を処理するデータ処理装置及び方法並びにその方法によるコンピュータ・プログラム製品

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US (1) US6959351B2 (enExample)
JP (1) JP4166615B2 (enExample)
GB (1) GB2388929B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4847036B2 (ja) * 2005-03-30 2011-12-28 キヤノン株式会社 バスアクセスを調停する制御装置およびデータ処理装置の制御方法
US20060248247A1 (en) * 2005-04-29 2006-11-02 Mtekvision Co., Ltd. Apparatus and method for controlling access to a memory
US7805578B2 (en) * 2005-04-29 2010-09-28 Mtekvision Co., Ltd. Data processor apparatus and memory interface
US7689735B2 (en) * 2005-10-03 2010-03-30 Arm Limited Instruction stream control
WO2007109810A2 (en) * 2006-03-23 2007-09-27 Novartis Ag Methods for the preparation of imidazole-containing compounds
EP2007765B1 (en) * 2006-03-23 2012-06-27 Novartis AG Immunopotentiating compounds
CA2646539A1 (en) * 2006-03-23 2007-09-27 Novartis Ag Imidazoquinoxaline compounds as immunomodulators
JP5600517B2 (ja) 2010-08-18 2014-10-01 キヤノン株式会社 情報処理装置、情報処理方法、およびプログラム
JP6107904B2 (ja) * 2015-09-09 2017-04-05 日本電気株式会社 プロセッサ及びストア命令の変換方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175829A (en) * 1988-10-25 1992-12-29 Hewlett-Packard Company Method and apparatus for bus lock during atomic computer operations
WO1996003697A1 (en) * 1994-07-21 1996-02-08 Apple Computer, Inc. Method for semaphore communication between incompatible bus locking architectures
US5727172A (en) * 1995-05-01 1998-03-10 Motorola, Inc. Method and apparatus for performing atomic accesses in a data processing system
JPH10177560A (ja) * 1996-12-17 1998-06-30 Ricoh Co Ltd 記憶装置
US6473849B1 (en) * 1999-09-17 2002-10-29 Advanced Micro Devices, Inc. Implementing locks in a distributed processing system
EP1226493B1 (en) * 1999-11-05 2006-05-03 Analog Devices, Inc. Bus architecture and shared bus arbitration method for a communication processor
US6901505B2 (en) * 2001-08-09 2005-05-31 Advanced Micro Devices, Inc. Instruction causing swap of base address from segment register with address from another register

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Publication number Publication date
GB2388929B (en) 2005-05-18
US6959351B2 (en) 2005-10-25
US20030221032A1 (en) 2003-11-27
JP2003345648A (ja) 2003-12-05
GB2388929A (en) 2003-11-26
GB0211950D0 (en) 2002-07-03

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