JP4152929B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an internal circuit that performs a predetermined operation in accordance with an external signal, and a semiconductor device formed on a semiconductor substrate.

  FIG. 6 is a block diagram showing a configuration of a conventional dynamic random access memory (hereinafter referred to as DRAM). Referring to FIG. 6, this DRAM includes control signal input terminals 31, 32, 34, and 42, an address signal input terminal 33, a data signal input / output terminal 41, power supply terminals 35 to 39, and a ground terminal 40. The DRAM also includes a RAS buffer 43, CAS buffer 44, WE buffer 45, OE buffer 46, clock generation circuit 47, address buffer 48, row decoder 49, column decoder 50, memory cell array 51, and sense amplifier + input / output control circuit. 52. The DRAM further includes a preamplifier 53, an output buffer 54, a data-in buffer 55, a write driver 56, a VPP circuit 57, a sense amplifier VDC circuit 58, and a column-related circuit VDC circuit 59.

  Buffers 43 to 46 are respectively connected to external control signals ext. Provided externally via control signal input terminals 31, 32, 34, 42. / RAS, ext. / CAS, ext. / WE, ext. An internal control signal is generated in response to / OE. The clock generation circuit 47 selects a predetermined operation mode based on the internal control signals supplied from the buffers 43 to 46, and controls the entire DRAM.

  Address buffer 48 receives external address signal ext. Provided externally through address signal input terminal 33. Add. In response to this, an internal address signal is generated, and the internal address signal is selectively applied to the row decoder 49 and the column decoder 50. Memory cell array 51 includes a plurality of memory cells MC arranged in a matrix in the row and column directions, word lines WL provided corresponding to each row, and bit line pairs BLP provided corresponding to each column. Including.

  The row decoder 49 selects any word line WL in the memory cell array 51 in response to the internal address signal supplied from the address buffer 48. A boosted potential VPP is applied to the selected word line WL, and the memory cell MC corresponding to the word line WL is activated. Column decoder 50 selects any bit line pair BLP in memory cell array 51 in response to an internal address signal applied from address buffer 48. The sense amplifier + input / output control circuit 52 connects the bit line pair BLP selected by the column decoder 50 to one end of the global signal input / output line pair GIO. That is, the memory cell MC located at the intersection of the word line WL selected by the row decoder 49 and the bit line pair BLP selected by the column decoder 50 is connected to one end of the global signal input / output line pair GIO.

  The other end of global signal input / output line pair GIO is connected to preamplifier 53 and write driver 56. Preamplifier 53 and output buffer 54 amplify the read data from selected memory cell MC and output it to data signal input / output terminal 41 during a read operation. Data-in buffer 55 and write driver 56 apply data externally applied via data signal input / output terminal 41 to selected memory cell MC via global signal input / output line pair GIO during a write operation.

  An external power supply potential ext. VCC is given to buffers 43 to 46 (B section in the figure). VPP circuit 57 is connected to external power supply potential ext. The boosted potential VPP for the word line WL is generated by boosting VCC. The VDC circuit 58 is connected to the external power supply potential ext. VCC is stepped down to reduce internal power supply potential int. VCC is generated and its internal potential int. VCC is supplied to the sense amplifier + input / output control circuit 52. The VDC circuit 59 is connected to the external power supply potential ext. VCC is stepped down to reduce internal power supply potential int. VCC is generated and its internal power supply potential int. VCC is applied to a column circuit (A portion in the figure). An external power supply potential ext. VCC is supplied to the output buffer 54. The external ground potential ext. VSS is given to the entire DRAM.

  FIG. 7 is a partially omitted plan view showing the configuration of the DRAM chip 60 incorporated in the package.

  In FIG. 7, the DRAM of FIG. 6 is formed on the surface of a DRAM chip 60. A plurality of pads (only P1 to P8 are shown in the figure) are arranged on the center surface of the DRAM chip 60. Pads P1, P3, and P8 constitute power supply terminals 37, 39, and 36 in FIG. 6, respectively. Pads P5 and P6 constitute control signal input terminals 31 and 32 of FIG. 6, respectively. The pad 7 constitutes the power supply terminals 35 and 38 in FIG.

  A plurality of lead frames (only 61 to 65 are shown in the figure) are arranged above the DRAM chip 60. The lead frame 61 includes a trunk portion 61a and a branching portion 61b branched from the distal end portion of the trunk portion 61a. The proximal end portion of the trunk portion 61 a is connected to a pin of a package (not shown), and the distal end portion is connected to the pads P 1 and P 2 by bonding wires 66. The distal end portion of the branch portion 61b is connected to the pad P3 by the bonding wire 66. The base ends of the lead frames 62 to 65 are respectively connected to pins of a package (not shown), and the respective leading ends are connected to pads P5 to P8 by bonding wires 66, respectively. External power supply potential ext. VCC and an external control signal are applied to the DRAM via lead frames 61 to 65, bonding wires 66, and pads P1 to P8.

  DRAM external power supply potential ext. VCC line and external ground potential ext. Between the VSS line, as shown in FIG. 8, a noise removing capacitor composed of an n-channel MOS transistor 70 is provided. The gate of n channel MOS transistor 70 is ext. Connected to the VCC line, and its source and drain are connected to the external ground potential ext. Commonly connected to the VSS line.

  FIG. 9A is a partially cutaway plan view showing the configuration of a portion including the n-channel MOS transistor 70 of the DRAM chip 60, and FIG. 9B is a cross-sectional view taken along the line YY 'of FIG. 9A. . Referring to FIG. 9, gate electrode 73 is formed on the surface of p-type silicon substrate 71 of DRAM chip 60 via gate oxide film 72. An n-type source region 74 is formed on one side of the gate electrode 73, an n-type drain region 75 is formed on the other side, and an n-channel MOS transistor 70 is formed.

  An external ground potential ext. Is provided above the surface of the silicon substrate 71 via an insulating layer 78. VSS line 76 is provided, and an external power supply potential ext. A VCC line 77 is provided. External ground potential ext. The VSS line 76 is formed of the first aluminum wiring layer (Al1), and the external power supply potential ext. The VCC line 77 is formed of the second aluminum wiring layer (Al2). External power supply potential ext. VCC line 77 is connected to gate electrode 73 of n-channel MOS transistor 70 through contact hole 79, and is connected to external ground potential ext. The VSS line 76 is connected to the source region 74 and the drain region 75 of the n-channel MOS transistor 70 through contact holes 80 and 81.

  An external power supply potential ext. VCC is applied, and external source potential ext. Since VSS is applied, a channel is formed in a region under the gate oxide film 72 on the surface of the p-type silicon substrate 71, and a capacitor is formed between the gate electrode 73 and the channel.

  FIG. 10 is a circuit diagram showing a configuration of the output buffer 54 of FIG. Referring to FIG. 10, output buffer 54 includes two inverters 82 and 83 and an output circuit 84. Inverter 82 is connected to internal power supply potential int. VCC line and external ground potential ext. An inversion signal / φd of internal data signal φd output from preamplifier 53 is generated, including p-channel MOS transistor 85 and n-channel MOS transistor 86 connected in series with VSS line. Inverter 83 receives internal power supply potential ext. VCC line and external ground potential ext. A p-channel MOS transistor 87 and an n-channel MOS transistor 88 connected in series with the VSS line are generated, and an inverted signal φd of the internal data signal / φd output from the preamplifier 53 is generated.

  Output circuit 84 includes two n-channel MOS transistors 89 and 90. N channel MOS transistor 89 has external power supply potential ext. Connected between the VCC line and the data signal input / output terminal 41, the gate thereof receives the output of the inverter 82. N-channel MOS transistor 90 includes data signal input / output terminal 41 and external ground potential ext. It is connected to the VSS line, and its gate receives the output of the inverter 83.

  When internal data signal φd is at “H” level, inverters 82 and 83 output “L” level and “H” level, respectively, n channel MOS transistor 89 is turned off, and n channel MOS transistor 90 is turned on. The data signal input / output terminal 41 is at the “L” level. When internal data signal φd is at “L” level, inverters 82 and 83 output “H” level and “L” level, respectively, n channel MOS transistor 89 is turned on, and n channel MOS transistor 90 is turned off. Thus, the data signal input / output terminal 41 becomes “H” level.

  FIG. 11 is a partially cutaway plan view showing the configuration of the portion including the output circuit 84 of the DRAM chip 60. Referring to FIG. 11, a plurality (three in the figure) of output circuits 84 are provided on the surface of DRAM chip 60. The external ground potential ext. VSS line 91 and external power supply potential ext. A VCC line 92 is arranged. External ground potential ext. The VSS line and each output circuit 84 are connected by a contact hole 93. External power supply potential ext. The VCC line and each output circuit 84 are connected by a contact hole 94. External ground potential ext. One end of the VSS line 91 is connected to the pad P0, and the pad P0 is connected to the external ground potential ext. Receive VSS. External power supply potential ext. VCC line 92 is once connected to external ground potential ext. It passes below the VSS line 91 and is connected to the pad P3.

  12A is an enlarged view showing the configuration of the cross-under part (C part in the drawing) of FIG. 11, and FIG. 12B is a cross-sectional view taken along the line ZZ ′ of FIG. An external ground potential ext. Is applied by the second aluminum wiring layer (Al2). VSS line 91 and external power supply potential ext. A VCC line 92 is formed. External ground potential ext. Below the VSS line 91, an external ground potential ext. Connection electrode 95 wider than VSS line 91 is formed, and both ends of connection electrode 95 are connected to external power supply potential ext. Connected to VCC line 92.

  FIG. 13 is a circuit diagram showing a configuration of VDC circuit 59. Referring to FIG. 13, VDC circuit 59 includes a p-channel MOS transistor 97 and an operational amplifier 98. P channel MOS transistor 97 has external power supply potential ext. VCC line and internal power supply potential int. It is connected to the VCC line, and its gate receives the output of the operational amplifier 98. The non-inverting input terminal of the operational amplifier 98 receives the reference potential VREF (VREF <VCC), and the inverting input terminal thereof receives the internal power supply potential int. Connected to VCC line. The operational amplifier 98 has an internal power supply potential int. The gate potential of p channel MOS transistor 97 is controlled so that VCC coincides with reference potential VREF.

  FIG. 14 is a partially cutaway plan view showing the configuration of the portion including the VDC circuit 59 of the DRAM chip 60.

  Referring to FIG. 14, VDC circuit 59 is provided on the surface of DRAM chip 60. The external power supply potential ext. VCC line 100 and external ground potential ext. VSS line 101 and internal power supply potential int. VCC line 102 is arranged. External power supply potential ext. VCC of 100, external ground potential ext. VSS line 101 and internal power supply potential int. The VCC line 102 is connected to the VDC circuit 59 through contact holes 103, 104, and 105, respectively. External power supply potential ext. One end of the VCC line 100 is connected to the pad P7. External power supply potential ext. VCC line 100 and internal power supply potential int. The lines 102 of the VCC intersect each other. External ground potential ext. The VSS line 101 once passes below the lines 100 and 102 and is connected to the pad P0.

  Since the conventional DRAM is configured as described above, it has the following problems.

  First, when the internal data signals φd and / φd are switched in FIG. 10, both the n-channel MOS transistors 89 and 90 of the output circuit 84 become conductive, and the potential of the pad P3 temporarily decreases. This temporary potential drop is transmitted as power supply noise from the pad P3 in FIG. 7 to the other pads P1 and P2 via the lead frame 61, causing the VDC circuit 58 and the like to malfunction.

  As shown in FIG. 15, it may be possible to prevent lead noise from being transmitted from the pad P3 to the pads P1 and P2 by providing lead frames 110 and 111 on the pads P1 and P2 and the pad P3, respectively. The number will increase.

  Second, the VDC circuit 59 and the buffers 43 to 46 are connected to the external power supply potential ext. Since VCC was received, there was a problem that the buffers 43 to 46 malfunctioned due to power supply noise of the VDC circuit 59, or conversely, the VDC circuit 59 malfunctioned due to power supply noise of the buffers 43 to 46.

  Third, in FIG. 9, the external power supply potential ext. Since the VCC line is formed, the external power supply potential ext. The wiring resistance of the VCC line was high.

  Fourth, since the power line has cross under portions C and D as shown in FIGS. 11 and 14, the wiring resistance of the power line is high.

  Therefore, a main object of the present invention is to provide a semiconductor device having a small power line resistance.

A semiconductor device according to the present invention is a semiconductor device formed on a semiconductor substrate, and is formed on the surface of the semiconductor substrate and used as a capacitor element. The MOS transistor is formed above the semiconductor substrate, and the source region of the MOS transistor. And a first power supply wiring for applying a first power supply potential to the drain region and a first power supply wiring formed above the first power supply wiring, and applying a second power supply potential different from the first power supply potential to the gate electrode of the MOS transistor A second power supply wiring , a third power supply wiring formed in parallel with the second power supply wiring above the second power supply wiring and connected to the second power supply wiring ; A step-down circuit that generates an internal power supply voltage and applies the internal power supply voltage between at least one of the second and third power supply wirings and the first power supply wiring; Source at least one of the wires and those having a load circuit connected between the first power supply wiring.

  In the semiconductor device according to the present invention, the first to third power supply lines are provided above the MOS transistor used as the capacitive element, and the second and third power supply lines are connected to each other. A power supply voltage is supplied by the second and third power supply wirings and the first power supply wiring. Therefore, the wiring resistance of the power supply wiring is reduced as compared with the conventional case where the power supply voltage is supplied by only two power supply wirings.

Further, the second and third power supply lines, the internal power supply voltage generated by the step-down circuit between the first power supply wiring is provided. For this reason, a voltage drop between the step-down circuit and the load circuit can be suppressed to be small, and oscillation of the step-down circuit can be prevented.

[Embodiment 1]
FIG. 1 is a partially omitted plan view showing the structure of a DRAM according to the first embodiment of the present invention, which is compared with FIG.

  Referring to FIG. 1, this DRAM is different from the conventional DRAM in that lead frame 61 is replaced with lead frame 2 and pad P7 'is newly provided on the surface of chip 1. is there.

  The lead frame 2 includes a base end portion 2c and two branch portions 2a and 2b branched from the base end portion 2c. The base end 2c is connected to a package pin (not shown). The tip of the branching portion 2a is connected to the pads P1 and P2 by the bonding wire 66. The leading end of the branch 2b is connected to the pad P3 by a bonding wire 66.

  The pad P7 constitutes the power supply terminal 35 for the buffers 43 to 46 in FIG. 6, and the pad P7 ′ constitutes the power supply terminal 38 for the VDC circuit 59 in FIG. The base end portion of the lead frame 64 is connected to a pin of a package (not shown), and the tip end portion is connected to the pads P7 and P7 ′ by a bonding wire 66. That is, the buffers 43 to 46 and the VDC circuit 59 are connected to the external power supply potential ext. Receive VCC. External power supply potential ext. Between pad P7 and buffers 43-46. VCC line, external power supply potential ext. Between pad P7 'and VDC circuit 59. VCC line and external power supply potential ext. Between pad P8 and VPP circuit 57. The VCC lines are insulated from each other. The other configuration is the same as that of the conventional DRAM shown in FIGS.

  In this embodiment, since the lead frame 2 is branched from the base end portion 2c, the power supply noise generated in the output buffer 54 flows out of the chip having a lower impedance, and the VDC circuit 58 or the like is passed through the branch portion 2a. There is no wraparound. This prevents malfunction of the DRAM due to power supply noise during data output.

  Further, since the buffers 43 to 46 and the VDC circuit 59 are connected to different power supply pads P7 and P7 ', respectively, the buffers 43 to 46 and the VDC circuit 59 are connected to the same power supply pad P7. The generated power noise is difficult to be transmitted to the other. For this reason, malfunction of the DRAM due to power supply noise is prevented.

  In this embodiment, the lead frames 2, 62 to 65 and the pads P1 to P8 are connected by the bonding wires 66. However, the lead frames 2, 62 to 65 and the pads P1 to P8 are not used without using the bonding wires 66. May be connected directly.

  In this embodiment, the case where the present invention is applied to a so-called lead-on-chip (LOC) configuration in which the lead frames 2, 62 to 65 are arranged on the chip 1 has been described. It goes without saying that the same effect can be obtained even when applied to a configuration other than the configuration.

[Embodiment 2]
FIG. 2A is a partially broken plan view showing a configuration of a portion including n channel MOS transistor 70 of DRAM chip 25 according to the second embodiment of the present invention, and is compared with FIG. 9A. FIG. 2 and FIG. 2B are cross-sectional views taken along line XX ′ in FIG.

  Referring to FIG. 2, in DRAM chip 25, external ground potential ext. Is applied via insulating layer 6 above n channel MOS transistor 70 on the surface of silicon substrate 71. VSS line 3 is formed, and external power supply potential ext. VCC line 4 is formed, and external power supply potential ext. VCC line 5 is formed. External ground potential ext. VSS line 3 is formed of a polysilicon wiring layer (p-Si), and has an external power supply potential ext. VCC line 4 is formed of the first aluminum wiring layer (Al1), and the external power supply potential ext. The VCC line 5 is formed of a second aluminum wiring layer (Al2). External ground potential ext. VSS line 3 is connected to source region 74 and drain region 75 of the n-channel MOS transistor through contact holes 7 and 8, and external power supply potential ext. VCC line 4 is connected to gate electrode 73 of n-channel MOS transistor 70 through contact hole 9, and external power supply potential ext. VCC line 5 is connected to external power supply potential ext. Connected to VCC line 4.

  In this embodiment, a polysilicon wiring layer (p-Si) is used for external ground potential ext. VSS line 3 is formed, and external power supply potential ext. Is applied by first and second aluminum wiring layers (Al1, Al2). Since the VCC lines 4 and 5 are formed, the external ground potential ext. The VSS line 76 is formed, and the external power supply potential ext. Compared to the conventional case where the VCC line 77 is formed, the external power supply potential ext. The wiring resistance value of the VCC line can be reduced. Therefore, external power supply potential ext. External power supply potential ext. Due to the wiring resistance of the VCC line. The voltage drop of VCC can be suppressed small.

[Embodiment 3]
FIG. 3 is a circuit block diagram showing a main part of a DRAM according to the third embodiment of the present invention.

  Referring to FIG. 3, the DRAM includes a VDC circuit 59, a capacitor formed of an n-channel MOS transistor 70, and a load circuit 11. The VDC circuit 59 is the circuit shown in FIG. 6 and FIG. 13, and the load circuit 11 represents the column system circuit (A portion in FIG. 6) of FIG. The internal power supply potential int. VCC is the internal power supply potential int. The voltage is supplied to the load circuit 11 through the VCC line. Internal power supply potential int. VCC line and external ground potential ext. A capacitor formed of an n-channel MOS transistor 70 is provided between the VSS line.

  The internal power supply potential int. VCC line and external ground potential ext. The VSS line is configured in the same manner as in FIG. That is, external ground potential ext. The VSS line is composed of a polysilicon wiring layer (p-Si), and the internal power supply potential int. The VCC line is composed of first and second aluminum wiring layers (Al1, Al2).

  Also in this embodiment, the same effect as in the second embodiment can be obtained.

  The internal power supply potential int. VCC line and external ground potential ext. Since the capacitor composed of the n-channel MOS transistor 70 is provided between the VSS line and the VSS line, the load on the VDC circuit 59 can be increased moderately and the VDC circuit 59 can be prevented from oscillating.

[Embodiment 4]
FIG. 4 is a partially broken plan view showing a configuration of a portion including output circuit 84 of DRAM chip 26 according to the fourth embodiment of the present invention, and is a diagram compared with FIG.

  Referring to FIG. 4, DRAM chip 26 is different from DRAM chip 60 in FIG. 11 in that there is no cross-under portion (C portion in FIG. 11). That is, the external ground potential ext. VSS line 12 and external power supply potential ext. VCC line 13 is arranged in parallel. External ground potential ext. One end of the VSS line 12 is connected to the pad P0, and the external power supply potential ext. One end of the VCC line 13 is connected to the pad P3. External ground potential ext. The VSS line 12 is connected to the output circuit 84 through the contact hole 14, and the external power supply potential ext. The VCC line 13 is connected to the output circuit 84 through the contact hole 15. External ground potential ext. VSS line 12 and external power supply potential ext. It does not cross the VCC line 13 at all.

  In this embodiment, external ground potential ext. VSS line 12 and external power supply potential ext. Since VCC line 13 does not cross at all, external ground potential ext. VSS line 91 and external power supply potential ext. The wiring resistance of the power supply line can be reduced as compared with the conventional case where the VCC lines 92 intersect each other. For this reason, the voltage drop due to the wiring resistance of the power supply line can be kept small.

[Embodiment 5]
FIG. 5 is a partially broken plan view showing a configuration of a portion including VDC circuit 59 of DRAM chip 27 according to the fifth embodiment of the present invention, which is compared with FIG.

  Referring to FIG. 5, DRAM chip 27 is different from DRAM chip 60 in FIG. 14 in that there is no cross-under part (D part in FIG. 14). In other words, external power supply potential ext. VCC line 16, external ground potential ext. VSS line 17 and internal power supply potential int. The VCC line 18 is arranged. External power supply potential ext. One end of VCC line 16 is connected to pad P7 'and external ground potential ext. One end of the VSS line 17 is connected to the pad P0. External power supply potential ext. VCC line 16, external ground potential ext. VSS line 17 and internal power supply potential int. The VCC line 18 is connected to a VDC circuit 59 through contact holes 19, 20, and 21, respectively. The three lines 16, 17 and 18 do not intersect at all.

  In this embodiment, since the three lines 16, 17 and 18 do not intersect at all, the wiring resistance of the power supply line is reduced as compared with the conventional case where the three lines 100, 101 and 102 intersect each other. For this reason, the voltage drop due to the wiring resistance of the power supply line can be kept small.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a partially omitted plan view showing a configuration of a DRAM according to a first embodiment of the present invention; FIG. 10 is a partially broken view showing a configuration of a portion including an n-channel MOS transistor 70 of a DRAM chip according to a second embodiment of the present invention. FIG. 10 is a circuit block diagram showing a configuration of a main part of a DRAM according to a third embodiment of the present invention. It is the partially broken top view which shows the structure of the part containing the output circuit 84 of the DRAM chip by Embodiment 4 of this invention. FIG. 10 is a partially broken plan view showing a configuration of a portion including a VDC circuit 59 of a DRAM chip according to a fifth embodiment of the present invention. It is a circuit block diagram which shows the structure of the conventional DRAM. FIG. 7 is a partially omitted plan view showing a configuration of a DRAM chip including the DRAM shown in FIG. 6. FIG. 8 is a circuit diagram showing a capacitor formed of an n-channel MOS transistor 70 included in the DRAM chip shown in FIG. 7. FIG. 8 is a partially broken view showing a configuration of a portion including a capacitor formed by an n-channel MOS transistor 70 of the DRAM chip shown in FIG. 7. FIG. 7 is a circuit diagram showing a configuration of an output buffer 54 shown in FIG. 6. FIG. 8 is a partially broken plan view showing a configuration of a portion including an output circuit 84 of the DRAM chip shown in FIG. 7. It is an enlarged view which shows the structure of the cross under part shown in FIG. FIG. 7 is a circuit diagram showing a configuration of a VDC circuit 59 shown in FIG. 6. FIG. 8 is a partially broken plan view showing a configuration of a portion including a VDC circuit 59 of the DRAM chip shown in FIG. 7. FIG. 10 is a partially omitted plan view showing a configuration of another conventional DRAM chip.

Explanation of symbols

  1, 25-27, 60 DRAM chip, 2, 61-65, 110, 111 lead frame, 3, 12, 17, 76, 91, 101 External ground potential ext. VSS line, 4, 13, 16, 77, 92, 100 External power supply potential ext. VCC line, 6, 78 insulating layer, 7, 8, 9, 10, 14, 15, 19-21, 79-81, 93, 94, 96, 104, 105 contact hole, 11 load circuit, 18 internal power supply potential int. VCC line, 31, 32, 34, 42 Control signal input terminal, 33 Address signal input terminal, 35 to 39 Power supply terminal, 40 Ground terminal, 41 Data signal input / output terminal, 43 RAS buffer, 44 CAS buffer, 45 WE buffer 46 OE buffer, 47 clock generation circuit, 48 address buffer, 49 row decoder, 50 column decoder, 51 memory cell array, 52 sense amplifier + input / output control circuit, 53 preamplifier, 54 output buffer, 55 data-in buffer, 56 write driver 57 VPP circuit, 58, 59 VDC circuit, 70, 86, 88, 90 n-channel MOS transistor, 71 p-type silicon substrate, 72 gate oxide film, 73 gate electrode, 74 n-type source region, 75 n-type drain region, 82,8 Inverter, 84 an output circuit, 85, 87 p-channel MOS transistors, 98 operational amplifier, P0 to P8 pad.

Claims (1)

A semiconductor device formed on a semiconductor substrate,
A MOS transistor formed on the surface of the semiconductor substrate and used as a capacitive element;
A first power supply line formed above the semiconductor substrate and for applying a first power supply potential to the source region and the drain region of the MOS transistor;
A second power supply line formed above the first power supply line and for applying a second power supply potential different from the first power supply potential to the gate electrode of the MOS transistor ;
A third power line formed above the second power line in parallel with the second power line and connected to the second power line ;
A step-down circuit that steps down an external power supply voltage to generate an internal power supply voltage, and applies the internal power supply voltage between at least one of the second and third power supply wirings and the first power supply wiring;
A semiconductor device comprising a load circuit connected between at least one of the second and third power supply wirings and the first power supply wiring .

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