JP4141549B2 - Manufacturing method of semiconductor light emitting device - Google Patents

Description

【００５２】
また、各実施の形態における温度プロファイルを図４もしくは図５で説明したが、これは、理想的な温度変化を示したものであって、実際には、過程ＢやＤで厳密に一定温度が保持される必要があるものでもなく、それぞれの過程で徐々に温度変化があるようなプロファイルであってもかまわない。
【００５３】
〔実施の形態３〕
図６は、本発明に密接に関連する参考的な実施の形態３の半導体レーザ装置を示す断面図である。図において、３０は、本実施の形態の半導体レーザ装置、３００はサブマウント、３０１は導電性樹脂であり、その他実施の形態１と同様の部分については図１と同一の符号で示した。本実施の形態の半導体レーザ装置の構成は、実施の形態２における第２のハンダを導電性樹脂に置換した他は、実施の形態２とほぼ同様である。
【００５４】
ここで、導電性樹脂とは、熱可塑性樹脂、熱硬化性樹脂、あるいはこれらの混合物のいずれかの樹脂の中に、金属粉等を所定量混入したものであり、接着性と導電性を併せ持つものである。本実施の形態の半導体レーザ装置において、導電性樹脂接着剤３０１には、熱硬化性エポキシ樹脂の中に、Ａｇ粒子を５０ないし９０ｗｔ％配合したものを用いた。これにより、導電性樹脂は、金属並の導電性を有している。樹脂の硬化温度として１８０℃程度のものを用いた。また、第１のハンダには融点が１５６℃であるＩｎを用いた。
【００５５】
本実施の形態についても実施の形態２と同様に、半導体レーザチップにおいて、正電極が発光部に隣接する側の電極となり、負電極がその反対側の電極に相当する。また、サブマウントにおいては、正側金属パターンが、正電極に対向する導電膜パターンとなり、負側金属パターンが負電極に対向する導電膜パターンに相当する。
【００５６】
次に、本実施の形態の半導体レーザ装置を製造するためのダイボンディング工程について説明する。
【００５７】
あらかじめ、図３に示されたのと同様のサブマウントを準備する。ただし、負側の電極パターン上には、第２のハンダに代えて、上記導電性樹脂が設けられている。この段階で、樹脂は未硬化である。
【００５８】
次に、サブマウントの温度を上昇させ、ハンダが融解した後、図２に示した半導体レーザチップを、適切にアライメントし、レーザチップ電極形成面とサブマウント積載面とが突き合わされるように、サブマウント上に積載した。
【００５９】
その後、レーザチップに３０ｇの荷重を加えつつ、ハンダの融点以上の温度である１８０℃の状態を１分間保持して、ハンダと金属パターンおよび電極とを良くなじませ、また、樹脂を硬化させた。
【００６０】
それから、ハンダを固化させ、室温に近い適当な温度まで冷却されたところで、ダイボンディング工程を、終了した。
以上により、本実施の形態の半導体レーザ装置が完成した。
【００６１】
本実施の形態の半導体レーザ装置は、第２のハンダに替えて、導電性樹脂を用いたので、従来の技術の問題点が以下のように、解消されている。
【００６２】
上記過程において融解したハンダが固化する際には、既に、導電性樹脂が硬化しており、よって、半導体レーザチップは、第１のハンダの固化に伴って動くことがない。つまり、ハンダ冷却の途中でレーザチップが動き、アライメントずれが発生してしまう従来の技術第１の問題が回避される。
【００６３】
また、従来の技術において、両ハンダが同時に固化する際の、予測できないそれぞれの接着面に加わる力の偶然の集中によって、ブリッジ状にサブマウントに固定される半導体レーザチップに大きな熱歪みが加わることも無い。結果として、半導体レーザチップに大きな応力・熱歪みが発生してしまう従来の技術における第２の問題点が回避される。
【００６４】
また、本実施の形態の半導体発光素子の製造方法において、半導体レーザチップの発光部に隣接する側の電極は、従来同様ハンダにてサブマウントに接着されており、半導体レーザ装置の熱抵抗は、従来のものと同等である。本実施の形態と逆に、発光部に隣接する側の電極を、導電性樹脂で接続する構成とすると、熱抵抗が大きくなり、半導体発光装置の温度特性が悪化してしまう。
【００６５】
比較のために、本実施の形態の半導体レーザ装置における導電性樹脂に替えて、第１のハンダと同一の材料を用いた、対照半導体レーザ装置を作製した。サブマウントの端面垂直方向から±２°以内にレーザビーム中心がくることをダイボンディング工程の位置ずれに関する良品条件と規定したとき、本実施の形態の半導体レーザ装置においては、良品の得られる率が９８％だったのに対し、対象半導体レーザ装置においては、７５％であった。また、それぞれの半導体レーザ装置に、３ｍＷ、５０℃（初期電流５０ｍＡ程度）の条件での通電試験を１０００時間行ったところ、前者では、駆動電流の上昇がほとんど見られなかったのに対し、後者では、約３０％の装置で駆動電流値の２０％以上の上昇が観察された。
【００６６】
さらに、図２に示したように、半導体レーザチップの正負電極がほぼ同一面上にある場合に限らず、図１９に示されるように、発光層に隣接する側と逆側の電極（負電極）が窪んだ面上に設けられていても良い。特に、本実施の形態のように、発光層に隣接する側と逆側の電極の接続に、導電性樹脂を用いたので、この硬度を調整することによって、窪みが大きくても、確実に電気的導通を確保することができるようになる。
【００６７】
このように、本実施の形態のサブマウントを用いれば、従来の技術の場合と比較して、半導体レーザ装置の生産性が向上した。さらに、半導体レーザ装置の長期信頼性も向上した。
【００６８】
〔実施の形態４〕
図７は、本発明に密接に関連する参考的な実施の形態４の半導体レーザ装置を示す断面図である。図において、４０は、本実施の形態の半導体レーザ装置、４００はサブマウント、４０１はサブマウント積載面上の金属パターン間に設けられた溝、４０２は異方導電性樹脂であり、その他実施の形態１と同様の部分については図１と同一の符号で示した。本実施の形態の半導体レーザ装置の構成は、実施の形態３における導電性樹脂を異方導電性樹脂とした他は、実施の形態３と同様である。溝のサイズは、深さ０．２ｍｍ、幅０．１ｍｍとした。
【００６９】
ここで、導電性樹脂を異方性とするために、本実施の形態においては、熱硬化性エポキシ樹脂の中に、Ａｇ粒子を数ないし数１０ｗｔ％配合したものを用いた。これにより、異方導電性樹脂は、荷重を加えずに硬化した場合、金属粉が分散するので、絶縁性となり、所定の荷重を加えて硬化した場合、金属粉同士が接触するので、導電性となる。樹脂の硬化温度は１８０℃程度とした。また、第１のハンダには融点が１５６℃であるＩｎを用いた。
【００７０】
本実施の形態についても実施の形態１と同様に、半導体レーザチップにおいて、正電極が発光部に隣接する側の電極となり、負電極がその反対側の電極に相当する。また、サブマウントにおいては、正側金属パターンが、正電極に対向する導電膜パターンとなり、負側金属パターンが負電極に対向する導電膜パターンに相当する。
【００７１】
次に、本実施の形態の半導体レーザ装置を製造するためのダイボンディング工程について説明する。
【００７２】
あらかじめ、図３に示されたのと同様ではあるが、上記溝が設けられたサブマウントを準備する。また、負側の電極パターン上には、第２のハンダに代えて、上記異方導電性樹脂が設けられる。ただし、この段階で、樹脂は未硬化である。
【００７３】
次に、サブマウントの温度を上昇させ、ハンダが融解した後、図２に示した半導体レーザチップを、適切にアライメントし、レーザチップ電極形成面とサブマウント積載面とが突き合わされるように、サブマウント上に積載した。このとき、樹脂が拡がり、図７に示されるように、正側のハンダ等に接触した。
【００７４】
その後、レーザチップに３０ｇの荷重を加えつつ、ハンダの融点以上の温度である１８０℃の状態を１分間保持して、ハンダと金属パターンおよび電極とを良くなじませ、また、樹脂を硬化させた。
【００７５】
それから、ハンダを固化させ、室温に近い適当な温度まで冷却されたところで、ダイボンディング工程を、終了した。
以上により、本実施の形態の半導体レーザ装置が完成した。
【００７６】
本実施の形態の半導体レーザ装置は、第２のハンダに替えて、導電性樹脂を用いたので、従来の技術の問題点が実施の形態３の場合と同様、以下の如く解消されている。
【００７７】
上記過程において融解したハンダが固化する際には、既に、導電性樹脂が硬化しており、よって、半導体レーザチップは、第１のハンダの固化に伴って動くことがない。つまり、ハンダ冷却の途中でレーザチップが動き、アライメントずれが発生してしまう従来の技術第１の問題が回避される。
【００７８】
また、従来の技術において、両ハンダが同時に固化する際の、予測できないそれぞれの接着面に加わる力の偶然の集中によって、ブリッジ状にサブマウントに固定される半導体レーザチップに大きな熱歪みが加わることも無い。結果として、半導体レーザチップに大きな応力・熱歪みが発生してしまう従来の技術における第２の問題点が回避される。
【００７９】
また、本実施の形態の半導体発光素子の製造方法において、半導体レーザチップの発光部に隣接する側の電極は、従来同様ハンダにてサブマウントに接着されており、半導体レーザ装置の熱抵抗は、従来のものと同等である。
【００８０】
比較のために、本実施の形態の半導体レーザ装置における第２のハンダを、第１のハンダと同一の材料で構成した、対照半導体レーザ装置を作製した。サブマウントの端面垂直方向から±２°以内にレーザビーム中心がくることをダイボンディング工程の位置ずれに関する良品条件と規定したとき、本実施の形態の半導体レーザ装置においては、良品の得られる率が９８％だったのに対し、対象半導体レーザ装置においては、７５％であった。また、それぞれの半導体レーザ装置に、３ｍＷ、５０℃（初期電流５０ｍＡ程度）の条件での通電試験を１０００時間行ったところ、前者では、駆動電流の上昇がほとんど見られなかったのに対し、後者では、約３０％の装置で駆動電流値の２０％以上の上昇が観察された。
【００８１】
このように、本実施の形態のサブマウントを用いれば、従来の技術の場合と比較して、半導体レーザ装置の生産性が向上した。さらに、半導体レーザ装置の長期信頼性も向上した。
【００８２】
さらに、図２に示したように、半導体レーザチップの正負電極がほぼ同一面上にある場合に限らず、図１９に示されるように、発光層に隣接する側と逆側の電極（負電極）が窪んだ面上に設けられていても良い。特に、本実施の形態のように、発光層に隣接する側と逆側の電極の接続に、導電性樹脂を用いたので、この硬度を調整することによって、窪みが大きくても、確実に電気的導通を確保することができるようになる。
【００８３】
また、特に、本実施の形態の半導体発光素子においては、異方導電性樹脂を用い、サブマウント金属膜パターン間に溝を設けたので、樹脂の溝上の領域には荷重が加わらず絶縁性であり、金属パターン上の領域には荷重が加わり導電性となる。よって、負電極と負側金属パターン間には、電気的など導通が確保されるが、図７に示される如く、たとえ樹脂が正電極等と接触したとしても、ショートすることがない。よって、ダイボンディング工程における、ショート発生による生産性の低下を防止することができる。
【００８４】
以上、本発明に関連する構成を特定の例を挙げて説明したが、本発明の適用範囲はこれに限られるものではなく、当然ながら、各構成要素をそれぞれ用途を同じくする材料に置換し得るし、他の技術を組み合わせて用いることもできる。
【００８５】
上述の絶縁性サブマウント基体は、ダイヤモンド、Ｓｉ、ＳｉＣ、ｃＢＮ、ＢｅＯ、ＡｌＯ等の他の絶縁材料や、さらには、ダイヤモンド／Ｓｉ、ＳｉＯ／Ｓｉに代表されるように、それら各絶縁材料の積層構造からなる、他の絶縁性サブマウント基体に置き換えることができる。
【００８６】
また、必ずしもサブマウント基体は絶縁性である必要はなく、正負両電極の間を絶縁する工夫を行ったうえで、導電性サブマウント基体を用いることができる。導電性サブマウント基体としては、Ｓｉ、Ｇｅ、ＳｉＣ、Ｃｕ、ＣｕＷ、Ｍｏ等の材料や、それら各物質の積層構造を用いることができる、
上述の半導体レーザチップは、図２に示した特定の例に限られるものではなく、基板としてＧａＮ、ＳｉＣ、Ｓｉ、ＳｉＯ／サファイア等の他の材料を用いる等の変更が可能であり、また、半導体成長層の材料系として、例えば、ＩｎＧａＡｓＰ系、ＩｎＧａＡｌＰ系、ＡｌＧａＮ系、ＣｄＺｎＳｅ系等の他のもの用いることも可能である。また、半導体レーザチップを、ＬＥＤ、スーパールミネッセンスダイオード等の他の発光素子チップにも置換し得る。
【００８７】
また、上記実施の形態のサブマウントにおいて、各ハンダおよび各金属パターンの形状を、図３に特定の例で示したが、本発明はこれに限られるものではなく、適宜変更され得るものである。例えば、必ずしも、金属パターンがサブマウントのほぼ全面を覆うように設けられる必要はない。また、サブマウント積載面上に、さらに、ワイヤボンディング用のパッド部を設けることや、ダイボンディング時の位置合わせのための印を設けることは、当業者には、容易に想定し得る事項である。あるいは、いわゆるマルチビームレーザのように、３以上の電極を有する半導体レーザチップを積載した半導体レーザ装置にも、上記原理に基づいて、本発明を応用することは、当業者にとって容易に想定し得る。
【００８８】
さらに、ハンダ層とサブマウント基体との間には、公知のごとく、種々の膜を介在させることが可能であり、例えば、サブマウントとハンダ間の密着性を向上させるための膜、サブマウントとハンダ間の反応を防止するための膜、さらには、これらの膜の間の密着性を高めたり、酸化を防止するための膜が適宜積層形成させてもよい。上記実施の形態に示した金属パターンＡｕ／Ｐｔ／Ｔｉに置換し得るものとして、Ｐｔ／Ｃｒ、Ａｕ／Ｍｏ、Ａｕ／Ｐｔ／Ｃｒ、Ａｕ／Ｍｏ／Ｔｉ等も用いることが可能である。ハンダ、絶縁膜、ボンディングパッド、サブマウント基体相互の間にも、同様の目的で、種々の膜を介在させることが想定される。
【００８９】
またさらに、図１、３、６に示されたサブマウントの構成によれば、第１ハンダと第２ハンダとの間のスペースには、特別の構造は設けられていないが、ここに、ダイボンディング工程時のショートを防止したり、アライメントずれを防止するために、溝・梨地面・樹脂突起・絶縁体突起等の構造物を設けても良い。
【００９０】
上述の各実施の形態においては、半導体レーザ素子用サブマウントについて説明したが、本発明の適用は、これに限られるものでなく、発光素子チップのマウント部材全般に適用できる。すなわち、任意のマウント部材において、発光素子チップのダイボンディングされる部分が、上述の各実施の形態と同様の構成であれば、他の発光素子チップ用マウント部材においても上述同様の効果を奏することは、明白である。したがって、発光素子チップを、サブマウントを用いず直接ステム、フレーム、もしくはパッケージに積載する場合においては、このステム、フレームもしくはパッケージに、上記本発明に関連する構成を適用することができる。
【００９１】
〔実施の形態５〕
図８は、本発明に密接に関連する参考的な実施の形態５の半導体レーザ装置を示す断面模式図である。図８において、５０は本実施の形態の半導体レーザ装置、５００は本実施の形態のサブマウント、５０１ａ、５０１ｂは絶縁体で形成されるサブマウント基体、１０２は正側金属パターン、１０３は負側金属パターンであり、５０４、５０５は導電性接着剤としてハンダを用いている。ここで５０１ａと５０１ｂは、熱伝導率が異なる絶縁体材料で形成されている。図示されるように、サブマウント積載面のハンダおよび金属パターンは、適宜パターン形成されることにより、それぞれが絶縁分離されており、よって、片面に正負電極を有する半導体レーザ素子の積載を可能としていることは、従来の技術と同様である。本実施の形態では、サブマウント基体５０１ａは、その断面図においてＬ字型をしているが、断面図においてコの字型を形成するように掘り、その中に５０１ｂを埋め込んでもよい。
【００９２】
図９は、本実施の形態の半導体レーザ装置に用いた、本実施の形態のサブマウントを示す模式図である。各記号は図８と同一である。本実施の形態において、サブマウント基体５０１ａには絶縁体であるＡｌＮを用い、サブマウント基体５０１ｂにはＡｌＮより熱伝導率が低い絶縁体であるＡｌ₂Ｏ₃を用い、正側金属パターン１０２および負側金属パターン１０３には、Ａｕ（０．１μｍ）／Ｐｔ（０．１μｍ）／Ｔｉ（０．１μｍ）（Ａｕ オン Ｐｔ オン Ｔｉ、以下同様）、ハンダ５０４および５０５には融点が２１７℃であるＳｎＡｕ（Ｓｎ９０％、Ａｕ１０％）ハンダを用いた。サブマウント基体の作成方法の一例として、図１０（ａ）に示すように、サブマウント基体５０１ａをまず、ドライエッチングやウェットエッチング等のエッチング手段、また物理的に研削する手段等を用いで段差を形成したうえで、図１０（ｂ）に示すように真空蒸着法、ＣＶＤ法、スパッタ法、熱転写法、印刷法、焼結法、塗布法等の公知技術を適宜用いて５０１ｂを成膜し、図１０（ｃ）に示すように研磨により平坦化することにより形成する。そして、図１０（ｄ）に示すように正側金属パターン１０２、負側金属パターン１０３を、真空蒸着法、ＣＶＤ法、スパッタ法、熱転写法、印刷法、焼結法、塗布法等の公知技術を適宜用いて成膜する。本実施の形態においては、一例として、サブマウント基体５０１ａと５０１ｂを併せた全体のサイズを、長さ２ｍｍ×幅１．５ｍｍ×高さ０．２ｍｍとし、５０１ｂのみの大きさは長さ２ｍｍ×幅０．７ｍｍ×高さ０．１ｍｍとし、ハンダ間の距離を５０μｍ、ハンダの厚さを１μｍとした。
【００９３】
上述の構成によって、本半導体レーザチップにおいては、正電極が発光部に隣接する側の電極となり、負電極がその反対側の電極に相当する。また、本サブマウントにおいては、正側金属パターンが、正電極に対向する導電膜パターンとなり、負側金属パターンが負電極に対向する導電膜パターンに相当する。
また、５０１ａ、５０１ｂは放熱部となるので、放熱効率を高くするため、厚さが２０μｍ以上あるのが好ましい。
【００９４】
次に、本実施の形態の半導体レーザ装置を製造するためのダイボンディング工程について説明する。図１１は、工程の各過程におけるサブマウント積載面温度Ｔの変化を示したグラフ（温度プロファイル）である。ここで、Ｔは、各ハンダの温度に一致している。
〈過程Ａ〉始めに、図９に示した、本実施の形態のサブマウントを、ハンダの融点（Ｔｍ＝２１７℃）よりも高い温度であるＴｐ＝２５０℃まで加熱したところ、双方のハンダが融解した。
〈過程Ｂ〉図２に示したＧａＮ系半導体レーザチップ２００を、適切にアライメントし、レーザチップ電極形成面とサブマウント積載面とが突き合わされるように、サブマウント上に積載した。ここで、アライメントは、次の要領でなされる。正電極２０３とハンダ５０４および正側金属パターン１０２、負電極２０４とハンダ５０５および負側金属パターン１０３が、それぞれ一致するように、すなわち、図８に示されるように、また、半導体レーザチップのストライプ方向が、サブマウントの端面と垂直の関係になり、光出射面がサブマウントの端面とほぼ一致するように、方向および位置併せされる。
次いで、半導体レーザチップに約２０ｇの荷重を加えて、Ｔｐ＝２５０℃の状態を３０秒間保持し、ハンダと、金属パターンおよび電極とを良くなじませた。
〈過程Ｃ〉荷重を加えたまま、加熱を止めた。すると、図中実線で示すように、熱伝導率の大きいサブマウント基体５０１ａに対向するハンダ５０４は早く冷却され、ｔ１秒で融点Ｔｍまで下がり、固化する。ここで、荷重を加えるのを止めた。その後、図中破線で示すように、ｔ２秒で熱伝導率の小さいサブマウント基体に対向するハンダ５０５が融点Ｔｍまで下がり、固化する。室温に近い適当な温度まで冷却されたところで、ダイボンディング工程を、終了した。
以上により、図８に示す本実施の形態の半導体レーザ装置が完成した。
【００９５】
本実施の形態の半導体レーザ装置は、熱伝導率の異なるサブマウント基体を用いて、ハンダの固まる速度を正電極側と負電極側で異ならせることにより、固化の際に接着面毎にかかる力のバランスを保ちつつ、接着面にかかる力を分散させているので、従来の技術の問題点が以下のように、解消されている。
【００９６】
上記過程Ｂにおいて融解したハンダのうち、発光部に隣接するハンダ５０４のみが、先にｔ１秒で固化する。このとき、ハンダ５０５は、まだ、融解しているので、従来の技術において問題となったような、両方のハンダが同時に固化しようとすることに伴う、各接合面毎に加わる力のアンバランスが生じない。これにより、半導体レーザチップは、ハンダ５０４の固化に伴って、動くことなく固定される。よって、その後、ハンダ５０５が固化する際にチップがずれてしまうこともなく、結果として、ハンダ冷却の途中でレーザチップが動き、アライメントずれが発生してしまう従来の技術第１の問題が回避される。
【００９７】
また、従来の技術において、両ハンダが同時に固化する際の、予測できないそれぞれの接着面に加わる力の、偶然の集中によって、ブリッジ状にサブマウントに固定される半導体レーザチップに大きな熱歪みが加わることも無い。さらに、先にハンダ５０４側が固定された後、ハンダ５０５側の固定に至るまでの間に、チップに引き起こされる歪みが緩和されている。結果として、半導体レーザチップに大きな応力・熱歪みが発生してしまう従来の技術における第２の問題点が回避される。
【００９８】
本実施の形態の半導体発光素子の製造方法においては、過程Ｂの温度Ｔが、ハンダ５０４、５０５の融点より若干高い温度に設定されている。これは、電極と金属パターンの接合を、最適な条件で行うためのもので、これにより、それらとハンダの間での合金化が適正に進み、また、ハンダが厚すぎて介在されることがなくなり、よって、熱抵抗を最小限とした接合が可能になる。
【００９９】
また、本実施の形態の半導体レーザ装置では、発光部に隣接した電極が正電極である。レーザーチップの温度上昇による特性劣化を押さえるためには発光部に隣接した正電極からの放熱が良好な方がこのましい。そのため、正電極に接するハンダ５０４が、熱伝導率の大きい方のサブマウント基体に配置されている方が好ましい。さらに、正電極と負電極とで電気抵抗率が異なる場合はそれによっても各電極での発熱量が異なるため、その点も考慮するのが好ましい。
【０１００】
比較のために、本実施の形態の半導体レーザ装置における、サブマウント基体５０１ａおよび５０１ｂを同一の材料で構成した、対照半導体レーザを作成した。サブマウントの端面垂直方向から＋−２°以内にレーザビーム中心がくることをダイボンディング工程の位置ずれに関する良品条件として規定したとき、本実施の形態の半導体レーザ装置においては。良品の得られる率が９８％であったのに対し、対照半導体レーザにおいては、７８％であった。また、それぞれの半導体レーザ装置に、３ｍＷ、７０℃（初期電流９０ｍＡ程度）の条件での通電試験を１０００時間行ったところ、前者では、駆動電流の上昇がほとんど見られなかったのに対し、後者では、約４０％の装置で駆動電流値の２０％以上の上昇が観察された。このように、従来の技術を用いた半導体レーザ装置と比較して、ダイボンディング工程の生産性の向上と、装置寿命特性の向上が確認された。
また、本実施の形態のサブマウントによれば、従来の技術のものと比較して、半導体レーザ装置の生産性を向上せしめ、装置寿命特性を改善させる効果を奏する。
【０１０１】
本実施の形態においては、サブマウント基体５０１ａおよび５０１ｂがどちらも絶縁体であったが、熱伝導率の異なる材料の組合わせであれば、絶縁体と導電体の組合わせでもよいことは言うまでもない。例えば、図１２（ａ）に示すように金属で形成されるサブマウント基体５０１ａを途中まで形成した上に、真空蒸着法、ＣＶＤ法、スパッタ法、熱転写法、印刷法、焼結法、塗布法等の公知技術を適宜用いて、絶縁膜で形成されるサブマウント基体５０１ｂを成膜し、図１２（ｂ）に示すように、ドライエッチングやウェットエッチング等のエッチング手段、また物理的に研削する手段等の公知技術を適宜用いてを用いで段差形成を行い、図１２（ｃ）に示すように、めっき法によって段差部分へサブマウント基体５０１ａを埋め込み、図１２（ｄ）に示すように電極を形成することでも形成することができる。
【０１０２】
また、導電体を用いる場合は、金属パターンを兼ねることも可能であるし、さらにはマウント部材のレーザーチップに面した側からだけではなく、側面や裏面からもステム、パッケージ、外部リード等へ直接接続が可能となり、放熱効率のアップやシステム全体の簡略化へつながる。
また、本実施の形態では５０４、５０５には同一のハンダを用いたが、５０４側が先に固化するように設計されていれば異なるハンダを用いてもいいことは言うまでもない。
また、本実施の形態では放熱部に直接導電性接着剤が形成されているが、導電性を保つ程度であれば間に絶縁層が形成されていても良い。
【０１０３】
［実施の形態６］
本発明に密接に関連する参考的な実施の形態６によれば、実施の形態５のバリエーション実施の形態５のサブマウント基体以外にも、異なる熱伝導率をもった材料を組合わせた、図１３（ａ）、（ｂ）に示すような形のサブマウント基体を用いても同様の効果が得られる。
【０１０４】
例えば、図１３（ａ）のサブマウント基体は熱伝導率のことなる立方体あるいは直方体の二種類材料をある一面で接合させたものである。この場合、図８に比べ、５０１ｂの表面積を大きくできるので、熱を効果的に発散することができる。これは、２種材料を接着剤で接着してもよいし、一方の材料の上に、真空蒸着法、ＣＶＤ法、スパッタ法、メッキ法、熱転写法、印刷法、焼結法等の公知技術を用いて堆積してもよい。本実施の形態においては、一例として、サブマウント基体５０１ａには導電体であるＣｕを用い、サブマウント基体５０１ｂにはＣｕより熱伝導率が低い絶縁体であるＡｌ₂Ｏ₃を用い、正側金属パターンおよび負側金属パターン１０３には、Ａｕ（０．１μｍ）／Ｐｔ（０．１μｍ）／Ｔｉ（０．１μｍ）、導電性接着剤としてハンダ５０４および５０５には融点が１５６℃であるＩｎハンダを用いた。また本実施の形態においては、一例として、サブマウント基体５０１ａ、５０１ｂの大きさはそれぞれ長さ２ｍｍ×幅１ｍｍ×厚さ０．２ｍｍとし、接着剤で接着した。
【０１０５】
また、図１３（ｂ）のサブマウント基体は、５０１ｂが５０１ａの裏面まで覆う場合である。この場合、図８に比べ５０１ｂの表面積を大きくできるので、熱を効果的に発散することができる。これは、熱伝導率の異なる２種材料を接着剤で接着してもよいし、一方の材料の上に、真空蒸着法、ＣＶＤ法、スパッタ法、メッキ法、熱転写法、印刷法、焼結法等の公知技術を用いて堆積してもよい。本実施の形態で一例として、サブマウント基体５０１ａには絶縁体であるｃＢＮを用い、サブマウント基体５０１ｂにはｃＢＮより熱伝導率が低い導電体であるＦｅを用い、正側金属パターン１０２および負側金属パターン１０３には、Ａｕ（０．１μｍ）／Ｐｔ（０．１μｍ）／Ｔｉ（０．１μｍ）、導電性接着剤としてハンダ５０４および５０５には融点が１５６℃であるＩｎハンダを用いた。また本実施の形態においては、一例として、サブマウント基体５０１ａは長さ２ｍｍ×幅１．５ｍｍ×厚さ０．２ｍｍの上に、長さ２ｍｍ×幅０．７ｍｍ×厚さ０．１ｍｍの凹部を持ち、５０１ｂは５０１ａ上の凹部から裏面にかけて厚さ０．１ｍｍで覆うものとする。５０１ａ上の凹部はドライエッチングやウェットエッチング等のエッチング手段、また物理的に研削する手段等の公知技術を用いて形成し、その凹部から裏面にかけて表面を導電化処理（銀ペースト塗布等）をした後、Ｆｅメッキにより５０１ｂを形成する。
【０１０６】
以上図１３（ａ）、（ｂ）のサブマウント基体においても、実施の形態５と同様に、サブマウント基体５０１ａおよび５０１ｂが熱伝導率が異なる絶縁体同志であってもよいし、熱伝導率の異なる材料の組合わせであれば、絶縁体と導電体の組合わせでもよいことは言うまでもない。
また、５０１ａ、５０１ｂは放熱部となるので、放熱効率を高くするため、厚さが２０μｍ以上あるのが好ましい。
また、サブマウント基体に導電体を用いる場合は、金属パターンを兼ねることも可能であるし、さらにはマウント部材のレーザーチップに面した側からだけではなく、側面や裏面からもステム、パッケージ、外部リード等へ直接接続が可能となり、放熱効率のアップやシステム全体の簡略化へつながる。
【０１０７】
上記、実施の形態５、２に示したサブマウントにおいては、図８、図１３に示すように、サブマウント基体の表面がほぼ平面であるため、対面するレーザーチップの正および負の電極がほぼ平面上にある場合に容易にダイボンドできるが、もし対面するレーザーチップの正負の電極に高低差がある場合には、５０１ａまたは５０１ｂの厚さによって任意に調整することが可能である。
【０１０８】
〔実施の形態７〕
本発明に密接に関連する参考的な実施の形態７の構成は、サブマウントの形と材料が異なる他は、実施の形態５、６と同様である。本実施の形態を図１４に示す。６０は本実施の形態の半導体レーザ装置、６００はサブマウント、サブマウント基体には熱伝導率のことなる二種類の導電性材料を用いた６０１ａ、６０１ｂを絶縁体６０１ｃを介して接合させたものを用いた。本実施の形態ではサブマウント断面図における絶縁体はＬ字型をしているが、断面図でコの字型、平面図ではサブマウント基体６０1ｂの周囲を絶縁体６０１ｃが覆い、絶縁体６０１ｃの周囲をサブマウント基体６０１ｂを覆うような構造になっていてもよい。
【０１０９】
本実施の形態においては一例として、サブマウント基体６０１ａには導電体であるＡｇを用い、サブマウント基体６０１ｂにはＡｇより熱伝導率の低い導電体であるＡｌを用い、絶縁体６０１ｃにはＳｉＯ₂を用い、正側金属パターン１０２および負側金属パターン１０３には、Ａｕ（０．１μｍ）／Ｐｔ（０．１μｍ）／Ｔｉ（０．１μｍ）、導電性接着剤としてハンダ５０４および５０５には融点が２１７℃であるＳｎＡｕ（Ｓｎ９０％、Ａｕ１０％）ハンダを用いた。これは、サブマウント基体６０１ａをまず、ドライエッチングやウェットエッチング等のエッチング手段、また物理的に研削する手段等の公知技術を用いて段差を形成したうえで、６０１ｃ、６０１ｂを順次成膜して形成する。サブマウント基体６０１ｂおよび、正側金属パターン１０２、負側金属パターン１０３の成膜は、真空蒸着法、ＣＶＤ法、スパッタ法、メッキ法、熱転写法、印刷法、焼結法等の公知技術を適宜用いて作成することができる。例えば、図１５（ａ）に示すように、サブマウント基体６０１ａ上にフォトレジスト６０６でパターン形成した後、エッチングを行い段差を形成し、図１５（ｂ）に示すようにフォトレジスト６０６を除かずに、６０１ｃのＳｉＯ₂をＣＶＤ法で１μｍ堆積し、さらに６０１ｂのＡｌをスパッタ法で０．５μｍ堆積した後にレジストおよび、レジスト上のＳｉＯ₂、Ａｌをウェットエッチングで除去した後（リフトオフ法）、図１５（ｃ）に示すように凹部に６０１ｂのＡｌメッキを行い、図１５（ｄ）に示すように、その上に正側金属パターン１０２、負側金属パターン１０３を形成することで、作ることができる。
【０１１０】
本実施の形態においては、一例として、サブマウント基体６０１ａと６０１ｂを併せた全体のサイズを、長さ２ｍｍ×幅１．５ｍｍ×高さ０．２ｍｍとし、６０１ｂのみの大きさは長さ２ｍｍ×幅０．７ｍｍ×高さ０．１ｍｍとし、ハンダ間の距離を５０μｍ、ハンダの厚さを１μｍとした。
【０１１１】
また、６０１ａ、６０１ｂは放熱部となるので、放熱効率を高くするため、厚さが２０μｍ以上あるのが好ましい。６０１ｃの膜厚は、６０１ａと６０１ｂの間の絶縁性を保てるだけの膜厚があればよく、例えばＳｉＯ₂では最低０．１μｍ程度あれば十分である。絶縁耐厚の大小は、絶縁膜の種類、膜質により異なるため、必要最低限の膜厚は、使用する膜により適宜変更される。
【０１１２】
次に、実施の形態５と同様にして、本実施の形態の半導体レーザ装置を製造するためのダイボンディング工程を行った。工程の各過程におけるサブマウント積載面温度Ｔの変化（温度プロファイル）は実施の形態５で説明したのと同様である。
以上で、本実施の形態の半導体レーザ装置が完成した。
【０１１３】
本実施の形態の半導体レーザ装置は、熱伝導率の異なるサブマウント基体を用いて、ハンダの固まる速度を正電極側と負電極側で異ならせることにより、固化の際に接着面毎にかかる力のバランスを保ちつつ、接着面にかかる力を分散させているので、従来の技術の問題点が以下のように、解消されている。
【０１１４】
上記実施の形態５及び図１１で記した、過程Ｂにおいて融解したハンダのうち、発光部に隣接するハンダ５０４のみが、ｔ１秒で固化する。このとき、ハンダ５０５は、まだ、融解しているので、従来の技術において問題となったような、両方のハンダが同時に固化しようとすることに伴う、各接合面毎に加わる力のアンバランスが生じない。これにより、半導体レーザチップは、ハンダ５０４の固化に伴って、動くことなく固定される。よって、その後、ハンダ５０５が固化する際にチップがずれてしまうこともなく、結果として、ハンダ冷却の途中でレーザチップが動き、アライメントずれが発生してしまう従来の技術第１の問題が回避される。
【０１１５】
また、従来の技術において、両ハンダが同時に固化する際の、予測できないそれぞれの接着面に加わる力の、偶然の集中によって、ブリッジ状にサブマウントに固定される半導体レーザチップに大きな熱歪みが加わることも無い。さらに、先にハンダ５０４側が固定された後、ハンダ５０５側の固定に至るまでの間に、チップに引き起こされる歪みが緩和されている。結果として、半導体レーザチップに大きな応力・熱歪みが発生してしまう従来の技術における第２の問題点が回避される。
【０１１６】
本実施の形態についても実施の形態５と同様に、半導体レーザチップにおいて、正電極が発光部に隣接する側の電極となり、負電極がその反対側の電極に相当する。また、サブマウントにおいては、正側金属パターンが、正電極に対向する導電膜パターンとなり、負側金属パターンが負電極に対向する導電膜パターンに相当する。
【０１１７】
また、本実施の形態の半導体レーザ装置では、発光部に隣接した電極が正電極である。レーザーチップの温度上昇による特性劣化を押さえるためには発光部に隣接した正電極からの放熱が良好な方がこのましい。そのため、正電極に接するハンダ５０４が、熱伝導率の大きい方のサブマウント基体に配置されている方が好ましい。さらに、正電極と負電極とで電気抵抗率が異なる場合はそれによっても各電極での発熱量が異なるため、その点も考慮するのが好ましい。
【０１１８】
比較のために、本実施の形態の半導体レーザ装置におけるサブマウント基体６０１ａおよび６０１ｂを同一の材料で構成した、対照半導体レーザ装置を作製した。サブマウントの端面垂直方向から±２°以内にレーザビームの中心がくることをダイボンディング工程の位置ずれに関する良品条件と規定したとき、本実施の形態の半導体レーザ装置においては、良品の得られる率が９８％だったのに対し、対照半導体レーザ装置においては、７５％であった。また、それぞれの半導体レーザ装置に、５ｍＷ、６０℃（初期電流８０ｍＡ程度）の条件での通電試験を１０００時間行ったところ、前者では、駆動電流の上昇がほとんど見られなかったのに対し、後者では、約７０％の装置で駆動電流値の２０％以上の上昇が観察された。このように、従来の技術を用いた半導体レーザ装置と比較して、ダイボンディング工程の生産性の向上と、装置寿命特性の向上が確認された。
【０１１９】
また、本実施の形態のサブマウントによれば、従来の技術のものと比較して、半導体レーザ装置の生産性を向上せしめ、装置寿命特性を改善させる効果を奏する。本実施の形態においては、サブマウント基体６０１ａおよび６０１ｂともに導電体を用いているため、金属パターンを兼ねることも可能であるし、さらにはマウント部材のレーザーチップに面した側からだけではなく、側面や裏面からもステム、パッケージ、外部リード等へ直接接続が可能となり、放熱効率のアップやシステム全体の簡略化へつながる。また、一般的に導電体には熱伝導率の高い金属が多いため、材料選択の幅が広がり、より最適な材料を選ぶことができる。
【０１２０】
［実施の形態８］
本発明に密接に関連する参考的な実施の形態８によれば、実施の形態７のバリエーション実施の形態７のサブマウント基体以外にも、異なる熱伝導率をもった導電体材料を組合わせた、図１６（ａ）、（ｂ）に示すような形のサブマウント基体を用いても同様の効果が得られる。
【０１２１】
まず、図１６（ａ）のサブマウント基体は熱伝導率の異なる立方体あるいは直方体の二種類の導電体を絶縁体６０１ｃを介して一面で接合させたものである。この場合、図１４に比べ、６０１ｂの表面積を大きくできるので、熱を効果的に発散することができる。これは、各材料を接着剤で接着してもよいし、一方の材料の上に、真空蒸着法、ＣＶＤ法、スパッタ法、メッキ法、熱転写法、印刷法、焼結法等の公知技術を用いて堆積してもよい。本実施の形態においては、一例として、サブマウント基体６０１ａには導電体であるＣｕを用い、サブマウント基体６０１ｂにはＣｕより熱伝導率が低い導電体であるＦｅを用い、絶縁体６０１ｃにはＳｉＯ₂を用い、正側金属パターン１０２および負側金属パターン１０３には、Ａｕ（０．１μｍ）／Ｍｏ（０．１μｍ）、導電性接着剤としてハンダ５０４および５０５には融点が１５６℃であるＩｎハンダを用いた。また本実施の形態においては、一例として、サブマウント基体６０１ａ、６０１ｂの大きさはそれぞれ長さ２ｍｍ×幅１ｍｍ×厚さ０．２ｍｍとし、６０１ａまたはｂの一面にＣＶＤ法でＳｉＯ₂膜を１μｍ堆積した後、接着剤で接着した。この接着剤が十分な絶縁性を持つ場合には、６０１ｃを兼ねる事も可能である。
【０１２２】
また、図１６（ｂ）のサブマウント基体は、６０１ｂが６０１ｃを介して６０１ａの裏面まで覆う場合である。この場合、図１４に比べ６０１ｂの表面積を大きくできるので、熱を効果的に発散することができる。これは、熱伝導率の異なる各材料を接着剤で接着してもよいし、一方の材料の上に、真空蒸着法、ＣＶＤ法、スパッタ法、メッキ法、熱転写法、印刷法、焼結法等の公知技術を用いて堆積してもよい。本実施の形態で一例として、サブマウント基体６０１ａには導電体であるＣｕを用い、サブマウント基体６０１ｂにはＣｕより熱伝導率が低い導電体であるＦｅを用い、絶縁体６０１ｃにはＳｉＯ₂を用い、正側金属パターン１０２および負側金属パターン１０３には、Ａｕ（０．１μｍ）／Ｍｏ（０．０３μｍ）、ハンダ５０４および５０５には融点が１５６℃であるＩｎハンダを用いた。また本実施の形態においては、一例として、サブマウント基体６０１ａは長さ２ｍｍ×幅１．５ｍｍ×厚さ０．２ｍｍの上に、長さ２ｍｍ×幅０．７ｍｍ×厚さ０．１ｍｍの凹部を持ち、６０１ｂは６０１ａ上の凹部から裏面にかけて厚さ約０．１ｍｍで覆うものとする。６０１ａ上の凹部はドライエッチングやウェットエッチング等のエッチング手段、また物理的に研削する手段等の公知技術を用いて形成し、その凹部から裏面にかけてＣＶＤ法でＳｉＯ₂膜１μｍを堆積した後、ＳｉＯ₂表面を導電化処理（銀ペースト塗布等）をした後、Ｆｅメッキにより６０１ｂを形成する。
【０１２３】
また、６０１ａ、６０１ｂは放熱部となるので、放熱効率を高くするため、厚さが２０μｍ以上あるのが好ましい。６０１ｃの膜厚は、６０１ａと６０１ｂの間の絶縁性を保てるだけの膜厚があればよく、例えばＳｉＯ₂では最低０．１μｍ程度あれば十分である。絶縁耐厚の大小は、絶縁膜の種類、膜質により異なるため、必要最低限の膜厚は、使用する膜により適宜変更される。
【０１２４】
本実施の形態においては、サブマウント基体に導電体を用いているので、金属パターンを兼ねることも可能であるし、さらにはマウント部材のレーザーチップに面した側からだけではなく、側面や裏面からもステム、パッケージ、外部リード等へ直接接続が可能となり、放熱効率のアップやシステム全体の簡略化へつながる。
【０１２５】
上記、図１４、図１６においては、サブマウント基体の表面がほぼ平面であるため、対面するレーザーチップの正および負の電極がほぼ平面上にある場合に容易にダイボンドできるが、もし対面するレーザーチップの正負の電極に高低差がある場合には、６０１ａまたは６０１ｂの厚さによって調整することが可能である。
【０１２６】
また、実施の形態５〜８における温度プロファイルを図１２で説明したが、これは、理想的な温度変化を示したものであって、実際には、過程Ｂで厳密に一定温度が保持される必要があるものでもなく、それぞれの過程で徐々に温度変化があるようなプロファイルであってもかまわない。
【０１２７】
上記実施の形態７、８においては、サブマウントの１０１ａと１０１ｂを熱伝導率の異なる金属で形成したが、絶縁膜１０１ｃの熱伝導率や厚さを考慮すれば、熱伝導率の同じ金属で形成した場合にも、本発明と同様の効果が得られる。
【０１２８】
例えば、図１４や図１６（ｂ）において、１０１ａと１０１ｂに銅を用い、１０１ｃとして銅の千分の一程度の熱伝導率であるアニリン樹脂やエポキシ樹脂あるいはシリコン樹脂（いずれも熱硬化性樹脂）を厚さ１００μｍ形成した場合、正電極１０１ａにおける熱伝導は不電極側の１０１ｂより大きくなるため、正、負電極側での導電性接着剤の固化するタイミングがずれることとなる。この場合、金属と絶縁物の熱伝導率の比は、大きい方が固化のタイミングをずらしやすいため好ましく、１０以上あるのが好ましい。同様に絶縁物の膜厚が厚い方が好ましく、１０〜１５０μｍあるのが好ましい。
【０１２９】
さらに加えて、１０１ａと１０１ｂの大きさを、１０１ａが１０１ｂに比べて十分大きくしてやることで、放熱効果に差を生じさせれば、より大きな効果が得られる。
【０１３０】
本方法は前記熱伝導率の異なる金属を用いる場合にもより効果を高めるために有効である。
【０１３１】
〔実施の形態９〕
図１７は、本発明に密接に関連する参考的な実施の形態９の半導体レーザ装置を示す断面図である。これは、実施の形態５の図８に記載の装置において、サブマウントの表面に溝が形成されている点、及び導電性接着剤が異方導電性樹脂である点が異なる。図において、７０は、本実施の形態の半導体レーザ装置、７００はサブマウント、７０３は実施の形態５のサブマウントの積載面上の金属パターン間に設けられた溝、７０２は異方導電性樹脂であり、その他実施の形態５と同様の部分については図８と同一の符号で示した。
【０１３２】
本実施の形態においては、実施の形態５と同様にサブマウント基体７０１ａには絶縁体であるＡｌＮを用い、サブマウント基体７０１ｂにはＡｌＮより熱伝導率が低い絶縁体であるＡｌ₂Ｏ₃を用い、正側金属パターン１０２および負側金属パターン１０３には、Ａｕ（０．１μｍ）／Ｐｔ（０．１μｍ）／Ｔｉ（０．１μｍ）（Ａｕ オン Ｐｔ オン Ｔｉ、以下同様）、異方導電性接着剤として７０２には異方導電性樹脂を用いた。本実施の形態においては、一例として、サブマウント基体７０１ａと７０１ｂ全体のサイズを、長さ２ｍｍ×幅１．５ｍｍ×高さ０．２ｍｍとし、７０１ｂのみの大きさは長さ２ｍｍ×幅０．７ｍｍ×高さ０．１ｍｍとし、異方導電性樹脂の厚さを１μｍとした。また、溝のサイズは、深さ０．１ｍｍ、幅０．１ｍｍとした。
【０１３３】
ここで、導電性樹脂を異方性とするために、本実施の形態においては、熱硬化性エポキシ樹脂の中に、Ａｇ粒子を数ないし数１０ｗｔ％配合したものを用いた。これにより、異方導電性樹脂は、荷重を加えずに硬化した場合、金属粉が分散するので、絶縁性となり所定の荷重を加えて硬化した場合、金属粉同士が接触するので、導電性となる。樹脂の硬化温度は１８０℃程度とした。
【０１３４】
本実施の形態についても実施の形態５と同様に、半導体レーザチップにおいて、正電極が発光部に隣接する側の電極となり、負電極がその反対側の電極に相当する。また、サブマウントにおいては、正側金属パターンが、正電極に対向する導電膜パターンとなり、負側金属パターンが負電極に対向する導電膜パターンに相当する。
【０１３５】
また、本実施の形態の半導体レーザ装置では、発光部に隣接した電極が正電極である。レーザーチップの温度上昇による特性劣化を押さえるためには発光部に隣接した正電極からの放熱が良好な方がこのましい。そのため、正電極が、熱伝導率の大きい方のサブマウント基体に対応して配置されている方が好ましい。さらに、正電極と負電極とで電気抵抗率が異なる場合はそれによっても各電極での発熱量が異なるため、その点も考慮するのが好ましい。
【０１３６】
次に、本実施の形態の半導体レーザ装置を製造するためのダイボンディング工程を行った。工程の各過程におけるサブマウント積載面温度Ｔの変化（温度プロファイル）を図１８に示す。ここで、Ｔは異方導電性樹脂の温度に一致している。
【０１３７】
あらかじめ、図９に示されたのと同様ではあるが、上記溝が設けられたサブマウントを準備する。
まず、サブマウント電極上に上記異方導電性樹脂を配置する。ただし、この段階で、樹脂は未硬化である。次に図２に示した半導体レーザチップを、適切にアライメントし、レーザチップ電極形成面とサブマウント積載面とが突き合わされるように、サブマウント上に積載し、樹脂が拡がった。このとき、樹脂の粘度等によっては、正電極側と負電極側とが接触しない場合もあるが、本実施の形態では図１７に示されるように、正電極側および負電極側の樹脂が接触し、溝内に入り込んだ例で説明する。
【０１３８】
〈過程Ａ〉レーザチップに３０ｇの荷重を加えつつ、サブマウントの温度を上昇させた。まず、実線で示すように、熱伝導率が高いサブマウント基体７０１ａ上の異方導電性樹脂がｔ１秒で硬化温度Ｔｓ＝１８０℃に達し、硬化する。
〈過程Ｂ〉荷重を加えるのをやめ、加熱を続ける。次に熱伝導率が低いサブマウント基体７０１ｂ上の異方導電性樹脂がｔ２秒で硬化温度Ｔｓに達し、硬化する。この後硬化温度より若干高い温度Ｔｐ＝２００℃で３０秒保持し、硬化反応を完全に進行させた。
〈過程Ｃ〉室温に近い適当な温度まで冷却されたところで、ダイボンディング工程を、終了した。
以上により、本実施の形態の半導体レーザ装置が完成した。
【０１３９】
本実施の形態の半導体レーザ装置は、ハンダに替えて、異方導電性樹脂を用いたので、従来の技術の問題点が実施の形態５の場合と同様、以下の如く解消されている。
【０１４０】
上記過程において熱伝導率の低い材料のサブマウント基体７０１ｂに接する側の異方導電性樹脂が固化する際には、既に、熱伝導率の高い材料のサブマウント基体７０１ａに接する側の異方導電性樹脂が硬化しており、よって、半導体レーザチップは、第１の導電性樹脂の固化に伴って動くことがない。つまり、ハンダ冷却の途中でレーザチップが動き、アライメントずれが発生してしまう従来の技術第１の問題が回避される。
【０１４１】
また、従来の技術において、両ハンダが同時に固化する際の、予測できないそれぞれの接着面に加わる力の偶然の集中によって、ブリッジ状にサブマウントに固定される半導体レーザチップに大きな熱歪みが加わることも無い。結果として、半導体レーザチップに大きな応力・熱歪みが発生してしまう従来の技術における第２の問題点が回避される。
【０１４２】
さらに、半導体レーザチップの正負電極がほぼ同一面上にある場合に限らず、発光層に隣接する側と逆側の電極（負電極）が窪んだ面上に設けられていても良い。特に、本実施の形態では、電極の接続に、導電性樹脂を用いたので、正電極側と負電極側で、異なる硬度の導電性樹脂を用いれば、窪みが大きくても、確実に電気的導通を確保することができるようになる。
【０１４３】
また、特に、本実施の形態の半導体発光素子においては、異方導電性樹脂を用い、サブマウント金属膜パターン間に溝を設けたので、樹脂の溝上の領域には荷重が加わらず絶縁性であり、金属パターン上の領域には荷重が加わり導電性となる。よって、負電極と負側金属パターン間には、電気的な導通が確保されるが、図１７に示される如く、たとえ樹脂が正電極等と接触したとしても、ショートすることがない。よって、ダイボンディング工程における、ショート発生による生産性の低下を防止することができる。
【０１４４】
比較のために、本実施の形態の半導体レーザ装置におけるサブマウント基体７０１ａおよび７０１ｂを同一の材料で構成した、対照半導体レーザ装置を作製した。サブマウントの端面垂直方向から±２°以内にレーザビーム中心がくることをダイボンディング工程の位置ずれに関する良品条件と規定したとき、本実施の形態の半導体レーザ装置においては、良品の得られる率が９８％だったのに対し、対照半導体レーザ装置においては、７５％であった。また、それぞれの半導体レーザ装置に、５ｍＷ、５０℃（初期電流５０ｍＡ程度）の条件での通電試験を１０００時間行ったところ、前者では、駆動電流の上昇がほとんど見られなかったのに対し、後者では、約３０％の装置で駆動電流値の２０％以上の上昇が観察された。このように、従来の技術を用いた半導体レーザ装置と比較して、ダイボンディング工程の生産性の向上と、装置寿命特性の向上が確認された。
【０１４５】
本実施の形態においては、実施の形態５に示した、図８及び９の構造のマウント部材を用いて説明したが、これを、実施の形態６〜８で示した図１３、１４、１６の様な、他のマウント部材と置き換えても同様の効果が得られる。
【０１４６】
以上、実施の形態５ないし９によって、本発明に関連する構成を特定の例を挙げて説明したが、本発明の適用範囲はこれに限られるものではなく、当然ながら、各構成要素をそれぞれ用途を同じくする材料に置換し得るし、他の技術を組み合わせて用いることもできる。
【０１４７】
絶縁性サブマウント基体は、上述の材料以外にも、ダイヤモンド、Ｓｉ、ＳｉＣ、ＢｅＯ等の他の絶縁材料や、さらには、ダイヤモンド／Ｓｉ、ＳｉＯ₂／Ｓｉに代表されるように、それら各絶縁材料の積層構造からなる、他の絶縁性サブマウント基体に置き換えることができる。
導電性サブマウント基体としては、上述の材料以外にも、Ｓｉ、Ｇｅ、ＳｉＣ、ＣｕＷ、Ｍｏ等の材料や、それら各物質の積層構造を用いることができる、
上述の半導体レーザチップは、図２に示した特定の例に限られるものではなく、基板としてＧａＮ、ＳｉＣ、Ｓｉ、、ＳｉＯ₂／サファイア等の他の材料を用いる等の変更が可能であり、また、半導体成長層の材料系として、例えば、ＩｎＧａＡｓＰ系、ＩｎＧａＡｌＰ系、ＡｌＧａＮ系、ＣｄＺｎＳｅ系等の他のもの用いることも可能である。また、半導体レーザチップを、ＬＥＤ、スーパールミネッセンスダイオード等の他の発光素子チップにも置換し得る。
【０１４８】
また、上記実施の形態５ないし９のサブマウントにおいて、各導電性接着剤および各金属パターンの形状を、図９に特定の例で示したが、本発明はこれに限られるものではなく、適宜変更され得るものである。例えば、必ずしも、金属パターンがサブマウントのほぼ全面を覆うように設けられる必要はない。また、サブマウント積載面上に、さらに、ワイヤボンディング用のパッド部を設けることや、ダイボンディング時の位置合わせのための印を設けることは、当業者には、容易に想定し得る事項である。あるいは、いわゆるマルチビームレーザのように、３以上の電極を有する半導体レーザチップを積載した半導体レーザ装置にも、上記原理に基づいて、本発明を応用することは、当業者にとって容易に想定し得る。
【０１４９】
さらに、ハンダ層とサブマウント基体との間には、公知のごとく、種々の膜を介在させることが可能であり、例えば、サブマウントとハンダ間の密着性を向上させるための膜、サブマウントとハンダ間の反応を防止するための膜、さらには、これらの膜の間の密着性を高めたり、酸化を防止するための膜が適宜積層形成させてもよい。上記実施の形態に示した金属パターンに置換し得るものとして、Ａｕ／Ｐｔ／Ｔｉ、Ｐｔ／Ｃｒ、Ａｕ／Ｍｏ、Ａｕ／Ｐｔ／Ｃｒ、Ａｕ／Ｍｏ／Ｔｉ等も用いることが可能である。導電性接着層、絶縁膜、ボンディングパッド、サブマウント基体相互の間にも、同様の目的で、種々の膜を介在させることが想定される。
【０１５０】
またさらに、図８、９、１３、１４、１６に示されたサブマウントの構成によれば、ハンダ５０４とハンダ５０５との間のスペースには、特別の構造は設けられていないが、ここに、ダイボンディング工程時のショートを防止したり、アライメントずれを防止するために、溝・梨地面・樹脂突起・絶縁体突起等の構造物を設けても良い。
【０１５１】
上述の実施の形態５ないし９においては、半導体レーザ素子用サブマウントについて説明したが、本発明の適用は、これに限られるものでなく、発光素子チップのマウント部材全般に適用できる。すなわち、任意のマウント部材において、発光素子チップのダイボンディングされる部分が、上述の各実施の形態と同様の構成であれば、他の発光素子チップ用マウント部材においても上述同様の効果を奏することは、明白である。したがって、発光素子チップを、サブマウントを用いず直接ステム、フレーム、もしくはパッケージに積載する場合においては、このステム、フレームもしくはパッケージに、上記本発明に関連する構成を適用することができる。
【０１５２】
【発明の効果】
本発明によれば、上記構成により、ダイボンディング工程時におけるアライメントずれが防止され、また、ダイボンディング工程により引き起こされる半導体発光素子チップ内部の応力・熱歪みを削減できる。これにより、半導体発光装置のダイボンディング工程歩留まりが改善され、また、寿命特性も向上する。
【図面の簡単な説明】
【図１】本発明の実施の形態１の半導体レーザ装置を示す、模式断面図である。
【図２】本発明の実施の形態１の半導体レーザチップを示す、模式断面図である。
【図３】本発明の実施の形態１のサブマウントを示す、模式図である。
【図４】本発明の実施の形態１のダイボンディング工程における温度プロファイルを示すグラフである。
【図５】本発明の実施の形態２のダイボンディング工程における温度プロファイルを示すグラフである。
【図６】本発明に密接に関連する参考的な実施の形態３の半導体レーザ装置を示す、模式断面図である。
【図７】本発明に密接に関連する参考的な実施の形態４の半導体レーザ装置を示す、模式断面図である。
【図８】本発明に密接に関連する参考的な実施の形態５の半導体レーザ装置（本発明のサブマウントを含む）を示す、模式断面図である。
【図９】本発明に密接に関連する参考的な実施の形態５のサブマウントを示す、模式図である。
【図１０】本発明に密接に関連する参考的な実施の形態５のサブマウントの製造方法を示すフローチャート図である。
【図１１】本発明に密接に関連する参考的な実施の形態５のサブマウントの製造方法を示すフローチャート図である。
【図１２】本発明の実施の形態のダイボンディング工程における温度プロファイルを示すグラフである。
【図１３】本発明に密接に関連する参考的な実施の形態６の半導体レーザ装置を示す、模式図である。
【図１４】本発明の実施の形態７の半導体レーザ装置を示す、模式断面図である。
【図１５】本発明に密接に関連する参考的な実施の形態７のサブマウントの製造方法を示すフローチャート図である。
【図１６】本発明に密接に関連する参考的な実施の形態８の半導体レーザ装置を示す、模式断面図である。
【図１７】本発明に密接に関連する参考的な実施の形態９の半導体レーザ装置を示す、模式断面図である。
【図１８】本発明に密接に関連する参考的なの実施の形態９のダイボンディング工程における温度プロファイルを示すグラフである。
【図１９】従来の技術の半導体レーザ装置を示す模式断面図である。
【符号の説明】
１０、３０、４０、５０、６０、７０ 半導体レーザ装置
１００、３００、４００、５００、６００、７００ サブマウント
１０１、５０１ａ、５０１ｂ、６０１ａ、６０１ｂ、７０１ サブマウント基体
１０２ 正側金属パターン
１０３ 負側金属パターン
１０４ 第１のハンダ
１０５ 第２のハンダ
２００ ＧａＮ系半導体レーザチップ
２０１ サファイア基板
２０２ 半導体成長層
２０３ 正電極
２０４ 負電極
３０１ 導電性樹脂
４０１ 溝
４０２ 異方導電性樹脂
５０４、５０５ ハンダ
６０１ｃ 絶縁体
６０６ フォトレジスト
７０２ 異方導電性樹脂
７０３ 溝[0001]
BACKGROUND OF THE INVENTION
The present invention uses a semiconductor light emitting element chip having a plurality of electrodes on one side. Half Conductor light emitting device Set Manufacturing method To the law Related.
[0002]
[Prior art]
GaN-based semiconductors are attracting attention as materials for realizing light-emitting elements in the ultraviolet or green region, and among them, it is desired to put into practical use a semiconductor laser device that oscillates at a shorter wavelength than before. . A feature of GaN-based semiconductors is that sapphire, which is an insulator, is used for the substrate. Therefore, in a light-emitting element chip using such a semiconductor, both positive and negative electrodes are formed on the epi layer side, unlike before. It is usual. Therefore, the GaN-based semiconductor laser chip is different from the conventional semiconductor laser chip in which only one electrode is formed on the epi layer side in order to perform the junction bonding die bonding with the epi layer side down. Mounting method is required.
[0003]
FIG. 19 shows an example of a semiconductor laser device using such a technique disclosed in Japanese Patent Laid-Open No. 7-235729. In the figure, 1 is a submount substrate, 2 is a metal pattern provided on the submount mounting surface, 3 is solder, 4 is a GaN-based semiconductor laser chip body, and 5 is provided on the GaN-based semiconductor laser chip epilayer side. Positive and negative electrodes. In this example, an insulating submount is used, and a metal film pattern corresponding to the positive and negative electrodes of the semiconductor laser is provided on the upper surface of the submount, and each is joined to the positive and negative electrodes of the semiconductor laser by soldering and junction-down is performed. Die bonding is realized.
[0004]
Here, die bonding is generally the following process. Usually, the solder is provided in advance on the submount. This is heated above the melting point, the laser chip aligned at a predetermined position is pressed against the melted solder, and then the solder is cooled and solidified. As a result, the laser chip and the submount are bonded with good thermal conductivity.
[0005]
[Problems to be solved by the invention]
In a semiconductor laser chip having positive and negative electrodes on one side as shown in the prior art, as shown in FIG. 19, the positive and negative electrodes cannot be soldered and joined to the submount in a bridge shape. . This causes the following problems that could not occur in the conventional semiconductor laser chip in which only one electrode is formed on the epi layer side.
[0006]
In the die bonding process, when the molten solder is cooled, the solidification and alloying of the solder does not necessarily proceed uniformly in each part, so the volume change and surface tension of the solder part vary from region to region. A complex force is applied to the bonding surface. As shown in FIG. 19, in the semiconductor laser device in which the bonding surface is divided on both the positive and negative sides, the balance of the force applied to each bonding surface is lost, so that the laser chip moves during cooling and misalignment occurs. Resulting in. Actually, according to the experimental knowledge of the present inventor, the probability of occurrence of misalignment in the semiconductor laser device shown in FIG. 19 is higher than that in a conventional semiconductor laser in which only one electrode is formed on the epilayer side. About 5 times higher. Such misalignment not only causes a problem in the optical characteristics of the semiconductor laser device, i.e., the laser beam emission direction, but also has a positive / negative electrode formed on one side. It also caused a problem of leakage. This is the first problem in the conventional semiconductor laser device.
[0007]
In addition, since the laser chip is joined to the submount in a bridge shape, there is a structural problem that a large stress is easily applied to the laser chip. In particular, when both the solders are solidified at the same time, a large thermal strain is applied to the semiconductor laser chip depending on the concentration of the force applied to each unpredictable bonding surface as described above. Such stress / strain shortens the life of the semiconductor laser device. This is the second problem in the conventional semiconductor laser device.
[0008]
The object of the present invention is to eliminate the above-mentioned problems in the prior art.
[0009]
[Means for Solving the Problems]
According to the invention, on one side 1st and 2nd The semiconductor light emitting device chip having the electrodes is stacked on a mounting member having a conductive film pattern facing each electrode on the stacking surface by using solder, and the first electrode and the first conductive film pattern are the first. In the method of manufacturing a semiconductor light emitting device in which the second electrode and the second conductive film pattern are connected by a second solder different from the first solder, the first solder previously installed on the mount member And heating the second solder to a temperature higher than the melting point T1 of the first solder and the melting point T2 of the second solder, and holding the first solder and the second solder at a constant temperature between T1 and T2 for a predetermined time. The first solder and the second 2 Solder of Among them, solidifying the solder having a high melting point, holding the solder having a low melting point in a molten state, and cooling the first solder and the second solder to a temperature lower than any of T1 and T2. Thus, the step of solidifying the solder having a low melting point out of the first solder and the second solder is performed in the order described above.
In addition, it is preferable that a space between the first solder and the second solder on the mount member is provided with any one of a groove, a matte surface, a resin protrusion, and an insulator protrusion. The semiconductor light emitting element chip may be a semiconductor laser chip.
[0024]
In this specification, the semiconductor light emitting device represents a semiconductor light emitting element chip such as a semiconductor laser chip or an LED chip stacked on a mount member and integrated.
[0025]
In the present specification, the mount member means a component for directly stacking a semiconductor light emitting element chip. For example, a submount for a semiconductor light emitting element chip or a direct stem or frame without using a submount. Or, when loading on a package, this stem, frame, or package itself.
In this specification, the conductive adhesive includes solder, brazing material, and conductive resin.
Examples of materials known as heat dissipation materials include diamond>cBN>Ag>Cu>SiC>CuW>BeO>AlN>Fe>Mo>Si>Al2O3> GaAs, etc. in descending order of thermal conductivity. is there. (Ref: Baifukan, Ryoichi Ito, Michiharu Nakamura, “Semiconductor Laser” P.232, FIG. 16.19) However, in the present invention, the difference in thermal conductivity is different in order to focus on the difference in thermal conductivity of the heat dissipation material. If a combination is selected, a material other than the above materials may be selected.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
In the following embodiments, the submount substrate serves as a heat radiating portion.
[0027]
[Embodiment 1]
FIG. 1 is a schematic cross-sectional view showing a semiconductor laser device according to Embodiment 1 of the present invention. In the figure, 10 is a semiconductor laser device of the present embodiment, 100 is a submount of the present embodiment, 101 is an insulating submount base, 102 is a positive metal pattern, 103 is a negative metal pattern, and 104 is a first metal pattern. , 105 is a second solder, 200 is a GaN-based semiconductor laser chip, 201 is a sapphire substrate, 202 is a semiconductor growth layer, 203 is a positive electrode, and 204 is a negative electrode. As shown in the figure, the solder and the metal pattern on the submount loading surface are appropriately formed so as to be insulated from each other, thereby enabling the mounting of semiconductor laser elements having positive and negative electrodes on one side. This is the same as the conventional technique.
[0028]
FIG. 2 is a cross-sectional view showing the configuration of the GaN-based semiconductor laser chip 200 in more detail, and the configuration will be described below with reference to this.
[0029]
On the surface of the sapphire substrate 201, a buffer layer 210 made of AlN or GaN, an n-GaN layer 211, an n-AlGaN cladding layer 212, a quantum well active layer 213 made of multi-layer InGaN, and a ridge stripe along the cavity direction of the semiconductor laser A p-AlGaN cladding layer 214 having a shape is sequentially formed. Further, an n-AlGaN current blocking layer 215 is stacked outside the stripe, and a p-GaN cap layer 216 is stacked on the current blocking layer surface and the ridge stripe portion p-AlGaN cladding layer surface. A semiconductor growth layer 202 is constituted by the buffer layer 210 to the cap layer 216. A part of the semiconductor growth layer 202 is provided with a groove extending from the surface to the n-GaN layer in parallel with the ridge stripe, and each p-type growth layer is divided into two. On the surface of the p-GaN cap layer on the side where the ridge stripe exists, a positive electrode 203 is provided, and a negative electrode 204 is provided in contact with the n-GaN layer exposed at the bottom of the groove, which is opposite It extends to the surface of the side p-GaN cap layer. As a result, the positive and negative electrodes are exposed on the growth layer side surface of the semiconductor laser chip. Further, an insulator 205 made of SiO or the like is provided inside the groove, and plays a role of preventing a short circuit in the die bonding process. With the above configuration, the stripe-shaped portion indicated by symbol 206 in FIG. 2 becomes the light emitting portion of the semiconductor laser. In this embodiment, as an example, the size of the laser chip is set to length 0.5 × width 0.6 × height 0.1 mm, and the distance between the electrodes is 50 m. Since such a semiconductor laser chip can be easily configured by a known technique, description of its manufacturing method is omitted.
[0030]
FIG. 3 is a schematic diagram showing the submount of the present embodiment used in the semiconductor laser device of the present embodiment. Each symbol is the same as in FIG. In the present embodiment, AlN that is an insulator is used for the submount base 101, and Au (0.1 m) / Pt (0.1 m) / Ti (0.1 is used for the metal patterns 102 and 103. m) (Au on Pt on Ti, the same shall apply hereinafter), AuSn (Au 80%, Sn 20%) with a melting point T1 of 280 ° C. for the first solder 104, and a melting point T2 of 232 ° C. for the second solder. Some Sn was used. That is, in the present embodiment, the relationship of T1> T2 is established. Each metal pattern and each solder can be formed by appropriately using known techniques such as vacuum deposition, CVD, sputtering, plating, thermal transfer, printing, and sintering. In the present embodiment, as an example, the size of the submount base 101 is length 1.5 × width 2 × height 0.2 mm, the distance between the solders is 50 μm, and the thickness of the solder is 1 μm.
[0031]
With the above configuration, in the present semiconductor laser chip, the positive electrode corresponds to the electrode adjacent to the light emitting portion, and the negative electrode corresponds to the opposite electrode. In this submount, the positive side metal pattern corresponds to the conductive film pattern facing the positive electrode, and the negative side metal pattern corresponds to the conductive film pattern facing the negative electrode.
[0032]
Next, a die bonding process for manufacturing the semiconductor laser device of the present embodiment will be described with reference to FIG. FIG. 4 is a graph (temperature profile) showing changes in the submount loading surface temperature T in each process. Here, T corresponds to the temperature of each solder.
[0033]
<Process A> First, when the submount of the present embodiment shown in FIG. 3 was heated to T = 300 ° C., which is higher than the melting point of the first and second solders, Melted.
<Process B> The semiconductor laser chip shown in FIG. 2 was appropriately aligned and loaded on the submount so that the laser chip electrode formation surface and the submount loading surface were abutted. Here, alignment is performed in the following manner. The positive electrode and the first solder and the positive side metal pattern, and the negative electrode and the second solder and the negative side metal pattern are matched with each other, that is, as shown in FIG. The direction and the position are aligned so that the direction is perpendicular to the end face of the submount, and the light exit surface substantially coincides with the end face of the submount.
Next, a load of about 20 g was applied to the semiconductor laser chip, and the state of T = 300 ° C. was maintained for 30 to 120 seconds, so that the solder, the metal pattern, and the electrode were well blended. (T> T1, T2)
<Process C> T was changed to 250 ° C., which is lower than the melting point of the first solder and higher than the melting point of the second solder, while the load was applied.
<Process D> The state of T = 250 ° C. was maintained for 30 seconds. During this time, the first solder was solidified, and the semiconductor laser chip was fixed to the submount. After the first solder solidified, the load was stopped. (T1>T> T2)
<Process E> The submount was cooled and the second solder was solidified. When the temperature was cooled to an appropriate temperature close to room temperature, the die bonding process was terminated.
Thus, the semiconductor laser device of the present embodiment shown in FIG. 1 was completed.
[0034]
In the semiconductor laser device according to the present embodiment, since the melting point of the first solder is higher than the melting point of the second solder, the problems of the conventional technique are solved as follows.
[0035]
Of the solder melted in the process B, only the first solder 104 adjacent to the light emitting portion is solidified in the process D. At this time, since the second solder is still melted, the force applied to each joint surface caused by both the solders trying to solidify at the same time, which has been a problem in the prior art, is uncertain. There is no balance. Thus, the semiconductor laser chip is fixed without moving as the first solder is solidified. Therefore, after that, the chip does not shift when the second solder is solidified, and as a result, the laser chip moves during the solder cooling, resulting in the first problem of the conventional technique that misalignment occurs. Avoided. In addition, in the conventional technology, a large thermal strain is applied to the semiconductor laser chip fixed to the submount due to accidental concentration of unpredictable forces on the bonding surfaces when both solders are solidified simultaneously. There is nothing. Further, the distortion caused to the chip is alleviated after the first solder side is first fixed and before the second solder side is fixed. As a result, the second problem in the prior art that causes a large stress / thermal distortion in the semiconductor laser chip is avoided.
[0036]
In the method for manufacturing the semiconductor light emitting device of the present embodiment, the temperature T in the process B is set to a temperature slightly higher than the melting point of the first solder. This is for joining the positive electrode and the positive side metal pattern under the optimum conditions, so that the alloying between them and the solder proceeds properly, and the solder is interposed too thickly. Therefore, it is possible to perform bonding with a minimum thermal resistance. On the other hand, since solder having a lower melting point is used for joining on the negative electrode side, the temperature T in the process B is not necessarily appropriate as the melting temperature of the second solder. Compared with the case of the die bonding process using an appropriate processing temperature of solder No. 2, the optimum value as the thermal resistance of the bonding cannot be obtained. However, in the semiconductor laser device of the present embodiment, since the electrode adjacent to the light emitting portion is a positive electrode, the thermal resistance on the negative electrode side hardly affects the thermal resistance of the semiconductor laser device. As a result, the semiconductor laser The thermal resistance of the device is optimized, which contributes to improving temperature characteristics.
[0037]
For comparison, a control semiconductor laser device was fabricated in which the second solder in the semiconductor laser device of the present embodiment was made of the same material as the first solder. In the semiconductor laser device of this embodiment, when the laser beam center within ± 2 ° from the vertical direction of the end face of the submount is defined as a non-defective condition regarding the positional deviation in the die bonding process, the yield of non-defective products is While it was 96%, it was 78% in the target semiconductor laser device. Further, when each semiconductor laser device was subjected to an energization test under the conditions of 3 mW and 70 ° C. (initial current of about 90 mA) for 1000 hours, the former showed almost no increase in driving current, whereas the latter In about 40% of the devices, an increase of 20% or more in the drive current value was observed. As described above, it was confirmed that the productivity of the die bonding process and the improvement of the device life characteristics were improved as compared with the semiconductor laser device using the conventional technique.
[0038]
In addition, according to the submount of the present embodiment, the productivity of the semiconductor laser device can be improved and the device life characteristics can be improved as compared with the conventional one.
[0039]
[Embodiment 2]
The configuration of the present embodiment is the same as that of the first embodiment except that the materials of the first solder and the second solder are different.
[0040]
In the semiconductor laser device of this embodiment and the submount of this embodiment used therefor, the first solder has a melting point T1 of 156 ° C. In and the second solder has a melting point T2 of 217. SnAu (Sn 90%, Au 10%) at a temperature of 0 ° C. was used. That is, in the present embodiment, there is a relationship of T1 <T2.
[0041]
Also in the present embodiment, as in the first embodiment, in the semiconductor laser chip, the positive electrode corresponds to the electrode adjacent to the light emitting portion, and the negative electrode corresponds to the opposite electrode. In the submount, the positive side metal pattern corresponds to the conductive film pattern facing the positive electrode, and the negative side metal pattern corresponds to the conductive film pattern facing the negative electrode.
[0042]
Next, a die bonding process for manufacturing the semiconductor laser device of the present embodiment will be described with reference to FIG. FIG. 5 is a graph showing changes in the submount loading surface temperature T in each process of the die bonding process. Here, T substantially matches the temperature of each solder.
[0043]
<Process A> First, when the submount of the present embodiment was heated to T = 250 ° C., which is higher than the melting point of the first and second solders, both the solders melted.
<Process B> The semiconductor laser chip shown in FIG. 2 was appropriately aligned and loaded on the submount so that the laser chip electrode formation surface and the submount loading surface were abutted. Here, alignment is performed in the following manner. The positive electrode and the first solder and the positive side metal pattern, the negative electrode and the second solder and the negative side metal pattern are respectively coincided, that is, as shown in FIG. The stripe direction of the chip is perpendicular to the end face of the submount, and the direction and alignment are made so that the light exit surface substantially coincides with the end face of the submount.
Next, a load of about 30 g was applied to the semiconductor laser chip, and the state of T = 250 ° C. was maintained for 30 seconds, so that the solder, the metal pattern, and the electrode were well blended. (T> T1, T2)
<Process C> T was changed to 190 ° C., which is higher than the melting point of the first solder and lower than the melting point of the second solder, while the load was applied.
<Process D> The state of T = 190 ° C. was maintained for 30 seconds. During this time, the second solder was solidified, and the semiconductor laser chip was fixed to the submount. After the second solder solidified, the load was stopped. (T1 <T <T2)
<Process E> The submount was cooled and the first solder was also solidified. When the temperature was cooled to an appropriate temperature close to room temperature, the die bonding process was terminated.
Thus, the semiconductor laser device of the present embodiment has been completed.
[0044]
In the semiconductor laser device of the present embodiment, since the melting point of the first solder is lower than the melting point of the second solder, the problems of the prior art are solved as follows.
[0045]
Of the solder melted in the process B, only the second solder adjacent to the light emitting portion is solidified in the process D. At this time, since the first solder is still melted, an unbalance of the force applied to each joint surface caused by both the solders trying to solidify at the same time, which has been a problem in the prior art. Does not occur. In this process, the semiconductor laser chip is fixed without moving as the second solder is solidified. Therefore, after that, when the first solder is solidified, the chip is not displaced, and as a result, the laser chip moves during the solder cooling, resulting in the first problem of the conventional technique that misalignment occurs. Avoided.
[0046]
In addition, in the conventional technology, a large thermal strain is applied to the semiconductor laser chip fixed to the submount due to accidental concentration of unpredictable forces on the bonding surfaces when both solders are solidified simultaneously. There is nothing. Further, the distortion caused to the chip is alleviated after the second solder side is first fixed and before the first solder side is fixed. As a result, the second problem in the prior art that causes a large stress / thermal distortion in the semiconductor laser chip is avoided.
[0047]
In the method for manufacturing a semiconductor light emitting device of this embodiment, the electrode on the side adjacent to the light emitting portion of the semiconductor laser chip, that is, the positive electrode is fixed only in the final process E of the die bonding process. Therefore, since the distortion caused in the light emitting portion during the die bonding process can be relaxed to the final process stage, the stress / thermal strain in the light emitting portion of the semiconductor laser device that has undergone this die bonding step is the same as that of the first embodiment. Smaller than that. Therefore, according to the present embodiment, the life characteristics of the semiconductor laser device can be further improved.
[0048]
For comparison, a control semiconductor laser device was fabricated in which the second solder in the semiconductor laser device of the present embodiment was made of the same material as the first solder. In the semiconductor laser device of this embodiment, when the laser beam center within ± 2 ° from the vertical direction of the end face of the submount is defined as a non-defective condition regarding the positional deviation in the die bonding process, the yield of non-defective products is While it was 98%, it was 75% in the target semiconductor laser device. Further, when each semiconductor laser device was subjected to an energization test under conditions of 5 mW and 60 ° C. (initial current of about 80 mA) for 1000 hours, the former showed almost no increase in driving current, whereas the latter In about 70% of the devices, an increase of 20% or more in the drive current value was observed. As described above, it was confirmed that the productivity of the die bonding process and the improvement of the device life characteristics were improved as compared with the semiconductor laser device using the conventional technique.
[0049]
In addition, according to the submount of the present embodiment, the productivity of the semiconductor laser device can be improved and the device life characteristics can be improved as compared with the conventional one.
[0050]
Each of the above-described solders in the first and second embodiments can be replaced with other solders such as In, Sn, Pb, InAl, SnAg, PbIn, PbSn, AuSn, AuSi, and AuGe, and a metallic brazing material. At this time, it is necessary to select positive and negative solders while paying attention to the melting point. Table 1 shows melting points of typical electronic industry solders. Thus, even if only shown in this table, the melting point of the solder ranges from 150 ° C. to 400 ° C., so it is clear that each embodiment can easily obtain a combination of solders having different melting points. is there.
[0051]
[Table 1]

[0052]
Also, each Embodiment The temperature profile in FIG. 4 has been described with reference to FIG. 4 or FIG. 5, but this shows an ideal temperature change. In practice, it is necessary to maintain a strictly constant temperature in the processes B and D. It may be a profile that gradually changes in temperature in each process.
[0053]
[Embodiment 3]
FIG. Reference information closely related to the present invention FIG. 6 is a cross-sectional view showing a semiconductor laser device according to a third embodiment. In the figure, 30 is the semiconductor laser device of the present embodiment, 300 is a submount, 301 is a conductive resin, and other parts similar to those of the first embodiment are denoted by the same reference numerals as in FIG. The configuration of the semiconductor laser device of the present embodiment is substantially the same as that of the second embodiment except that the second solder in the second embodiment is replaced with a conductive resin.
[0054]
Here, the conductive resin is a resin in which a predetermined amount of metal powder or the like is mixed in any one of a thermoplastic resin, a thermosetting resin, or a mixture thereof, and has both adhesiveness and conductivity. Is. In the semiconductor laser device of the present embodiment, the conductive resin adhesive 301 is a mixture of 50 to 90 wt% of Ag particles in a thermosetting epoxy resin. Thereby, the conductive resin has conductivity similar to that of metal. A resin having a curing temperature of about 180 ° C. was used. Further, In having a melting point of 156 ° C. was used for the first solder.
[0055]
Also in the present embodiment, as in the second embodiment, in the semiconductor laser chip, the positive electrode corresponds to the electrode adjacent to the light emitting portion, and the negative electrode corresponds to the opposite electrode. In the submount, the positive side metal pattern corresponds to the conductive film pattern facing the positive electrode, and the negative side metal pattern corresponds to the conductive film pattern facing the negative electrode.
[0056]
Next, a die bonding process for manufacturing the semiconductor laser device of the present embodiment will be described.
[0057]
A submount similar to that shown in FIG. 3 is prepared in advance. However, the conductive resin is provided on the negative electrode pattern instead of the second solder. At this stage, the resin is uncured.
[0058]
Next, after the temperature of the submount is raised and the solder is melted, the semiconductor laser chip shown in FIG. 2 is properly aligned so that the laser chip electrode formation surface and the submount loading surface are abutted. Loaded on the submount.
[0059]
After that, while applying a load of 30 g to the laser chip, the state of 180 ° C., which is a temperature higher than the melting point of the solder, was maintained for 1 minute, and the solder, the metal pattern and the electrode were well blended, and the resin was cured. .
[0060]
Then, after the solder was solidified and cooled to an appropriate temperature close to room temperature, the die bonding process was completed.
Thus, the semiconductor laser device of the present embodiment has been completed.
[0061]
Since the semiconductor laser device of the present embodiment uses a conductive resin instead of the second solder, the problems of the prior art are solved as follows.
[0062]
When the solder melted in the above process is solidified, the conductive resin is already cured, and therefore the semiconductor laser chip does not move as the first solder is solidified. That is, the first problem of the prior art in which the laser chip moves during the solder cooling and the misalignment occurs is avoided.
[0063]
Also, in the conventional technology, when both solders are solidified at the same time, a large thermal strain is applied to the semiconductor laser chip fixed to the submount due to accidental concentration of the force applied to each bonding surface which cannot be predicted. There is no. As a result, the second problem in the prior art that causes a large stress / thermal distortion in the semiconductor laser chip is avoided.
[0064]
Further, in the method for manufacturing the semiconductor light emitting device of the present embodiment, the electrode on the side adjacent to the light emitting portion of the semiconductor laser chip is bonded to the submount with solder as in the prior art, and the thermal resistance of the semiconductor laser device is It is equivalent to the conventional one. Contrary to the present embodiment, when the electrode on the side adjacent to the light emitting portion is connected with a conductive resin, the thermal resistance increases and the temperature characteristics of the semiconductor light emitting device deteriorate.
[0065]
For comparison, a reference semiconductor laser device using the same material as the first solder was produced instead of the conductive resin in the semiconductor laser device of the present embodiment. In the semiconductor laser device of this embodiment, when the laser beam center within ± 2 ° from the vertical direction of the end face of the submount is defined as a non-defective condition regarding the positional deviation in the die bonding process, the yield of non-defective products is While it was 98%, it was 75% in the target semiconductor laser device. Further, when each semiconductor laser device was subjected to an energization test under conditions of 3 mW and 50 ° C. (about 50 mA initial current) for 1000 hours, the former showed almost no increase in driving current, whereas the latter In about 30% of the devices, an increase of 20% or more in the drive current value was observed.
[0066]
Further, as shown in FIG. 2, not only when the positive and negative electrodes of the semiconductor laser chip are substantially on the same plane, but as shown in FIG. 19, an electrode (negative electrode) opposite to the side adjacent to the light emitting layer is used. ) May be provided on the recessed surface. In particular, as in this embodiment, a conductive resin is used to connect the electrode on the side opposite to the side adjacent to the light-emitting layer. It becomes possible to ensure the electrical continuity.
[0067]
As described above, when the submount of the present embodiment is used, the productivity of the semiconductor laser device is improved as compared with the conventional technique. Furthermore, the long-term reliability of the semiconductor laser device has also been improved.
[0068]
[Embodiment 4]
FIG. Reference information closely related to the present invention Embodiment 4 It is sectional drawing which shows this semiconductor laser apparatus. In the figure, 40 is a semiconductor laser device of the present embodiment, 400 is a submount, 401 is a groove provided between metal patterns on the submount mounting surface, 402 is an anisotropic conductive resin, and other implementations. Portions similar to those in Embodiment 1 are denoted by the same reference numerals as in FIG. The configuration of the semiconductor laser device of the present embodiment is the same as that of the third embodiment except that the conductive resin in the third embodiment is an anisotropic conductive resin. The size of the groove was 0.2 mm deep and 0.1 mm wide.
[0069]
Here, in order to make the conductive resin anisotropic, in the present embodiment, a thermosetting epoxy resin containing several to several tens wt% of Ag particles is used. As a result, when anisotropically conductive resin is cured without applying a load, the metal powder is dispersed, so that it becomes insulative, and when cured with a predetermined load, the metal powder comes into contact with each other. It becomes. The curing temperature of the resin was about 180 ° C. Further, In having a melting point of 156 ° C. was used for the first solder.
[0070]
Also in the present embodiment, as in the first embodiment, in the semiconductor laser chip, the positive electrode corresponds to the electrode adjacent to the light emitting portion, and the negative electrode corresponds to the opposite electrode. In the submount, the positive side metal pattern corresponds to the conductive film pattern facing the positive electrode, and the negative side metal pattern corresponds to the conductive film pattern facing the negative electrode.
[0071]
Next, a die bonding process for manufacturing the semiconductor laser device of the present embodiment will be described.
[0072]
In advance, a submount provided with the groove is prepared in the same manner as shown in FIG. Further, the anisotropic conductive resin is provided on the negative electrode pattern in place of the second solder. However, at this stage, the resin is uncured.
[0073]
Next, after the temperature of the submount is raised and the solder is melted, the semiconductor laser chip shown in FIG. 2 is properly aligned so that the laser chip electrode formation surface and the submount loading surface are abutted. Loaded on the submount. At this time, the resin spread and contacted the positive-side solder or the like as shown in FIG.
[0074]
After that, while applying a load of 30 g to the laser chip, the state of 180 ° C., which is a temperature higher than the melting point of the solder, was maintained for 1 minute, and the solder, the metal pattern and the electrode were well blended, and the resin was cured. .
[0075]
Then, after the solder was solidified and cooled to an appropriate temperature close to room temperature, the die bonding process was completed.
Thus, the semiconductor laser device of the present embodiment has been completed.
[0076]
Since the semiconductor laser device of the present embodiment uses a conductive resin instead of the second solder, the problems of the prior art are solved as in the case of the third embodiment as follows.
[0077]
When the solder melted in the above process is solidified, the conductive resin is already cured, and therefore the semiconductor laser chip does not move as the first solder is solidified. That is, the first problem of the prior art in which the laser chip moves during the solder cooling and the misalignment occurs is avoided.
[0078]
Also, in the conventional technology, when both solders are solidified at the same time, a large thermal strain is applied to the semiconductor laser chip fixed to the submount due to accidental concentration of the force applied to each bonding surface which cannot be predicted. There is no. As a result, the second problem in the prior art that causes a large stress / thermal distortion in the semiconductor laser chip is avoided.
[0079]
Further, in the method for manufacturing the semiconductor light emitting device of the present embodiment, the electrode on the side adjacent to the light emitting portion of the semiconductor laser chip is bonded to the submount with solder as in the prior art, and the thermal resistance of the semiconductor laser device is It is equivalent to the conventional one.
[0080]
For comparison, a control semiconductor laser device was fabricated in which the second solder in the semiconductor laser device of the present embodiment was made of the same material as the first solder. In the semiconductor laser device of this embodiment, when the laser beam center within ± 2 ° from the vertical direction of the end face of the submount is defined as a non-defective condition regarding the positional deviation in the die bonding process, the yield of non-defective products is While it was 98%, it was 75% in the target semiconductor laser device. Further, when each semiconductor laser device was subjected to an energization test under conditions of 3 mW and 50 ° C. (about 50 mA initial current) for 1000 hours, the former showed almost no increase in driving current, whereas the latter In about 30% of the devices, an increase of 20% or more in the drive current value was observed.
[0081]
As described above, when the submount of the present embodiment is used, the productivity of the semiconductor laser device is improved as compared with the conventional technique. Furthermore, the long-term reliability of the semiconductor laser device has also been improved.
[0082]
Further, as shown in FIG. 2, not only when the positive and negative electrodes of the semiconductor laser chip are substantially on the same plane, but as shown in FIG. 19, an electrode (negative electrode) opposite to the side adjacent to the light emitting layer is used. ) May be provided on the recessed surface. In particular, as in this embodiment, a conductive resin is used to connect the electrode on the side opposite to the side adjacent to the light-emitting layer. It becomes possible to ensure the electrical continuity.
[0083]
In particular, in the semiconductor light emitting device of the present embodiment, an anisotropic conductive resin is used, and a groove is provided between the submount metal film patterns. A load is applied to the region on the metal pattern to make it conductive. Therefore, electrical conduction such as electrical conductivity is ensured between the negative electrode and the negative metal pattern, but as shown in FIG. 7, even if the resin contacts the positive electrode or the like, there is no short circuit. Therefore, it is possible to prevent a decrease in productivity due to occurrence of a short in the die bonding process.
[0084]
As described above, the present invention is connected with Although the configuration has been described with a specific example, the scope of the present invention is not limited to this, and it is a matter of course that each component can be replaced with a material having the same application, and other technologies are combined. Can also be used.
[0085]
The above-mentioned insulating submount substrate is composed of other insulating materials such as diamond, Si, SiC, cBN, BeO, AlO, and further, as represented by diamond / Si, SiO / Si. It can be replaced with another insulating submount substrate having a laminated structure.
[0086]
In addition, the submount substrate does not necessarily have to be insulative, and the conductive submount substrate can be used after devising to insulate between the positive and negative electrodes. As the conductive submount substrate, materials such as Si, Ge, SiC, Cu, CuW, and Mo, and laminated structures of these substances can be used.
The above-mentioned semiconductor laser chip is not limited to the specific example shown in FIG. 2, but can be changed such as using other materials such as GaN, SiC, Si, SiO / sapphire as a substrate, As the material system of the semiconductor growth layer, other materials such as an InGaAsP system, an InGaAlP system, an AlGaN system, and a CdZnSe system can be used. In addition, the semiconductor laser chip can be replaced with another light emitting element chip such as an LED or a super luminescence diode.
[0087]
Further, in the submount of the above embodiment, the shape of each solder and each metal pattern is shown as a specific example in FIG. 3, but the present invention is not limited to this, and can be appropriately changed. . For example, the metal pattern is not necessarily provided so as to cover almost the entire surface of the submount. Further, it is easy for those skilled in the art to provide a wire bonding pad portion and a mark for alignment during die bonding on the submount stacking surface. . Alternatively, it is easily conceivable for those skilled in the art to apply the present invention to a semiconductor laser device loaded with a semiconductor laser chip having three or more electrodes, such as a so-called multi-beam laser, based on the above principle. .
[0088]
Further, as is well known, various films can be interposed between the solder layer and the submount base. For example, a film for improving the adhesion between the submount and the solder, the submount, and the like. A film for preventing a reaction between solders, and a film for improving adhesion between these films or preventing oxidation may be appropriately laminated. Pt / Cr, Au / Mo, Au / Pt / Cr, Au / Mo / Ti, or the like can be used as the metal pattern Au / Pt / Ti described in the above embodiment. It is assumed that various films are interposed between the solder, the insulating film, the bonding pad, and the submount substrate for the same purpose.
[0089]
Furthermore, according to the submount configuration shown in FIGS. 1, 3, and 6, no special structure is provided in the space between the first solder and the second solder. In order to prevent a short circuit during the bonding process or to prevent misalignment, a structure such as a groove, a matte surface, a resin protrusion, or an insulator protrusion may be provided.
[0090]
In each of the above-described embodiments, the semiconductor laser element submount has been described. However, the application of the present invention is not limited to this, and the present invention can be applied to all light emitting element chip mounting members. That is, in any mounting member, if the portion to be die-bonded of the light-emitting element chip has the same configuration as that of each of the above-described embodiments, the same effects as described above can be obtained in other light-emitting element chip mounting members. Is obvious. Therefore, when the light emitting element chip is directly mounted on the stem, the frame, or the package without using the submount, the above-described present invention is attached to the stem, the frame, or the package. is connected with Configuration can be applied.
[0091]
[Embodiment 5]
Figure 8 is the present invention Closely related to the reference FIG. 10 is a schematic cross-sectional view showing a semiconductor laser device according to a fifth embodiment. In FIG. 8, 50 is the semiconductor laser device of the present embodiment, 500 is the submount of the present embodiment, 501a and 501b are submount bases formed of an insulator, 102 is a positive metal pattern, and 103 is a negative side. A metal pattern 504 and 505 uses solder as a conductive adhesive. Here, 501a and 501b are formed of insulator materials having different thermal conductivities. As shown in the figure, the solder and the metal pattern on the submount loading surface are appropriately formed so as to be insulated from each other, thereby enabling the mounting of semiconductor laser elements having positive and negative electrodes on one side. This is the same as the conventional technique. Implementation Form of Then, although the submount base 501a is L-shaped in the cross-sectional view, it may be dug so as to form a U-shape in the cross-sectional view, and 501b may be embedded therein.
[0092]
FIG. 9 is a schematic diagram showing the submount of the present embodiment used in the semiconductor laser device of the present embodiment. Each symbol is the same as in FIG. In this embodiment, AlN that is an insulator is used for the submount base 501a, and Al that is an insulator having a lower thermal conductivity than AlN is used for the submount base 501b. ₂ O _Three In the positive side metal pattern 102 and the negative side metal pattern 103, Au (0.1 μm) / Pt (0.1 μm) / Ti (0.1 μm) (Au on Pt on Ti, the same applies hereinafter), solder 504 For Sn and 505, SnAu (Sn 90%, Au 10%) solder having a melting point of 217 ° C. was used. As an example of the method for producing the submount substrate, as shown in FIG. 10A, the submount substrate 501a is first stepped by using an etching means such as dry etching or wet etching, or a means for physically grinding. After forming, as shown in FIG. 10 (b), 501b is formed as appropriate using known techniques such as vacuum deposition, CVD, sputtering, thermal transfer, printing, sintering, coating, etc. As shown in FIG. 10C, it is formed by flattening by polishing. Then, as shown in FIG. 10 (d), the positive side metal pattern 102 and the negative side metal pattern 103 are applied to a known technique such as a vacuum deposition method, a CVD method, a sputtering method, a thermal transfer method, a printing method, a sintering method, a coating method, or the like. As appropriate, a film is formed. In the present embodiment, as an example, the total size of the submount bases 501a and 501b is 2 mm in length, 1.5 mm in width, 0.2 mm in height, and the size of only 501b is 2 mm in length. The width was 0.7 mm × height was 0.1 mm, the distance between the solders was 50 μm, and the thickness of the solder was 1 μm.
[0093]
With the above configuration, in the present semiconductor laser chip, the positive electrode corresponds to the electrode adjacent to the light emitting portion, and the negative electrode corresponds to the opposite electrode. In this submount, the positive side metal pattern corresponds to the conductive film pattern facing the positive electrode, and the negative side metal pattern corresponds to the conductive film pattern facing the negative electrode.
Further, since 501a and 501b serve as heat radiating portions, the thickness is preferably 20 μm or more in order to increase the heat radiation efficiency.
[0094]
Next, a die bonding process for manufacturing the semiconductor laser device of the present embodiment will be described. FIG. 11 is a graph (temperature profile) showing changes in the submount loading surface temperature T in each step of the process. Here, T corresponds to the temperature of each solder.
<Process A> First, when the submount of the present embodiment shown in FIG. 9 was heated to Tp = 250 ° C., which is higher than the melting point of solder (Tm = 217 ° C.), both solders were Melted.
<Process B> The GaN-based semiconductor laser chip 200 shown in FIG. 2 was appropriately aligned and loaded on the submount so that the laser chip electrode formation surface and the submount loading surface were abutted. Here, alignment is performed in the following manner. The positive electrode 203, the solder 504, and the positive metal pattern 102, and the negative electrode 204, the solder 505, and the negative metal pattern 103 are aligned with each other, that is, as shown in FIG. The direction and the position are aligned so that the direction is perpendicular to the end face of the submount, and the light exit surface substantially coincides with the end face of the submount.
Next, a load of about 20 g was applied to the semiconductor laser chip, and the state of Tp = 250 ° C. was maintained for 30 seconds, so that the solder, the metal pattern, and the electrode were well blended.
<Process C> Heating was stopped while the load was applied. Then, as shown by the solid line in the figure, the solder 504 facing the submount base 501a having a high thermal conductivity is quickly cooled, and decreases to the melting point Tm in t1 seconds and solidifies. Here, the load was stopped. Thereafter, as indicated by a broken line in the figure, the solder 505 facing the submount substrate having a low thermal conductivity is lowered to the melting point Tm and solidified at t2 seconds. When the temperature was cooled to an appropriate temperature close to room temperature, the die bonding process was terminated.
Thus, the semiconductor laser device of this embodiment shown in FIG. 8 was completed.
[0095]
The semiconductor laser device of this embodiment uses submount bases with different thermal conductivities and varies the solder hardening speed between the positive electrode side and the negative electrode side, so that the force applied to each bonding surface during solidification Since the force applied to the bonding surface is dispersed while maintaining the balance of the above, the problems of the conventional techniques are solved as follows.
[0096]
Of the solder melted in the process B, only the solder 504 adjacent to the light emitting portion is solidified in t1 seconds. At this time, since the solder 505 is still melted, there is an unbalance of the force applied to each joint surface as both the solders try to solidify at the same time, which is a problem in the conventional technique. Does not occur. Thereby, the semiconductor laser chip is fixed without moving as the solder 504 is solidified. Therefore, after that, the chip is not displaced when the solder 505 is solidified. As a result, the first problem of the conventional technique in which the laser chip moves during the solder cooling and the misalignment occurs is avoided. The
[0097]
In addition, in the conventional technology, a large thermal strain is applied to the semiconductor laser chip fixed to the submount due to accidental concentration of unpredictable forces on the bonding surfaces when both solders are solidified simultaneously. There is nothing. Furthermore, the distortion caused to the chip is reduced after the solder 504 side is fixed first and before the solder 505 side is fixed. As a result, the second problem in the prior art that causes a large stress / thermal distortion in the semiconductor laser chip is avoided.
[0098]
In the method for manufacturing the semiconductor light emitting device of the present embodiment, the temperature T in the process B is set to a temperature slightly higher than the melting points of the solders 504 and 505. This is for joining the electrode and the metal pattern under optimum conditions, and as a result, alloying between them and the solder proceeds appropriately, and the solder may be too thick to be interposed. Therefore, it is possible to join with a minimum thermal resistance.
[0099]
In the semiconductor laser device of the present embodiment, the electrode adjacent to the light emitting part is a positive electrode. In order to suppress the deterioration of characteristics due to the temperature rise of the laser chip, it is preferable that the heat radiation from the positive electrode adjacent to the light emitting part is good. For this reason, it is preferable that the solder 504 in contact with the positive electrode is disposed on the submount substrate having the higher thermal conductivity. Furthermore, when the electrical resistivity is different between the positive electrode and the negative electrode, the amount of heat generated at each electrode is also different, which is preferably taken into consideration.
[0100]
For comparison, a control semiconductor laser was fabricated in which the submount bases 501a and 501b were made of the same material in the semiconductor laser device of the present embodiment. In the semiconductor laser device of the present embodiment, when it is defined as a non-defective condition regarding the positional deviation in the die bonding process that the center of the laser beam comes within + -2 ° from the direction perpendicular to the end face of the submount. The yield of good products was 98%, compared with 78% for the control semiconductor laser. Further, when each semiconductor laser device was subjected to an energization test under the conditions of 3 mW and 70 ° C. (initial current of about 90 mA) for 1000 hours, the former showed almost no increase in driving current, whereas the latter In about 40% of the devices, an increase of 20% or more in the drive current value was observed. As described above, it was confirmed that the productivity of the die bonding process and the improvement of the device life characteristics were improved as compared with the semiconductor laser device using the conventional technique.
In addition, according to the submount of the present embodiment, the productivity of the semiconductor laser device can be improved and the device life characteristics can be improved as compared with the conventional one.
[0101]
In the present embodiment, both the submount bases 501a and 501b are insulators. However, it is needless to say that a combination of an insulator and a conductor may be used as long as it is a combination of materials having different thermal conductivities. . For example, as shown in FIG. 12 (a), a submount substrate 501a formed of metal is formed halfway, and then a vacuum deposition method, a CVD method, a sputtering method, a thermal transfer method, a printing method, a sintering method, and a coating method are used. A submount substrate 501b formed of an insulating film is formed by appropriately using a known technique such as the above, and as shown in FIG. 12B, etching means such as dry etching or wet etching, or physical grinding is performed. Steps are formed by appropriately using known techniques such as means, and as shown in FIG. 12 (c), the submount base 501a is embedded in the stepped portion by a plating method, and electrodes as shown in FIG. 12 (d). It can also be formed by forming.
[0102]
In the case of using a conductor, it is also possible to serve as a metal pattern. Furthermore, not only from the side of the mounting member facing the laser chip, but also from the side and back, directly to the stem, package, external lead, etc. Connection is possible, leading to increased heat dissipation efficiency and simplification of the entire system.
In the present embodiment, the same solder is used for 504 and 505, but it goes without saying that different solder may be used as long as the 504 side is designed to solidify first.
In the present embodiment, the conductive adhesive is directly formed on the heat radiating portion. However, an insulating layer may be formed between them as long as the conductivity is maintained.
[0103]
[Embodiment 6]
According to a reference embodiment 6 closely related to the present invention, Variation of Embodiment 5 In addition to the submount substrate of the fifth embodiment, a submount substrate having a shape as shown in FIGS. 13A and 13B in which materials having different thermal conductivities are combined. Even if it is used, the same effect can be obtained.
[0104]
For example, the submount substrate shown in FIG. 13A is formed by joining two kinds of materials of a cube or a rectangular parallelepiped having different thermal conductivity on one surface. In this case, since the surface area of 501b can be increased as compared with FIG. 8, heat can be effectively dissipated. Two types of materials may be bonded with an adhesive, or a known technique such as a vacuum deposition method, a CVD method, a sputtering method, a plating method, a thermal transfer method, a printing method, or a sintering method on one material. You may deposit using. In this embodiment, as an example, Cu, which is a conductor, is used for the submount base 501a, and Al, which is an insulator having a lower thermal conductivity than Cu, is used for the submount base 501b. ₂ O _Three The positive side metal pattern 103 and the negative side metal pattern 103 are Au (0.1 μm) / Pt (0.1 μm) / Ti (0.1 μm), and the solder 504 and 505 as the conductive adhesive have a melting point. In solder at 156 ° C. was used. In the present embodiment, as an example, the submount bases 501a and 501b have a length of 2 mm, a width of 1 mm, and a thickness of 0.2 mm, and are bonded with an adhesive.
[0105]
Further, the submount substrate of FIG. 13B is a case where 501b covers the back surface of 501a. In this case, since the surface area of 501b can be increased compared to FIG. 8, heat can be effectively dissipated. This can be done by bonding two materials with different thermal conductivities with an adhesive, or vacuum deposition, CVD, sputtering, plating, thermal transfer, printing, sintering on one of the materials. You may deposit using well-known techniques, such as a method. As an example in the present embodiment, cBN that is an insulator is used for the submount base 501a, Fe that is a conductor having lower thermal conductivity than cBN is used for the submount base 501b, and the positive-side metal pattern 102 and the negative metal pattern 102 are negative. Au (0.1 μm) / Pt (0.1 μm) / Ti (0.1 μm) was used for the side metal pattern 103, and In solder with a melting point of 156 ° C. was used for the solders 504 and 505 as the conductive adhesive. . In the present embodiment, as an example, the submount base 501a is a recess having a length of 2 mm, a width of 1.5 mm, a thickness of 0.2 mm, a length of 2 mm, a width of 0.7 mm, and a thickness of 0.1 mm. 501b shall be covered with a thickness of 0.1 mm from the concave portion on 501a to the back surface. The recesses on 501a were formed by using known techniques such as etching means such as dry etching and wet etching, and physically grinding means, and the surface was subjected to a conductive treatment (silver paste application, etc.) from the recesses to the back surface. Thereafter, 501b is formed by Fe plating.
[0106]
13A and 13B, as in the fifth embodiment, the submount bases 501a and 501b may be insulators having different thermal conductivities, or the thermal conductivities. Needless to say, a combination of an insulator and a conductor may be used as long as the materials are different from each other.
Further, since 501a and 501b serve as heat radiating portions, the thickness is preferably 20 μm or more in order to increase the heat radiation efficiency.
In addition, when a conductor is used for the submount base, it can also serve as a metal pattern. Furthermore, not only from the side of the mount member facing the laser chip, but also from the side and back, the stem, package, and external Direct connection to leads is possible, leading to higher heat dissipation efficiency and simplification of the entire system.
[0107]
In the submounts shown in the fifth and second embodiments, as shown in FIGS. 8 and 13, since the surface of the submount base is substantially flat, the positive and negative electrodes of the facing laser chip are almost the same. Although it can be easily die-bonded when it is on a flat surface, if there is a difference in height between the positive and negative electrodes of the laser chip facing each other, it can be arbitrarily adjusted by the thickness of 501a or 501b.
[0108]
[Embodiment 7]
Reference information closely related to the present invention Embodiment 7 The configuration of is the same as in the fifth and sixth embodiments except that the shape and material of the submount are different. This embodiment is shown in FIG. 60 is a semiconductor laser device according to the present embodiment, 600 is a submount, and a submount substrate is formed by bonding 601a and 601b using two kinds of conductive materials having different thermal conductivity through an insulator 601c. Was used. Implementation Form of In the sectional view of the submount, the insulator is L-shaped. However, in the sectional view, the insulator 601c covers the periphery of the submount base 601b, and the insulator 601c is surrounded by the submount. The structure may cover the base 601b.
[0109]
In this embodiment, as an example, the submount base 601a is made of Ag, which is a conductor, the submount base 601b is made of Al, which is a conductor having a lower thermal conductivity than Ag, and the insulator 601c is made of SiO. ₂ For the positive-side metal pattern 102 and the negative-side metal pattern 103, Au (0.1 μm) / Pt (0.1 μm) / Ti (0.1 μm), and the solder 504 and 505 as the conductive adhesive have a melting point SnAu (Sn 90%, Au 10%) solder having a temperature of 217 ° C. was used. This is because the submount substrate 601a is first formed by using a known technique such as an etching means such as dry etching or wet etching, or a means for physically grinding the submount substrate 601a, and then 601c and 601b are sequentially formed. Form. The submount substrate 601b and the positive side metal pattern 102 and the negative side metal pattern 103 are formed by appropriately using known techniques such as vacuum deposition, CVD, sputtering, plating, thermal transfer, printing, and sintering. Can be used to create. For example, as shown in FIG. 15A, a pattern is formed with a photoresist 606 on the submount substrate 601a and then etched to form a step, and the photoresist 606 is not removed as shown in FIG. 15B. 601c SiO ₂ 1 μm is deposited by CVD, and 601b Al is deposited by 0.5 μm by sputtering, and then the resist and SiO on the resist are deposited. ₂ After removing Al by wet etching (lift-off method), 601b Al plating is performed on the recess as shown in FIG. 15 (c), and the positive side metal pattern 102 is formed thereon as shown in FIG. 15 (d). The negative metal pattern 103 can be formed.
[0110]
In the present embodiment, as an example, the total size of the submount bases 601a and 601b is 2 mm long × 1.5 mm wide × 0.2 mm high, and the size of only 601b is 2 mm long × The width was 0.7 mm × height was 0.1 mm, the distance between the solders was 50 μm, and the thickness of the solder was 1 μm.
[0111]
Further, since 601a and 601b serve as heat radiating portions, the thickness is preferably 20 μm or more in order to increase the heat radiation efficiency. The film thickness of 601c only needs to be large enough to maintain the insulation between 601a and 601b. ₂ Then, at least about 0.1 μm is sufficient. Since the thickness of the insulation thickness varies depending on the type and film quality of the insulating film, the necessary minimum film thickness is appropriately changed depending on the film to be used.
[0112]
Next, in the same manner as in the fifth embodiment, a die bonding process for manufacturing the semiconductor laser device of the present embodiment was performed. The change (temperature profile) of the submount loading surface temperature T in each step of the process is the same as that described in the fifth embodiment.
Thus, the semiconductor laser device of this embodiment has been completed.
[0113]
The semiconductor laser device of this embodiment uses submount bases with different thermal conductivities and varies the solder hardening speed between the positive electrode side and the negative electrode side, so that the force applied to each bonding surface during solidification Since the force applied to the bonding surface is dispersed while maintaining the balance of the above, the problems of the conventional techniques are solved as follows.
[0114]
Of the solder melted in the process B described in the fifth embodiment and FIG. 11, only the solder 504 adjacent to the light emitting portion is solidified in t1 seconds. At this time, since the solder 505 is still melted, there is an unbalance of the force applied to each joint surface as both the solders try to solidify at the same time, which is a problem in the conventional technique. Does not occur. Thereby, the semiconductor laser chip is fixed without moving as the solder 504 is solidified. Therefore, after that, the chip is not displaced when the solder 505 is solidified. As a result, the first problem of the conventional technique in which the laser chip moves during the solder cooling and the misalignment occurs is avoided. The
[0115]
In addition, in the conventional technology, a large thermal strain is applied to the semiconductor laser chip fixed to the submount due to accidental concentration of unpredictable forces on the bonding surfaces when both solders are solidified simultaneously. There is nothing. Furthermore, the distortion caused to the chip is reduced after the solder 504 side is fixed first and before the solder 505 side is fixed. As a result, the second problem in the prior art that causes a large stress / thermal distortion in the semiconductor laser chip is avoided.
[0116]
Also in the present embodiment, as in the fifth embodiment, in the semiconductor laser chip, the positive electrode corresponds to the electrode adjacent to the light emitting portion, and the negative electrode corresponds to the opposite electrode. In the submount, the positive side metal pattern corresponds to the conductive film pattern facing the positive electrode, and the negative side metal pattern corresponds to the conductive film pattern facing the negative electrode.
[0117]
In the semiconductor laser device of the present embodiment, the electrode adjacent to the light emitting part is a positive electrode. In order to suppress the deterioration of characteristics due to the temperature rise of the laser chip, it is preferable that the heat radiation from the positive electrode adjacent to the light emitting part is good. For this reason, it is preferable that the solder 504 in contact with the positive electrode is disposed on the submount substrate having the higher thermal conductivity. Furthermore, when the electrical resistivity is different between the positive electrode and the negative electrode, the amount of heat generated at each electrode is also different, which is preferably taken into consideration.
[0118]
For comparison, a control semiconductor laser device was fabricated in which the submount bases 601a and 601b in the semiconductor laser device of the present embodiment were made of the same material. When it is defined that the center of the laser beam is within ± 2 ° from the vertical direction of the end face of the submount as a non-defective condition regarding the misalignment in the die bonding process, in the semiconductor laser device of the present embodiment, the rate at which the non-defective product is obtained Was 98%, whereas it was 75% in the control semiconductor laser device. Further, when each semiconductor laser device was subjected to an energization test under conditions of 5 mW and 60 ° C. (initial current of about 80 mA) for 1000 hours, the former showed almost no increase in driving current, whereas the latter In about 70% of the devices, an increase of 20% or more in the drive current value was observed. As described above, it was confirmed that the productivity of the die bonding process and the improvement of the device life characteristics were improved as compared with the semiconductor laser device using the conventional technique.
[0119]
In addition, according to the submount of the present embodiment, the productivity of the semiconductor laser device can be improved and the device life characteristics can be improved as compared with the conventional one. Implementation Form of Since the submount bases 601a and 601b use conductors, they can also serve as a metal pattern. Furthermore, not only from the side of the mount member facing the laser chip, but also from the side and back surfaces. Direct connection to the stem, package, external leads, etc. is possible, leading to increased heat dissipation efficiency and simplification of the entire system. In general, since there are many metals having high thermal conductivity in the conductor, the range of material selection is widened, and a more optimal material can be selected.
[0120]
[Embodiment 8]
According to a reference embodiment 8 closely related to the present invention, Variations of Embodiment 7 In addition to the submount substrate of Embodiment 7, a submount having a shape as shown in FIGS. 16A and 16B in which conductor materials having different thermal conductivities are combined. Even if a substrate is used, the same effect can be obtained.
[0121]
First, the submount substrate of FIG. 16A is obtained by bonding two types of conductors of cubes or rectangular parallelepipeds having different thermal conductivities on one surface via an insulator 601c. In this case, since the surface area of 601b can be increased compared to FIG. 14, heat can be effectively dissipated. This may be achieved by bonding each material with an adhesive, or by using known techniques such as vacuum deposition, CVD, sputtering, plating, thermal transfer, printing, and sintering on one material. May be used to deposit. In this embodiment, as an example, Cu, which is a conductor, is used for the submount base 601a, Fe, which is a conductor whose thermal conductivity is lower than Cu, is used for the submount base 601b, and the insulator 601c is used as the insulator 601c. SiO ₂ In solder with a melting point of 156 ° C. for the solder 504 and 505 as the conductive adhesive, Au (0.1 μm) / Mo (0.1 μm) for the positive side metal pattern 102 and the negative side metal pattern 103 Was used. In the present embodiment, as an example, the submount bases 601a and 601b have a length of 2 mm, a width of 1 mm and a thickness of 0.2 mm, respectively. ₂ After 1 μm of the film was deposited, it was adhered with an adhesive. When this adhesive has sufficient insulation, it can also serve as 601c.
[0122]
Further, the submount substrate of FIG. 16B is a case where 601b covers the back surface of 601a via 601c. In this case, since the surface area of 601b can be increased compared to FIG. 14, heat can be effectively dissipated. This may be achieved by bonding materials with different thermal conductivities with an adhesive, or by vacuum deposition, CVD, sputtering, plating, thermal transfer, printing, or sintering on one material. It may be deposited using a known technique such as. As an example in this embodiment, Cu, which is a conductor, is used for the submount base 601a, Fe, which is a conductor whose thermal conductivity is lower than Cu, is used for the submount base 601b, and SiO is used for the insulator 601c. ₂ For the positive metal pattern 102 and the negative metal pattern 103, Au (0.1 μm) / Mo (0.03 μm) was used, and for the solders 504 and 505, In solder having a melting point of 156 ° C. was used. In the present embodiment, as an example, the submount base 601a is a recess having a length of 2 mm, a width of 1.5 mm, a thickness of 0.2 mm, and a length of 2 mm × width of 0.7 mm × thickness of 0.1 mm. 601b is covered with a thickness of about 0.1 mm from the concave portion on 601a to the back surface. The recess on 601a is formed using a known technique such as an etching means such as dry etching or wet etching, or a physical grinding means. ₂ After depositing 1 μm of film, SiO ₂ After the surface is subjected to conductive treatment (silver paste coating or the like), 601b is formed by Fe plating.
[0123]
Further, since 601a and 601b serve as heat radiating portions, the thickness is preferably 20 μm or more in order to increase the heat radiation efficiency. The film thickness of 601c only needs to be large enough to maintain the insulation between 601a and 601b. ₂ Then, at least about 0.1 μm is sufficient. Since the thickness of the insulation thickness varies depending on the type and film quality of the insulating film, the necessary minimum film thickness is appropriately changed depending on the film to be used.
[0124]
In the present embodiment, since the conductor is used for the submount base, it is also possible to serve as a metal pattern, and moreover, not only from the side facing the laser chip of the mount member, but also from the side and back. Can be directly connected to the stem, package, external leads, etc., leading to higher heat dissipation efficiency and simplification of the entire system.
[0125]
14 and 16, since the surface of the submount substrate is substantially flat, it can be easily die-bonded when the positive and negative electrodes of the facing laser chip are substantially on the flat surface. When there is a difference in height between the positive and negative electrodes of the chip, it can be adjusted by the thickness of 601a or 601b.
[0126]
Moreover, although the temperature profile in Embodiments 5 to 8 has been described with reference to FIG. 12, this shows an ideal temperature change, and in practice, a strictly constant temperature is maintained in the process B. It may be a profile that is not necessary and that gradually changes in temperature in each process.
[0127]
Implementation above Form of 7 and 8, the submounts 101a and 101b are formed of metals having different thermal conductivities. However, in consideration of the thermal conductivity and thickness of the insulating film 101c, Also, the same effect as the present invention can be obtained.
[0128]
For example, in FIGS. 14 and 16B, copper is used for 101a and 101b, and 101c is aniline resin, epoxy resin, or silicon resin having a thermal conductivity about one thousandth of that of copper (both are thermosetting resins). ) Is formed with a thickness of 100 μm, the heat conduction at the positive electrode 101a is larger than that at the non-electrode side 101b, and therefore the timing of solidification of the conductive adhesive on the positive and negative electrode sides is shifted. In this case, it is preferable that the ratio of the thermal conductivity of the metal and the insulator is large, since it is easy to shift the solidification timing, and it is preferably 10 or more. Similarly, it is preferable that the thickness of the insulator is thick, and it is preferably 10 to 150 μm.
[0129]
In addition, if the size of 101a and 101b is made sufficiently larger than 101b for 101a to produce a difference in the heat dissipation effect, a greater effect can be obtained.
[0130]
This method is effective to enhance the effect even when the metals having different thermal conductivities are used.
[0131]
[Embodiment 9]
Figure 17 Reference information closely related to the present invention Embodiment 9 It is sectional drawing which shows this semiconductor laser apparatus. This differs from the apparatus shown in FIG. 8 of the fifth embodiment in that a groove is formed on the surface of the submount and that the conductive adhesive is an anisotropic conductive resin. In the figure, 70 is the semiconductor laser device of the present embodiment, 700 is a submount, 703 is a groove provided between metal patterns on the mounting surface of the submount of Embodiment 5, and 702 is an anisotropic conductive resin. The other parts similar to those of the fifth embodiment are indicated by the same reference numerals as in FIG.
[0132]
In the present embodiment, AlN, which is an insulator, is used for the submount base 701a, and Al, which is an insulator having a lower thermal conductivity than AlN, is used for the submount base 701a, as in the fifth embodiment. ₂ O _Three For the positive side metal pattern 102 and the negative side metal pattern 103, Au (0.1 μm) / Pt (0.1 μm) / Ti (0.1 μm) (Au on Pt on Ti, the same applies hereinafter), anisotropic An anisotropic conductive resin was used for 702 as the conductive adhesive. In the present embodiment, as an example, the total size of the submount bases 701a and 701b is 2 mm long × 1.5 mm wide × 0.2 mm high, and the size of only 701b is 2 mm long × 0 mm wide. The thickness was 7 mm × height 0.1 mm, and the thickness of the anisotropic conductive resin was 1 μm. The size of the groove was set to a depth of 0.1 mm and a width of 0.1 mm.
[0133]
Here, in order to make the conductive resin anisotropic, in the present embodiment, a thermosetting epoxy resin containing several to several tens wt% of Ag particles is used. As a result, when the anisotropic conductive resin is cured without applying a load, the metal powder is dispersed. Therefore, when the anisotropic conductive resin is cured and applied with a predetermined load, the metal powder comes into contact with each other. Become. The curing temperature of the resin was about 180 ° C.
[0134]
Also in the present embodiment, as in the fifth embodiment, in the semiconductor laser chip, the positive electrode corresponds to the electrode adjacent to the light emitting portion, and the negative electrode corresponds to the opposite electrode. In the submount, the positive side metal pattern corresponds to the conductive film pattern facing the positive electrode, and the negative side metal pattern corresponds to the conductive film pattern facing the negative electrode.
[0135]
In the semiconductor laser device of the present embodiment, the electrode adjacent to the light emitting part is a positive electrode. In order to suppress the deterioration of characteristics due to the temperature rise of the laser chip, it is preferable that the heat radiation from the positive electrode adjacent to the light emitting part is good. Therefore, it is preferable that the positive electrode is disposed corresponding to the submount substrate having the higher thermal conductivity. Furthermore, when the electrical resistivity is different between the positive electrode and the negative electrode, the amount of heat generated at each electrode is also different, which is preferably taken into consideration.
[0136]
Next, a die bonding process for manufacturing the semiconductor laser device of the present embodiment was performed. FIG. 18 shows the change (temperature profile) of the submount loading surface temperature T in each step of the process. Here, T corresponds to the temperature of the anisotropic conductive resin.
[0137]
Although the same as that shown in FIG. 9 is prepared in advance, a submount provided with the groove is prepared.
First, the anisotropic conductive resin is disposed on the submount electrode. However, at this stage, the resin is uncured. Next, the semiconductor laser chip shown in FIG. 2 was appropriately aligned and loaded on the submount so that the laser chip electrode formation surface and the submount loading surface were abutted, and the resin spread. At this time, depending on the viscosity of the resin, the positive electrode side and the negative electrode side may not contact each other, but in this embodiment, as shown in FIG. 17, the resin on the positive electrode side and the negative electrode side contact each other. An example of entering the groove will be described.
[0138]
<Process A> The temperature of the submount was raised while applying a load of 30 g to the laser chip. First, as shown by a solid line, the anisotropic conductive resin on the submount substrate 701a having a high thermal conductivity reaches the curing temperature Ts = 180 ° C. and is cured at t1 seconds.
<Process B> Stop applying load and continue heating. Next, the anisotropic conductive resin on the submount substrate 701b having a low thermal conductivity reaches the curing temperature Ts at t2 seconds and is cured. Thereafter, the temperature was kept at a temperature Tp = 200 ° C. slightly higher than the curing temperature for 30 seconds to complete the curing reaction.
<Process C> The die bonding process was completed when the process was cooled to an appropriate temperature close to room temperature.
Thus, the semiconductor laser device of the present embodiment has been completed.
[0139]
Since the semiconductor laser device of the present embodiment uses an anisotropic conductive resin instead of solder, the problems of the prior art are solved as in the case of the fifth embodiment as follows.
[0140]
In the above process, when the anisotropic conductive resin on the side in contact with the submount base 701b made of a material having low thermal conductivity is solidified, the anisotropic conductivity on the side in contact with the submount base 701a made of a material having high thermal conductivity has already been made. Therefore, the semiconductor laser chip does not move as the first conductive resin is solidified. That is, the first problem of the prior art in which the laser chip moves during the solder cooling and the misalignment occurs is avoided.
[0141]
Also, in the conventional technology, when both solders are solidified at the same time, a large thermal strain is applied to the semiconductor laser chip fixed to the submount due to accidental concentration of the force applied to each bonding surface which cannot be predicted. There is no. As a result, the second problem in the prior art that causes a large stress / thermal distortion in the semiconductor laser chip is avoided.
[0142]
Furthermore, the positive and negative electrodes of the semiconductor laser chip are not limited to being on the same plane, and the electrode (negative electrode) opposite to the side adjacent to the light emitting layer may be provided on the recessed surface. In particular, in this embodiment, since the conductive resin is used for the connection of the electrodes, if the conductive resin having different hardness is used on the positive electrode side and the negative electrode side, even if the depression is large, the electrical connection is ensured. It becomes possible to ensure conduction.
[0143]
In particular, in the semiconductor light emitting device of the present embodiment, an anisotropic conductive resin is used, and a groove is provided between the submount metal film patterns. A load is applied to the region on the metal pattern to make it conductive. Therefore, electrical continuity is ensured between the negative electrode and the negative metal pattern, but as shown in FIG. 17, even if the resin contacts the positive electrode or the like, there is no short circuit. Therefore, it is possible to prevent a decrease in productivity due to occurrence of a short in the die bonding process.
[0144]
For comparison, a reference semiconductor laser device was fabricated in which the submount bases 701a and 701b in the semiconductor laser device of the present embodiment were made of the same material. In the semiconductor laser device of this embodiment, when the laser beam center within ± 2 ° from the vertical direction of the end face of the submount is defined as a non-defective condition regarding the positional deviation in the die bonding process, the yield of non-defective products is Compared to 98%, it was 75% in the control semiconductor laser device. Further, when each semiconductor laser device was subjected to an energization test under conditions of 5 mW and 50 ° C. (an initial current of about 50 mA) for 1000 hours, the former showed almost no increase in driving current, whereas the latter. In about 30% of the devices, an increase of 20% or more in the drive current value was observed. As described above, it was confirmed that the productivity of the die bonding process and the improvement of the device life characteristics were improved as compared with the semiconductor laser device using the conventional technique.
[0145]
In the present embodiment, the mount member having the structure of FIGS. 8 and 9 shown in the fifth embodiment has been described, but this is the same as that of FIGS. 13, 14, and 16 shown in the sixth to eighth embodiments. The same effect can be obtained by replacing with other mounting members.
[0146]
As described above, according to the fifth to ninth embodiments, the present invention. is connected with Although the configuration has been described with a specific example, the scope of the present invention is not limited to this, and it is a matter of course that each component can be replaced with a material having the same application, and other technologies are combined. Can also be used.
[0147]
In addition to the materials described above, the insulating submount substrate may be made of other insulating materials such as diamond, Si, SiC, BeO, and diamond / Si, SiO. ₂ As represented by / Si, it can be replaced with another insulating submount substrate having a laminated structure of these insulating materials.
As the conductive submount substrate, in addition to the above-described materials, materials such as Si, Ge, SiC, CuW, and Mo, and a laminated structure of these substances can be used.
The above-described semiconductor laser chip is not limited to the specific example shown in FIG. 2, but GaN, SiC, Si, SiO as a substrate. ₂ / Other materials such as sapphire can be used, and other materials such as InGaAsP, InGaAlP, AlGaN, and CdZnSe can be used as the material system of the semiconductor growth layer. is there. In addition, the semiconductor laser chip can be replaced with another light emitting element chip such as an LED or a super luminescence diode.
[0148]
Further, in the submounts of Embodiments 5 to 9 described above, the shape of each conductive adhesive and each metal pattern is shown as a specific example in FIG. 9, but the present invention is not limited to this, and is appropriately selected. It can be changed. For example, the metal pattern is not necessarily provided so as to cover almost the entire surface of the submount. Further, it is easy for those skilled in the art to provide a wire bonding pad portion and a mark for alignment during die bonding on the submount stacking surface. . Alternatively, it is easily conceivable for those skilled in the art to apply the present invention to a semiconductor laser device loaded with a semiconductor laser chip having three or more electrodes, such as a so-called multi-beam laser, based on the above principle. .
[0149]
Further, as is well known, various films can be interposed between the solder layer and the submount base. For example, a film for improving the adhesion between the submount and the solder, the submount, and the like. A film for preventing a reaction between solders, and a film for improving adhesion between these films or preventing oxidation may be appropriately laminated. Au / Pt / Ti, Pt / Cr, Au / Mo, Au / Pt / Cr, Au / Mo / Ti, or the like can be used as a substitute for the metal pattern described in the above embodiment. It is assumed that various films are interposed between the conductive adhesive layer, the insulating film, the bonding pad, and the submount substrate for the same purpose.
[0150]
Furthermore, according to the submount configuration shown in FIGS. 8, 9, 13, 14, and 16, no special structure is provided in the space between the solder 504 and the solder 505. In order to prevent a short circuit during the die bonding process or to prevent misalignment, a structure such as a groove, a matte surface, a resin protrusion, or an insulator protrusion may be provided.
[0151]
In the above-described fifth to ninth embodiments, the semiconductor laser element submount has been described. However, the application of the present invention is not limited to this, and the present invention can be applied to all mounting members of light emitting element chips. That is, in any mounting member, if the portion to be die-bonded of the light-emitting element chip has the same configuration as that of each of the above-described embodiments, the same effects as described above can be obtained in other light-emitting element chip mounting members. Is obvious. Therefore, when the light emitting element chip is directly mounted on the stem, the frame, or the package without using the submount, the above-described present invention is attached to the stem, the frame, or the package. is connected with Configuration can be applied.
[0152]
【The invention's effect】
According to the present invention, the above configuration prevents misalignment during the die bonding process, and can reduce stress and thermal distortion inside the semiconductor light emitting element chip caused by the die bonding process. Thereby, the yield of the die bonding process of the semiconductor light emitting device is improved, and the life characteristics are also improved.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a semiconductor laser device according to a first embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view showing the semiconductor laser chip according to the first embodiment of the present invention.
FIG. 3 is a schematic diagram showing a submount according to the first embodiment of the present invention.
FIG. 4 is a graph showing a temperature profile in a die bonding process according to the first embodiment of the present invention.
FIG. 5 is a graph showing a temperature profile in a die bonding process according to a second embodiment of the present invention.
FIG. 6 shows the present invention. Closely related to the reference FIG. 6 is a schematic cross-sectional view showing a semiconductor laser device according to a third embodiment.
FIG. 7 shows the present invention. Closely related to the reference FIG. 6 is a schematic cross-sectional view showing a semiconductor laser device according to a fourth embodiment.
FIG. 8 shows the present invention. Closely related to the reference FIG. 10 is a schematic cross-sectional view showing a semiconductor laser device (including a submount of the present invention) according to a fifth embodiment.
FIG. 9 shows the present invention. Closely related to the reference FIG. 10 is a schematic diagram showing a submount according to a fifth embodiment.
FIG. 10 shows the present invention. Closely related to the reference FIG. 10 is a flowchart showing a method for manufacturing a submount according to the fifth embodiment.
FIG. 11 shows the present invention. Closely related to the reference FIG. 10 is a flowchart showing a method for manufacturing a submount according to the fifth embodiment.
FIG. 12 is a graph showing a temperature profile in a die bonding process according to the embodiment of the present invention.
FIG. 13 shows the present invention. Closely related to the reference Semiconductor laser device according to the sixth embodiment Place It is a schematic diagram shown.
FIG. 14 is a semiconductor laser device according to a seventh embodiment of the present invention. Place It is a schematic cross section shown.
FIG. 15 shows the present invention. Closely related to the reference FIG. 23 is a flowchart showing a method for manufacturing a submount according to the seventh embodiment.
FIG. 16 shows the present invention. Closely related to the reference Semiconductor laser device of embodiment 8 Place It is a schematic cross section shown.
FIG. 17 shows the present invention. Closely related to the reference Semiconductor laser device of embodiment 9 Place It is a schematic cross section shown.
FIG. 18 shows the present invention. Closely related to the reference It is a graph which shows the temperature profile in the die-bonding process of the ninth embodiment.
FIG. 19 is a schematic cross-sectional view showing a conventional semiconductor laser device.
[Explanation of symbols]
10, 30, 40, 50, 60, 70 Semiconductor laser device
100, 300, 400, 500, 600, 700 Submount
101, 501a, 501b, 601a, 601b, 701 Submount substrate
102 Positive metal pattern
103 Negative metal pattern
104 First solder
105 Second solder
200 GaN semiconductor laser chip
201 Sapphire substrate
202 Semiconductor growth layer
203 Positive electrode
204 Negative electrode
301 conductive resin
401 groove
402 Anisotropic conductive resin
504, 505 Solder
601c insulator
606 photoresist
702 Anisotropic conductive resin
703 groove

Claims (3)

A semiconductor light emitting element chip having first and second electrodes on one side is mounted using solder on a mount member having a conductive film pattern facing each electrode on the mounting surface, and the first electrode and the first electrode A method of manufacturing a semiconductor light emitting device in which a conductive film pattern is connected by a first solder, and a second electrode and the second conductive film pattern are connected by a second solder different from the first solder,
Heating the first solder and the second solder previously installed on the mount member to a temperature higher than the melting point T1 of the first solder and the melting point T2 of the second solder;
By holding a predetermined time in the middle of the constant temperature of the first solder and the second solder T1 and T2, together with the solidified solder having a high melting point among the first solder and the second solder, solder having a lower melting point Holding the melted state; and
The first solder and the second solder are cooled to a temperature lower than both T1 and T2 to solidify the solder having a lower melting point among the first solder and the second solder in the above order. A method for manufacturing a semiconductor light emitting device. 2. The space between the first solder and the second solder on the mount member is provided with any one of a groove, a matte surface, a resin protrusion, and an insulator protrusion. Of manufacturing a semiconductor light emitting device. 3. The method of manufacturing a semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting element chip is a semiconductor laser chip.

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