JP4130643B2 - Semiconductor element - Google Patents

Description

  The present invention relates to a power semiconductor device having a buried insulated gate structure.

  As is well known, various thyristors such as GTO can realize a low on-resistance (thus, a small on-voltage) because they are latched up in an on-state, but have a small maximum breaking current density. In particular, a thyristor with an insulated gate that performs turn-off using an insulated gate structure has a lower current interruption capability than a normal GTO thyristor. On the contrary, an IGBT or the like has a built-in thyristor structure, but is designed to be used under the condition that it does not latch up. Therefore, the maximum cutoff current density is relatively large, but the on-resistance is high because it does not latch up.

  As described above, the conventional power semiconductor device has a problem that it is necessary to latch up the pnpn thyristor in order to obtain a low on-resistance, and it is difficult to interrupt the current when the thyristor is latched up. .

  The present invention provides a buried insulated gate type power semiconductor device capable of realizing a sufficiently low on-resistance without latch-up and having a large maximum cutoff current density without latch-up. The purpose is to provide.

  In the power semiconductor device according to the present invention, the first conductivity type emitter region and the first conductivity type carrier injection from the first conductivity type emitter region are substantially performed through the channel, and the conductivity modulation is performed in the ON state. A high-resistance base region that causes the second resistance type region, a second conductivity-type emitter region that injects a second conductivity-type carrier into the high-resistance base region, and a second conductivity-type drain that discharges the second conductivity-type carrier in the high-resistance base region The carrier concentration in the high resistance base region in the on state has a portion whose concentration is higher on the first conductivity type emitter region side than the concentration in the central portion of the high resistance base region. Features.

The power semiconductor device according to the present invention includes a high resistance base layer, an insulating gate embedded in the surface of the high resistance base layer with a predetermined interval, and a first region formed in a region sandwiched between the insulating gates. A conductivity type emitter layer, a channel region induced by the insulated gate and injecting a first conductivity type carrier from the first conductivity type emitter layer into the high resistance base layer; and a second conductivity type carrier in the high resistance base layer. A second conductivity type emitter layer to be injected; and a second conductivity type drain layer formed in a region sandwiched between the insulated gates and discharging second conductivity type carriers from the high resistance base layer. When the distance between the drain layers is 2C, the width of the region sandwiched between the insulated gates is 2W, and the distance from the interface between the second conductivity type drain and the high resistance base layer to the tip of the insulated gate is D
X = {(C−W) + D} / W
The parameter X represented by the following formula satisfies X ≧ 5.

[Action]
According to the present invention, the parasitic thyristor structure is latched up by optimally designing the emitter layer with low injection efficiency and optimal design, and the depth, width, and spacing of the trenches of the buried insulated gate portion formed with fine dimensions. Therefore, the on-resistance as low as the thyristor can be obtained. The reason for this will be described in detail later. In the structure of the present invention, when the buried gate electrode portion is defined as a broadly defined emitter region including the second conductive type drain layer and the first conductive type emitter layer adjacent thereto, By setting the ratio Rp / Rn of the resistance Rp of the second conductivity type carrier in the emitter region and the resistance Rn of the turn-on channel formed on the side surface of the groove to the first conductivity type carrier to be 4 or more, it is sufficiently large. This is because emitter injection efficiency can be obtained.

  The parameter X is an amount representing how far the bypass or drain layers of the second conductivity type carriers on the first conductivity type emitter layer side are separated from each other, and the high resistance base layer short-circuit resistance on the first conductivity type emitter layer side is This is introduced because it is proportional to the distance 2D + 2 (C−W) straddling adjacent buried gate portions and inversely proportional to the emitter width 2W. The smaller this parameter X is, the smaller the discharge resistance of the second conductivity type carrier on the first conductivity type emitter layer side is. Then, by optimizing the dimensions of each part so as to satisfy X ≧ 5, a sufficiently low on-voltage can be obtained without performing a thyristor operation.

The emitter injection efficiency γ in a broad sense including the buried gate in the device of the present invention is obtained as follows. First, the current flowing between the grooves is considered by dividing it into an electron current Ich [A] flowing through the on-MOS channel and other current density JT [A / cm ² ]. However, the current density is considered as a unit depth of 1 cm from the element cross section. The current density flowing in the unit cell is J [A / cm ² ], the groove interval is 2 W [cm], the unit cell size is 2 C [cm], and the virtual injection efficiency in the groove is γT.
γ = (Ich + γT × JT × W × 1) / (Ich + JT × W × 1) (1)
here,
C ・ J = JT x W x 1 + Ich (2)
Ich = Δψ / Rch (3)
Rch is the resistance of the on-MOS channel. Δψ is a potential difference between both ends of the on-MOS channel (potential difference between both ends of the depth D), and the equation of current continuity in the groove Jp = (1-γT) JT
= −kTμp (dn / dx) −qμp · n (dψ / dx) (4)
Jn = γT JT
= KT [mu] n (dn / dx) -q [mu] n.n (d [psi] / dx) (5)
Obtained from
Δψ = (kT / q) ×
{Μn (1-γT) + μp γT} / {μn (1-γT) -μp γT}
X [log (n) -log {n- (dn / dx) D}] (6)
dn / dx = − (JT / 2kT) {(1-γT) / μp−γT / μn} (7)
It becomes. From these equations (2) to (7), the injection efficiency of equation (1) can be obtained. By optimizing W, D, and C, the injection efficiency of the emitter region in a broad sense can be increased without increasing the injection efficiency of the cathode-side emitter (or source) layer. As a result, carriers accumulated in the high-resistance base layer at the time of ON can be increased, and bipolar transistors and IGBTs that have a smaller ON-state carrier accumulation (conductivity modulation) than the thyristor originally are used in the present invention. By applying the “carrier injection concept”, the on-voltage of these elements can be made as low as that of a thyristor.

  As described above, according to the present invention, a large current blocking capability is realized with a fine cell structure having a buried insulated gate, and the thyristor parallelism is achieved without latching up the parasitic thyristor by designing the width and interval of the buried insulated gate portion. Thus, an insulated gate power semiconductor device that realizes the on-resistance can be obtained.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a layout of a buried insulated gate power semiconductor device according to the first embodiment of the present invention. FIGS. 2, 3, 4 and 5 are respectively A-A 'and B of FIG. It is -B ', CC', and DD 'sectional drawing.

  In this insulated gate semiconductor element, a p-type emitter layer 3 is formed on one surface of a high-resistance n-type base layer 1 via an n-type buffer layer 2. A p-type base layer 4 is diffused on the other surface of the n-type base layer 1.

  A plurality of stripe-shaped grooves 5 are formed in the p-type base layer 1 with a minute interval. Inside these trenches 5, a gate electrode 7 is buried and formed through a gate oxide film 6. An n-type turn-off channel layer 8 is formed every other stripe region between the grooves 5, and a p-type drain layer 9 is formed on the surface of the turn-off channel layer 8. Thus, a vertical p-channel MOSFET in which the side surface of the n-type turn-off channel layer 8 is controlled by the buried gate electrode 7 is configured. In the remaining stripe region, the n-type source layer 10 is diffused and formed on the surface portion. Here, the n-type source layer 10 is shallowly diffused so that the parasitic thyristor structure constituted by the n-type source layer 10, the p-type base layer 4, the n-type base layer 1 and the p-type emitter layer 3 is not latched up. ing.

  Therefore, the layout on the cathode side has a pattern in which the arrangement of the buried gate electrode 7 -p type drain layer 9 -the buried gate electrode 7 -n type source layer 10 is repeated.

  The cathode electrode 11 as the first main electrode is disposed in contact with the n-type source layer 10 and the p-type drain layer 9 simultaneously. On the p-type emitter layer 3, an anode electrode 12 as a second main electrode is formed.

  Specific element dimensions are, for example, as follows. The high resistance to be the n-type base layer 1 is such that the thickness of the n-type wafer is 450 μm, and the n-type buffer layer 2 and the p-type base layer 4 are formed at a depth of 15 μm and 2 μm from both sides. The groove 5 formed in the p-type base layer 4 has a width and interval of 1 μm and a depth of 5 μm. The gate oxide film 6 is a thermal oxide film or ONO film (oxide film / nitride film / oxide film) of 0.1 μm or less. The n-type turn-off channel layer 8 has a p-type drain layer 9 formed on the surface and has a channel length of substantially 0.5 μm. The n-type source layer 10 is diffused to a depth of 1 μm or less, and the p-type emitter layer 3 is diffused to a depth of about 4 μm.

  The operation of the insulated gate semiconductor device configured as described above is as follows. When a positive voltage is applied to the gate electrode 7 with respect to the cathode, the turn-on channel around the p-type base layer 4 conducts and electrons are injected from the n-type source layer 10 into the n-type base layer 1 and turned on by the IGBT operation. To do. When a negative voltage is applied to the gate electrode 7, the groove side surface portion of the n-type turn-off channel layer 8 in the buried gate portion is inverted, and the carrier of the p-type base layer 4 causes the p-type drain layer 9 to move by p-channel MOS transistor operation. To the cathode electrode 11 and turn off.

  In this embodiment, the parasitic thyristor constituted by the n-type source layer 10 -p-type base layer 4 -n-type base layer 1 -p-type emitter layer 3 is designed not to latch up even when the element is turned on. If the on-channel is closed, the electron injection from the n-type source layer 10 stops.

  According to this embodiment, the depth and density of the buried gate portion are sufficiently small with a unit cell size of 4 μm (ie, buried gate 1 μm−p-type drain layer 1 μm−embedded gate portion 1 μm−n-type source layer 1 μm). By designing the size, a sufficiently small on-resistance can be obtained even though the thyristor operation is not performed. The fact that the turn-off channel is closed in the on state of the element is also a reason why a small on-resistance can be obtained. In addition, the parasitic thyristor does not latch up in the on state, and when it is off, the turn-off channel is opened and the holes are bypassed. Therefore, the maximum current blocking capability is larger than a GTO thyristor that is turned off after being latched up.

  FIG. 6 is a layout of a buried insulated gate power semiconductor device according to the second embodiment of the present invention. FIGS. 7, 8 and 9 are respectively A-A ', BB' and C of FIG. It is -C 'sectional drawing. Portions corresponding to those of the previous embodiment are denoted by the same reference numerals as those of the previous embodiment, and detailed description thereof is omitted.

  In this embodiment, the grooves 5 that are periodically arranged are formed so as to penetrate through the p-type base layer 4 deeply. For example, the p-type base layer is 3 μm, and the groove 5 is about 6 μm. The gate electrode 7 is embedded in the trench 5 via the gate oxide film 6 as in the previous embodiment.

  In this embodiment, the interval between the grooves 5 is wider than that of the previous embodiment, for example, 2 μm. An n-type turn-off channel layer 8 and a p-type drain layer 9 are formed in contact with the groove 5 in all stripe regions between the grooves 5, and an n-type source layer 10 is formed at a position away from the groove 5. Here, the n-type source layer 10 is formed so that the parasitic thyristor formed between the n-type source layer 10 and the p-type base layer 4, the n-type base layer 1 and the p-type emitter layer 3 is not latched up. This is the same as the previous embodiment. However, the n-type source layer 10 and the n-type turn-off channel layer 8 are continuous.

  In this embodiment, the side surface of the groove 5 of the p-type base layer 4 under the n-type turn-off channel layer 8 is a turn-on channel. That is, the gate electrode 7 embedded in the trench 5 serves both as a turn-on and a turn-off, and is formed in a state in which a turn-off p-channel MOSFET and a turn-on n-channel MOSFET are stacked vertically.

  The element of this embodiment is turned on by applying a positive voltage to the gate electrode 7 and forming an n-type channel on the side surface of the groove 5 of the p-type base layer 4. At this time, electrons are injected from the n-type source layer 10 into the n-type base layer 1 through the n-type turn-off channel layer 8 and the inverted n-type channel. A negative voltage or a zero voltage is applied to the gate electrode 7 to turn off as in the previous embodiment.

  According to this embodiment, the same effect as the previous embodiment can be obtained.

  FIG. 10 is a layout of a buried insulated gate type power semiconductor device according to the third embodiment of the present invention. FIGS. 11, 12 and 13 are respectively A-A ', BB' and C-- of FIG. It is C 'sectional drawing. In this embodiment, on the basis of the configuration of the second embodiment, the ratio of the width of the buried gate electrode portion to the width of the region sandwiched between them is made larger.

  The specific element size is that the high resistance to be the n-type base layer 1 is such that the thickness of the n-type wafer is 450 μm, and the n-type buffer layer 2 and the p-type base layer 4 are formed at a depth of 15 μm and 2 μm from both sides. To do. The grooves 5 formed in the p-type base layer 4 have a width of 5 μm, an interval of 1 μm, and a depth of 5 μm. The gate oxide film 6 is a thermal oxide film or ONO film of 0.1 μm or less. The n-type turn-off channel layer 8 has a p-type drain layer 9 formed on the surface and has a channel length of substantially 0.5 μm. The n-type source layer 10 is diffused to a depth of 1 μm or less, and the p-type emitter layer 3 is diffused to a depth of about 4 μm.

  The element of this embodiment also operates in the same manner as the second embodiment. In this embodiment, the area occupied by the buried gate electrode portion in the element is made sufficiently larger than the area of the region sandwiched between them. As a result, the resistance to holes in the broad emitter region including the buried gate electrode portion increases, and as a result, the electron injection efficiency of the broad emitter region increases. That is, although the area of the buried gate electrode region is larger than the area of the n-type source layer 10 region, an equivalently large electron injection efficiency is obtained by the difference between the resistance to the electron current and the resistance to the hole current, Low on-resistance is achieved. Since the actual electron injection efficiency of the n-type source layer 10 itself is low, the turn-off capability is as high as the IGBT.

  FIG. 14 is a layout of a modified example of the third embodiment, and FIGS. 15, 16 and 17 are cross-sectional views taken along lines AA ′, BB ′ and CC ′ of FIG. 14, respectively. is there. In this embodiment, unlike the previous embodiment, the groove 5 remains in the p-type base layer 4.

  Also in this embodiment, by optimizing the element dimensions of each part, it is possible to achieve both a low on-resistance and a high current interruption capability as in the previous embodiment.

  FIG. 18 shows a cross-sectional structure of a unit cell portion of an embodiment in which a similar buried gate structure is applied to the anode side on the basis of the element of the second embodiment. That is, as described in the second embodiment, the embedded gate electrode 7 is formed on the cathode side surface of the n-type base layer, and the p-type base layer and the n-type source layer are formed between the embedded grooves 4. An n-type turn-off channel layer and a p-type drain layer are formed on the side surfaces of the trench 4. In contrast to the cathode side, a groove 20 is also formed on the anode side, and a gate electrode 21 is embedded therein. Between the grooves 20, a diffusion layer in which the conductivity type of each part is reversed from that of the cathode side. Is formed.

  FIG. 18 shows specific element dimensions. Further, the impurity concentration distributions in the AA 'portion and the BB' portion on the cathode side are as shown in FIGS. 19 (a) and 19 (b), respectively.

  In the element of this embodiment, at the time of turn-on, a negative voltage is applied to the anode side buried gate electrode 21 with respect to the anode electrode. At the time of turn-off, a zero or positive voltage is applied to the buried gate electrode 21 on the anode side with respect to the anode electrode. Even with the element of this embodiment, the same effect as the previous embodiment can be obtained.

  Here, the reason why the buried on-gate device according to the present invention adopts a pnpn structure that does not operate as a thyristor even in a large current region and can provide a low on-resistance similar to a thyristor will be described in detail with reference to simulation data.

  FIG. 20 is a cross-sectional view of a half cell of the model used for the calculation, and FIG. 21 is a diagram for explaining the principle of the new emitter structure. Since the basis of FIG. 20 is an IGBT, there is no n-type emitter in a normal thyristor. Electron injection on the cathode side is performed by the MOS channel, and the bypass resistance of the hole current is designed to be sufficiently small so that the n-type drain layer constituting the MOSFET serves as an n-type emitter and the parasitic thyristor does not latch up. However, reducing the bypass resistance of the hole current is equivalent to lowering the injection efficiency of the n-type emitter when the structure of FIG. 20 is compared with a thyristor (or diode), which means an increase in the on-voltage of the element. Results.

  FIG. 21 shows this easily. In the element of the present invention in which the MOS source layer and the buried gate are arranged in fine dimensions, it is easier to understand the injection efficiency by considering the entire region including the MOS source layer and the buried gate portion as the emitter region. That is, if a region surrounded by a broken line in the figure is defined as a broad emitter region, the injection efficiency γ of this broad emitter region can be expressed as follows by the hole current resistance Rp and the electron current resistance Rn.

γ = Jn / (Jn + Jp)
= (Rp / Rn) / {1+ (Rp / Rn)} (8)
However, it is assumed that there is no potential distribution in the lateral direction at the end of the emitter region in a broad sense. Here, if Rp / Rn = 3, then γ = 0.75, and if Rp / Rn = 4, then γ = 0.8.

  Considering that the emitter injection efficiency of a normal thyristor or diode is 0.7 or more, even in the IGBT having the buried insulated gate structure of FIG. 20, if the emitter injection efficiency in a broad sense is 0.8 or more, that is, Rp / If Rn> 4, it means that an ON voltage equivalent to that of a thyristor can be obtained.

In the current planar gate structure IGBT, Rp / Rn is approximately 3 and when Rp / Rn> 4, the latch-up resistance is lowered. There are several reasons for this. For example, in the case of an IGBT having a planar gate structure, it may be difficult to make a difference between the electron current resistance and the hole current resistance in the lateral direction. Low lateral resistance in the on state (there is about 3 × 10 ¹⁶ / cm ³ carriers when current density of 100 A / cm ² is applied, and the lateral resistance of the holes due to the p-type base layer is reduced) Even if this lateral resistance is used to increase the hole current resistance, the number of MOS on-channels per unit area is reduced, and conversely, the electron current resistance is increased, thus reducing the emitter injection efficiency in a broad sense. Resulting in. In the case of EST, the cell size is increased to increase the hole current resistance, but this method reduces the number of on-channels per unit area and increases the electron current resistance before the hole current resistance increases sufficiently. As a result, the injection efficiency of the emitter region in a broad sense does not increase, and it is difficult to reduce the on-resistance of the element. In addition, if the hole current resistance is simply increased by lowering the short-circuit rate of the hole current, the latch-up resistance is lowered.

  Therefore, it is necessary to have a structure in which the hole current resistance is at least four times the electron current resistance without increasing the short-circuit resistance of the hole current while increasing the number of MOS channels per unit area. According to the examination results of the present inventors, it has become clear that such a condition can be realized by optimizing the width and depth of the buried gate structure, the interval, and the like.

Specific shredding data is shown below. First, the IGBT structure of FIG. 20 used for the calculation has a forward blocking withstand voltage of 4500 V, and its element parameters are as follows. Using an n-type high resistance silicon substrate having an impurity concentration of 1 × 10 ¹³ / cm ³ and a thickness of 450 μm, an n-type buffer layer having a depth of 15 μm and a surface concentration of 1 × 10 ¹⁶ / cm ³ is formed on the anode side. A p-type emitter layer having a thickness of 4 μm and a surface concentration of 1 × 10 ¹⁹ / cm ³ is formed. The cathode side, depth 2 [mu] m, are formed with p-type base layer of the surface concentration 1 × 10 ¹⁷ / cm ^3, the depth 0.2 [mu] m, the p-type source layer on the surface concentration of 1 × 10 ¹⁹ / cm ³ . The gate electrode of the buried gate portion on the cathode side is separated by a 0.05 μm thick silicon oxide film or ONO film.

  As shown in FIG. 20, the depth of the buried gate portion is D (portion protruding from the p-type base layer into the n-type base layer), the cell size is 2C, and the emitter width is 2 W. Therefore, the buried gate portion The ratio of the width to the emitter width is W / (C−W). Using these dimensions C, W, D and hole lifetime τp as parameters, the effect of the buried gate electrode structure on the on-voltage of the device was investigated. The results are shown in FIGS.

  FIG. 22 shows a model in which the cell size is 2C = 6 μm, the emitter width is 2W = 1 μm, the buried gate width is 2 (C−W) = 5 μm, and the hole lifetime is τp = τn = 2.0 μsec. This is a result of obtaining the element current density at an anode-cathode voltage of 2.6 V when the depth D of the buried gate portion is changed. The gate applied voltage is +15 V (common to all on-voltage calculations).

  FIG. 23 shows a model with an emitter width of 2 W = 1 μm, a buried gate portion depth D = 5 μm, and a hole lifetime τp = 30 μsec. It is the result of calculating | requiring the element current density in the voltage 2.6V.

  As shown in FIG. 23, when the width of the buried gate portion increases from about 1 μm to about 5 μm, the device current increases rapidly as the width of the buried gate portion increases. However, when the width of the buried gate portion increases to about 15 μm, Conversely, the current starts to decrease. This phenomenon can be explained as follows. When the width of the buried gate portion becomes wider than the emitter width, the hole current density near the buried trench side surface immediately under the emitter increases, and as a result, the potential rises on the buried trench lower side surface. As a result, in the state where the MOS channel is not saturated, the ratio of the hole current to the electron current increases, and as a result, the injection efficiency of the emitter region in a broad sense increases and the device current density increases. However, when the width of the buried gate portion is further increased, the MOS channel is saturated and the number of MOS channels per unit area is reduced, thereby increasing the MOS channel resistance of the electron current and limiting the electron current flowing through the device. As a result, the emitter injection efficiency is lowered and the device current is reduced.

  Further, when the contact between the p-type base layer and the n-type emitter layer is considered as a cathode short circuit, the same effect as increasing the lateral resistance of the cathode short circuit when the width of the buried gate portion is widened (in terms of injection efficiency, the emitter in a broad sense). This is equivalent to reducing the cathode short-circuit rate in the region). As a result, the injection efficiency increases and the on-voltage decreases. However, if the width of the buried gate portion becomes too wide, the number of on-channels per unit area decreases, and as a result, the electron current resistance increases, so that the injection efficiency decreases and the on-voltage increases.

  FIG. 24 is a model of emitter width 2W = 1 μm, buried gate portion depth D = 5 μm, hole lifetime τp = 2.0 μsec, and anode / cathode when the width C-W of the buried gate portion is changed. It is the result of calculating | requiring the element current density in the voltage between 2.6V. The current increases rapidly when the width of the buried gate portion is about 1 μm to 5 μm, but reaches a peak at 10 μm to 15 μm. The reason why the width of the buried gate where the current saturates is wider than when τp = 30 μsec is that the absolute value of the current flowing through the element is small (about 1/10).

  FIG. 25 shows a model with an emitter width of 2 W = 1 μm, a buried gate portion depth D = 5 μm, and a hole lifetime τp = 2 μsec. When the buried gate portion width 2 (C−W) is 1 μm (A), FIG. FIG. 6 is a plot of current characteristics when the forward voltage between the anode and the cathode is changed in the case of 15 μm (B).

  As shown in the figure, the current crosses when the anode-cathode voltage is 13V. Below 13V, the model with a buried gate portion width of 15 μm has a larger current value, and especially at 2V or less, the current value is one digit larger. Above 13V, the magnitude of the current value is reversed.

26 shows a device model of FIG. 30 in which the IGBT device model of FIG. 20 is changed to the device structure of the second embodiment, and the emitter width 2W = 3 μm and the buried gate portion width 2 (C−W) = 13 μm, embedded gate depth D = 12.5 μm, p-type base layer depth 2.5 μm, n-type source layer depth 1 μm, p-type drain layer depth 0.5 μm, hole lifetime τp = It is a current-voltage characteristic when it is set to 1.85 μsec. Τp is set so that the device current becomes 100 A / cm ² when the anode-cathode voltage is 2.6V.

Similarly, FIG. 27 shows a turn-off waveform with a resistive load from the current density Iak = 5223 [A / cm ² ] and Vak = 25 V in the model of FIG. The gate voltage is changed from +15 V to −15 V at a gate voltage increase rate dVG / dt = −30 [V / μsec].

By the way, assuming that the carrier concentration just below the emitter region at 100 A / cm ² is 1 × 10 ¹⁶ / cm ³ , the holes with an emitter width W = 1.5 μm and a buried gate portion depth D = 12.5 μm. The current resistance is
Rp = 0.5 × 12.5 × 10 ⁻⁴ ÷ 1.5 × 10 ⁻⁴ = 4.2Ω (9)
When the electron current resistance is Rn = 1Ω, the injection efficiency is γ = 0.81.

  As is clear from the above data, it can be seen that by optimizing the shape of the emitter region including the buried insulating gate portion, the on-resistance as low as that of the thyristor can be realized without performing the thyristor operation.

  In the conventional method, the emitter layer is composed of a single high-concentration impurity diffusion layer, and carriers are injected from this emitter diffusion layer into the high-resistance base layer. The present invention provides a structure for controlling the flow of MOS channel and carrier discharge for carrier injection and discharge into a high resistance base instead of a conventional single high concentration impurity diffusion layer (ie, carrier discharge resistance or diffusion current locally). In other words, the present invention relates to a structure that achieves high implantation efficiency without using a conventional high-concentration impurity diffusion layer.

  In the present invention, the p-base short-circuit resistance on the cathode side tends to be proportional to the distance 2D + 2 (C−W) straddling adjacent buried gate portions and inversely proportional to the emitter width 2W. Therefore, the following parameter X is introduced.

X = {2D + 2 (C−W)} / 2W
= {D + (C−W)} / W (10)
This parameter X is an amount representing how far the cathode-side hole bypass or drain layers are separated from each other. The smaller the parameter X, the smaller the cathode-side hole discharge resistance (short-circuit resistance).

  FIG. 28 shows the current density flowing through the element when the lifetime τp of the element and the aforementioned D, C, and W are changed, with the parameter X as the horizontal axis. The white circle is when C is changed with τp = 30 μsec, W = 0.5 μm and D = 5 μm, and the black circle is when D is changed with τp = 2 μsec, W = 0.5 μm and C = 1 μm. The double circle is the one when τp = 2 μsec, W = 1.5 μm, C = 8 μm, D = 15 μm, and the x mark changes D with τp = 2 μsec, W = 0.4 μmec, C = 1 μm Is.

In order to secure a current capacity of 100 A / cm ² with an element having a forward breakdown voltage of 4500 V, for example, W = 0.5 μm, D = 2 μm, C = 1 μm,
X ≧ 5
Is necessary. Further, from the data of FIGS. 22 to 28, when W = 0.5 μm, D = 5 μm, and C = 1 μm, X = 11, and when W = 1.5 μm, D = 13.5 μm, and C = 8 μm, X to 13. That is, it can be seen that the characteristics are remarkably improved by setting X> 8 or X> 10, more preferably X> 13.

FIG. 29 shows the carrier concentration distribution in the on state in this case together with the corresponding cross section. In the graph on the right, the solid line is the present invention, and the broken line is the conventional example. Compared to the IGBT structure, the present invention is characterized by having a carrier concentration distribution peak on the cathode side of the n ⁻ -type base layer. The carrier concentration of the n-type base layer in the ON state is designed to be about 10 ¹¹ to 10 ¹⁸ / cm ³ , more preferably about 1 × 10 ¹⁵ to 1 × 10 ¹⁸ / cm ³ .

  In addition, the smaller W of dimensions W, D, and C, the larger X becomes and the actual device characteristics are improved. However, as D increases, not only does the hole resistance increase, but the resistance of carriers injected through the on-channel into the high resistance base also increases. For example, when D = 500 μm, the voltage drop due to the resistance of the injected carriers and the voltage drop due to the resistance of the discharged holes become equal, and the total on-voltage of the element becomes high.

  Increasing C increases the current density in the W range and increases the emitter injection efficiency in a broad sense. However, increasing C decreases the number of on-channels per unit area, and increasing C excessively increases the actual density. On-channel resistance increases. As seen in FIG. 28, since the tendency appears when X> 30 μm or more, C is preferably designed to be 500 μm or less.

  FIG. 31 is a layout of a buried insulated gate power semiconductor device according to another embodiment of the present invention, and FIGS. 32 and 33 are cross-sectional views taken along lines AA ′ and BB ′ of FIG. 31, respectively.

  In this embodiment, the groove 5 is formed to have a depth that reaches the n-type base layer 1 so as to surround the p-type base layer 4 in a rectangular shape, and a plurality of stripe-shaped grooves 5 are formed in the periphery of the peripheral grooves 5. It is formed continuously. A buried gate electrode 7 is formed in the trench 5 via a gate oxide film 6.

  An n-type turn-off channel layer 8 is formed in the p-type base layer 4 in the stripe region between the grooves 5. In the n-type turn-off channel layer 8, p-type drain layers 9 and n-type source layers 10 are alternately distributed along the longitudinal direction of the groove 5. The p-type drain layer 9 is formed on the surface of the n-type turn-off channel layer 8, and the n-type source layer 10 and the n-type turn-off channel layer 8 are actually the same diffusion layer.

  In the device of this embodiment, the side surface of the groove 5 of the p-type base layer 4 under the n-type emitter layer 10 is a turn-on channel. Further, the side surface of the groove 5 of the n-type turn-off channel layer 8 under the p-type drain layer 9 becomes a turn-off channel. Therefore, as in the previous embodiment, the gate electrode 7 embedded in the trench 5 serves both for turn-on and for turn-off.

  The device of this embodiment is turned on by applying a positive voltage to the buried gate electrode 7 to form an n-type channel on the groove side surface of the p-type base layer 4. When a negative voltage is applied to the buried gate electrode 7, a p-type channel is formed on the side surface of the groove of the n-type turn-off channel layer 8, and the turn-off is performed in the same manner as in the previous embodiments.

According to this embodiment, the same effects as those of the previous embodiments can be obtained. Further, since the element of this embodiment bears the breakdown voltage in the buried gate portion as in the previous embodiment, the impurity concentration of the p-type base layer 4 can be made low. For example, the p-type base layer 4 can have a peak impurity concentration of about 1 × 10 ¹⁶ / cm ^3, and the n-type turn-off channel layer 8 has a peak impurity concentration of about 1 × 10 ¹⁷ / cm ^3. can do. As a result, the threshold required to form the p-type channel on the groove side surface of the n-type turn-off channel layer 8 can be as small as about 5 V, for example, and the off control can be performed with a small gate voltage.

  FIG. 34 is a layout of a buried insulated gate semiconductor device according to another embodiment of the present invention, and FIGS. 35 and 36 are sectional views taken along lines AA ′ and BB ′ in FIG. 34, respectively.

  The device of this embodiment is a so-called electrostatic induction thyristor in which the p-type base layer 4 of the device of the embodiment of FIGS. 31 to 33 is omitted. If the impurity concentration of the n-type base layer 1 and the width of the groove 5 (the width of the n-type base layer 1 sandwiched between the grooves 5 shown in the cross section of FIG. 35) are set to appropriate values, they are sandwiched between the grooves 5. Further, the potential of the entire portion of the n-type base layer 1 can be controlled by the buried gate electrode 7.

  When a positive voltage is applied to the gate electrode 7 to raise the potential of the n-type base layer 1 sandwiched between the grooves 5, electrons are injected from the n-type source layer 10 and the device is turned on. When a negative voltage is applied to the gate electrode 7, a p-type channel is formed on the groove side surface of the n-type turn-off channel layer 8, and carriers in the n-type base layer 1 are discharged to the cathode electrode 13 through the p-type drain layer 9. The device turns off.

  FIG. 37 is a layout of a buried insulated gate semiconductor device according to still another embodiment, and FIGS. 38 and 39 are cross-sectional views taken along lines AA ′ and BB ′ of FIG. 37, respectively.

  This embodiment is a slight modification of the device of the embodiment of FIGS. The plurality of stripe-shaped grooves 5 are independent from each other, and their periphery is surrounded by a deep p-type base layer 4 '. The distribution, depth, and the like of the n-type turn-off channel layer 8, the p-type drain layer 9, and the n-type source layer 10 formed in the p-type base layer 4 between the buried gate portions are the same as in the previous embodiment.

  40 is a layout of a buried insulated gate semiconductor device according to still another embodiment, and FIGS. 41 and 42 are sectional views taken along lines AA ′ and BB ′ in FIG. 40, respectively.

  In this embodiment, the device of the embodiment shown in FIGS. 34 to 35 is modified in the same manner as the embodiment shown in FIGS.

  Also in these embodiments, the same effects as in the previous embodiments can be obtained.

  42 to 44 are embodiments in which the embodiment of FIGS. 31 to 33 is modified to make the p-type base layer 4 deeper than the buried gate portion.

  46 to 48 are embodiments in which the embodiment of FIGS. 43 to 45 is further modified and the n-type turn-off channel layer 8 is omitted.

  49 to 51 show further embodiments in which the p-type base layer is omitted from the structure shown in FIGS.

  Also according to these embodiments, as described above, the shape and size of each part, in particular, the width and interval of the buried gate part are optimally designed to sufficiently increase the injection efficiency of the emitter region in a broad sense and realize a low on-resistance. Can do.

  52 to 55 are embodiments in which the same structure as that of the embodiment of FIGS. 11 to 14 is applied to the IGBT. An n-type source layer 10 is formed in contact with the side surface of the groove 5, and the cathode electrode 1 is simultaneously in contact with the n-type source layer 10 and the p-type base layer 4 exposed therebetween.

  56 to 58 show an embodiment in which the structure shown in FIGS. 37 to 39 is similarly applied to an IGBT.

  FIG. 59 is a modification of FIG. If the width 2 (C-W) of the buried gate portion is too large with respect to the emitter width 2W, the reliability of the groove processing is lowered. In such a case, the yield can be improved by forming a plurality of grooves that are essentially one. No p-type base or n-type source is formed in the n-type base layer portion exposed in the width 2 (C-W).

60 to 62 are layouts of unit cell portions of the embodiment in which the present invention is applied to a lateral IGBT and sectional views taken along the lines AA ′ and BB ′. The wafer obtained by directly bonding the first silicon substrate 20 and the second silicon substrate 22 with the oxide film 21 in between is used as the element region on the second silicon substrate 22 side and processed into a predetermined thickness. N-type base layer 1. A groove 5 having a depth reaching the bottom oxide film 21 is formed in the n-type base layer 1, and a gate electrode 71 is buried therein. A p-type base layer 4 and an n-type source layer 10 are formed between the buried gates, and a surface gate electrode 72 which is continuous with the buried gate electrode 7 is formed thereon via a gate oxide film 6. A p-type emitter layer 3 is formed at a position away from the buried gate portion by a predetermined process. A p ⁻ type RESURF layer 23 is formed between the p type emitter layer 3 and the buried gate portion.

FIG. 63 to FIG. 65 are a layout of an embodiment of a lateral IGBT in which the above embodiment is modified and a buried gate is provided on the anode side, and AA ′ and BB ′ sectional views thereof. Using the second substrate 22 on the element forming side as the p ⁻ -type base layer 24, the trench 5 is formed in the same manner as in the above embodiment, and the buried gate electrode 71 is formed therein. An n-type base layer 1 'and a p-type drain layer 3' are formed between the trenches, and a surface gate electrode 72 is formed thereon as in the above embodiment. An n-type source layer 10 'is formed at a predetermined distance from the drain region.

  66 to 68 are layouts of an embodiment in which the same element as that of the embodiment of FIGS. 1 to 5 is realized as a lateral element, and AA ′ and BB ′ sectional views thereof. Portions corresponding to those of the previous embodiment are denoted by the same reference numerals as those of the previous embodiment, and detailed description thereof is omitted.

  69 to 71 are element layouts of the embodiment in which the conductivity types of the respective parts of the above embodiment are reversed and their AA 'and BB' sectional views.

  In the embodiment of FIG. 31, the width dN + of the n-type source layer and the width dP + of the p-type drain layer are shown to be substantially equal. However, if dN +> dP +, the on-characteristic is improved and dN + <dP +. Off characteristics are improved. Therefore, desired characteristics can be obtained by optimally designing these width relationships. The same applies to the elements shown in FIGS. 34, 37, 40, 43, 46, 49, and 56.

  In order to increase the controllable maximum current, it is desirable to form dN + to be about the carrier diffusion length or less, and when it is desired to reduce the on-voltage, it is necessary to increase this to the extent that the minimum controllable maximum current can be guaranteed. desirable.

  As described above, according to the present invention, a deep buried insulated gate structure, a structure in which narrow hole current paths sandwiched between the buried insulated gates are formed at wide intervals, and a cathode emitter structure in which injection efficiency is kept small. By combining these, it is a voltage driven type element, and it is possible to realize the same characteristics as a GTO thyristor without latching up.

  Several further embodiments of the lateral element will be described.

  72 to 74 are examples in which the elements of the examples of FIGS. 66 to 68 are modified. In this embodiment, the p-type drain layer 9 is provided not only in the region sandwiched between the buried gates 72 but also extending to the cathode side end side wall of the buried gate 72.

  75 to 77 show an embodiment in which the structure shown in FIGS. 72 to 74 is modified. The n-type emitter layer 8 is diffused to a depth that does not reach the bottom of the device.

78 to 80, the p ⁻ type substrate having the p ⁺ type layer 25 at the bottom is used as the second substrate 22 and the n ⁻ type base layer 1 is formed on the surface thereof. This is the same as the embodiment of FIG.

  FIGS. 81 to 83 are modifications of the embodiment shown in FIGS. 78 to 80. The width of the surface gate electrode 72 is selected larger than the width of the buried gate electrode 71, and the region sandwiched by the buried gate electrode 71 is used. In this embodiment, a turn-on channel region and a turn-off channel region controlled by the surface gate electrode 72 are formed on the cathode side separated by a predetermined distance.

  FIG. 84 and subsequent figures show a half-cell cross-sectional structure of another embodiment of the vertical element.

  FIG. 84 shows an embodiment in which a buried gate as shown in FIG. 59 is not provided in a region (shown by width L) between regions (shown by width W) where a long electron injection channel is formed.

  FIG. 85 shows an example in which a buried insulated gate structure is formed also in a region where an electron injection channel is not formed in the element of FIG. The gate electrode 7 is continuously formed along the plurality of grooves 5 without completely filling the grooves 5. A CVD oxide film 31 is formed so as to flatten the surface by filling the groove 5 in the element surface on which the gate electrode 7 is formed.

  FIG. 86 shows an example in which the p-type layer 32 is formed between the grooves in which the electron injection channel of the element of FIG. 84 is not formed. By providing the p-type layer 32, the breakdown voltage between the cathode electrode 11 and the n-type base layer 1 in a region where no channel is formed can be made sufficient.

  In FIG. 87, in the element structure of FIG. 86, the gate electrode 7 is formed of a polycrystalline silicon film so as not to completely fill the groove 5, and is overlapped with Al, Ti, Mo, etc. in a region where the channel is not formed. The low-resistance metal gate 33 is formed. The low resistance metal gate 33 is covered with an organic insulating film 34 such as polyimide.

  FIG. 88 further shows that a trench 5 is formed in the entire region where a channel is not formed, a polycrystalline silicon gate electrode 7 is formed along the trench 5, and a low-resistance metal gate 33 is buried at the bottom of the trench 5. This is an example.

  In each of the embodiments described above, in order to increase the hole current bypass resistance in the channel region sandwiched between the buried gates, n carrier having a higher concentration than the low carrier lifetime layer or the n-type base layer by ion implantation or the like. It is also effective to provide a mold layer or the like.

  For example, FIG. 89 shows an embodiment in which an n-type layer 35 having a higher concentration than the n-type base layer 1 is provided below the p-type base layer 4 in the element of FIG. FIG. 90 shows an example in which the low carrier lifetime layer 36 is formed under the p-type base layer 4.

FIG. 91 shows an embodiment in which the structure of FIG. 87 is modified, in which a floating n ⁺ -type emitter layer 36 is formed on the p-type layer 32. The electron injection portion has no p-type drain and has an IGBT structure. When a positive voltage is applied to the gate electrode 7, a channel is formed between the n-type source layer 10 and the n ⁺ -type emitter layer 36 along the sidewall of the groove 5. Are formed, and the n ⁺ -type emitter layer 36 is connected to the cathode electrode 11.

  FIG. 92 is an embodiment in which the element shown in FIG. 86 is similarly modified as in FIG.

  FIG. 93 is an example in which the p-type layer 32 formed simultaneously with the p-type base layer 4 is provided between the grooves outside the electron injection channel region in the device of the example of FIG. Further, FIG. 94 shows an embodiment in which the p-type layer 32 of FIG. 93 is formed deeper than the p-type base layer 4 and a floating n-type emitter layer 36 is formed thereon.

FIG. 95 shows an embodiment in which the p-type layer 32 and the n ⁺ -type emitter layer 36 of FIG. 91 are formed deeper to shorten the turn-on channel controlled by the buried gate 27.

  Each of the above-described embodiments is based on the concept of “increasing hole bypass resistance with a uniquely arranged trench gate electrode structure, thereby improving electron injection efficiency and reducing the on-resistance of the semiconductor device”. The important fact to note here is that, according to the present invention, achieving a reduced on-resistance does not have to be inherent in “increasing the hole-bypass resistance”. This is because the enhancement of carrier injection is based on the principle of “increasing the ratio of the hole diffusion current and the electron current” which includes the idea of “increasing the hole bypass resistance”.

  FIG. 96 is a layout of an IEGT (injection-enhanced gate bipolar transistor) according to a further embodiment of the present invention. FIGS. 97, 98, 99 and 100 are respectively taken along lines A-A 'and B-- of FIG. It is B ', CC', and DD 'sectional drawing. In this transistor structure, parts similar to those in the embodiment of FIGS. 6 to 9 are given the same reference numerals.

The n-type source layer is composed of the n ⁺ -type semiconductor layer 10. These source regions 10 extend at right angles to the trench gate electrode 7 in the surface portion of the p-type drain layer 4 as shown in FIG. A cross section of the source region 10 relating to the trench gate electrode 7 is shown in FIG. The n ⁺ -type layer 10 positioned between each pair of two adjacent trench gate electrodes 7 is electrically insulated from the first main electrode layer 11 by the surface insulating layer 202.

As shown in FIG. 98, between adjacent trench gate electrodes 7, n ⁺ -type layers 10 are alternately arranged with p ⁺ -type layers 9 functioning as p-type drains. The sectional view of each trench gate electrode 7 shown in FIG. 99 is the same as that of FIG. A cross-sectional view of the p ⁺ -type drain region 9 in a direction perpendicular to the trench gate electrode 7 is shown in FIG. Here, the p-type drain layer 9 located between each pair of two adjacent trench gate electrodes 7 in the manner similar to the case of FIG. 97 is formed into the first main electrode layer 11 by the surface insulating layer 202. Is electrically isolated from. The specific dimensions of this transistor structure may be similar to those in the devices of FIGS.

  The operation of IEGT in this embodiment is as follows. When a positive voltage is applied to the gate electrode 7 with respect to the cathode electrode 11, the turn-on channel located in the periphery of the p-type base layer 4 becomes conductive. Electrons are injected from the n-type source layer 10 into the n-type base layer 1 and cause conductivity modulation in the n-type base layer 1. As a result, IEGT is turned on by the IGBT operation.

  When a negative voltage is applied to the gate electrode 7 with respect to the cathode electrode 11, the injection of electrons from the turn-on channel region stops. An inversion layer is formed on the side surface portion (groove side surface portion) facing the trench 5 of the trench gate portion. Carriers in the p-type base layer 4 are discharged to the cathode electrode 11 through the p-type drain layer 9 by a known p-channel MOS transistor operation. The semiconductor device is turned off. In this embodiment, the parasitic thyristor constituted by the n-type source layer 10, the p-type base layer 4, the n-type base layer 1 and the p-type emitter layer 3 is prevented from being latched up even when the device is turned on. It is especially arranged as described in If the on-channel is closed, the electron injection from the n-type source layer 10 is immediately stopped.

According to IEBT, a pair of trench gates 7, a P ⁺ -type drain layer 9 positioned between the pair of trench gate electrodes and insulated from the electrode 11, and the insulated P ⁺ -type drain layer A “unit cell” is defined by another P ⁺ -type drain layer 9 that is adjacent to and in contact with the electrode 11 with the corresponding trench gate electrode 7 interposed therebetween.

A wide trench groove (2C-2W) is formed by forming a region surrounded by a relatively narrow trench groove and insulated from the electrode 11 between the p ⁺ drain layer in contact with the electrode 11. It is possible to avoid the technical difficulty of doing so and to achieve the same effect as a wide trench.

  By appropriately arranging the depth, interval, and number of the plurality of trench gate electrodes 7 (specific examples have already been presented), a sufficiently low on-resistance can be obtained while preventing the device from operating as a thyristor. The “thinned-out” contact of the IEGT main electrode 11 to the p-type drain layer 9 contributes to the reduction of the hole bypass current, ie the realization of a reduced on-resistance. In this embodiment, the parasitic thyristor does not latch up in the ON state, and the turn-off channel is opened at the time of turn-off to form a bypass path for the hole flow. Therefore, the maximum breaking current capability is enhanced as compared to current GTO thyristors that are configured to turn off once latched up.

  Here, a description will be given of the fact that a large electron injection efficiency can be obtained by arranging the ratio of the hole diffusion current to the total current.

  When the impurity concentration in the broad emitter region (an example is shown in a portion surrounded by a broken line in FIG. 21) is relatively low, for example, when there is a portion that causes n to p conduction modulation in the broad emitter region. A structure that increases the ratio of the hole diffusion current Ip, particularly the longitudinal direction (diffusion current flowing parallel to the anode-cathode direction of the element) and the electron current In (= I-Ip, I: total current). By providing it in the broad emitter region, the injection efficiency of the broad emitter region can be increased and the on-resistance of the element can be reduced.

The hole current Jp (A / cm ² ) flowing in the emitter region in the broad sense and the emitter-side carrier concentration n (cm ⁻³ ) in the broad sense of n-base (n in FIG. 29).

If the hole current flowing in the emitter region in a broad sense is only the diffusion current of carriers in the vertical direction (AK direction),
Jp = 2 · μp · k · T · W · n / (C · D) (12)
Can be expressed as Here, μp is the hole mobility, k is the Boltzmann coefficient, and T is the temperature.

The hole injection efficiency γp in the emitter region in the broad sense is γp = Jp / J = Jp / (Jn + Jp)
= 2μp · k · T · W · n / (C · D · J) (13)
If Y = W / (C · D),
γp = 2 (μp · k · T · n / J) · Y
The values of γp are as follows: μp = 500, k · T = 4.14 × 10 ⁻²¹ , J = 100 A / cm ²
γp = 2 × (500 × 4.14 × 10 ⁻²¹ / 100) × 1 × 10 ¹⁶ × Y
= 4.14 × 10 ⁻⁴ · Y (16)
When γp is sufficiently low in injection efficiency, γp = Jp / (Jn + Jp) = μp / (μn + μp) = 0.3 (17)
It will be about. In other words, the injection efficiency of the emitter region in a broad sense is high.
γp <0.3 (18)
Therefore, Y that satisfies this condition is
4.14 × 10 ⁻⁴ · Y <0.3
Y <0.3 / 4.14 × 10 ⁻⁴
Y <7.25 × 10 ² (cm ⁻¹ ) (19)
When n = 7 × 10 ¹⁵ when the on-voltage is relatively high,
Y <1.0 × 10 ³ (cm ⁻¹ ) (20)
It is.

  That is, by designing the parameter Y within the above range, the injection efficiency of the emitter region in a broad sense can be increased even if the injection efficiency of the impurity diffusion layer in contact with the cathode electrode is low. That is, the accumulation of carriers in the on state of the high resistance base layer can be increased, and the on resistance of the element can be decreased.

  When the elements are arranged in this manner, the cathode diffusion layer having a low injection efficiency ensures high current control capability, high-speed switching, and increases the injection efficiency of the emitter region in a broad sense, which is the effect of the present invention. Resistance can also be realized at the same time.

  When the emitter region in a broad sense has a trench structure as shown in FIG. 20, the value of Y is determined by D, C, and W in FIG. 20 as described above.

  In addition, when a high impurity concentration (Jp flows by resistance) and a low impurity concentration coexist in the emitter region in a broad sense, the injection efficiency of the emitter region in the broad sense has both the parameters X and Y described above. It is necessary to consider.

The cross-sectional structure of FIG. 100 is modified as shown in FIG. Here, the n ⁺ -type source layer 10 extends so as to be joined to both end faces of each trench 5 in which the trench gate electrode 7 is embedded.

The IEGT shown in FIGS. 102 to 106 is basically a combination of the devices of FIGS. 96 to 100 and the devices of FIGS. In other words, this IEGT is characteristically different from FIGS. 96 to 100 in that each p ⁺ type drain layer 9 has a “ladder type planar shape”. In particular, the n-type source layer 10 described in FIG. 7 is formed on the surface portion of the p ⁺ -type base layer 4. In the n-type source layer 10, the p-type drain layer 9 is arranged so as to be joined to both upper side end portions of each trench 5. The p-type drain layer 9 is shallower than the n-type source layer 10. The portion of the n-type source layer 10 sandwiched between the bottom of the p-type drain layer 9 and the p-type drain layer 4 functions as the n-type turn-off channel layer 10 described with reference to FIG. A central portion of the n-type source layer 10 between two adjacent trench gate electrodes 7 corresponds to the n-type source layer 10 in FIG. When viewed on the substrate surface, the p-type drain layer 9 planarly surrounds the n-type source layer 10 between two adjacent trench gate electrodes 7, thereby exhibiting a ladder-type planar shape.

As shown in FIG. 104, the n-type source layer 10 is deeper than the p ⁺ -type drain layer 9, and therefore the n-type source layer 10 is formed of the p ⁺ -type drain in view of the cross-sectional structure shown here. Surrounding layer 9. The cross-sectional structure of each trench gate electrode 7 shown in FIG. 105 is the same as that of FIG. As shown in FIG. 106, the p ⁺ -type drain layer 9 is “thinned out” by the surface insulating layer 202 and is in contact with the electrode 11.

  According to the IEGT of this embodiment, the trench junction side surface portion of the p-type base layer 4 located immediately below the n-type turn-off channel layer functions as a turn-on channel. Therefore, it can be said that both of the plurality of trench gate electrodes 7 serve as both the turn-on drive electrode and the turn-off drive electrode. That is, a turn-off p-channel MOSFET and a turn-on n-channel MOSFET are vertically stacked inside the device. When a positive voltage is applied to the trench gate electrode 7, an n-type channel is formed on each trench junction side surface of the p-type base layer 4, thereby turning on the device. At this time, electrons are injected from each n-type source layer 10 into the n-type base layer 1 via the n-type channel formed by the n-type turn-off channel and the inversion layer formation. The turn-off operation is performed by applying the negative voltage to the trench gate electrode 7 with the same manner as in the embodiment 200 of FIGS. According to the IEGT of this embodiment, the same effects as those of the embodiments of FIGS. 96 to 100 can be obtained.

  Finally, two variations of the lateral IGBT disclosed in FIGS. 60 to 83 are presented in FIGS. 107 to 202. The characteristic difference between the lateral IGBT of FIGS. 107 to 109 and the previous example of the IGBT of FIGS. 110 to 112 is that the difference in cell structure parameters “C” and “W” is set along the thickness direction of the substrate. It is in the point.

As shown in FIGS. 108 and 109, a trench 222 having a generally uniform rectangular cross-sectional shape is formed on the surface of the n ⁻ -type upper substrate on the intermediate insulating layer 21. The conductive layer 224 is embedded in the trench 222 in an insulating manner. The thickness of the conductive layer 224 is greater than the depth of the trench 222, so that the upper half of the conductive layer 224 protrudes from the upper substrate surface. The conductive layer 224 functions as a trench gate electrode. The thickness of the upper substrate is C. As shown in FIG. 108, the thickness of the trench portion of the information substrate, that is, the thickness of the active layer sandwiched between the bottom portion of the trench 222 and the intermediate insulating layer 21 is W. A channel region for electron injection or turn-off is formed in a portion in contact with the bottom of the trench gate electrode 224.

  In such a lateral IGBT, the turn-off control electrode has a MOS control thyristor (MCT) structure. As in the embodiments of FIGS. 31 to 33, if the p-type drain layer width Dp and the n-type source layer width Dn are set to Dp <Dn, the on characteristics are enhanced, and if Dp> Dn, the turn-off characteristics are obtained. Strengthened. If the width relationship of these layers is optimally arranged, the desired IGBT on / off characteristics can be easily realized. In order to increase the maximum controllable current of the IGBT, it is desirable to form the width Dn to be about the carrier diffusion length or less. In order to lower the on-voltage, it is desirable to increase the width Dn within a range that can guarantee the minimum required level of the maximum controllable current.

  According to this IGBT, a structure formed with a wide interval between narrow (W) hole current paths sandwiched between the trench gate electrode structure 224 and the intermediate insulating film 21, and the injection efficiency are suppressed to a low level. By combining the cathode-emitter structure, it is possible to realize a voltage-driven power switch device in which the on-voltage is lowered as in the current GTO thyristor while achieving suppressed latch-up.

The lateral IGBTs of FIGS. 110-112 are similar to those of FIGS. 107-109 except that an n-type hole bypass resistor layer 226 is added. The hole bypass resistor layer 226 is formed at the bottom of the trench gate electrode 224 and is in contact with the n ⁺ -type layer 10 as shown in FIG. If the impurity concentration of the hole bypass resistance layer 226 is high (for example, about 10 ¹⁶ to 10 ²¹ cm ⁻³ ), the on-characteristic of the IGBT is improved. If the impurity concentration of the hole bypass resistance layer 226 is low (for example, about 10 ¹³ to 10 ¹⁸ cm ⁻³ ), a moderate improvement of the on-state characteristics can be expected while maintaining the IGBT off-state characteristics high.

  In addition, the present invention can be implemented with various modifications without departing from the spirit of the present invention.

1 is a layout diagram of an insulated gate semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line AA ′ in FIG. 1. BB 'sectional drawing of FIG. CC 'sectional drawing of FIG. DD 'sectional drawing of FIG. The layout diagram of the insulated gate semiconductor element of another Example. AA 'sectional drawing of FIG. BB 'sectional drawing of FIG. CC 'sectional drawing of FIG. The layout diagram of the insulated gate semiconductor element of another Example. FIG. 11 is a cross-sectional view taken along line AA ′ of FIG. 10. BB 'sectional drawing of FIG. CC 'sectional drawing of FIG. The layout diagram of the insulated gate semiconductor element of another Example. AA 'sectional drawing of FIG. BB 'sectional drawing of FIG. CC 'sectional drawing of FIG. Sectional drawing which shows the unit cell structure of the insulated gate semiconductor element of another Example. FIG. 19 is a diagram showing an impurity concentration distribution of AA ′ and BB ′ in the element of FIG. 18. Sectional drawing of the embedded insulated gate type IBGT of a simulation model. The figure for demonstrating the principle of operation of the model of FIG. The figure which shows the relationship between the depth of the embedded gate part of this model, and current density. The figure which shows the relationship between the width | variety of the embedded gate part of this model, and current density. The figure which shows the relationship between the width | variety of a buried gate part on the other conditions of the model, and current density. The figure which shows the current-voltage characteristic of the model. The figure which shows the current-voltage characteristic on other conditions of the model. The figure which shows the electric current and voltage change characteristic of the model. The figure which shows the relationship between parameter X (D, W, C) and carrier lifetime (tau) p, and the current density of an element. The figure which shows carrier concentration distribution in the ON state of an element. The figure which shows the structure which applied the model to the element of the Example of FIG. The layout diagram of the insulated gate semiconductor element of another Example. FIG. 32 is a cross-sectional view taken along the line AA ′ in FIG. 31. BB 'sectional drawing of FIG. The layout diagram of the insulated gate semiconductor element of another Example. AA 'sectional drawing of FIG. BB 'sectional drawing of FIG. The layout diagram of the insulated gate semiconductor element of another Example. AA 'sectional drawing of FIG. BB 'sectional drawing of FIG. The layout diagram of the insulated gate semiconductor element of another Example. AA 'sectional drawing of FIG. BB 'sectional drawing of FIG. The layout diagram of the insulated gate semiconductor element of another Example. AA 'sectional drawing of FIG. BB 'sectional drawing of FIG. The layout diagram of the insulated gate semiconductor element of another Example. FIG. 47 is a cross-sectional view taken along line AA ′ of FIG. 46. FIG. 47 is a sectional view taken along line BB ′ in FIG. 46. The layout diagram of the insulated gate semiconductor element of another Example. AA 'sectional drawing of FIG. BB 'sectional drawing of FIG. The layout diagram of the insulated gate semiconductor element of another Example. FIG. 53 is a cross-sectional view taken along line AA ′ in FIG. 52. FIG. 53 is a sectional view taken along line BB ′ in FIG. 52. CC 'sectional drawing of FIG. The layout diagram of the insulated gate semiconductor element of another Example. AA 'sectional drawing of FIG. BB 'sectional drawing of FIG. The figure which shows the modification of FIG. The layout diagram of the insulated gate semiconductor element of another Example. FIG. 61 is a cross-sectional view taken along the line AA ′ in FIG. 60. BB 'sectional drawing of FIG. The layout diagram of the insulated gate semiconductor element of another Example. FIG. 64 is a cross-sectional view taken along the line AA ′ of FIG. 63. FIG. 64 is a BB ′ cross-sectional view of FIG. 63. The layout diagram of the insulated gate semiconductor element of another Example. FIG. 66 is a cross-sectional view taken along the line AA ′ of FIG. 66. FIG. 66 is a sectional view taken along line BB ′ in FIG. 66. The layout diagram of the insulated gate semiconductor element of another Example. FIG. 70 is a cross-sectional view taken along line AA ′ of FIG. 69. FIG. 70 is a sectional view taken along line BB ′ of FIG. 69. The layout diagram of the insulated gate semiconductor element of another Example. FIG. 73 is a cross-sectional view taken along the line AA ′ of FIG. 72. FIG. 73 is a sectional view taken along line BB ′ of FIG. 72. The layout diagram of the insulated gate semiconductor element of another Example. FIG. 76 is a cross-sectional view taken along line AA ′ of FIG. 75. FIG. 76 is a sectional view taken along line BB ′ in FIG. 75. The layout diagram of the insulated gate semiconductor element of another Example. FIG. 79 is a cross-sectional view taken along the line AA ′ of FIG. 78. FIG. 79 is a sectional view taken along line BB ′ of FIG. 78. The layout diagram of the insulated gate semiconductor element of another Example. FIG. 82 is a cross-sectional view taken along line AA ′ of FIG. 81. FIG. 82 is a sectional view taken along line BB ′ in FIG. 81. The figure which shows the 1/2 cell cross-section of another Example. The figure which shows the 1/2 cell cross-section of another Example. The figure which shows the 1/2 cell cross-section of another Example. The figure which shows the 1/2 cell cross-section of another Example. The figure which shows the 1/2 cell cross-section of another Example. The figure which shows the 1/2 cell cross-section of another Example. The figure which shows the 1/2 cell cross-section of another Example. The figure which shows the 1/2 cell cross-section of another Example. The figure which shows the 1/2 cell cross-section of another Example. The figure which shows the 1/2 cell cross-section of another Example. The figure which shows the 1/2 cell cross-section of another Example. The figure which shows the 1/2 cell cross-section of another Example. The layout diagram of IEGT of another Example. AA 'sectional drawing of FIG. FIG. 96 is a cross-sectional view taken along the line BB ′ of FIG. FIG. 96 is a cross-sectional view taken along the line CC ′ in FIG. 96. 96 is a cross-sectional view taken along the line DD ′ of FIG. FIG. 100 is a cross-sectional view showing a modification of FIG. 100. The layout diagram of IEGT of another Example. AA 'sectional drawing of FIG. BB 'sectional drawing of FIG. CC 'sectional drawing of FIG. DD 'sectional drawing of FIG. The figure which shows the modification of horizontal type | mold IGBT of FIGS. The figure which shows the modification of horizontal type | mold IGBT of FIGS. The figure which shows the modification of horizontal type | mold IGBT of FIGS. The figure which shows the modification of horizontal type | mold IGBT of FIGS. The figure which shows the modification of horizontal type | mold IGBT of FIGS. The figure which shows the modification of horizontal type | mold IGBT of FIGS.

Explanation of symbols

1 ... n-type base layer,
2 ... n-type buffer layer,
3 ... p-type emitter layer,
4 ... p-type base layer,
5 ... groove,
6 ... Gate oxide film,
7 ... Gate electrode,
8 ... n-type turn-off channel layer,
9 ... p-type drain layer,
10 ... n-type source layer,
11 ... cathode electrode,
12 ... Anode electrode.

Claims (2)

A substrate,
An insulating film formed on the substrate;
A first conductivity type base layer formed on the insulating film;
A second conductivity type emitter layer connected to the first conductivity type base layer;
Periodically formed in the first conductivity type base layer at a predetermined distance from the second conductivity type emitter layer, and buried in each of a plurality of trenches having a depth reaching the insulation film via a gate insulation film. Embedded gate,
A second conductivity type base layer formed in a part of the first conductivity type base layer between adjacent grooves to a depth reaching the insulating film;
A first conductivity type source layer formed on a part of the surface of the second conductivity type base layer;
A surface gate formed on the first conductivity type base layer, the second conductivity type base layer, and the first conductivity type source layer through a gate insulating film and electrically connected to the buried gate;
A semiconductor element comprising: a main electrode formed in contact with the second conductivity type base layer and the first conductivity type source layer. 2. The resurfacing layer according to claim 1, further comprising a second conductivity type resurf layer provided in a surface region of the first conductivity type base layer between the second conductivity type emitter layer and the buried gate . Semiconductor element.

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