JPH0974197A - High withstand voltage semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase channel density and obtain high withstnd property excel lent in on-characteristics, by forming two or more channel regions, in MOS structure constituted of a gate insulating film, a gate electrode, a source region, a base region and an active region. SOLUTION: An insulating film 2 is formed on a semiconductor substrate 1. An active region 3 is formed on the film 2, A drain region 5 and a base region 9 are formed on the surface of the active region 3. Source regions 8a-8c are formed on the surface of the base region 9. Trenches 10a, 10b are formed penetrating the base region 9. Gate insulating films 11a, 11b and gate electrodes 12a, 12b are formed in the trenches 10a, 10b. In the MOS structure constituted of the gate insulating film 11a 11b, the gate electrodes 12a, 12b, the source region 8, the base region 9 and the active region 3, two or more channel regions are formed. Thereby the channel density is increased, the resistance of the whale channel region is reduced, and excellent on-resistance can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor device having a MOS structure such as a lateral IGBT and a lateral power MOSFET.

[0002]

2. Description of the Related Art An IGBT (Insulated Gate Bipolar Transistor) is known as one of high breakdown voltage semiconductor devices having a MOS structure.
or) The IGBT is a new high breakdown voltage semiconductor element having both the high speed switching characteristic of a power MOSFET and the high output characteristic of a bipolar transistor, and has been widely used in the field of power electronics such as an inverter and a switching power supply in recent years.

FIG. 1 is a sectional view showing the element structure of a conventional lateral IGBT. In FIG. 1, reference numeral 81 denotes a silicon substrate, and an n-type silicon active layer 83 having a low impurity concentration (high resistance) is provided on the silicon substrate 81 via a silicon oxide film 82. These silicon substrate 81, silicon oxide film 82, n-type silicon active layer 83
Constitutes an SOI substrate. An n-type silicon layer 90 having a high impurity concentration (low resistance) is formed on the bottom of the n-type silicon active layer 83.

A p-type base layer 89 is selectively formed on the surface of the n-type silicon active layer 83, and a high impurity concentration n-type source layer 88 is formed on the surface of the p-type base layer 89.
Are selectively formed.

A gate insulating film (not shown) having a thickness of about 60 nm is formed on the p-type base layer 89 sandwiched between the n-type source layer 88 and the n-type silicon active layer 83.
A gate electrode 91 is provided on this gate insulating film. The source electrode 87 is arranged so as to contact the n-type source layer 88 and the p-type base layer 89.

An n-type buffer layer 84 is selectively formed on the surface of the n-type silicon active layer 83 separated from the p-type base layer 89 by a predetermined distance, and the drain is formed on the surface of the n-type buffer layer 84. A high impurity concentration p-type drain layer 85 provided with an electrode 86 is selectively formed.

The operation of the lateral IGBT constructed as described above is as follows.

At the time of turn-on, a positive voltage with respect to the source electrode 87 is applied to the gate electrode 91. Gate electrode 9
When a positive voltage is applied to 1, the channel region on the surface of the p-type base layer 89 below the gate electrode 91 becomes conductive, and electrons are injected from the n-type source layer 88 to the n-type silicon active layer 83. At the same time, holes are injected from the p-type drain layer 85 into the n-type silicon active layer 83. As a result, n
The type silicon active layer 83 has conductivity and has a low resistance, and a main current flows between the drain and the source.

On the other hand, at the time of turn-off, the source electrode 87
A negative voltage is applied to the gate electrode 91. When a negative voltage is applied to the gate electrode 91, the channel region on the surface of the p-type base layer 89 below the gate electrode 91 becomes non-conductive, and electrons are transferred from the n-type source layer 88 to the n-type silicon active layer 83. Not injected. As a result, the n-type silicon active layer 83 does not cause conduction modulation, and eventually the main current does not flow between the drain and the source.

By the way, this type of lateral IGBT has the following problems. That is, at turn-on,
By applying a positive voltage to the gate electrode 91, the p-type base layer 8
Although the channel region on the surface of 9 is made conductive, the voltage drop occurring in this channel region is large and the on-voltage becomes high.

FIG. 2 is a sectional view showing the element structure of another conventional lateral IGBT. This lateral IGBT is shown in Fig. 1.
The first difference from what is shown in FIG. 3 is that a trench gate structure is adopted. That is, the silicon oxide film 8
A gate electrode 97 is embedded in the trench groove reaching 2 via a gate insulating film 93.

The second difference is that the n-type source layer 8
8, a p-type diffusion layer 94 having a high impurity concentration is selectively formed on the surface of the p-type base layer 89 closer to the p-type drain layer 85.

According to this lateral IGBT, the holes in the device flow into the source electrode 87 through the p-type diffusion layer 94, so that there is an advantage that the latch-up withstand capability is higher than that of the lateral IGBT of FIG.

However, even in the trench gate structure, the area of the channel region (channel density) is the same as that of the lateral IGBT shown in FIG. 1, so that the problem of high ON voltage has not been solved.

[0015]

As described above, the conventional lateral IGBT has a problem that the ON voltage becomes high due to the voltage drop in the channel region.

An object of the present invention is to provide a high breakdown voltage semiconductor device having excellent on-characteristics.

Another object of the present invention is to provide a high withstand voltage semiconductor device having a low on-voltage and a high latch-up withstand voltage.

[0018]

In order to solve the above-mentioned problems, the present invention (claim 1) provides a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a first film formed on the insulating film. A conductive type active region, a drain region formed on the surface of the active region, a second conductive type base region formed on the surface of the active region and separated from the drain region, and formed on the surface of the base region. The first conductive type source region, the first gate insulating film formed on the inner surface of the first trench penetrating the base region so as to be in contact with the source region and reaching the active region, and the inner surface of the first gate insulating film. A first gate electrode embedded in the first trench in which a first gate insulating film is formed, and the base region in contact with the source region at a position separated from the first trench. Through the active area A second gate insulating film formed on the inner surface of the reaching second groove, and a second gate electrode embedded in the second groove having the second gate insulating film formed on the inner surface. A source electrode electrically contacting the source region and the base region, and a drain electrode electrically contacting the drain region, the gate insulating film, the gate electrode, the source region, the Provided is a high breakdown voltage semiconductor device having two or more channel regions formed in a MOS structure composed of a base region and the active region.

In the above high breakdown voltage semiconductor element, the present invention (claim 2) is characterized in that the first and second grooves extend substantially parallel to the drain region. I will provide a.

In the above high breakdown voltage semiconductor element, the present invention (claim 3) provides a high breakdown voltage semiconductor element characterized in that the first and second grooves are connected to each other to form a lattice shape.

In the above high breakdown voltage semiconductor element, the present invention (claim 4) provides at least one of the first and second grooves.
One provides a high breakdown voltage semiconductor element characterized by having a zigzag shape.

In the above high breakdown voltage semiconductor element, according to the present invention (claim 5), the first and second grooves are respectively formed.
There is provided a high breakdown voltage semiconductor element comprising a plurality of short grooves arranged obliquely with respect to the extending direction of the drain region.

In the high withstand voltage semiconductor element according to the present invention (claim 6), the first groove is arranged on the drain region side, and the source region is on the drain region side of the first groove. A high withstand voltage semiconductor element is provided.

In the above high breakdown voltage semiconductor element, the present invention (claim 7) provides a high breakdown voltage semiconductor element characterized in that the side walls of the first and second grooves have a plane orientation of approximately {100}. provide.

In the high breakdown voltage semiconductor device according to the present invention (claim 8), the first groove is arranged on the drain region side, and the base on the opposite side of the first groove from the drain region is provided. A high breakdown voltage semiconductor device is provided, in which one channel region is formed in the base region and two channel regions are formed in the base region around the second groove.

In the high breakdown voltage semiconductor element, the present invention (claim 9) provides the high breakdown voltage semiconductor element, wherein the drain region is of the second conductivity type.

In the high breakdown voltage semiconductor element, the present invention (claim 10) provides the high breakdown voltage semiconductor element, wherein the drain region is of the first conductivity type.

In the above high breakdown voltage semiconductor element, according to the present invention (claim 11), the distance from the bottom of the first or second groove to the bottom of the active layer is 1, the distance between the grooves is w, Provided is a high breakdown voltage semiconductor device characterized by satisfying a condition of (l · d / w)> 3.45 × 10 ⁻⁶ cm, where d is a depth of a portion of the groove in contact with the active layer. To do.

In the high breakdown voltage semiconductor element, according to the present invention (claim 12), a dummy groove filled with an insulating film is formed closer to the drain region than the first or second groove. A high withstand voltage semiconductor element is provided.

In the above high breakdown voltage semiconductor device, according to the present invention (claim 13), each of the first and second trenches has a sub-trench connected to them and divided into a plurality of discontinuous trenches. Provided is a high breakdown voltage semiconductor element characterized in that a sub-gate insulating film is formed on the inner surface thereof and a sub-gate electrode is embedded therein.

In the above high breakdown voltage semiconductor device, according to the present invention (claim 14), the diffusion depth of the base region is 3 μm.
Provided is a high breakdown voltage semiconductor element having a thickness of m or less.

In the above high breakdown voltage semiconductor element, the present invention (claim 15) is characterized in that a groove is formed on the surface of the base region and the groove is filled with the source electrode. A high breakdown voltage semiconductor device is provided.

In the high withstand voltage semiconductor device according to the present invention (claim 16), a groove embedded with an insulator or a semiconductor is formed in the active region between the base region and the drain region. Provided is a high breakdown voltage semiconductor device characterized in that a first conductivity type bypass region is formed below the groove.

In the high breakdown voltage semiconductor device of the present invention (claim 1), a plurality of trenches penetrating the base region so as to contact the source region and reaching the active region are formed, and the gate insulating film is formed on the inner surfaces of these trenches. At the same time, the inside of the groove is filled with a gate electrode to form a plurality of MOS structures. With these MOS structures, two or more channel regions are formed in one device. Therefore, the channel density is increased and the resistance of the entire channel region is decreased.

Since the groove forming the MOS structure penetrates the second conductivity type base layer and reaches the first conductivity type active layer, carrier flow is hindered in the area of the active layer near the bottom of the groove. It

Therefore, at the time of turn-on and in the on-state,
In the case of the power MOSFET, carriers having the same polarity as the majority carriers of the first conductivity type source layer, and in the case of the IGBT, carriers having the same polarity and opposite polarities are effectively accumulated in the region of the active layer near the groove bottom. It

This reduces the resistance of the active layer,
A sufficient amount of carriers are supplied to the source layer and its vicinity, so that a channel can be easily formed.

As a result of these comprehensive effects, superior ON characteristics (for example, ON voltage) can be obtained as compared with the conventional case.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 3 is a plan view of a lateral IGBT according to a first embodiment of the present invention. 4 is a cross-sectional view of the lateral IGBT of FIG. 3 taken along the line I-I.

In the figure, reference numeral 1 denotes a silicon substrate, and on this silicon substrate 1, a silicon oxide film 2 is provided,
An n-type silicon active layer 3 having a low impurity concentration is provided. These silicon substrate 1, silicon oxide film 2 and n
The type silicon active layer 3 constitutes an SOI substrate. Further, in the figure, reference numeral 13 indicates an element isolation insulating film.

The SOI substrate in the present invention means a substrate having a semiconductor layer / insulating layer laminated structure, and is an SOI substrate in a broad sense including a substrate having a silicon layer / insulating layer laminated structure.

Here, the thickness of the silicon oxide film 2 is 1 to 5
About μm is preferable. If it is thinner than 1 μm, the withstand voltage will be low, and if it is thicker than 5 μm, the wafer will warp and it will take time to form an oxide film. Further, the film thickness of the n-type silicon active layer 3 is preferably 20 μm or less, and more preferably 10 μm or less in consideration of facilitating element isolation. In addition, the total amount of impurities in the n-type silicon active layer 3 is 1.0 × 10 ¹⁰ to be considered to increase the breakdown voltage.
It is preferably 3.0 × 10 ¹² cm ⁻² , more preferably 0.
It is 5 to 1.8 × 10 ¹² cm ^-2 .

An n-type buffer layer 4 is selectively formed on the surface of the n-type silicon active layer 3, and a high-impurity-concentration p-type drain layer 5 is selected on the surface of the n-type buffer layer 4. And the drain electrode 6 is provided on the p-type drain layer 5.

A p-type base layer 9 is selectively formed on the surface of the n-type silicon active layer 3 which is apart from the p-type drain layer 5 by a predetermined distance. Two trench grooves 10a and 10b penetrating the p-type base layer 9 and reaching the n-type silicon active layer 3 are formed. Gate oxide films 11a and 11b having a thickness of about 20 to 100 nm are formed on the inner surfaces of the trench grooves 10a and 10b, and trench gate electrodes 12a and 1 made of, for example, polysilicon are formed in the trench grooves 10a and 10b.
2b is embedded and formed.

N type source layers 8a, 8b and 8c having a high impurity concentration are selectively formed on the upper sidewalls of the trench grooves 10a and 10b. A source electrode 7 is provided on the n-type source layer 8 and the p-type base layer 9 in the region where the n-type source layer 8 is formed. The source electrode 7 extends to the region of the n-type silicon active layer 3 where the p-type base layer 9 is not formed via the insulating film 50, and thus the source electrode 7 can have a function of a field plate. It is possible to improve the breakdown voltage. In addition, p-type contact layers 51a, 51 having a high impurity concentration are selectively formed in a contact portion between the source electrode 7 and the p-type base layer 9.
b is formed.

These n-type source layers 8a, 8b, 8c, p
Type base layer 9, n type silicon active layer 3, gate oxide film 1
1 and the trench gate electrodes 12a and 12b,
An n-type MOS transistor is formed.

Here, for the trench groove 10a closer to the drain side, the n-type source layer 8a is formed only on the upper side wall opposite to the drain side, while for the trench groove 10b farther to the drain side. , N-type source layers 8b and 8c are formed on both upper side walls.

As shown in FIG. 3, the plane patterns of the trench grooves 10a and 10b are stripe patterns substantially parallel to the longitudinal direction of the p-type drain layer 5. That is, the longitudinal direction of the trench grooves 10a and 10b is substantially parallel to that of the p-type drain layer 5. In other words, the trench grooves 10a and 10b are formed along the p-type drain layer 5. In other words, trench grooves 10a and 10b are formed substantially parallel to the surface of the p-type base layer 9 facing the p-type drain layer 5.

In the lateral IGBT constructed as described above, when a positive voltage with respect to the source voltage is applied to the trench gate electrodes 12a, 12b, the trench grooves 10a, 1 are formed.
The channel region (p-type base layer 9) around 0b becomes conductive.

As a result, the n-type source layers 8a, 8b, 8c
Electrons are injected into the n-type silicon active layer 3 from
Since holes are injected from the p-type drain layer 5 into the n-type silicon active layer 3, the n-type silicon active layer 3 causes conduction modulation, and the element is turned on by the IGBT operation.

At this time, in this embodiment, three n-channel type MOS transistors are formed, which makes it possible to form three parallel channel regions in one element at the time of turn-on and conduction (compared with the conventional one). ), The channel density is higher and the on-voltage is lower than in the past (first point).

Since the longitudinal directions of the trench grooves 10a and 10b are substantially parallel to that of the p-type drain layer 5 as described above, the channel widths of the three parallel channel regions of the n-channel type MOS transistor are the same as those of the conventional one. Will be longer than.

Further, since the trench grooves 10a and 10b block the flow of carriers in the n-type silicon active layer 3 below the trench grooves 10a and 10b, the n-type source layers 8a and 8b are turned on and turned on. , 8c
Electrons injected into the p-type base layer 9 from and holes (drain current) flowing from the drain side to the source side are effectively accumulated in the low-concentration n-type base layer 3 below the trench grooves 10a and 10b.

As a result, the resistance of the n-type silicon active layer 3 becomes small, a sufficient amount of carriers are supplied to the source regions of the three n-channel type MOS transistors and their vicinity, and the three parallel channel regions can be easily formed. You will be able to work at the same time (second point).

As will be described later, the trench groove 10a,
By optimizing the size (geometrical shape) of 10b, a larger current can be passed.

Furthermore, the trench grooves 10a, 10b
Are formed so that the plane orientations of the four side surfaces thereof are approximately {100} as shown in FIG. That is, the trench groove 10 has three {10
It is almost parallel to any of the 0 planes. Set the plane orientation to {10
If 0} is selected, the roughness of the silicon crystal lattice is reduced and the effective mass of electrons is also reduced, so that the mobility in the channel region is increased, the current density is increased, and the on-resistance is reduced ( Point 3).

FIG. 6 is a diagram showing a current flow when the lateral IGBT of this embodiment is turned on. The proportion of electrons passing through the three channel regions decreases as the distance from the drain region increases, but all the channel regions work (become conductive). From this, it can be seen that carriers are effectively accumulated below the n-type source layers 8a, 8b, and 8c, so that the entire channel region becomes conductive.

FIGS. 7A to 7C are diagrams showing carrier concentration profiles in the present example and the conventional element in the ON state. Fig.7 (a) is II-II of Fig.7 (c).
Direction carrier concentration profile, FIG.
The carrier concentration profile in the III-III direction (depth direction) in (c) is schematically shown. FIG. 7 (a)
From (c), it can be seen that carriers are more effectively accumulated in the vicinity of the source regions of the three n-type MOS transistors than in the conventional IGBT of FIG. The p-type contact layer is omitted in the sectional view of FIG.

In FIGS. 7A and 7B, the solid line a
(Invention) is a device parameter (for example, concentration profile of each diffusion layer, depth of trench groove 10, trench groove 10).
The width) of the device is set appropriately, and the solid line b (invention) shows the case where the device parameters are optimized. From FIG. 7B, it can be seen that by optimizing the device parameters, the excess carriers do not monotonically decrease toward the source side and the carriers are effectively accumulated in the vicinity of the source region.

Further, FIG. 8 shows a measured view of FIG. 7 (a). The left and right sides of FIG. 8 are reversed from those of FIG. 7A, and are omitted when the element parameters are optimized.

From FIG. 8, even when the device parameters are appropriately set, the excess carriers on the source side are 10 ¹⁶ cm.
^-It turns out that it will be ^-3 or more. On the other hand, in the conventional case, excess carriers are reduced to 10 ¹⁵ cm ⁻³ or less on the source side.

The turn-on voltage is sufficiently lower than that of the prior art, and after turn-on, the conduction state of the channel region is maintained at a lower on-voltage than before.

As described above, according to this embodiment, the on-resistance can be significantly reduced as compared with the conventional case.

The preferred dimensions (geometrical shape) of the trench grooves 10a and 10b are as follows.

As shown in FIG. 9, the trench grooves 10a, 1
The distance from the bottom (tip) of 0b to the bottom of the n-type silicon active layer 3 is l, the distance between trench grooves is w, and the trench grooves 10a and 10b penetrating from the p-type base layer 9 are formed.
Let the depth of d be d. The hole current J _p flowing through the trench gate region is J _p = 2 · μ · k · T (n / l) w, where the unit length (1 cm) is the depth direction of the device. However, n is carrier concentration (cm ⁻³ ), μ is mobility, k is Boltzmann coefficient, and T is temperature.

The value of the hole current J _p corresponds to 30% of the total current J, and J _p = 0.3 J.

The lateral resistivity under the trench gate is d · n
In proportion to, d · n = (0.3J · l · d) / (2μ · k · T · w) (1)

Here, in equation (1), μ = 500, kT =
Substituting 4.14 × 10 ²¹ results in d · n = 1.45 × 10 ¹⁷ (l · d / w) (2).

Equation (2) shows that when the thickness of the n-type silicon active layer 3 is about 10 μm, d> 5 [μm] and n> 1 × 10.
It is preferably ¹⁵ [cm ⁻³ ]. Therefore, substituting this value into the equation (2), d · n = 1.45 × 10 ¹⁷ (l · d / w)> (5 × 10
⁻⁴ [cm]) (1 × 10 ¹⁵ [cm ⁻³ ]), and the conditional expression (l · d / w)> 3.45 × 10 ⁻⁶ [cm] is obtained. When this conditional expression is satisfied, a current larger than that of the conventional lateral IGBT can always be obtained.

More preferably, d = 5 μm, n = 1 × 1
0 ¹⁶ [cm ⁻³ ], and by substituting this value into the equation (2), a conditional expression of (l · d / w)> 3.45 × 10 ⁻⁵ [cm] is obtained. If this conditional expression is satisfied, a larger current can be obtained.

Summarizing the above results, (l · d / w)
> 3.45 × 10 ⁻⁶ [cm], preferably (l · d /
w)> By setting the parameters l, d, and w in the range of> 3.45 × 10 ⁻⁵ [cm], the conventional horizontal IG
A larger current than BT can be obtained.

FIG. 10 is a diagram showing turn-off waveforms of the lateral IGBT of this embodiment and the conventional lateral IGBT of FIG. This shows the case where the turn-off is started from the same drain voltage and the same gate voltage in both the present embodiment and the conventional case. In this embodiment, the drain current value at the start of turn-off is set to 100% and the fall time, which is the time required for the drain current value to fall from 90% to 10%, becomes longer due to the larger drain current. You get time.

FIG. 11 is a waveform diagram in which the waveform of FIG. 10 is rewritten with the drain current value at the start of turn-off being 1, and FIG. 12 is a graph showing the turn-off loss. It can be seen from FIGS. 11 and 12 that the present invention has a smaller area in the fall time portion and therefore a smaller turn-off loss. Therefore, according to the IGBT according to the present embodiment, it is possible to perform the switching operation at a speed substantially equal to that of the conventional IGBT and with a small turn-off loss. (Second Embodiment) FIG. 13 is a sectional view showing an element structure of a lateral IGBT according to a second embodiment of the present invention. In addition,
In the following figures, the same reference numerals (including those with different subscripts) as in the above figures indicate the same or corresponding parts, and detailed description thereof will be omitted. In addition, in the following figures, the insulating film 50
Also, the p-type contact layer 51 is not particularly shown.

The lateral IGBT of this embodiment differs from that of the first embodiment in that the trench grooves 10a, 10b, 10 are formed.
It has been increased to 3 of c. According to the present embodiment, since the channel region is increased to 5 places, the channel density per element area becomes higher and the ON voltage can be further lowered. The number of trench grooves may be four or more. (Third Embodiment) FIG. 14 is a main part of the element structure of a lateral IGBT according to a third embodiment of the present invention (source-side element structure).
FIG.

The lateral IGBT of this embodiment differs from that of the first embodiment in that the p-type base layer 9 closest to the drain side is floating among the p-type base layers 9 separated by the trench grooves 10a and 10b. There is no p-type base layer in the state.

Even with such an element structure, the same channel density as that of the first embodiment can be obtained, so that the same effect as that of the first embodiment can be obtained. (Fourth Embodiment) FIG. 15 is a principal part of a lateral IGBT device structure according to a fourth embodiment of the present invention (source-side device structure).
FIG.

The lateral IGBT of this embodiment is different from that of the first embodiment in that two n-type source layers 8a, 8b, 8 are provided on the upper side walls of each trench groove 10a, 10b.
c and 8d are formed.

According to this embodiment, since four channel regions are formed during turn-on and turn-on, the channel density is higher than in the first embodiment, and the turn-on voltage can be lowered. become.

Further, since the source electrode 7 is in contact with the p-type base layer 9 on the most drain side, the latch-up withstand capability is increased and the turn-off speed can be improved. (Fifth Embodiment) FIG. 16 is a principal part of a lateral IGBT device structure according to a fifth embodiment of the present invention (source-side device structure).
FIG.

The lateral IGBT of this embodiment is different from that of the fourth embodiment in that the source electrode 7 is not in contact with the p-type base layer 9 and the n-type source layers 8a and 8b closest to the drain side. It is in.

According to the present embodiment, since the source electrode 7 is not in contact with the p-type base layer 9, it is possible to prevent holes from escaping from the p-type source layer 9 on the most drain side at the time of turn-on. Therefore, the turn-on characteristic is improved. (Sixth Embodiment) FIG. 17 is a principal part of a lateral IGBT device structure according to a sixth embodiment of the present invention (source-side device structure).
FIG.

The lateral IGBT of this embodiment is different from that of the fourth embodiment in that an oxide film 15 different from the trench grooves 10a and 10b (trench gate groove) forming the gate portion of the n-type MOS transistor is buried. Trench groove 20
(Dummy trench groove) is added. The dummy trench groove 20 is formed on the drain side of the trench gate grooves 10a and 10b.

According to this embodiment, the dummy trench groove 20 is formed.
With this, it is possible to prevent holes from escaping from the contact portion between the p-type base layer 9 on the most drain side and the source electrode 7 at the time of turn-off. Accumulation is promoted and the on-characteristics are further improved.

The above-mentioned l · d / W> 3.45 × 1
The range of 0 ⁻⁶ [cm] is also applied between the dummy trench groove and the trench gate groove. (Seventh Embodiment) FIG. 18 is a main part (source-side device structure) of a lateral IGBT device structure according to a seventh embodiment of the present invention.
FIG.

The lateral IGBT of this embodiment is different from that of the sixth embodiment in that the structure of the dummy trench groove 20 is the same as that of the trench gate grooves 10a and 10b, and the trench gate electrode 12 in the dummy trench groove 20 is the same. Is in a floating state.

According to this embodiment, the dummy trench groove 20 is formed.
Since the trench gate grooves 10a and 10b can be formed in the same step, the process is simplified as compared with the sixth embodiment. (Eighth Embodiment) FIG. 19 is a principal part of the element structure of a lateral IGBT according to an eighth embodiment of the present invention (source-side element structure).
FIG.

The lateral IGBT of this embodiment is different from that of the sixth embodiment in that the dummy trench groove 20 is formed in the end portion of the p-type base layer 9. Also in this embodiment,
The same effect as the sixth embodiment can be obtained. (Ninth Embodiment) FIG. 20 shows the essential part of the element structure of a lateral IGBT according to a ninth embodiment of the present invention (source-side element structure).
It is a cross-sectional perspective view showing. 21 is a cross-sectional view taken along the line I-I of the lateral IGBT shown in FIG.

In this embodiment, the dummy trench groove 20 in the eighth embodiment is formed to have a plane pattern as shown in FIG.

According to this embodiment, the dummy trench groove 20 is formed.
By narrowing the distance from the trench gate groove 10, the p-type base layer 9 on the most drain side can be brought into a floating state.

22 to 24 are views showing a plane pattern of the dummy trench groove which can obtain the same effect as that of the present embodiment.

FIG. 22 shows a rectangle having a plane pattern of the dummy trench groove 20a, and FIG. 23 shows a dummy trench groove 20a.
The plane pattern of b is a plurality of rectangles, and FIG. 24 shows the dummy trench groove 20c having a comb-shaped plane pattern. (Tenth Embodiment) FIG. 25 is a plan view (tenth embodiment) showing an example in which the pattern between the trench grooves of the first embodiment is changed. Further, FIG. 26 shows I of the lateral IGBT of FIG.
-I sectional view, and FIG. 27 is a II-II sectional view of the lateral IGBT of FIG.

In this embodiment, the trench gate groove 10a,
The n-type source layer 8 is formed between 10b, and the n-type source layer 8 is formed so as to surround the plurality of p-type base layers 9.

Also in this embodiment, since a plurality of channel regions are formed in the element, the same effect as in the first embodiment can be obtained.

When the number of trench gate grooves 10a and 10b increases, this plane pattern is repeated.

25 to 27 show only the region sandwiched by the trench grooves, and not the embodiment in which two trench gates form two channels. (Eleventh Embodiment) FIG. 28 is a plan view of a lateral IGBT according to an eleventh embodiment of the present invention. Also, FIG. 29 is shown in FIG.
8 is a sectional view taken along line I-I of the lateral IGBT shown in FIG. 8, and FIG. 30 is a sectional view taken along line II-II of the lateral IGBT shown in FIG. 28.

In this embodiment, the p-type base layer 9 and the n-type base layer 9 are formed so as to be substantially perpendicular to the trench gate groove 10.
The mold source layers 8 are formed alternately.

In the case of this embodiment, a channel cannot be formed in the portion where the n-type source layer 8 is not formed on the side wall of the trench gate groove 10 unlike in FIG. 25, but instead, the distance between the trench gate grooves is shortened. Therefore, the channel density can be increased, and the same effect as that of the previous embodiment can be obtained. (Twelfth Embodiment) FIG. 31 is a sectional view showing an essential part (source-side element structure) of the element structure of a lateral IGBT according to a twelfth embodiment of the present invention.

The lateral IGBT of this embodiment is different from that of the sixth embodiment in that the dummy trench groove 20 is formed deeper than the trench gate grooves 10a and 10b.

According to the present embodiment, it is possible to more effectively prevent holes from escaping from the contact portion between the p-type base layer 9 on the most drain side and the source electrode 7, and further improve the ON characteristics. To be done. (Thirteenth Embodiment) FIG. 32 is a sectional view showing a main part (source-side element structure) of the element structure of a lateral IGBT according to a thirteenth embodiment of the present invention.

In this embodiment, the trench gate groove 10c farthest from the drain is formed so as to reach the bottom of the n-type silicon active layer 2. That is, it is formed deeper than the other trench gate grooves 10a and 10b. (Fourteenth Embodiment) FIG. 33 is a plan view of an essential part (source-side element structure) of the element structure of the lateral IGBT according to the fourteenth embodiment of the present invention. Further, FIG. 34 shows the horizontal IG of FIG.
FIG. 35 is a cross-sectional view of the BT taken along the line I-I of FIG.
II-II sectional view, FIG. 36 shows III-III of the lateral IGBT of FIG.
It is a III sectional view.

The feature of this embodiment is that the trench gate groove 10 is formed.
Is formed in a lattice shape.

According to this embodiment, since the p-type base layer 9 is surrounded by the n-type source layer 8, the trench gate trench 10 is formed.
The channel region can be formed on all of the side walls of, and the channel density can be further increased. (Fifteenth Embodiment) FIG. 37 is a plan view of the main part (source-side element structure) of the element structure of the lateral IGBT according to the fifteenth embodiment of the present invention. Further, FIG. 38 is a horizontal IG of FIG.
FIG. 39 is a cross-sectional view of the BT taken along the line I-I of FIG.
It is a II-II sectional view.

The lateral IGBT of this embodiment is different from that of the fourteenth embodiment in that a part of the p-type base layer 9 (two surfaces parallel to the longitudinal direction of the p-type drain layer) is n-type source layer 8.
It is surrounded by.

According to this embodiment, the distance between the trench gate grooves extending parallel to the line I-I can be narrowed and the channel density can be increased. (Sixteenth Embodiment) FIG. 40 is a plan view of the main part (source-side element structure) of the element structure of the lateral IGBT according to the sixteenth embodiment of the present invention. Further, FIG. 41 shows the horizontal IG of FIG.
42 is a sectional view taken along the line I-I of the BT, and FIG.
II-II sectional view, FIG. 43 is a lateral IGBT III- of FIG.
It is a III sectional view.

The lateral IGBT of this embodiment is different from that of the fourteenth embodiment in that a part of the p-type base layer 9 (two surfaces perpendicular to the longitudinal direction of the p-type drain layer) is the n-type source layer 8.
It is surrounded by.

According to this embodiment, the distance between the trench gate grooves extending perpendicularly to the line I-I can be reduced and the channel density can be increased. (Seventeenth Embodiment) FIG. 44 is a sectional view showing an essential part (source-side element structure) of the element structure of a lateral IGBT according to a seventeenth embodiment of the present invention.

The lateral IGBT of this embodiment is different from that of the sixth embodiment in that the n-type source layer 8 is not formed between the dummy trench groove 20 and the trench gate groove 10 adjacent thereto, and the channel region is not formed. The reason for this is that a region in which is not formed is provided.

According to the present embodiment, holes are bypassed when the above region is turned off, and the off characteristic is improved.
Further, due to the dummy trench groove 20, at the time of turn-on, holes do not flow out from the p-type base layer 9 closest to the drain side, and good ON characteristics can be maintained. (Eighteenth Embodiment) FIG. 45 is a sectional view showing an essential part (source-side element structure) of the element structure of a lateral IGBT according to an eighteenth embodiment of the present invention.

The main difference between the lateral IGBT of this embodiment and that of the first embodiment is that the diode 21 is provided on the p-type base layer 9 on the most drain side through the electrode 102.

At turn-off, the depletion layer 30 is formed under the p-type base layer 9. At this time, trench gate groove 1
Due to the presence of 0, the depletion layer 30, the p-type base layer 9, and the source electrode 7 are suppressed in the hole discharge path p1 and the turn-off is delayed.

However, since the voltage drop of the diode 21 is smaller than that of the depletion layer 30, the holes in the device are effectively discharged by the hole discharging path p2 of the p-type base layer 9 and the diode 21. Therefore, the turn-off characteristic is excellent.

On the other hand, in the conductive state, the potential of the p-type base layer 9 provided with the diode 21 (on the most drain side) becomes higher than that of the other p-type base layers 9 by about 0.7V (silicon). In this case), holes can be prevented from being discharged from the p-type base layer 9, and the on-characteristic becomes good.

Instead of the diode 21, the electrode 102 of the p-type base layer 9 on the most drain side may be used as the Schottky electrode. (Nineteenth Embodiment) FIG. 46 is a sectional view showing an essential part (source-side element structure) of the element structure of a lateral IGBT according to a nineteenth embodiment of the present invention.

The feature of this embodiment is that an n-type semiconductor layer 32 having a high impurity concentration is provided at the bottom of the n-type silicon active layer 3 below the p-type base layer 9.

According to this embodiment, the electrons injected from the n-type source layer 8 into the n-type silicon active layer 3 through the channel region flow in the device through the n-type semiconductor layer 32. Resistance can be reduced.

Therefore, the trench gate trenches 10a, 10
Even if a large number of b and 10c are formed in parallel, the n-type MOS transistor effectively contributes to the injection of electrons, so that it is possible to expect a decrease in the on-voltage corresponding to the number of trench gate grooves 10a, 10b and 10c.

Further, since the depletion layer 30 generated just below the p-type source layer 9 prevents the n-type semiconductor layer 32 from being in a floating state and a potential increase, there is no fear of lowering the breakdown voltage. (Twentieth Embodiment) FIG. 47 is a plan view showing an element structure of a lateral IGBT according to a twentieth embodiment of the present invention. In the figure, the structure inside the upper source electrode 7 is the same as that inside the lower source electrode 7 and is omitted. Further, in the figure, 16 indicates a contact hole between the source electrode 7 and the base.

The lateral IGBT of the present embodiment is of a type in which each layer is formed concentrically, and the region 14 is not directly contacted with the source electrode 7 so that the region 14 is formed. Holes do not flow directly into the trench gates, electrons are accumulated under the trench gate trenches 10a and 10b, and electrons can be injected also from a plurality of trench gates in the back. (Twenty-first Embodiment) FIG. 48 is a sectional view showing a main part (source-side element structure) of the element structure of a lateral IGBT according to a twenty-first embodiment of the present invention.

The feature of this embodiment is that, on the p-type base layer 9 between the n-type source layer 8a closest to the drain side and the n-type silicon active layer 3, a gate insulating film (not shown) is provided. The gate electrode 40 is provided.

That is, the trench gate MOS transistor and the surface gate MOS transistor are combined.

Also in this embodiment, since there is a trench gate MOS transistor, a conventional surface gate MOS transistor is used.
The on-characteristics are improved as compared with a lateral IGBT having only a transistor. (Twenty-second Embodiment) FIG. 49 is a sectional view showing an essential part (source-side element structure) of the element structure of a lateral IGBT according to a twenty-second embodiment of the present invention.

The feature of this embodiment is that the gate oxide film 11a in the trench gate groove 10 closest to the drain side is thickest.

As a result, it is possible to effectively prevent a channel from being formed on the side surface of the trench gate closest to the drain. (Twenty-third Embodiment) FIG. 50 is a sectional view showing an essential part (source-side element structure) of the element structure of a lateral IGBT according to a twenty-third embodiment of the present invention.

The feature of this embodiment is that, in the region of the p-type base layer 9 in which the trench gate groove 10c farthest on the drain side is formed, the p-type region in which the n-type source layer is not formed is formed.
The source electrode 7 is not in contact with the mold base layer 9.

According to this embodiment, the n-type source layers 8a, 8
It is possible to prevent holes from being discharged from the p-type base layer 9 in the region where b, 8c, and 8d are formed to the source electrode 7. (Twenty-fourth Embodiment) FIG. 51 is a sectional view showing an essential part (source-side element structure) of the element structure of a lateral IGBT according to a twenty-fourth embodiment of the present invention.

The feature of this embodiment is that the dummy trench groove 20 is formed on the source side of the trench gate groove 10b farthest to the drain side.

According to this embodiment, the dummy trench groove 20 is formed.
As a result, carriers (electrons) can be effectively accumulated in the regions where the trench gate grooves 10a and 10b are formed, so that excellent ON characteristics can be obtained. (Twenty-fifth Embodiment) FIG. 52 is a plan view showing an essential part (source-side element structure) of the element structure of a lateral IGBT according to a twenty-fifth embodiment of the present invention. Further, FIG. 53 is a cross-sectional view of the lateral IGBT of FIG. 52 taken along the line I-I.

The feature of this embodiment is that the trench gate groove 10 having a sawtooth pattern is used. The plane directions of all the side wall surfaces of the trench gate grooves 10a and 10b are {10
0} is preferable. In this case, the angle θ formed by the saw blade
Is 90 °.

According to the present embodiment, the trench gate groove 10 is formed as compared with the case where the stripe-shaped trench gate groove is used.
Since the side wall areas of a and 10b are large and the channel area is large, the on-resistance can be further reduced. (Twenty-sixth Embodiment) FIG. 54 is a plan view showing the main part (source-side element structure) of the element structure of a lateral IGBT according to a twenty-sixth embodiment of the present invention.

The lateral IGBT of this embodiment is different from that of the twenty-fifth embodiment in that only the drain-side trench gate groove 10a has a saw-like shape. The other trench gate grooves 10b are stripe-shaped. Since the effect of the trench gate groove becomes smaller as the distance from the drain increases, it is important to increase the channel area formed by the trench gate groove 10a closest to the drain in order to effectively reduce the on-resistance. Also in this embodiment, as compared with the case where only the stripe-shaped trench gate groove is used,
Since the side wall area of the trench gate groove is increased and the channel area is increased, the on-resistance can be further reduced. (Twenty-seventh Embodiment) FIG. 55 is a plan view showing the main part (source-side element structure) of the element structure of a lateral IGBT according to a twenty-seventh embodiment of the present invention. Further, FIG. 56 is a cross-sectional view of the lateral IGBT of FIG. 55 taken along the line I-I.

The feature of this embodiment is that the short trench gate grooves 10s are obliquely arranged along the drain to increase the channel area.

A stripe-shaped dummy trench groove 10d in which an oxide film 17 is embedded is formed in the drift region on the drain side of the trench gate groove 10s. As a result, the hole current discharged from the source electrode 7 (particularly the portion of the trench gate groove on the most drain side which is in contact with the p-type base layer 9 and the n-type source layer 8) can be reduced, and the holes are discontinuously formed. Further, carriers can be effectively accumulated in the n-type silicon active layer 3 below the trench gate groove 10s, and excellent ON characteristics can be obtained.

Further, in this embodiment, two n-type source layers 8a, 8 are provided in each of the two trench gate grooves 10s.
Since b, 8c and 8d are provided, four channels are formed in the two trench gate grooves 10s.

Therefore, since the channel density is higher than that in the case of FIG. 3, even if the discharge amount of the hole current is slightly increased so that the turn-off characteristic is improved, the ON characteristic is not deteriorated. Therefore, according to the present embodiment, both the on characteristic and the turn off characteristic can be easily improved. (Twenty-eighth Embodiment) FIG. 57 is a plan view showing an essential part (source-side element structure) of the element structure of a lateral IGBT according to a twenty-eighth embodiment of the present invention. Also, FIG. 58, FIG. 59, and FIG.
0 is a sectional view taken along the line I-I of the lateral IGBT in FIG. 57, and II, respectively.
-II sectional view and III-III sectional view.

The lateral IGBT of this embodiment is different from that of the twenty-seventh embodiment in that the hole current is suppressed without using the dummy trench groove.

That is, in this embodiment, as shown in FIG. 58, the source electrode 7 is formed so as not to contact the p-type base layer 9 and the n-type source layer 8 of the trench gate groove 10a on the most drain side. That is, the hole current is prevented from being discharged from the source electrode 7 in this portion.

As shown in FIGS. 59 and 60, the p-type base layer 9 and the n-type source layer 8 in this region contact the source electrode 7 in the region on the drain side where the trench gate groove 10a is not formed. ing.

Also in this embodiment, the discharge of the hole current can be prevented and the channel density becomes high, so that the ON characteristics can be improved as in the 27th embodiment. (Twenty-ninth Embodiment) FIG. 61 is a plan view showing the main part (source-side element structure) of the element structure of a lateral IGBT according to a twenty-ninth embodiment of the present invention. 62 is a cross-sectional view taken along the line I-I of the lateral IGBT of FIG.

The lateral IGBT of this embodiment is different from that of the 28th embodiment in that a dummy trench groove 20 is added. Therefore, according to the present embodiment, the hole current is less likely to be discharged than in the 28th embodiment, so that the ON characteristics can be further improved. (30th Embodiment) FIG. 63 is a plan view showing an element structure of a lateral power MOSFET according to a 30th embodiment of the present invention. Further, FIG. 62 shows a lateral power MOSF of FIG.
It is an II sectional view of ET.

The device structure of the lateral power MOSFET of this embodiment is similar to that of the lateral IGBT shown in FIG. 3 except that the high impurity concentration p-type drain layer 5 is replaced by the high impurity concentration n-type drain layer 5n.
Has been replaced.

Also in this embodiment, the ON characteristic and the turn-off characteristic are improved by the same effect as that of the first embodiment. Therefore, according to the present embodiment, the lateral power MOSFE which is superior in on-characteristics and turn-off characteristics to the conventional ones.
T can be realized.

Similarly, even if the p-type drain layer 5 of the lateral IGBT according to the other embodiment is replaced with the high-concentration n-type drain layer 5n, a lateral power MOSFET having better characteristics than the conventional one can be obtained.

The present invention is not limited to the above embodiment. For example, in the above embodiment, as the groove,
The case of the trench gate groove (dummy trench groove) having a rectangular cross-sectional shape has been described. However, as shown in FIG. 65 (a), the cross-sectional shape is triangular, and as shown in FIG. 65 (b),
The cross-sectional shape may be a forward taper, the cross-sectional shape may be an inverse taper as shown in FIG. 65 (c), or the cross-sectional shape may be a parallelogram as shown in FIG. 65 (d).

Further, in the above embodiment, the case where the trench is a trench gate trench (dummy trench trench) whose plane pattern is mainly parallel to the longitudinal direction of the p-type drain layer 4 is described as the trench, but it is shown in FIG. 66 (a). Thus, the plane pattern is inclined with respect to the longitudinal direction of the p-type drain layer 4, and as shown in FIGS. 66 (b) and 66 (c), the plane pattern is substantially along the p-type drain layer 4 as a whole. It may be a thing.

The pattern of FIG. 66 (b) has been described in the twenty-fifth embodiment. Further, in the case of FIG. 66C, it is preferable to provide the dummy trench groove as in the case of FIG.

The shape of the entire groove may be a combination of the sectional shape of FIG. 65 and the sectional shape of the above-described embodiment, and the planar pattern of FIG. 66 and the planar pattern of the above-described embodiment as appropriate. To be The number of grooves is not limited to the number shown in the above embodiment.

The trench gate groove forming the channel and the dummy trench groove may be designed separately or may be designed the same. (31st Embodiment) FIG. 67 is a plan view of a lateral IGBT according to a 31st embodiment of the present invention. Also, FIG. 68 shows
67 is a sectional view taken along the line I-I of the lateral IGBT of FIG. 67, and FIG.
7 is a sectional view taken along line II-II of the lateral IGBT, and FIG. 70 is a sectional view taken along line III-III of the lateral IGBT shown in FIG.

The lateral IGBT of this embodiment is different from that of the first embodiment in that sub-trench grooves 10a 'and 10b' derived from the main trench grooves 10a and 10b are provided. The sub trench grooves 10a 'and 10b' extend in parallel to the main trench grooves 10a and 10b, and
It is connected to a and 10b, but is composed of a plurality of discontinuous portions. The distance between the main trench grooves 10a and 10b and the sub-trench grooves 10a ′ and 10b ′ is preferably 4 μm or less, and more preferably 2 μm or less.

As shown in FIG. 69, the main trench groove 10 is formed.
The portions 8d and 8e of the n-type region surrounded by a and 10b and the sub-trench grooves 10a 'and 10b' are the portions where the sub-trench grooves 10a 'and 10b' are discontinuous. It can be seen that it is electrically connected to the regions 8a and 8c and has the same potential as the source regions 8a and 8c. That is,
Main trench grooves 10a and 10b and sub-trench groove 10a
It can be seen that channels are also formed in the n-type regions 8d and 8e surrounded by 'and 10b'.

Further, these n-type regions 8d and 8e are not
Since it does not have a contact with the electrode 7, it is possible to narrow the interval between the trench grooves accordingly. The closer the trench groove is to the drain region, the greater the proportion that contributes to increasing the current density. Therefore, the main trench grooves 10a, 10
The sub-trench groove 10 is provided more than when only b is provided.
When combined with a'and 10b ', better on-voltage characteristics can be obtained. (32nd Embodiment) FIG. 71 is a plan view of a lateral IGBT according to a 32nd embodiment of the present invention. In addition, FIG.
71 is a cross-sectional view taken along the line I-I of the lateral IGBT of FIG. 71, and FIG.
II-II sectional view of the lateral IGBT of FIG. 1, and FIG. 74 is a III-III sectional view of the lateral IGBT of FIG.

This embodiment is a modification of the 31st embodiment. The lateral IGBT of this embodiment is the 31st
The difference from that of the embodiment is that the sub-trench groove 10a ′,
That is, the p ⁺ contact regions 101a and 101b enter the discontinuous portion 10b '.
For this reason, the contact between the channel region and the source electrode is not separated. As a result, it is possible to increase the latch-up tolerance. (Thirty-third Embodiment) FIG. 75 is a plan view of a lateral IGBT according to a thirty-third embodiment of the present invention. This embodiment is an embodiment related to a modification of the 31st embodiment. The difference between the lateral IGBT of this embodiment and that of the thirty-first embodiment is that
That is, two sub-trench grooves derived from the main trench grooves 10a and 10b are provided. That is, the sub trench groove 10a
′, 10a ″, 10b ′, 10b ″ are main trench grooves 1
0a, 10b parallel to the main trench grooves 10a, 10
It is provided by being connected to b.

As described above, by increasing the number of sub-trench grooves that do not have contact with the source electrode 7, it is possible to increase the channel density and further reduce the on-resistance. (34th Embodiment) FIG. 76 is a plan view of a lateral IGBT according to a 34th embodiment of the present invention. In addition, FIG.
FIG. 77 is a cross-sectional view of the lateral IGBT in FIG. 76. The lateral IGBT of this embodiment is different from that of the first embodiment in that it is a p-type base.
By shortening the diffusion time for forming the base layer 9, the diffusion length of the p-type base layer 9 is shortened.

By shortening the diffusion length of the p-type base layer 9 in this way, the channel length formed by the p-type base layer 9 and the n ⁺ -type source layer is shortened. as a result,
It is possible to reduce the voltage drop in the channel part,
It is possible to reduce the on-resistance of the entire device, that is, increase the current density.

FIG. 78 is a graph showing current-voltage characteristics in IGBTs of various channel lengths when the gate voltage is 12V. In the graph of FIG. 78, a curve a is an IGBT according to the present invention having a channel length of 0.5 μm, a curve b is an IGBT according to the present invention having a channel length of 1.0 μm, and a curve c is an IGBT according to the present invention having a channel length of 3.0 μm. , Curve d
Shows the characteristics of the conventional IGBT shown in FIG. 1 having a channel length of 3.0 μm. The IGBT according to the present invention is
Both have the structure shown in FIG. 3 or FIG.

From the graph of FIG. 78, it can be seen that a larger drain current flows and a higher current density can be obtained as the channel length becomes shorter. Further, even if the channel length is the same, the IGBT according to the present invention is
It can be seen that, as compared with,

FIGS. 79 (a) to 79 (c) are diagrams showing the flow of the heating process of the p-type base layer. In a normal IGBT manufacturing process, as shown in FIG. 79 (a), ion implantation for forming a p-type base layer is performed simultaneously with formation of an n-type buffer layer, and then base diffusion is performed. On the other hand, in this embodiment, as shown in FIG.
Ion implantation for forming the p-type base layer is performed, or ion implantation for forming the p-type base layer is performed after the base diffusion is completed as shown in FIG. 79 (c).

By performing the ion implantation for forming the p-type base layer by such a procedure, the p-type base layer can be obtained without changing the thermal process, that is, without affecting other diffusion layers. It is possible to reduce only the diffusion length of the layer. (35th Embodiment) FIG. 80 is a plan view of a lateral IGBT according to a 35th embodiment of the present invention. Also, FIG.
It is sectional drawing of the horizontal type IGBT of FIG. The lateral IGBT of this embodiment is different from that of the first embodiment in that a groove is formed in the contact portion between the source electrode 7 and the p ⁺ layers 101a and 101b, and the source electrode 7 is embedded in the groove. That is.

By adopting such a structure, the channel region, which is the electron path, remains unchanged.
Since the source electrode can be formed deeply, the latch-up withstand capability can be increased.

FIG. 82 shows a modification of the lateral IGBT shown in FIG. 81, in which the groove for embedding the source electrode is formed by LOCOS. By adopting such a structure,
It is possible to form the groove by a simpler process while maintaining good latch-up characteristics.

FIG. 83 shows a modification of the lateral IGBT shown in FIG. 81, in which the source electrode 7 and the p ⁺ layers 101a and 101b are formed.
The channel length is shortened by forming a groove in the contact portion with the source electrode 7 and burying the groove in the groove, and further shortening the diffusion length of the p-type base layer 9.

By doing so, the advantages of both the IGBT shown in FIG. 77 and the IGBT shown in FIG. 81 can be utilized, and an IGBT having a low on-resistance and a high latch-up resistance can be obtained.

FIG. 84 is an IG according to the first embodiment.
A cross-sectional view showing an example in which a groove 107 in which polysilicon or the like is buried is further formed in the first conductivity type active layer 3 with respect to BT, and a first conductivity type bypass layer 112 is formed under the groove 107. is there. According to such a configuration, the following effects are exhibited in addition to the effects according to the first embodiment.
That is, the groove 107 formed in the active layer of the first conductivity type and the first conductivity type bypass layer 112 under the groove increase the carrier current of the second kind having the opposite polarity to the drain layer of the second conductivity type in the total current. Since the accumulation of the second type carrier current on the source side increases, the on-voltage of the element decreases.

Although various embodiments of the present invention have been described above, the same effect can be obtained by reversing the conductivity type of each layer in these embodiments.

Besides, various modifications can be made without departing from the scope of the present invention.

[0165]

As described above, in the high breakdown voltage semiconductor device of the present invention, a plurality of trenches are formed which penetrate the base region so as to be in contact with the source region and reach the active region.
By forming the OS structure, two or more channel regions are formed in one device, which increases the channel density and reduces the resistance of the entire channel region.

In addition, the flow of carriers is obstructed near the bottom of the groove, carriers are accumulated, and the resistance of the active layer is reduced, which facilitates the formation of channels.

As a result, due to these effects, according to the present invention, superior ON characteristics can be obtained as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a device structure of a conventional lateral IGBT.

FIG. 2 is a cross-sectional view showing an element structure of another conventional lateral IGBT.

FIG. 3 is a plan view of a lateral IGBT according to the first embodiment of the present invention.

FIG. 4 is a sectional view of the lateral IGBT taken along line I-I of FIG. 3;

FIG. 5 is a sectional view for explaining the plane orientation of the trench groove.

FIG. 6 is a diagram showing a current flow when the lateral IGBT according to the present embodiment is turned on.

FIG. 7 is a diagram for explaining a difference in carrier concentration profile in the on state in the present invention and the conventional lateral IGBT.

FIG. 8 is a diagram showing an actual measurement diagram of FIG.

FIG. 9 is a view for explaining preferable geometrical shapes and dimensions of trench grooves.

FIG. 10 is a diagram showing turn-off waveforms in the present invention and a conventional lateral IGBT.

FIG. 11 is a waveform diagram in which the waveform of FIG. 10 is rewritten with the drain current value at the start of turn-off as 1.

FIG. 12 is a diagram showing turn-off loss of the present invention and a conventional lateral IGBT.

FIG. 13 is a sectional view showing an element structure of a lateral IGBT according to a second embodiment of the present invention.

FIG. 14 is a sectional view showing a main part (source-side element structure) of an element structure of a lateral IGBT according to a third example of the present invention.

FIG. 15 is a sectional view showing a main part (source-side element structure) of an element structure of a lateral IGBT according to a fourth example of the present invention.

FIG. 16 is a sectional view showing a main part (source-side element structure) of an element structure of a lateral IGBT according to a fifth example of the present invention.

FIG. 17 is a sectional view showing a main part (source-side element structure) of an element structure of a lateral IGBT according to a sixth example of the present invention.

FIG. 18 is a sectional view showing a main part (source-side element structure) of an element structure of a lateral IGBT according to a seventh example of the present invention.

FIG. 19 is a sectional view showing a main part (source-side element structure) of an element structure of a lateral IGBT according to an eighth example of the present invention.

FIG. 20 is a sectional perspective view showing a main part (source-side element structure) of an element structure of a lateral IGBT according to a ninth embodiment of the present invention.

21 is a cross-sectional view taken along line I-I of the lateral IGBT shown in FIG.

FIG. 22 is a view showing a plane pattern of a non-trench gate groove.

FIG. 23 is a diagram showing a plane pattern of another non-trench gate groove.

FIG. 24 is a view showing a plane pattern of still another non-trench gate groove.

FIG. 25 is a lateral IGBT according to a tenth embodiment of the present invention.
FIG.

26 is a cross-sectional view taken along the line I-I of the lateral IGBT shown in FIG. 20.

27 is a cross-sectional view taken along the line II-II of the lateral IGBT shown in FIG.

FIG. 28 is a lateral IGBT according to an eleventh embodiment of the present invention.
FIG.

29 is a cross-sectional view taken along the line I-I of the lateral IGBT shown in FIG. 20.

30 is a cross-sectional view taken along the line II-II of the lateral IGBT shown in FIG.

FIG. 31 is a lateral IGBT according to a twelfth embodiment of the present invention.
3 is a cross-sectional view showing the main part (source-side element structure) of the element structure of FIG.

FIG. 32 is a lateral IGBT according to a thirteenth embodiment of the present invention.
3 is a cross-sectional view showing the main part (source-side element structure) of the element structure of FIG.

FIG. 33 is a lateral IGBT according to the fourteenth embodiment of the present invention.
FIG. 3 is a plan view of a main part (source-side element structure) of the element structure of FIG.

34 is a cross-sectional view taken along the line I-I of the lateral IGBT shown in FIG. 28.

FIG. 35 is a sectional view taken along the line II-II of the lateral IGBT shown in FIG. 28.

36 is a sectional view taken along the line III-III of the lateral IGBT shown in FIG. 28.

FIG. 37 is a lateral IGBT according to a fifteenth embodiment of the present invention.
FIG. 3 is a plan view of a main part (source-side element structure) of the element structure of FIG.

38 is a cross-sectional view taken along the line I-I of the lateral IGBT shown in FIG. 32.

FIG. 39 is a sectional view taken along the line II-II of the lateral IGBT shown in FIG. 32.

FIG. 40 is a lateral IGBT according to the sixteenth embodiment of the present invention.
FIG. 3 is a plan view of a main part (source-side element structure) of the element structure of FIG.

41 is a cross-sectional view taken along the line I-I of the lateral IGBT of FIG. 35.

42 is a cross-sectional view taken along the line II-II of the lateral IGBT shown in FIG.

43 is a cross-sectional view taken along the line III-III of the lateral IGBT of FIG. 36.

FIG. 44 is a lateral IGBT according to a seventeenth embodiment of the present invention.
3 is a cross-sectional view showing the main part (source-side element structure) of the element structure of FIG.

FIG. 45 is a lateral IGBT according to the eighteenth embodiment of the present invention.
3 is a cross-sectional view showing the main part (source-side element structure) of the element structure of FIG.

FIG. 46 is a lateral IGBT according to the nineteenth embodiment of the present invention.
3 is a cross-sectional view showing the main part (source-side element structure) of the element structure of FIG.

FIG. 47 is a lateral IGBT according to the twentieth embodiment of the present invention.
FIG. 3 is a plan view showing the element structure of FIG.

FIG. 48 is a lateral IGBT according to the 21st embodiment of the present invention.
3 is a cross-sectional view showing the main part (source-side element structure) of the element structure of FIG.

FIG. 49 is a lateral IGBT according to the 22nd embodiment of the present invention.
3 is a cross-sectional view showing the main part (source-side element structure) of the element structure of FIG.

FIG. 50 is a lateral IGBT according to the 23rd embodiment of the present invention.
3 is a cross-sectional view showing the main part (source-side element structure) of the element structure of FIG.

FIG. 51 is a lateral IGBT according to the twenty-fourth embodiment of the present invention.
3 is a cross-sectional view showing the main part (source-side element structure) of the element structure of FIG.

FIG. 52 is a lateral IGBT according to the 25th embodiment of the present invention.
FIG. 3 is a plan view showing the element structure of FIG.

53 is a cross-sectional view taken along the line I-I of the lateral IGBT of FIG. 52.

FIG. 54 is a lateral IGBT according to the twenty sixth embodiment of the present invention.
FIG. 3 is a plan view showing the element structure of FIG.

FIG. 55 is a lateral IGBT according to the 27th embodiment of the present invention.
FIG. 3 is a plan view showing the element structure of FIG.

56 is a cross-sectional view taken along the line I-I of the lateral IGBT of FIG. 54.

FIG. 57 is a lateral IGBT according to the 28th embodiment of the present invention.
FIG. 3 is a plan view showing the element structure of FIG.

58 is a cross-sectional view taken along the line I-I of the lateral IGBT of FIG. 57.

59 is a sectional view taken along line II-II of FIG. 57.

FIG. 60 is a sectional view taken along the line III-III of FIG. 57.

FIG. 61 is a lateral IGBT according to the 29th embodiment of the present invention.
FIG. 3 is a plan view showing the element structure of FIG.

62 is a cross-sectional view taken along the line I-I of the lateral IGBT of FIG. 61.

FIG. 63 is a horizontal power M according to the thirtieth embodiment of the present invention.
The top view which shows the element structure of OSFET.

64 is a cross-sectional view taken along the line I-I of the lateral power MOSFET of FIG. 63.

FIG. 65 is a view showing a sectional shape of a groove.

FIG. 66 is a view showing a plane pattern of grooves.

FIG. 67 is a lateral IGBT according to the 31st embodiment of the present invention.
FIG.

68 is an I-I cross-sectional view of the lateral IGBT of FIG. 67.

69 is a cross-sectional view taken along the line II-II of the lateral IGBT shown in FIG. 67.

70 is a sectional view taken along the line III-III of the lateral IGBT shown in FIG. 67.

FIG. 71 is a lateral IGBT according to the 32nd embodiment of the present invention.
FIG.

72 is an I-I cross-sectional view of the lateral IGBT of FIG. 71.

73 is a cross-sectional view taken along the line II-II of the lateral IGBT shown in FIG. 71.

74 is a cross-sectional view taken along the line III-III of the lateral IGBT of FIG. 71.

FIG. 75 is a lateral IGBT according to the 33rd embodiment of the present invention.
FIG.

FIG. 76 is a lateral IGBT according to the 34th embodiment of the present invention.
FIG.

77 is a sectional view of the lateral IGBT of FIG. 76.

FIG. 78 is a characteristic diagram showing current-voltage characteristics of IGBTs having various channel lengths.

FIG. 79 is a view showing a flow of a heating step of the p-type base layer.

FIG. 80 is a lateral IGBT according to the thirty-fifth embodiment of the present invention.
FIG.

81 is a sectional view of the lateral IGBT shown in FIG. 80.

82 is a cross-sectional view showing a modified example of the lateral IGBT shown in FIG. 81.

83 is a cross-sectional view showing a modified example of the lateral IGBT shown in FIG. 81.

FIG. 84 is a cross-sectional view showing an example in which the trench according to the first embodiment is combined with the trench formed in the first conductivity type active layer and the first conductivity type bypass layer below the trench.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Silicon oxide film 3 ... N-type silicon active layer (1st conductivity type active layer) 4 ... N-type buffer layer 5 ... P-type drain layer (one conductivity type drain layer) 5n ... N-type drain layer ( One conductivity type drain layer 6 ... Drain electrode 7 ... Source electrode 8, 8a, 8b, 8c, 8d, 8e ... N type source layer (first conductivity type source layer) 9 ... P type base layer (second conductivity type base) Layers 10a, 10b ... Trench grooves (trench gate grooves) 11a, 11b, 11c ... Gate oxide films 12a, 12b, 12c ... Trench gate electrodes 13 ... Element isolation insulating films 15, 17, 50 ... Oxide film 20 ... Dummy trench grooves 51, 51a, 51b ... Contact layer 107 ... Groove 112 ... First conductivity type bypass layer.

Claims (16)

[Claims] 1. A semiconductor substrate, an insulating film formed on the semiconductor substrate, a first-conductivity-type active region formed on the insulating film, a drain region formed on the surface of the active region, A second conductivity type base region formed on the surface of the active region so as to be separated from the drain region, a first conductivity type source region formed on the surface of the base region, and the base region so as to be in contact with the source region. A first gate insulating film formed on the inner surface of the first groove reaching the active region, and embedded in the first groove having the first gate insulating film formed on the inner surface. And a first gate electrode formed on the inner surface of a second groove penetrating the base region so as to be in contact with the source region and reaching the active region at a position separated from the first groove. 2 gate insulating film, A second gate electrode buried in the second trench having an inner surface formed with the second gate insulating film; a source electrode electrically contacting the source region and the base region; A drain electrode electrically contacting the drain region, the gate insulating film, the gate electrode, the source region,
M composed of the base region and the active region
A high breakdown voltage semiconductor device having two or more channel regions formed in an OS structure. 2. The high breakdown voltage semiconductor device according to claim 1, wherein the first and second trenches extend substantially parallel to the drain region. 3. The high breakdown voltage semiconductor device according to claim 1, wherein the first and second grooves are connected to each other to form a lattice shape. 4. The high breakdown voltage semiconductor device according to claim 1, wherein at least one of the first and second grooves has a zigzag shape. 5. The high breakdown voltage semiconductor device according to claim 1, wherein the first and second trenches each include a plurality of short trenches arranged obliquely with respect to the extending direction of the drain region. 6. The high breakdown voltage semiconductor device according to claim 1, wherein the first groove is arranged on the drain region side, and the source region does not exist on the drain region side of the first groove. 7. The high breakdown voltage semiconductor device according to claim 1, wherein the side walls of the first and second trenches have a plane orientation of approximately {100}. 8. The first groove is disposed on the drain region side, and one channel region is formed in the base region opposite to the drain region of the first groove, and the second region is formed. The high breakdown voltage semiconductor device according to claim 1, wherein two channel regions are formed in the base region around the groove. 9. The high breakdown voltage semiconductor device according to claim 1, wherein the drain region is of a second conductivity type. 10. The high breakdown voltage semiconductor device according to claim 1, wherein the drain region is of a first conductivity type. 11. The distance from the bottom of the first or second groove to the bottom of the active layer is 1, the distance between the grooves is w,
2. The condition of (l · d / w)> 3.45 × 10 ⁻⁶ cm is satisfied, where d is the depth of a portion of the groove in contact with the active layer. High voltage semiconductor device. 12. The high breakdown voltage semiconductor device according to claim 1, wherein a dummy groove filled with an insulating film is formed closer to the drain region than the first or second groove. 13. Each of the first and second grooves comprises:
The high breakdown voltage semiconductor device according to claim 1, further comprising sub-grooves connected to them, each of which is divided into a plurality of discontinuous sections, a sub-gate insulating film is formed on an inner surface thereof, and a sub-gate electrode is embedded therein. . 14. The diffusion depth of the base region is 3 μm.
The high breakdown voltage semiconductor device according to claim 1, wherein: 15. The high breakdown voltage semiconductor device according to claim 1, wherein a groove is formed in the surface of the base region, and the source electrode is embedded in the groove. 16. A groove embedded with an insulator or a semiconductor is formed in the active region between the base region and the drain region, and a first conductivity type bypass region is formed below the groove. The high breakdown voltage semiconductor device according to claim 1, which is formed.