JP2004214701A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an embedded insulated gate-structured power semiconductor device capable of obtaining a big current breaking capacity and capable of realizing a low on-resistance as in almost a thyristor while preventing the latch up of a parasitic thyristor. <P>SOLUTION: A plurality of striped grooves 5 are formed on the side of an n-type base layer 4 having a p-type emitter layer 3, an n-type base layer 1 and a p-type base layer 4, and an insulated gate electrode 7 is embedded and formed in the grooves 5. In the p-type base layer 4, a n-type turn-off channel layer 8 contacting the sides of the grooves 5 is formed, and a p-type drain layer 9 is formed on the surface thereof. In the p-type base layer 4, a shallow diffusion-formed n-type source layer 10 is provided to prevent the thyristor from latching up, and the p-type drain layer 9 and the n-type source layer 10 are simultaneously contacted to form a cathode electrode 11. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a power semiconductor device having a buried insulated gate structure.

  As is well known, various thyristors such as GTO can realize a low on-resistance (and thus a small on-voltage) because of latch-up in an on-state, but have a small maximum breaking current density. In particular, a thyristor with an insulated gate that performs turn-off using an insulated gate structure has a lower current interrupting capability than a normal GTO thyristor. Conversely, IGBTs and the like have a built-in thyristor structure, but are designed to be used under conditions where they do not latch up. Therefore, the maximum breaking current density is relatively large, but the on-resistance is high because they do not latch up.

  As described above, the conventional power semiconductor device has a problem that it is necessary to latch up the pnpn thyristor in order to obtain a low on-resistance, and it is difficult to interrupt the current when the thyristor is latched up. .

  The present invention provides a buried insulated gate type power semiconductor device which can realize a sufficiently low on-resistance without causing latch-up and which can have a large maximum breaking current density in order to prevent latch-up. The purpose is to provide.

  In the power semiconductor device according to the present invention, the first conductive type emitter region and the injection of the first conductive type carrier from the first conductive type emitter region are substantially performed through the channel, and the conductive modulation is performed in the ON state. , A second conductivity type emitter region for injecting a second conductivity type carrier into the high resistance base region, and a second conductivity type drain for discharging the second conductivity type carrier in the high resistance base region. A region where the carrier concentration in the high-resistance base region in the on state is higher on the first conductivity type emitter region side than the concentration at the center of the high-resistance base region. Features.

Further, the power semiconductor device according to the present invention includes a high-resistance base layer, an insulating gate buried at a predetermined interval on the surface of the high-resistance base layer, and a first insulating layer formed in a region interposed between the insulating gates. A conductive type emitter layer; a channel region induced by the insulated gate to inject the first conductive type carrier from the first conductive type emitter layer to the high resistance base layer; and a second conductive type carrier to the high resistance base layer. A second conductivity type emitter layer to be implanted; and a second conductivity type drain layer formed in a region sandwiched by the insulated gate and discharging the second conductivity type carrier from the high resistance base layer. When the distance between the drain layers is 2C, the width of the region sandwiched by the insulating gates is 2W, and the distance from the interface between the second conductivity type drain and the high resistance base layer to the tip of the insulating gate is D.
X = {(C−W) + D} / W
The parameter X represented by the following formula satisfies X ≧ 5.

[Action]
According to the present invention, the parasitic thyristor structure is latched up by optimizing the depth, width and spacing of the buried insulated gate portion formed and arranged with a fine dimension by optimizing the design of the emitter layer with low injection efficiency. Thus, a low on-resistance equivalent to that of a thyristor can be obtained. The reason for this will be described in detail later. However, in the structure of the present invention, the buried gate electrode portion and the emitter region in a broad sense including the second conductivity type drain layer and the first conductivity type emitter layer adjacent thereto are defined. By setting the ratio Rp / Rn of the resistance Rp of the second conductivity type carrier in the emitter region to the resistance Rn of the first conductivity type carrier of the turn-on channel formed on the groove side surface to be 4 or more, a sufficiently large value can be obtained. This is because emitter injection efficiency can be obtained.

  The parameter X is a quantity indicating how far the bypass or drain layer of the second conductivity type carrier on the first conductivity type emitter layer is apart from each other, and the high resistance base layer short-circuit resistance of the first conductivity type emitter layer is This is introduced because it is proportional to the distance 2D + 2 (C−W) straddling the adjacent buried gate portion and is inversely proportional to the emitter width 2W. The smaller this parameter X is, the smaller the discharge resistance of the second conductivity type carrier on the first conductivity type emitter layer side is. By optimizing the dimensions of each part so as to satisfy X ≧ 5, it is possible to obtain a sufficiently low on-state voltage without performing a thyristor operation.

In the device of the present invention, the emitter injection efficiency γ in a broad sense including the buried gate is obtained as follows. First, the current flowing between the trenches is divided into an electron current Ich [A] flowing through the ON MOS channel and a current density JT [A / cm ² ] other than that. However, the current density is considered as a unit depth of 1 cm from the element cross section. The current density flowing in the unit cell is J [A / cm ² ], the groove interval is 2 W [cm], the unit cell size is 2 C [cm], and the virtual injection efficiency in the groove is γT.
γ = (Ich + γT × JT × W × 1) / (Ich + JT × W × 1) (1)
here,
C · J = JT × W × 1 + Ich (2)
Ich = Δψ / Rch (3)
Rch is the resistance of the ON MOS channel. Δψ is a potential difference between both ends of the ON MOS channel (a potential difference between both ends of the depth D), and the equation of current continuity in the groove Jp = (1−γT) JT
= −kTμp (dn / dx) −qμp · n (dψ / dx) (4)
Jn = γT JT
= KTμn (dn / dx) -qμn · n (dψ / dx) (5)
From
Δψ = (kT / q) ×
｛Μn (1-γT) + μpγT} / ｛μn (1-γT) -μpγT}
× [log (n) -log {n- (dn / dx) D}] (6)
dn / dx =-(JT / 2kT) {(1-γT) / μp-γT / μn} (7)
It becomes. From these equations (2) to (7), the injection efficiency of equation (1) can be obtained. By optimizing W, D, and C, the injection efficiency of the emitter region in a broad sense can be increased without increasing the injection efficiency of the emitter (or source) layer on the cathode side. As a result, carriers accumulated in the high-resistance base layer at the time of turning on can be increased, and bipolar transistors and IGBTs, which inherently have a small accumulation of carriers in the on state (small conduction modulation) as compared to thyristors, can be used in IGBTs. By applying the "carrier injection concept" described above, the on-voltage of these devices can be reduced to the level of a thyristor.

  As described above, according to the present invention, a large current interruption capability is realized by a fine cell structure having a buried insulated gate, and the thyristor is not latched up by the design of the width and the interval of the buried insulated gate part without latching up the thyristor. Can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a layout of a buried insulated gate power semiconductor device according to a first embodiment of the present invention, and FIGS. 2, 3, 4 and 5 are AA 'and B of FIG. 1, respectively. -B ', CC' and DD 'sectional drawing.

  In this insulated gate semiconductor device, a p-type emitter layer 3 is formed on one surface of a high-resistance n-type base layer 1 via an n-type buffer layer 2. On the other surface of the n-type base layer 1, a p-type base layer 4 is formed by diffusion.

  In the p-type base layer 1, a plurality of stripe-shaped grooves 5 are formed at minute intervals. A gate electrode 7 is buried in these trenches 5 via a gate oxide film 6. An n-type turn-off channel layer 8 is formed every other line in the striped region between the grooves 5, and a p-type drain layer 9 is formed on the surface of the turn-off channel layer 8. Thus, a vertical p-channel MOSFET in which the side surface of the n-type turn-off channel layer 8 is controlled by the buried gate electrode 7 is formed. An n-type source layer 10 is diffused on the surface of the remaining stripe region. Here, the n-type source layer 10 is shallowly diffused so that the parasitic thyristor structure constituted by the n-type source layer 10, the p-type base layer 4, the n-type base layer 1 and the p-type emitter layer 3 does not latch up. ing.

  Therefore, the layout on the cathode side has a pattern in which the arrangement of the buried gate electrode 7-p-type drain layer 9-buried gate electrode 7-n-type source layer 10 is repeated.

  The cathode electrode 11, which is the first main electrode, is provided so as to contact the n-type source layer 10 and the p-type drain layer 9 at the same time. On the p-type emitter layer 3, an anode electrode 12 as a second main electrode is formed.

  Specific element dimensions are, for example, as follows. The high resistance to be the n-type base layer 1 is such that the thickness of the n-type wafer is 450 μm, the n-type buffer layer 2 is formed from both sides with a depth of 15 μm, and the p-type base layer 4 is formed with a depth of 2 μm. The groove 5 formed in the p-type base layer 4 has a width and an interval of 1 μm and a depth of 5 μm. The gate oxide film 6 is a thermal oxide film or an ONO film (oxide film / nitride film / oxide film) of 0.1 μm or less. The n-type turn-off channel layer 8 has a channel length of substantially 0.5 μm with the p-type drain layer 9 formed on the surface. The n-type source layer 10 is formed to a depth of 1 μm or less, and the p-type emitter layer 3 is formed to a depth of about 4 μm.

  The operation of the insulated gate semiconductor device thus configured is as follows. When a positive voltage is applied to the gate electrode 7 with respect to the cathode, the turn-on channel around the p-type base layer 4 conducts, electrons are injected from the n-type source layer 10 into the n-type base layer 1, and turned on by the IGBT operation. I do. When a negative voltage is applied to the gate electrode 7, the side surface of the trench of the n-type turn-off channel layer 8 in the buried gate portion is inverted, and the carrier of the p-type base layer 4 causes the p-type drain layer 9 to move by the p-channel MOS transistor operation. It is sucked out to the cathode electrode 11 and turned off.

  In the case of this embodiment, the parasitic thyristor constituted by the n-type source layer 10-p-type base layer 4-n-type base layer 1-p-type emitter layer 3 is designed so as not to latch up even when the element is on. When the on-channel is closed, the injection of electrons from the n-type source layer 10 stops.

  According to this embodiment, the depth and density of the buried gate portion are sufficiently small as the unit cell size of 4 μm (that is, buried gate 1 μm-p-type drain layer 1 μm-buried gate portion 1 μm-n-type source layer 1 μm). By designing the size, a sufficiently small on-resistance can be obtained even though the thyristor is not operated. The fact that the turn-off channel is closed when the device is on is another reason why a small on-resistance is obtained. Also, since the parasitic thyristor does not latch up in the on state, and the turn-off channel opens to bypass the holes when the thyristor is off, the maximum current interrupting capability is greater than that of a GTO thyristor or the like which is turned off after latching up.

  FIG. 6 is a layout of a buried insulated gate power semiconductor device according to a second embodiment of the present invention, and FIGS. 7, 8 and 9 are AA ', BB' and C of FIG. 6, respectively. It is -C 'sectional drawing. Parts corresponding to those in the previous embodiment are denoted by the same reference numerals as in the previous embodiment, and detailed description is omitted.

  In this embodiment, the grooves 5 periodically formed are formed so as to penetrate the p-type base layer 4 deeply. For example, the p-type base layer is 3 μm, and the groove 5 is about 6 μm. The gate electrode 7 is buried in the trench 5 via the gate oxide film 6 as in the previous embodiment.

  In this embodiment, the interval between the grooves 5 is wider than that in the previous embodiment, for example, 2 μm. An n-type turn-off channel layer 8 and a p-type drain layer 9 are formed in all the stripe regions between the grooves 5 in contact with the grooves 5, and an n-type source layer 10 is formed at a position away from the grooves 5. Here, the fact that the n-type source layer 10 is formed such that the parasitic thyristor formed between it and the p-type base layer 4, the n-type base layer 1 and the p-type emitter layer 3 does not latch up is This is the same as the previous embodiment. However, the n-type source layer 10 and the n-type turn-off channel layer 8 are continuous.

  In this embodiment, the side surface of the groove 5 of the p-type base layer 4 below the n-type turn-off channel layer 8 is a turn-on channel. That is, the gate electrode 7 buried in the groove 5 serves both for turn-on and for turn-off, and is formed in a state where a turn-off p-channel MOSFET and a turn-on n-channel MOSFET are vertically stacked.

  The device of this embodiment is turned on by applying a positive voltage to the gate electrode 7 and forming an n-type channel on the side surface of the groove 5 of the p-type base layer 4. At this time, electrons are injected from the n-type source layer 10 to the n-type base layer 1 via the n-type turn-off channel layer 8 and the inverted n-type channel. A negative voltage or zero voltage is applied to the gate electrode 7, and the gate electrode 7 is turned off as in the previous embodiment.

  According to this embodiment, the same effect as that of the previous embodiment can be obtained.

  FIG. 10 is a layout of a buried insulated gate power semiconductor device according to a third embodiment of the present invention. FIGS. 11, 12 and 13 show AA ', BB' and C- of FIG. It is C 'sectional drawing. In this embodiment, based on the configuration of the second embodiment, the ratio of the width of the buried gate electrode portion to the width of the region sandwiched by the buried gate electrode portion is further increased.

  The specific dimensions of the element are as follows. The high resistance to be the n-type base layer 1 is such that the thickness of the n-type wafer is 450 μm, the n-type buffer layer 2 is 15 μm from both sides, and the p-type base layer 4 is 2 μm deep. I do. The groove 5 formed in the p-type base layer 4 has a width of 5 μm, an interval of 1 μm, and a depth of 5 μm. The gate oxide film 6 is a thermal oxide film or ONO film of 0.1 μm or less. The n-type turn-off channel layer 8 has a channel length of substantially 0.5 μm with the p-type drain layer 9 formed on the surface. The n-type source layer 10 is formed to a depth of 1 μm or less, and the p-type emitter layer 3 is formed to a depth of about 4 μm.

  The device of this embodiment operates in the same manner as the second embodiment. In this embodiment, the area occupied by the buried gate electrode portion in the device is made sufficiently larger than the area of the region sandwiched by the buried gate electrode portion. As a result, the resistance to holes in the broadly defined emitter region including the buried gate electrode portion increases, and as a result, the electron injection efficiency of the broadly defined emitter region increases. In other words, despite the area of the buried gate electrode region being larger than the area of the n-type source layer 10 region, an equivalently large electron injection efficiency is obtained by the difference between the resistance to the electron current and the resistance to the hole current, Low on-resistance is realized. Since the actual electron injection efficiency of the n-type source layer 10 itself is low, the turn-off capability is as high as that of an IGBT.

  FIG. 14 shows a layout of an embodiment obtained by modifying the third embodiment. FIGS. 15, 16 and 17 are sectional views taken along lines AA ', BB' and CC 'of FIG. 14, respectively. is there. In this embodiment, unlike the previous embodiment, the groove 5 stops in the p-type base layer 4.

  In this embodiment as well, by optimizing the element dimensions of each part, it is possible to achieve both low on-resistance and high current interrupting capability, as in the previous embodiment.

  FIG. 18 shows a sectional structure of a unit cell portion of an embodiment in which a similar buried gate structure is applied to the anode side on the basis of the device of the second embodiment. That is, as described in the second embodiment, the buried gate electrode 7 is formed on the surface of the n-type base layer on the cathode side, and the p-type base layer and the n-type source layer are formed between the buried grooves 4. On the side surface of the groove 4, an n-type turn-off channel layer and a p-type drain layer are formed. In contrast to the cathode side, a groove 20 is also formed on the anode side, in which a gate electrode 21 is buried, and a diffusion layer having a conductivity type opposite to that of the cathode side is provided between the grooves 20. Is formed.

  FIG. 18 shows specific element dimensions. 19 (a) and 19 (b) show the impurity concentration distributions of the AA 'portion and the BB' portion on the cathode side, respectively.

  In the device of this embodiment, at the time of turn-on, a negative voltage is applied to the buried gate electrode 21 on the anode side with respect to the anode electrode. At the time of turn-off, zero or positive voltage is applied to the buried gate electrode 21 on the anode side with respect to the anode electrode. According to the element of this embodiment, the same effect as that of the previous embodiment can be obtained.

  Here, the reason why the buried insulated gate element of the present invention employs a pnpn structure in which a thyristor does not operate even in a large current region and obtains an ON resistance as low as a thyristor will be described in detail with reference to simulation data.

  FIG. 20 is a cross-sectional view of a half cell of the model used for the calculation, and FIG. 21 is a diagram illustrating the principle of the new emitter structure. Since an IGBT is the basis of FIG. 20, there is no n-type emitter in a normal thyristor. Electron injection on the cathode side is performed by the MOS channel, and the bypass resistance of the hole current is designed to be sufficiently small so that the parasitic thyristor does not latch up with the n-type drain layer constituting the MOSFET as the n-type emitter. However, reducing the bypass resistance of the hole current is equivalent to lowering the injection efficiency of the n-type emitter when the structure of FIG. 20 is compared with a thyristor (or a diode). Results.

  FIG. 21 shows this fact clearly. In the device of the present invention in which the MOS source layer and the buried gate are arranged in fine dimensions, it is easier to understand the injection efficiency by considering the entire region including the MOS source layer and the buried gate as the emitter region. That is, if the region surrounded by the broken line in the drawing is defined as a broadly defined emitter region, the injection efficiency γ of the broadly defined emitter region can be expressed as follows by the hole current resistance Rp and the electron current resistance Rn.

γ = Jn / (Jn + Jp)
= (Rp / Rn) / {1+ (Rp / Rn)} (8)
However, it is assumed that there is no lateral potential distribution at the end of the emitter region in a broad sense. Here, if Rp / Rn = 3, γ = 0.75, and if Rp / Rn = 4, γ = 0.8.

  Considering that the emitter injection efficiency of a normal thyristor or diode is 0.7 or more, even in the IGBT having the buried insulated gate structure in FIG. 20, if the emitter injection efficiency in a broad sense is 0.8 or more, that is, Rp / If Rn> 4, it means that an on-voltage equivalent to that of a thyristor can be obtained.

In the current IGBT having a planar gate structure, Rp / Rn is about 3, and when Rp / Rn> 4, the latch-up resistance decreases. For several reasons, for example, in a IGBT having a planar gate structure, it may be difficult to make a difference between the electron current resistance and the hole current resistance in the lateral direction due to the structure. Low lateral resistance in the ON state (at a current density of 100 A / cm ² , there are about 3 × 10 ¹⁶ / cm ³ carriers, and the lateral resistance of holes due to the p-type base layer is reduced) However, even if an attempt is made to increase the hole current resistance with this lateral resistance, the number of MOS on-channels per unit area is reduced, and consequently the electron current resistance is increased, thus lowering the emitter injection efficiency in a broad sense. Resulting in. In the case of EST or the like, the cell size is increased in order to increase the hole current resistance. However, this method reduces the number of on-channels per unit area, and increases the electron current resistance before the hole current resistance increases sufficiently. As a result, the injection efficiency of the emitter region in a broad sense is not improved, and it is difficult to reduce the on-resistance of the device. In addition, simply trying to increase the hole current resistance by lowering the short-circuit rate of the hole current decreases the latch-up resistance.

  Therefore, a structure is required in which the hole current resistance is four times or more the electron current resistance without increasing the short-circuit resistance of the hole current while increasing the number of MOS channels per unit area. According to the examination results of the present inventors, it has become clear that such conditions can be realized by optimizing the width, depth, interval, and the like of the buried gate structure.

The following shows specific schlation data. First, the IGBT structure of FIG. 20 used for the calculation has a forward blocking voltage of 4500 V, and the device parameters are as follows. Using an n-type high-resistance silicon substrate having an impurity concentration of 1 × 10 ¹³ / cm ³ and a thickness of 450 μm, an n-type buffer layer having a depth of 15 μm and a surface concentration of 1 × 10 ¹⁶ / cm ³ is provided on the anode side. A p-type emitter layer having a thickness of 4 μm and a surface concentration of 1 × 10 ¹⁹ / cm ³ is formed. The cathode side, depth 2 [mu] m, are formed with p-type base layer of the surface concentration 1 × 10 ¹⁷ / cm ^3, the depth 0.2 [mu] m, the p-type source layer on the surface concentration of 1 × 10 ¹⁹ / cm ³ . The gate electrode of the buried gate on the cathode side is separated by a silicon oxide film or ONO film having a thickness of 0.05 μm.

  As shown in FIG. 20, the depth of the buried gate portion is D (a portion protruding from the p-type base layer into the n-type base layer), the cell size is 2C, and the emitter width is 2W. Is the ratio of W / (C−W). Using these dimensions C, W, and D and the hole lifetime τp as parameters, the effect of the buried gate electrode structure on the ON voltage of the device was examined. The results are shown in FIGS.

  FIG. 22 shows a model in which the cell size is 2C = 6 μm, the emitter width is 2W = 1 μm, the width of the buried gate is 2 (C−W) = 5 μm, and the hole lifetime is τp = τn = 2.0 μsec. This is a result of obtaining a device current density at an anode-cathode voltage of 2.6 V when the depth D of the buried gate portion is changed. The gate applied voltage is +15 V (common for all on-voltage calculations).

  FIG. 23 shows a model in which the emitter width is 2 W = 1 μm, the depth of the buried gate is D = 5 μm, and the hole lifetime is τp = 30 μsec. It is a result of obtaining the element current density at a voltage of 2.6 V.

  As shown in FIG. 23, when the width of the buried gate is from about 1 μm to about 5 μm, the device current sharply increases as the width of the buried gate increases. However, when the width of the buried gate is about 10 μm, the current reaches a plateau. The current starts to decrease in reverse. This phenomenon can be explained as follows. When the width of the buried gate is wider than the width of the emitter, the hole current density near the side of the buried groove immediately below the emitter increases, and as a result, the potential rises on the lower side of the buried groove. As a result, when the MOS channel is not saturated, the ratio of the hole current to the electron current increases, and as a result, the injection efficiency of the emitter region in a broad sense increases, and the element current density increases. However, when the width of the buried gate portion is further widened, the MOS channel is saturated and the number of MOS channels per unit area is reduced, so that the MOS channel resistance of the electron current is increased and the electron current flowing through the element is limited. As a result, the emitter injection efficiency decreases and the device current decreases.

  Further, when the contact between the p-type base layer and the n-type emitter layer is considered as a cathode short circuit, when the width of the buried gate portion is increased, the same effect as increasing the lateral resistance of the cathode short circuit is obtained (in terms of injection efficiency, the emitter is broadly defined). This is equivalent to reducing the cathode short-circuit rate in the region), and as a result, the injection efficiency increases and the on-voltage decreases. However, if the width of the buried gate portion becomes too wide, the number of on-channels per unit area decreases, and as a result, the electron current resistance increases, so that the injection efficiency decreases and the on-voltage increases.

  FIG. 24 shows a model having an emitter width of 2 W = 1 μm, a buried gate depth D of 5 μm, and a hole lifetime τp = 2.0 μsec. The anode / cathode when the width CW of the buried gate is changed It is the result of obtaining the element current density at an inter-voltage of 2.6 V. The current increases sharply when the width of the buried gate portion is about 1 μm to 5 μm, but reaches a plateau at 10 μm to 15 μm. The reason why the width of the buried gate where the current is saturated is wider than in the case of τp = 30 μsec is that the absolute value of the current flowing through the element is small (about 1/10).

  FIG. 25 shows a model in which the emitter width 2W = 1 μm, the depth D of the buried gate portion is 5 μm, and the hole lifetime τp = 2 μsec, and the case where the width 2 (C−W) of the buried gate portion is 1 μm is (A). It is a plot of the current characteristics when the forward voltage between the anode and the cathode is changed in the case of 15 μm (B).

  As shown in the figure, the current crosses at a point where the anode-cathode voltage is 13V. At 13 V or less, the current value is larger in the buried gate portion having a width of 15 μm, and especially at 2 V or less, the single digit current value is larger. Above 13V, the magnitude of the current value is reversed.

FIG. 26 shows the device model of FIG. 30 in which the IGBT device model of FIG. 20 is changed to the device structure of the second embodiment, with an emitter width 2W = 3 μm and a buried gate portion width 2 (C−W) = 13 μm, buried gate depth D = 12.5 μm, p-type base layer depth 2.5 μm, n-type source layer depth 1 μm, p-type drain layer depth 0.5 μm, hole lifetime τp = This is a current-voltage characteristic when 1.85 μsec is set. Τp is set so that the device current becomes 100 A / cm ² when the anode-cathode voltage is 2.6 V.

Similarly, FIG. 27 shows a turn-off waveform in the model of FIG. 30 with a current density Iak = 5223 [A / cm ² ] and a resistance load from Vak = 25 V. The gate voltage is changed from +15 V to -15 V at a gate voltage rise rate dVG / dt = -30 [V / .mu.sec].

Incidentally, assuming that the carrier concentration immediately below the emitter region at 100 A / cm ² is 1 × 10 ¹⁶ / cm ³ , holes at an emitter width W of 1.5 μm and a buried gate depth D of 12.5 μm are obtained. The current resistance is
Rp = 0.5 × 12.5 × 10 ⁻⁴ ÷ 1.5 × 10 ⁻⁴ = 4.2Ω (9)
When the electron current resistance is Rn = 1Ω, the injection efficiency is γ = 0.81.

  As is clear from the above data, it is understood that by optimizing the shape and size of the emitter region in a broad sense including the buried insulated gate portion, it is possible to realize an on-resistance as low as that of the thyristor without operating the thyristor.

  In the conventional method, the emitter layer is composed of a single high-concentration impurity diffusion layer, and carriers are injected from the emitter diffusion layer into the high-resistance base layer. The present invention provides a structure for controlling the flow of MOS channel and carrier discharge for carrier injection and discharge to the high resistance base instead of the conventional single high concentration impurity diffusion layer (ie, the carrier discharge resistance or diffusion current is locally controlled). The present invention relates to a structure for obtaining high injection efficiency without using a conventional high-concentration impurity diffusion layer.

  In the present invention, the p-base short-circuit resistance on the cathode side tends to be proportional to the distance 2D + 2 (C−W) straddling the adjacent buried gate portion and inversely proportional to the emitter width 2W. Therefore, the following parameter X is introduced.

X = {2D + 2 (C−W)} / 2W
= {D + (C−W)} / W (10)
The parameter X is an amount indicating how far the hole bypass or drain layer on the cathode side is apart from each other. The smaller the parameter X, the smaller the discharge resistance (short-circuit resistance) of the hole on the cathode side.

  FIG. 28 shows the life time τp of the element and the current density flowing through the element when D, C, and W are changed with the parameter X as the horizontal axis. Open circles are when τp = 30 μsec, W = 0.5 μm, D = 5 μm and C is changed, and black circles are when τp = 2 μsec, W = 0.5 μm and C = 1 μm and D is changed. , Double circles are for τp = 2 μsec, W = 1.5 μm, C = 8 μm, D = 15 μm, and x marks are D for τp = 2 μsec, W = 0.4 μmec, C = 1 μm. Things.

In order to secure a current capacity of 100 A / cm ² with an element having a forward breakdown voltage of 4500 V, for example, W = 0.5 μm, D = 2 μm, and C = 1 μm.
X ≧ 5
It is necessary to Further, from the data of FIGS. 22 to 28, when W = 0.5 μm, D = 5 μm, and C = 1 μm, X = 11, and when W = 1.5 μm, D = 13.5 μm, and C = 8 μm, X to 13. That is, it is understood that the characteristics are remarkably improved by setting X> 8 or X> 10, and more preferably X> 13.

FIG. 29 shows the carrier concentration distribution in the ON state in this case together with the corresponding cross section. In the graph on the right side, the solid line is the present invention, and the broken line is the conventional example. The feature of the present invention is that the carrier concentration distribution peaks on the cathode side of the n ⁻ -type base layer as compared with the case of the IGBT structure. The carrier concentration of the n − -type base layer in the ON state is designed to be 10 ¹¹ to 10 ¹⁸ / cm ³ , more preferably about 1 × 10 ¹⁵ to 1 × 10 ¹⁸ / cm ³ .

  In addition, the smaller W among the dimensions W, D, and C, the larger X becomes, and the actual element characteristics are improved. However, as D increases, not only does the hole resistance increase, but also the resistance of carriers injected into the high-resistance base through the on-channel increases. For example, when D = 500 μm, the voltage drop due to the resistance of the injected carriers and the voltage drop due to the resistance of the discharged holes become equal, and the total on-voltage of the element increases.

  Also, when C is increased, the current density in the range of W is increased and the emitter injection efficiency in a broad sense is increased. However, increasing C decreases the number of on-channels per unit area, and increasing C too much increases The actual on-channel resistance increases. As can be seen from FIG. 28, the tendency appears when X> 30 μm or more, so that C is preferably designed to be 500 μm or less.

  FIG. 31 is a layout of a buried insulated gate power semiconductor device according to another embodiment of the present invention, and FIGS. 32 and 33 are sectional views taken along lines AA 'and BB' of FIG. 31, respectively.

  In this embodiment, the groove 5 is formed so as to surround the p-type base layer 4 in a rectangular shape with a depth reaching the n-type base layer 1, and a plurality of stripe-shaped grooves 5 are formed therein with the peripheral groove 5. It is formed continuously. A buried gate electrode 7 is formed in the trench 5 via a gate oxide film 6.

  An n-type turn-off channel layer 8 is formed in the p-type base layer 4 in the stripe region between the grooves 5. A p-type drain layer 9 and an n-type source layer 10 are formed in the n-type turn-off channel layer 8 alternately along the longitudinal direction of the trench 5. The p-type drain layer 9 is formed on the surface of the n-type turn-off channel layer 8, and the n-type source layer 10 and the n-type turn-off channel layer 8 are actually the same diffusion layer.

  In the device of this embodiment, the side surface of the groove 5 of the p-type base layer 4 below the n-type emitter layer 10 is a turn-on channel. The side surface of the groove 5 of the n-type turn-off channel layer 8 below the p-type drain layer 9 becomes a turn-off channel. Therefore, similarly to the previous embodiment, the gate electrode 7 buried in the groove 5 serves both for turning on and for turning off.

  The device of this embodiment is turned on by applying a positive voltage to the buried gate electrode 7 to form an n-type channel on the groove side surface of the p-type base layer 4. When a negative voltage is applied to the buried gate electrode 7, a p-type channel is formed on the side surface of the groove of the n-type turn-off channel layer 8, and the p-type channel is turned off in the same manner as in the above embodiments.

According to this embodiment, the same effects as those of the previous embodiments can be obtained. Further, in the device of this embodiment, since the buried gate portion bears the breakdown voltage as in the previous embodiment, the impurity concentration of the p-type base layer 4 can be reduced. For example, the peak impurity concentration of the p-type base layer 4 can be set to about 1 × 10 ¹⁶ / cm ³ , and accordingly, the peak impurity concentration of the n-type turn-off channel layer 8 is set to about 1 × 10 ¹⁷ / cm ^3. can do. As a result, the threshold necessary for forming a p-type channel on the trench side surface of the n-type turn-off channel layer 8 can be made as small as, for example, about 5 V, and off-control can be performed with a small gate voltage.

  FIG. 34 is a layout of a buried insulated gate semiconductor device according to another embodiment of the present invention, and FIGS. 35 and 36 are sectional views taken along AA 'and BB' of FIG. 34, respectively.

  The device of this embodiment is a device in which the p-type base layer 4 of the embodiment of FIGS. 31 to 33 is omitted, and is a so-called electrostatic induction thyristor. By setting the impurity concentration of the n-type base layer 1 and the width of the groove 5 (the width of the n-type base layer 1 sandwiched between the grooves 5 shown in the cross section of FIG. 35) to appropriate values, The entire potential of the n-type base layer 1 can be controlled by the buried gate electrode 7.

  When a positive voltage is applied to the gate electrode 7 to increase the potential of the n-type base layer 1 sandwiched between the trenches 5, electrons are injected from the n-type source layer 10 and the device turns on. When a negative voltage is applied to the gate electrode 7, a p-type channel is formed on the groove side surface of the n-type turn-off channel layer 8, and carriers of the n-type base layer 1 are discharged to the cathode electrode 13 via the p-type drain layer 9. And the device turns off.

  FIG. 37 is a layout of a buried insulated gate type semiconductor device of still another embodiment, and FIGS. 38 and 39 are sectional views taken along lines AA 'and BB' of FIG. 37, respectively.

  This embodiment is a slightly modified element of the embodiment shown in FIGS. The plurality of stripe-shaped grooves 5 are independent of each other, and the periphery thereof is surrounded by a deep p-type base layer 4 '. The distribution, depth, and the like of the n-type turn-off channel layer 8, p-type drain layer 9, and n-type source layer 10 formed in the p-type base layer 4 between the buried gate portions are the same as those in the previous embodiment.

  FIG. 40 is a layout of a buried insulated gate semiconductor device of still another embodiment, and FIGS. 41 and 42 are cross-sectional views taken along AA 'and BB' of FIG. 40, respectively.

  This embodiment is a modification of the element of the embodiment of FIGS. 34 to 35 in the same manner as the embodiment of FIGS. 37 to 39.

  According to these embodiments, effects similar to those of the preceding embodiments can be obtained.

  42 to 44 show an embodiment in which the embodiment of FIGS. 31 to 33 is modified to make the p-type base layer 4 deeper than the buried gate portion.

  FIGS. 46 to 48 show an embodiment in which the n-type turn-off channel layer 8 is omitted from the embodiment shown in FIGS. 43 to 45.

  FIGS. 49 to 51 show an embodiment in which the p-type base layer is omitted from the structures of FIGS. 46 to 48.

  Also according to these embodiments, as described above, the shape and dimensions of each part, particularly the width and the interval of the buried gate part, are optimally designed, and the injection efficiency of the emitter region in a broad sense is sufficiently increased to realize a low on-resistance. Can be.

  FIGS. 52 to 55 show an embodiment in which the same structure as the embodiment of FIGS. 11 to 14 is applied to an IGBT. An n-type source layer 10 is formed in contact with the side surface of groove 5, and cathode electrode 1 simultaneously contacts n-type source layer 10 and p-type base layer 4 exposed therebetween.

  FIGS. 56 to 58 are examples in which the structures of FIGS. 37 to 39 are similarly applied to IGBTs.

  FIG. 59 is a modification of FIG. If the width 2 (CW) of the buried gate portion is too large with respect to the emitter width 2W, the reliability of the groove processing is reduced. In such a case, the yield can be improved by forming a single groove, which is originally required, into a plurality of grooves. No p-type base or n-type source is formed in the n-type base layer exposed in the width 2 (C-W).

60 to 62 are a layout of a unit cell portion of an embodiment in which the present invention is applied to a horizontal IGBT and sectional views taken along the lines AA 'and BB'. A wafer obtained by directly bonding the first silicon substrate 20 and the second silicon substrate 22 with the oxide film 21 interposed therebetween is used as a device region on the side of the second silicon substrate 22, and is processed to a predetermined thickness. To form an n-type base layer 1. A groove 5 having a depth reaching the bottom oxide film 21 is formed in the n-type base layer 1, and a gate electrode 71 is buried therein. A p-type base layer 4 and an n-type source layer 10 are formed between the buried gates, and a surface gate electrode 72 continuous with the buried gate electrode 7 via a gate oxide film 6 is formed thereon. A p-type emitter layer 3 is formed at a position away from the buried gate portion by a predetermined process. A p ⁻ -type RESURF layer 23 is formed between the p-type emitter layer 3 and the buried gate portion.

FIG. 63 to FIG. 65 are a layout of an embodiment of a lateral IGBT in which a buried gate is provided on the anode side by modifying the above embodiment, and its AA ′ and BB ′ sectional views. Using the second substrate 22 on the element formation side as the p ⁻ type base layer 24, a groove 5 is formed in the same manner as in the above embodiment, and a buried gate electrode 71 is formed therein. An n-type base layer 1 'is formed between the grooves, and a p-type drain layer 3' is formed therein. A surface gate electrode 72 is formed thereon similarly to the above embodiment. Then, an n-type source layer 10 'is formed at a predetermined distance from the drain region.

  66 to 68 are a layout of an embodiment in which elements similar to the embodiment of FIGS. 1 to 5 are realized as horizontal elements, and sectional views taken along the lines AA 'and BB'. Parts corresponding to those in the previous embodiment are denoted by the same reference numerals as in the previous embodiment, and detailed description is omitted.

  FIGS. 69 to 71 are a layout of the device of the embodiment in which the conductivity type of each part of the above embodiment is reversed, and sectional views taken along AA 'and BB' thereof.

  In the embodiment of FIG. 31, the width dN + of the n-type source layer and the width dP + of the p-type drain layer are shown to be substantially equal. However, if dN +> dP +, the ON characteristics are improved, and dN + <dP +. In this case, the off characteristic is improved. Therefore, a desired characteristic can be obtained by optimally designing the relationship between these widths. This applies to the elements shown in FIGS. 34, 37, 40, 43, 46, 49, and 56.

  In order to increase the maximum controllable current, it is desirable to form dN + to be equal to or less than the carrier diffusion length, and when it is desired to reduce the on-voltage, it is necessary to form dN + as large as possible so that the minimum controllable maximum current can be guaranteed. desirable.

  As described above, according to the present invention, a deep buried insulated gate structure, a structure in which narrow hole current paths sandwiched between the buried insulated gates are formed at wide intervals, and a cathode emitter structure in which the injection efficiency is suppressed to be small By combining these, it is possible to realize characteristics similar to those of a GTO thyristor without causing a latch-up due to a voltage-driven element.

  Some further examples of the lateral element will be described.

  FIGS. 72 to 74 show embodiments in which the elements of the embodiments of FIGS. 66 to 68 are modified. In this embodiment, the p-type drain layer 9 is provided so as to extend not only to the region sandwiched by the buried gates 72, but also to the side wall on the cathode side of the buried gates 72.

  75 to 77 show an embodiment in which the structure of FIGS. 72 to 74 is modified, in which the n-type emitter layer 8 is diffused to a depth that does not reach the bottom of the element.

The embodiment of FIGS. 78 to 80 uses a p ⁻ type substrate having ap ⁺ type layer 25 at the bottom as the second substrate 22 and forms the n ⁻ type base layer 1 on the surface thereof. This is similar to the embodiment of FIG.

  FIGS. 81 to 83 show modifications of the embodiment shown in FIGS. 78 to 80. The width of the surface gate electrode 72 is selected to be larger than that of the buried gate electrode 71, and the region between the buried gate electrodes 71 is selected. In this embodiment, a turn-on channel region and a turn-off channel region controlled by a surface gate electrode 72 are formed on the cathode side at a predetermined distance.

  FIG. 84 et seq. Show a half-cell sectional structure of another embodiment of the vertical element.

  FIG. 84 shows an embodiment in which a buried gate as shown in FIG. 59 is not provided in a region (represented by width L) between regions (represented by width W) in which a long electron injection channel is formed.

  FIG. 85 shows an embodiment in which a buried insulated gate structure is formed also in a region where an electron injection channel is not formed in the device of FIG. The gate electrode 7 is formed continuously along the plurality of trenches 5 without completely filling the trenches 5. Then, a CVD oxide film 31 is formed on the element surface on which the gate electrode 7 is formed so as to fill the groove 5 and flatten the surface.

  FIG. 86 shows an embodiment in which the p-type layer 32 is formed between the grooves where the electron injection channel is not formed in the device of FIG. 84. By providing the p-type layer 32, the withstand voltage between the cathode electrode 11 and the n-type base layer 1 in a region where a channel is not formed can be made sufficient.

  FIG. 87 shows that, in the device structure of FIG. 86, the gate electrode 7 is formed by a polycrystalline silicon film so as not to completely fill the groove 5, and is overlapped with Al, Ti, Mo, etc. in a region where a channel is not formed. In which the low resistance metal gate 33 is formed. The low resistance metal gate 33 is covered with an organic insulating film 34 such as polyimide.

  FIG. 88 further shows that a groove 5 is formed in the entire region where a channel is not formed, a polysilicon gate electrode 7 is formed along the groove 5, and a low-resistance metal gate 33 is buried at the bottom of the groove 5. This is a working example.

  In each of the embodiments described above, in the channel region sandwiched between the buried gates, in order to increase the hole current bypass resistance, a low carrier lifetime layer by ion implantation or the like or a higher concentration of n than the n-type base layer. It is also effective to provide a mold layer and the like.

  For example, FIG. 89 shows an embodiment in which an n-type layer 35 having a higher concentration than the n-type base layer 1 is provided under the p-type base layer 4 in the device of FIG. FIG. 90 shows an embodiment in which the low carrier lifetime layer 36 is formed under the p-type base layer 4.

FIG. 91 shows an embodiment in which the structure shown in FIG. 87 is modified, in which a floating n ⁺ -type emitter layer 36 is formed on the p-type layer 32. The electron injection portion has no p-type drain and has an IGBT structure. When a positive voltage is applied to the gate electrode 7, a channel is formed between the n-type source layer 10 and the n ⁺ -type emitter layer 36 along the side wall of the groove 5. Is formed, and the n ⁺ -type emitter layer 36 is connected to the cathode electrode 11.

  FIG. 92 shows an embodiment in which the same modification as that of FIG. 91 is applied to the element of FIG.

  FIG. 93 shows an embodiment in which the p-type layer 32 formed simultaneously with the p-type base layer 4 is provided between the grooves outside the electron injection channel region in the device of the embodiment shown in FIG. FIG. 94 shows an embodiment in which the p-type layer 32 of FIG. 93 is formed deeper than the p-type base layer 4 and a floating n-type emitter layer 36 is formed thereon.

FIG. 95 shows an embodiment in which the p-type layer 32 and the n ⁺ -type emitter layer 36 of FIG. 91 are formed deeper to shorten the turn-on channel controlled by the buried gate 27.

  Each of the embodiments described above is based on the concept of "increase the hole bypass resistance due to the uniquely arranged trench gate electrode structure, thereby improving the electron injection efficiency and reducing the on-resistance of the semiconductor device". An important fact to note here is that according to the present invention, achieving a reduced on-resistance does not have to be inherently "increasing the hole bypass resistance". This is because the enhancement of carrier injection is based on the principle of "increase the ratio of hole diffusion current to electron current" which includes the concept of "increase in hole bypass resistance".

  FIG. 96 is a layout of an IEGT (Injection-Enhanced Gate Bipolar Transistor) according to a further embodiment of the present invention, and FIGS. 97, 98, 99 and 100 are respectively AA ′ and B− of FIG. It is B ', CC' and DD 'sectional drawing. In this transistor structure, the same parts as those in the embodiment of FIGS. 6 to 9 are denoted by the same reference numerals.

The n-type source layer is constituted by the n ⁺ -type semiconductor layer 10. These source regions 10 extend at right angles to the trench gate electrode 7 on the surface of the p-type drain layer 4, as shown in FIG. Cross sections of these source regions 10 associated with the trench gate electrode 7 are shown in FIG. The n ⁺ -type layer 10 located between each pair of two adjacent trench gate electrodes 7 is electrically insulated from the first main electrode layer 11 by the surface insulating layer 202.

As shown in FIG. 98, between adjacent trench gate electrodes 7, n ⁺ -type layers 10 are alternately arranged with p ⁺ -type layers 9 functioning as p-type drains. The sectional view of each trench gate electrode 7 shown in FIG. 99 is the same as that of FIG. A cross-sectional view of the p ⁺ -type drain region 9 in a direction perpendicular to the trench gate electrode 7 is shown in FIG. Here, with the same manner as in the case of FIG. 97, the p-type drain layer 9 located between each pair of two adjacent trench gate electrodes 7 is separated from the first main electrode layer 11 by the surface insulating layer 202. Is electrically insulated from The specific dimensions of this transistor structure may be similar to those of the device of FIGS.

  The operation of the IEGT in the present embodiment is as follows. When a positive voltage is applied to the gate electrode 7 with respect to the cathode electrode 11, the turn-on channel located in the peripheral portion of the p-type base layer 4 conducts. Electrons are injected from the n-type source layer 10 into the n-type base layer 1, causing conductivity modulation in the n-type base layer 1. As a result, the IEGT is turned on by the IGBT operation.

  When a negative voltage is applied to the gate electrode 7 with respect to the cathode electrode 11, the injection of electrons from the turn-on channel region stops. An inversion layer is formed on a side surface portion (groove side surface portion) of the trench gate portion facing the trench 5. By the well-known p-channel MOS transistor operation, carriers in the p-type base layer 4 are discharged to the cathode electrode 11 via the p-type drain layer 9. The semiconductor device turns off. In the case of this embodiment, even when the device is turned on, the parasitic thyristor constituted by the n-type source layer 10, the p-type base layer 4, the n-type base layer 1, and the p-type emitter layer 3 is so described as to prevent latch-up. It is especially arranged as described in When the on-channel is closed, the injection of electrons from the n-type source layer 10 stops immediately.

According to the IEBT, a certain pair of trench gates 7, a P ⁺ -type drain layer 9 located between the pair of trench gate electrodes and insulated from the electrode 11, and the insulated P ⁺ -type drain layer A “unit cell” is defined by another P ⁺ -type drain layer 9 adjacent to and sandwiching the corresponding trench gate electrode 7 and in contact with the electrode 11.

A wide trench groove (2C-2W) is formed by forming a region surrounded by a relatively narrow trench groove and insulated from the electrode 11 between the p ⁺ drain layer in contact with the electrode 11. Therefore, it is possible to avoid the technical difficulty of performing such a process, and to achieve the same effect as a wide trench.

  By appropriately arranging the depth, interval, and number of the plurality of trench gate electrodes 7 (specific examples have already been given), it is possible to obtain a sufficiently low on-resistance while preventing the device from operating as a thyristor. The “thinned-out” contact of the IEGT main electrode 11 to the p-type drain layer 9 contributes to a reduction in hole bypass current, that is, a reduced on-resistance. Further, in this embodiment, the parasitic thyristor does not latch up in the ON state, and the turn-off channel is opened at the time of turn-off, thereby forming a bypass for the flow of holes. Thus, the maximum breaking current capability is enhanced compared to current GTO thyristors configured to turn off once latched up.

  Here, the fact that a large electron injection efficiency can be obtained by arranging the ratio of the hole diffusion current to the total current will be described.

  When the impurity concentration of the emitter region in a broad sense (an example is shown in a portion surrounded by a broken line in FIG. 21) is relatively low, for example, when there is a portion in the emitter region in a broad sense that causes n to p conduction modulation. Such a structure as to increase the hole diffusion current Ip, particularly the ratio between the vertical direction (diffusion current flowing parallel to the anode-cathode direction of the device) and the electron current In (= I-Ip, I: total current). The provision in the broadly-defined emitter region can increase the injection efficiency of the broadly-defined emitter region and reduce the on-resistance of the device.

The hole current Jp (A / cm ² ) flowing through the emitter region in a broad sense, and the carrier concentration n (cm ⁻³ ) in the broad sense of the n-base emitter (n in FIG. 29).

If the hole current flowing through the emitter region in a broad sense is only the diffusion current of carriers in the vertical direction (AK direction),
Jp = 2 · μp · k · T · W · n / (C · D) (12)
Can be expressed as Here, μp is Hall mobility, k is Boltzmann coefficient, and T is temperature.

The hole injection efficiency γp of the emitter region in a broad sense is γp = Jp / J = Jp / (Jn + Jp)
= 2μp ・ k ・ T ・ W ・ n / (C ・ D ・ J) (13)
If Y = W / (C · D),
γp = 2 (μp ・ k ・ T ・ n / J) ・ Y
Assuming that μp = 500, k · T = 4.14 × 10 ⁻²¹ and J = 100 A / cm ² ,
γp = 2 × (500 × 4.14 × 10 ⁻²¹ / 100) × 1 × 10 ¹⁶ × Y
= 4.14 × 10 ^-4 · Y (16)
When the injection efficiency is sufficiently low, γp = Jp / (Jn + Jp) = μp / (μn + μp) = 0.3 (17)
Will be about. In other words, the high injection efficiency of the emitter region in a broad sense means that
γp <0.3 (18)
That is, Y satisfying this condition is
4.14 × 10 ^-4 · Y <0.3
Y <0.3 / 4.14 × 10 ⁻⁴
Y <7.25 × 10 ² (cm ⁻¹ ) (19)
When n = 7 × 10 ¹⁵ when the on-voltage is relatively high,
Y <1.0 × 10 ³ (cm ⁻¹ ) (20)
It is.

  That is, by designing the parameter Y in the above range, the injection efficiency of the emitter region in a broad sense can be increased even if the injection efficiency of the impurity diffusion layer in contact with the cathode electrode is low. That is, the accumulation of carriers in the ON state of the high resistance base layer can be increased, and the ON resistance of the element can be reduced.

  When the devices are arranged in this manner, the cathode diffusion layer having a low injection efficiency guarantees high current control capability and high-speed switching, and the effect of the present invention is to increase the injection efficiency of the emitter region in a broad sense. Resistance can also be realized at the same time.

  When the emitter region in a broad sense has a trench structure as shown in FIG. 20, the value of Y is determined by D, C and W in FIG.

  Further, when a high impurity concentration portion (Jp flows through a resistor) and a low impurity concentration portion coexist in the broadly defined emitter region, the injection efficiency of the broadly defined emitter region depends on both the aforementioned parameters X and Y. It needs to be considered.

The sectional structure in FIG. 100 is modified as shown in FIG. Here, the n ⁺ type source layer 10 extends so as to be bonded to both side end surfaces of each trench 5 in which the trench gate electrode 7 is embedded.

The IEGT shown in FIGS. 102 to 106 is basically a combination of the devices in FIGS. 96 to 100 and the devices in FIGS. 6 to 9. In other words, this IEGT is characteristically different from FIGS. 96 to 100 in that each p ⁺ -type drain layer 9 has a “ladder-shaped planar shape”. In particular, the n-type source layer 10 described in FIG. 7 is formed on the surface of the p ⁺ -type base layer 4. In the n-type source layer 10, the p-type drain layer 9 is arranged so as to be joined to both upper side ends of each trench 5. The p-type drain layer 9 is shallower than the n-type source layer 10. The portion of the n-type source layer 10 sandwiched by the bottom of the p-type drain layer 9 and the p-type drain layer 4 functions as the n-type turn-off channel layer 10 described with reference to FIG. The central portion of the n-type source layer 10 between two adjacent trench gate electrodes 7 corresponds to the n-type source layer 10 in FIG. When viewed from above the substrate surface, between two adjacent trench gate electrodes 7, the p-type drain layer 9 planarly surrounds the n-type source layer 10, thereby exhibiting a ladder-shaped planar shape.

As shown in FIG. 104, n-type source layer 10 is deeper than the p ⁺ -type drain layer 9, therefore, when viewed with the sectional structure shown here, n-type source layer 10 is p ⁺ -type drain Surrounds layer 9. The cross-sectional structure of each trench gate electrode 7 shown in FIG. 105 is the same as that of FIG. As shown in FIG. 106, the p ⁺ -type drain layer 9 is “decimated” by the surface insulating layer 202 and is in contact with the electrode 11.

  According to the IEGT of this embodiment, the trench junction side surface of the p-type base layer 4 located immediately below the n-type turn-off channel layer functions as a turn-on channel. Therefore, it can be said that both of the plurality of trench gate electrodes 7 also serve as the turn-on drive electrode and the turn-off drive electrode. That is, it has a structure in which a turn-off p-channel MOSFET and a turn-on n-channel MOSFET are vertically stacked inside the device. When a positive voltage is applied to the trench gate electrode 7, an n-type channel is formed on each trench junction side surface of the p-type base layer 4, thereby turning on the device. At this time, electrons are injected from each of the n-type source layers 10 into the n-type base layer 1 via the n-type turn-off channel and the n-type channel appearing when the inversion layer is formed. The turn-off operation is performed in a manner similar to that of the embodiment 200 shown in FIGS. 96 to 100 by applying a negative voltage to the trench gate electrode 7. According to the IEGT of this embodiment, the same effects as those of the embodiments of FIGS. 96 to 100 can be obtained.

  Finally, two modifications of the horizontal IGBT disclosed in FIGS. 60 to 83 are presented in FIGS. 107 to 202. The characteristic difference between the horizontal IGBT of FIGS. 107 to 109 and the previous example of the IGBT of FIGS. 110 to 112 is that the difference of the cell structure parameters “C” and “W” is set along the thickness direction of the substrate. It is in the point.

As shown in FIGS. 108 and 109, a trench 222 having a generally uniform rectangular cross-sectional shape is formed on the surface of the n ⁻ -type upper substrate on the intermediate insulating layer 21. The conductive layer 224 is buried insulatively in the trench 222. The thickness of the conductive layer 224 is greater than the depth of the trench 222, so that the upper half of the conductive layer 224 protrudes from the surface of the upper substrate. The conductive layer 224 functions as a trench gate electrode. The thickness of the upper substrate is C. The thickness of the trench portion of the information substrate, that is, the thickness of the active layer sandwiched between the bottom of the trench 222 and the intermediate insulating layer 21 is W, as shown in FIG. A channel region for electron injection or turn-off is formed at a portion in contact with the bottom of trench gate electrode 224.

  In such a lateral IGBT, the turn-off control electrode has a MOS control thyristor (MCT) structure. As in the embodiment of FIGS. 31 to 33, if the p-type drain layer width Dp and the n-type source layer width Dn satisfy Dp <Dn, the ON characteristics are enhanced, and if Dp> Dn, the turn-off characteristics are improved. Be strengthened. By appropriately arranging the width relationship between these layers, desired IGBT on / off characteristics can be easily realized. In order to increase the maximum controllable current of the IGBT, the width Dn is desirably formed to be equal to or less than the carrier diffusion length. In order to reduce the ON voltage, it is desirable to increase the width Dn within a range in which the minimum required level of the maximum controllable current can be guaranteed.

  According to the IGBT, a structure in which a narrow (W) hole current path sandwiched between the trench gate electrode structure 224 and the intermediate insulating film 21 is formed at an extended interval, and the injection efficiency is suppressed to be low. By the combination of the cathode emitter structure, it is possible to realize a voltage-driven power switch device in which the on-voltage is reduced like a current GTO thyristor while achieving suppressed latch-up.

The horizontal IGBTs of FIGS. 110 to 112 are similar to those of FIGS. 107 to 109 except that an n-type hole bypass resistance layer 226 is added. The hole bypass resistance layer 226 is formed at the bottom of the trench gate electrode 224, and is in contact with the n ⁺ -type layer 10, as shown in FIG. If the impurity concentration of the hole bypass resistance layer 226 is high (for example, about 10 ¹⁶ to 10 ²¹ cm ⁻³ ), the ON characteristics of the IGBT are improved. If the impurity concentration of the hole bypass resistance layer 226 is low (for example, about 10 ¹³ to 10 ¹⁸ cm ⁻³ ), a moderate improvement in the ON characteristics while maintaining the OFF characteristics of the IGBT high can be expected.

  In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.

1 is a layout diagram of an insulated gate semiconductor device according to an embodiment of the present invention. AA 'sectional drawing of FIG. BB 'sectional drawing of FIG. FIG. 2 is a sectional view taken along the line CC ′ of FIG. 1. FIG. 2 is a sectional view taken along line DD ′ of FIG. 1. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. AA 'sectional drawing of FIG. FIG. 7 is a sectional view taken along line BB ′ of FIG. 6. FIG. 7 is a sectional view taken along line CC ′ of FIG. 6. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. AA 'sectional drawing of FIG. BB 'sectional drawing of FIG. FIG. 11 is a sectional view taken along the line CC ′ of FIG. 10. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. FIG. 15 is a sectional view taken along line AA ′ of FIG. 14. FIG. 15 is a sectional view taken along line BB ′ of FIG. 14. FIG. 15 is a sectional view taken along the line CC ′ of FIG. 14. FIG. 11 is a sectional view showing a unit cell structure of an insulated gate semiconductor device of another embodiment. FIG. 19 is a diagram showing one of AA ′ and BB ′ impurity concentration distributions of the device of FIG. 18. FIG. 2 is a cross-sectional view of a buried insulated gate IBGT of a simulation model. Diagram for explaining the operation principle of the model of FIG. 20, The figure which shows the relationship between the depth of a buried gate part and the current density of the same model. The figure which shows the relationship between the width | variety of an embedded gate part and the current density of the same model. The figure which shows the relationship between the width | variety of a buried gate part and current density on the other conditions of the model. The figure which shows the current-voltage characteristic of the same model. The figure which shows the current-voltage characteristic under other conditions of the same model. The figure which shows the current and voltage change characteristic of the same model. FIG. 7 is a diagram showing a relationship between parameters X (D, W, C) and carrier lifetime τp and current density of the element. FIG. 4 is a diagram showing a carrier concentration distribution in an ON state of the element. FIG. 7 is a diagram showing a structure in which the same model is applied to the device of the embodiment in FIG. 6. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. AA 'sectional drawing of FIG. FIG. 32 is a sectional view taken along line BB ′ of FIG. 31. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. FIG. 35 is a sectional view taken along the line AA ′ of FIG. 34. FIG. 35 is a sectional view taken along line BB ′ of FIG. 34. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. AA 'sectional drawing of FIG. FIG. 38 is a sectional view taken along line BB ′ of FIG. 37. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. AA 'sectional drawing of FIG. FIG. 41 is a sectional view taken along the line BB ′ of FIG. 40. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. FIG. 44 is a sectional view taken along line AA ′ of FIG. 43. FIG. 44 is a sectional view taken along line BB ′ of FIG. 43. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. AA 'sectional drawing of FIG. FIG. 47 is a sectional view taken along line BB ′ of FIG. 46. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. AA 'sectional drawing of FIG. FIG. 50 is a sectional view taken along the line BB ′ of FIG. 49. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. FIG. 53 is a sectional view taken along the line AA ′ of FIG. 52. FIG. 53 is a sectional view taken along the line BB ′ of FIG. 52. FIG. 53 is a sectional view taken along the line CC ′ of FIG. 52. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. AA 'sectional drawing of FIG. 56. FIG. 57 is a sectional view taken along the line BB ′ of FIG. 56. The figure which shows the modification of FIG. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. AA 'sectional drawing of FIG. FIG. 61 is a sectional view taken along the line BB ′ of FIG. 60. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. AA 'sectional drawing of FIG. 63. FIG. 63 is a sectional view taken along the line BB ′ of FIG. 63; FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. AA 'sectional drawing of FIG. FIG. 67 is a sectional view taken along the line BB ′ of FIG. 66. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. AA 'sectional drawing of FIG. 69. FIG. 69 is a sectional view taken along the line BB ′ of FIG. 69. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. FIG. 72 is a sectional view taken along the line AA ′ of FIG. 72. FIG. 72 is a sectional view taken along the line BB ′ of FIG. 72. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. AA 'sectional drawing of FIG. FIG. 76 is a sectional view taken along the line BB ′ of FIG. 75. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. AA 'sectional drawing of FIG. 78. FIG. 78 is a sectional view taken along the line BB ′ of FIG. 78. FIG. 10 is a layout diagram of an insulated gate semiconductor device of another embodiment. FIG. 82 is a sectional view taken along the line AA ′ of FIG. 81. FIG. 83 is a sectional view taken along the line BB ′ of FIG. 81. The figure which shows the 1/2 cell sectional structure of another Example. The figure which shows the 1/2 cell sectional structure of another Example. The figure which shows the 1/2 cell sectional structure of another Example. The figure which shows the 1/2 cell sectional structure of another Example. The figure which shows the 1/2 cell sectional structure of another Example. The figure which shows the 1/2 cell sectional structure of another Example. The figure which shows the 1/2 cell sectional structure of another Example. The figure which shows the 1/2 cell sectional structure of another Example. The figure which shows the 1/2 cell sectional structure of another Example. The figure which shows the 1/2 cell sectional structure of another Example. The figure which shows the 1/2 cell sectional structure of another Example. The figure which shows the 1/2 cell sectional structure of another Example. FIG. 13 is a layout diagram of an IEGT according to another embodiment. FIG. 96 is a sectional view taken along the line AA ′ of FIG. 96. FIG. 96 is a sectional view taken along the line BB ′ of FIG. 96. FIG. 96 is a sectional view taken along the line CC ′ of FIG. 96. FIG. 96 is a sectional view taken along the line DD ′ of FIG. 96. Sectional drawing which shows the modification of FIG. FIG. 13 is a layout diagram of an IEGT according to another embodiment. AA 'sectional drawing of FIG. FIG. 103 is a sectional view taken along the line BB ′ of FIG. 102. FIG. 103 is a sectional view taken along the line CC ′ of FIG. 102. FIG. 103 is a sectional view taken along the line DD ′ of FIG. 102. FIG. 84 is a view showing a modification of the horizontal IGBT of FIGS. 60 to 83. FIG. 84 is a view showing a modification of the horizontal IGBT of FIGS. 60 to 83. FIG. 84 is a view showing a modification of the horizontal IGBT of FIGS. 60 to 83. FIG. 84 is a view showing a modification of the horizontal IGBT of FIGS. 60 to 83. FIG. 84 is a view showing a modification of the horizontal IGBT of FIGS. 60 to 83. FIG. 84 is a view showing a modification of the horizontal IGBT of FIGS. 60 to 83.

Explanation of reference numerals

1 ... n-type base layer,
2 ... n-type buffer layer,
3 ... p-type emitter layer,
4: p-type base layer,
5 ... groove,
6 ... gate oxide film,
7 ... gate electrode,
8 ... n-type turn-off channel layer,
9 ... p-type drain layer,
10 ... n-type source layer,
11 ... cathode electrode,
12 ... Anode electrode.

Claims (1)

A second conductivity type emitter layer;
A first conductivity type base layer formed in contact with the second conductivity type emitter layer;
A gate electrode buried in a plurality of trenches formed in the first conductivity type base layer via a gate insulating film;
A first conductivity type turn-off channel layer formed on a surface of the first conductivity type base layer in contact with a side surface of the groove;
A second conductivity type drain layer formed on the surface of the turn-off channel layer in contact with a side surface of the groove;
A first conductivity type source layer diffused and formed to a depth not exceeding the turn-off channel layer on a surface portion of the first conductivity type base layer;
A first main electrode formed by simultaneously contacting the second conductivity type drain layer and the first conductivity type source layer;
A second main electrode formed on the second conductivity type emitter layer;
A power semiconductor device comprising:

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