JP4127815B2 - Avalanche photodiode - Google Patents

Avalanche photodiode Download PDF

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JP4127815B2
JP4127815B2 JP2003379299A JP2003379299A JP4127815B2 JP 4127815 B2 JP4127815 B2 JP 4127815B2 JP 2003379299 A JP2003379299 A JP 2003379299A JP 2003379299 A JP2003379299 A JP 2003379299A JP 4127815 B2 JP4127815 B2 JP 4127815B2
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幸弘 廣田
精後 安藤
忠夫 石橋
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Nippon Telegraph and Telephone Corp
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Description

本発明は、アバランシェフォトダイオードに関し、例えば、長波長帯域に好適なものである。   The present invention relates to an avalanche photodiode, and is suitable for a long wavelength band, for example.

アバランシェフォトダイオード(以下、APDと略す。)は、素子自体が増幅機能を有しているため、高感度の受光素子として光計測、光通信に広く用いられている。一般に、大容量長距離光通信用に採用されている1.55μm帯のInGaAs/InP−APDとしては、光吸収層となだれ(アバランシェ)増倍領域を分離し、暗電流の低減のため、光吸収層/なだれ増倍領域間に電界制御のための電荷層を導入したSACM(Separated Absorption, charge and Multiplication)構造が用いられる。但し、電子注入型APDの場合には、光吸収層を逆バイアス印加時に空乏化させるため、低濃度のp型InGaAs半導体とする必要がある。   An avalanche photodiode (hereinafter abbreviated as APD) is widely used as a highly sensitive light receiving element in optical measurement and optical communication because the element itself has an amplification function. In general, the 1.55 μm band InGaAs / InP-APD used for large-capacity long-distance optical communication separates the avalanche multiplication region from the light absorption layer, and reduces the dark current. A SACM (Separated Absorption, Charge and Multiplication) structure in which a charge layer for electric field control is introduced between the absorption layer / avalanche multiplication region is used. However, in the case of an electron injection type APD, it is necessary to use a low-concentration p-type InGaAs semiconductor in order to deplete the light absorption layer when a reverse bias is applied.

近年、このSACM構造の低濃度p型InGaAs光吸収層を高濃度にした電子注入型のAPDが注目されている(図4(a)参照)。
この電子注入型APDは、図4(a)に示すように、半絶縁性InP基板401上に、アンドープ半導体からなる半絶縁性バッファ層402を介して、高濃度n型半導体電極層403と、アンドープ半導体からなるなだれ増倍層404と、電界制御層405と、アンドープ半導体からなる電界緩和層406と、バンドギャップ傾斜層407と、光吸収層408と、高濃度p型半導体拡散バリア層409と、高濃度p型半導体電極層410とを順次積層して、メサ構造を形成し、更に、n型電極層403とp型電極層410上に、n電極411、p電極412を各々形成した構造である。
In recent years, attention has been focused on an electron injection type APD in which a low concentration p-type InGaAs light absorption layer having a SACM structure is formed at a high concentration (see FIG. 4A).
As shown in FIG. 4A, the electron injection type APD includes a high-concentration n-type semiconductor electrode layer 403 on a semi-insulating InP substrate 401 via a semi-insulating buffer layer 402 made of an undoped semiconductor. An avalanche multiplication layer 404 made of an undoped semiconductor, an electric field control layer 405, an electric field relaxation layer 406 made of an undoped semiconductor, a band gap inclined layer 407, a light absorption layer 408, a high-concentration p-type semiconductor diffusion barrier layer 409, Then, a high-concentration p-type semiconductor electrode layer 410 is sequentially laminated to form a mesa structure, and an n-electrode 411 and a p-electrode 412 are formed on the n-type electrode layer 403 and the p-type electrode layer 410, respectively. It is.

上記構造により、逆バイアス印加時においても光吸収層408が中性化しているので、光吸収層408の空乏化に必要となる電界が不用となり、比較的低電圧で駆動できる電子注入型APDを実現することができるため、注目されている。
図4(b)に上記構造の電子注入型APDのバンド構造を図示した。図4(b)に示すように、光吸収層408の下層側となるバンドギャップ傾斜層407、電界緩和層406、電界制御層405、なだれ増倍層404が空乏化することで、アバランシェ動作が可能な状態になると共に、光吸収層408自体は、略中性化を保つようになっている。
但し、電子注入型APDは、なだれ増倍層404中にn型拡散電極領域を作り込むのが困難であり、又、n電極層403の低抵抗化のため半絶縁性InP基板401側にとる必要から、一般には図4(a)に示すようなメサ型構造が採られる。
With the above structure, since the light absorption layer 408 is neutralized even when a reverse bias is applied, an electric field required for depletion of the light absorption layer 408 is unnecessary, and an electron injection type APD that can be driven at a relatively low voltage is provided. It is attracting attention because it can be realized.
FIG. 4B shows the band structure of the electron injection APD having the above structure. As shown in FIG. 4B, the band gap gradient layer 407, the electric field relaxation layer 406, the electric field control layer 405, and the avalanche multiplication layer 404 on the lower layer side of the light absorption layer 408 are depleted, so that the avalanche operation is performed. In addition to being in a possible state, the light absorption layer 408 itself is substantially neutralized.
However, in the electron injection type APD, it is difficult to form an n-type diffusion electrode region in the avalanche multiplication layer 404, and it is arranged on the semi-insulating InP substrate 401 side to reduce the resistance of the n-electrode layer 403. In general, a mesa structure as shown in FIG.

特許第3141847号公報Japanese Patent No. 3141847

電子注入型APDはメサ構造を採るがために、信頼性試験(例えば、雰囲気温度200℃、逆方向電流100μAのバイアス条件)において、表面の劣化による暗電流(図4(a)の矢印c参照)の増大という問題を抱えている。これは、メサ構造では、信頼性試験での加熱・通電により素子表面近傍に結晶欠陥が増大し、これに伴う表面準位密度の増大により、表面を通って流れる暗電流が次第に大きくなるためである。この表面を流れる暗電流は、表面劣化の進行が表面の暗電流値に依存するため加速度的に増大する。このため、表面を流れる暗電流の増大を如何にして抑えるかが電子注入型APDの実現上の問題となっており、電子注入型APDの安定性、寿命を左右する大きな要因となっていた。   Since the electron injection type APD adopts a mesa structure, in a reliability test (for example, a bias condition of an atmospheric temperature of 200 ° C. and a reverse current of 100 μA), a dark current due to surface degradation (see arrow c in FIG. 4A) ) Increase. This is because in the mesa structure, crystal defects increase in the vicinity of the element surface due to heating and energization in the reliability test, and the dark current flowing through the surface gradually increases due to the accompanying increase in the surface state density. is there. The dark current flowing on the surface increases at an accelerated rate because the progress of surface degradation depends on the dark current value of the surface. For this reason, how to suppress the increase in dark current flowing on the surface is a problem in realizing the electron injection APD, and is a major factor that affects the stability and life of the electron injection APD.

本発明は上記課題に鑑みなされたもので、安定で長寿命の電子注入型のアバランシェフォトダイオードを提供することを目的とする。   The present invention has been made in view of the above problems, and an object thereof is to provide a stable and long-life electron injection avalanche photodiode.

上記課題を解決する本発明の請求項1に係るアバランシェフォトダイオードは、
半絶縁性基板上に、アンドープ半導体からなるバッファ層を介して、
高濃度n型半導体電極層と、アンドープ半導体からなるなだれ増倍層と、p型電界制御層と、アンドープ半導体からなる電界緩和層と、バンドギャップ傾斜層と、p型半導体光吸収層と、高濃度p型半導体拡散バリア層と、高濃度p型半導体電極層とを順次積層して、メサ構造とすると共に、
前記電界緩和層の外周側の膜厚を、前記電界緩和層の中央部の膜厚に対して厚く形成したことを特徴とする。
An avalanche photodiode according to claim 1 of the present invention for solving the above-described problems is provided.
Through a buffer layer made of an undoped semiconductor on a semi-insulating substrate,
A high-concentration n-type semiconductor electrode layer, an avalanche multiplication layer made of an undoped semiconductor, a p-type electric field control layer, an electric field relaxation layer made of an undoped semiconductor, a band gap inclined layer, a p-type semiconductor light absorption layer, A concentration p-type semiconductor diffusion barrier layer and a high concentration p-type semiconductor electrode layer are sequentially stacked to form a mesa structure,
The film thickness on the outer peripheral side of the electric field relaxation layer is formed thicker than the film thickness of the central portion of the electric field relaxation layer.

上記課題を解決する本発明の請求項2に係るアバランシェフォトダイオードは、
半絶縁性基板上に、アンドープ半導体からなるバッファ層を介して、
高濃度n型半導体電極層と、アンドープ半導体からなるなだれ増倍層と、p型電界制御層と、アンドープ半導体からなる第1の電界緩和層と、中空部を有するアンドープ半導体からなる第2の電界緩和層と、バンドギャップ傾斜層と、p型半導体光吸収層と、高濃度p型半導体拡散バリア層と、高濃度p型半導体電極層とを順次積層して、メサ構造とすると共に、
前記第2の電界緩和層の前記中空部を、前記p型半導体光吸収層の外周より内側に形成したことを特徴とする。
An avalanche photodiode according to claim 2 of the present invention for solving the above-described problem is provided.
Through a buffer layer made of an undoped semiconductor on a semi-insulating substrate,
High-concentration n-type semiconductor electrode layer, avalanche multiplication layer made of undoped semiconductor, p-type electric field control layer, first electric field relaxation layer made of undoped semiconductor, and second electric field made of undoped semiconductor having a hollow portion A relaxation layer, a band gap inclined layer, a p-type semiconductor light absorption layer, a high-concentration p-type semiconductor diffusion barrier layer, and a high-concentration p-type semiconductor electrode layer are sequentially stacked to form a mesa structure.
The hollow portion of the second electric field relaxation layer is formed inside the outer periphery of the p-type semiconductor light absorption layer.

上記課題を解決する本発明の請求項3に係るアバランシェフォトダイオードは、
上記アバランシェフォトダイオードにおいて、
前記メサ構造を、前記半絶縁性基板側の層の外周の幅が大きくなる階段状にすると共に、
前記電界緩和層又は第2の電界緩和層の外周の幅を、前記p型半導体光吸収層の外周の幅より大きくしたことを特徴とする。
つまり、p型半導体光吸収層、バンドギャップ傾斜層側のメサ構造部分の周縁部直下に、電界緩和層の膜厚の厚い部分又はリング状の第2の電界緩和層が挿入され、そのリング状の部分は、p型半導体光吸収層、バンドギャップ傾斜層側のメサ構造部分の外周の位置に対して、その内側から外側へ横断する幅を持って配置される。なお、電界緩和層の中央部の膜厚の薄い部分又は第2の電界緩和層の中空部には、上層側のバンドギャップ傾斜層が形成される。
An avalanche photodiode according to claim 3 of the present invention for solving the above-described problem is provided.
In the avalanche photodiode,
The mesa structure is stepped so that the width of the outer periphery of the layer on the semi-insulating substrate side is increased,
The width of the outer periphery of the electric field relaxation layer or the second electric field relaxation layer is made larger than the width of the outer periphery of the p-type semiconductor light absorption layer.
That is, a thick portion of the electric field relaxation layer or a ring-shaped second electric field relaxation layer is inserted immediately below the peripheral portion of the mesa structure portion on the p-type semiconductor light absorption layer and the band gap inclined layer side, and the ring shape This portion is disposed with a width that traverses from the inside to the outside with respect to the position of the outer periphery of the mesa structure portion on the p-type semiconductor light absorption layer and band gap inclined layer side. An upper band gap gradient layer is formed in the thin portion of the central portion of the electric field relaxation layer or the hollow portion of the second electric field relaxation layer.

上記課題を解決する本発明の請求項4に係るアバランシェフォトダイオードは、
半絶縁性基板上に、アンドープ半導体からなるバッファ層を介して、
高濃度n型半導体電極層と、アンドープ半導体からなるなだれ増倍層と、p型電界制御層と、アンドープ半導体からなる電界緩和層と、バンドギャップ傾斜層と、p型半導体光吸収層と、高濃度p型半導体拡散バリア層と、高濃度p型半導体電極層とを順次積層して、メサ構造とすると共に、
前記p型電界制御層の外周側の膜厚を、前記p型電界制御層の中央部の膜厚に対して厚く形成したことを特徴とする。
An avalanche photodiode according to claim 4 of the present invention for solving the above-described problem is provided.
Through a buffer layer made of an undoped semiconductor on a semi-insulating substrate,
A high-concentration n-type semiconductor electrode layer, an avalanche multiplication layer made of an undoped semiconductor, a p-type electric field control layer, an electric field relaxation layer made of an undoped semiconductor, a band gap inclined layer, a p-type semiconductor light absorption layer, A concentration p-type semiconductor diffusion barrier layer and a high concentration p-type semiconductor electrode layer are sequentially stacked to form a mesa structure,
The film thickness on the outer peripheral side of the p-type electric field control layer is formed thicker than the film thickness of the central portion of the p-type electric field control layer.

上記課題を解決する本発明の請求項5に係るアバランシェフォトダイオードは、
半絶縁性基板上に、アンドープ半導体からなるバッファ層を介して、
高濃度n型半導体電極層と、アンドープ半導体からなるなだれ増倍層と、第1のp型電界制御層と、中空部を有する第2のp型電界制御層と、アンドープ半導体からなる電界緩和層と、バンドギャップ傾斜層と、p型半導体光吸収層と、高濃度p型半導体拡散バリア層と、高濃度p型半導体電極層とを順次積層して、メサ構造とすると共に、
前記第2のp型電界制御層の前記中空部を、前記p型半導体光吸収層の外周より内側に形成したことを特徴とする。
An avalanche photodiode according to claim 5 of the present invention for solving the above-described problem is provided.
Through a buffer layer made of an undoped semiconductor on a semi-insulating substrate,
High-concentration n-type semiconductor electrode layer, avalanche multiplication layer made of undoped semiconductor, first p-type electric field control layer, second p-type electric field control layer having a hollow portion, and electric field relaxation layer made of undoped semiconductor And a mesa structure by sequentially stacking a band gap inclined layer, a p-type semiconductor light absorption layer, a high-concentration p-type semiconductor diffusion barrier layer, and a high-concentration p-type semiconductor electrode layer,
The hollow portion of the second p-type electric field control layer is formed inside the outer periphery of the p-type semiconductor light absorption layer.

上記課題を解決する本発明の請求項6に係るアバランシェフォトダイオードは、
上記アバランシェフォトダイオードにおいて、
前記メサ構造を、前記半絶縁性基板側の層の外周の幅が大きくなる階段状にすると共に、
前記p型電界制御層又は第2のp型電界制御層の外周の幅を、前記p型半導体光吸収層の外周の幅より大きくしたことを特徴とする。
つまり、p型半導体光吸収層、バンドギャップ傾斜層側のメサ構造部分の周縁部直下に、p型電界制御層の膜厚の厚い部分又はリング状の第2のp型電界制御層が挿入され、そのリング状の部分は、p型半導体光吸収層、バンドギャップ傾斜層側のメサ構造部分の外周の位置に対して、その内側から外側へ横断する幅を持って配置される。なお、p型電界制御層の中央部の膜厚の薄い部分又は第2のp型電界制御層の中空部には、上層側の電界緩和層が形成される。
An avalanche photodiode according to claim 6 of the present invention for solving the above-described problem is provided.
In the avalanche photodiode,
The mesa structure is stepped so that the width of the outer periphery of the layer on the semi-insulating substrate side is increased,
The outer width of the p-type electric field control layer or the second p-type electric field control layer is made larger than the outer width of the p-type semiconductor light absorption layer.
That is, a thick portion of the p-type electric field control layer or a ring-shaped second p-type electric field control layer is inserted immediately below the peripheral edge of the p-type semiconductor light absorption layer and the mesa structure portion on the band gap inclined layer side. The ring-shaped portion is arranged with a width that traverses from the inside to the outside with respect to the position of the outer periphery of the mesa structure portion on the p-type semiconductor light absorption layer and the band gap inclined layer side. An upper electric field relaxation layer is formed in the thin portion at the center of the p-type electric field control layer or the hollow portion of the second p-type electric field control layer.

上記課題を解決する本発明の請求項7に係るアバランシェフォトダイオードは、
半絶縁性基板上に、アンドープ半導体からなるバッファ層を介して、
高濃度n型半導体電極層と、アンドープ半導体からなるなだれ増倍層と、p型電界制御層と、アンドープ半導体からなる電界緩和層と、バンドギャップ傾斜層と、p型半導体光吸収層と、高濃度p型半導体拡散バリア層と、高濃度p型半導体電極層とを順次積層して、メサ構造とすると共に、
前記p型電界制御層中に、前記p型電界制御層より高濃度のp型電界制御領域を、前記p型半導体光吸収層の周縁部に沿って中空形状に形成し、
前記高濃度のp型電界制御領域の内側の位置を、前記p型半導体光吸収層の外周より内側に配置したことを特徴とする。
An avalanche photodiode according to claim 7 of the present invention for solving the above-described problem is provided.
Through a buffer layer made of an undoped semiconductor on a semi-insulating substrate,
A high-concentration n-type semiconductor electrode layer, an avalanche multiplication layer made of an undoped semiconductor, a p-type electric field control layer, an electric field relaxation layer made of an undoped semiconductor, a band gap inclined layer, a p-type semiconductor light absorption layer, A concentration p-type semiconductor diffusion barrier layer and a high concentration p-type semiconductor electrode layer are sequentially stacked to form a mesa structure,
In the p-type electric field control layer, a p-type electric field control region having a higher concentration than the p-type electric field control layer is formed in a hollow shape along the peripheral edge of the p-type semiconductor light absorption layer,
The position inside the high-concentration p-type electric field control region is arranged inside the outer periphery of the p-type semiconductor light absorption layer.

上記課題を解決する本発明の請求項8に係るアバランシェフォトダイオードは、
上記アバランシェフォトダイオードにおいて、
前記メサ構造を、前記半絶縁性基板側の層の外周の幅が大きくなる階段状にすると共に、
前記p型電界制御層の外周の幅を、前記p型半導体光吸収層の外周の幅より大きくして、前記高濃度のp型電界制御領域の外側の位置を、前記p型半導体光吸収層の外周より外側に配置したことを特徴とする。
つまり、リング状の高濃度p型電界制御領域は、p型半導体光吸収層、バンドギャップ傾斜層側のメサ構造部分の外周の位置に対して、その内側から外側へ横断する幅を持って配置される。
An avalanche photodiode according to claim 8 of the present invention for solving the above-described problem is provided.
In the avalanche photodiode,
The mesa structure is stepped so that the width of the outer periphery of the layer on the semi-insulating substrate side is increased,
The width of the outer periphery of the p-type electric field control layer is made larger than the width of the outer periphery of the p-type semiconductor light absorption layer, and the position outside the high-concentration p-type electric field control region is positioned at the p-type semiconductor light absorption layer. It has arrange | positioned outside the outer periphery of.
That is, the ring-shaped high-concentration p-type electric field control region is arranged with a width that traverses from the inside to the outside with respect to the position of the outer periphery of the mesa structure portion on the p-type semiconductor light absorption layer and the band gap inclined layer side. Is done.

本発明によれば、電子注入型APDにおいて、メサ構造周縁部の光吸収層−電界制御層間の電界強度を緩和するので、又は、メサ構造周縁部に中性化領域を形成するので、メサ構造周縁部の表面を流れる暗電流及びメサ構造周縁部内部の暗電流を減少させることができ、その結果、暗電流による表面劣化を抑え、素子特性が安定した長寿命の電子注入型APDとすることができる。   According to the present invention, in the electron injection type APD, since the electric field strength between the light absorption layer and the electric field control layer at the periphery of the mesa structure is relaxed, or the neutralized region is formed at the periphery of the mesa structure, the mesa structure The dark current flowing on the surface of the peripheral portion and the dark current inside the peripheral portion of the mesa structure can be reduced. As a result, the surface deterioration due to the dark current is suppressed, and a long-life electron injection type APD with stable device characteristics is obtained. Can do.

本発明は、メサ型構造をとる電子注入型アバランシェフォトダイオード(APD)において、結晶再成長或いはイオン注入等の手法を用いて、光吸収層、バンドギャップ層を含むメサ構造部分の周縁部直下において、メサ構造周縁部にリング状の第2の電界緩和層(アンドープ層)や第2の電界制御層(P型層)を設けたり、その層厚を増大させたりすることにより、又は、メサ構造周縁部の電界制御層のドーピング濃度を高濃度にすることにより、光吸収層を含むメサ構造の周縁部の電界強度を緩和して、メサ構造の周縁部或いはメサ構造の周縁部の表面の暗電流を減少させて、表面の劣化を減少させるものである。   The present invention relates to an electron injection type avalanche photodiode (APD) having a mesa structure, using a technique such as crystal regrowth or ion implantation, immediately below the periphery of a mesa structure including a light absorption layer and a band gap layer. By providing a ring-shaped second electric field relaxation layer (undoped layer) or second electric field control layer (P-type layer) at the periphery of the mesa structure, or by increasing the layer thickness, or the mesa structure By increasing the doping concentration of the electric field control layer in the peripheral part, the electric field strength in the peripheral part of the mesa structure including the light absorption layer is relaxed, and darkness of the peripheral part of the mesa structure or the peripheral part of the mesa structure is reduced. It reduces the current and reduces the surface degradation.

以下、本発明に係るAPDの実施形態のいくつかを、図面を参照して説明する。   Hereinafter, some embodiments of the APD according to the present invention will be described with reference to the drawings.

図1は、本発明に係るAPDの実施形態の一例を示す図である。
図1(a)は、その概略図であり、図1(b)は、図1(a)のE1−E2線におけるバンド構造図である。
図1(a)に示すように、本実施例のAPDは、半絶縁性InP基板101上に、アンドープ半導体からなる半絶縁性バッファ層102を介して、高濃度n型半導体電極層103と、アンドープ半導体からなるなだれ増倍層104と、p型電界制御層105と、アンドープ半導体からなる第1の電界緩和層106と、エッチストップ層107と、中空部を有するアンドープ半導体からなる第2の電界緩和層108と、バンドギャップ傾斜層109と、p型半導体光吸収層110と、高濃度p型半導体拡散バリア層111と、高濃度p型半導体電極層112とを順次積層して、半絶縁性InP基板101側の層の外周の幅が大きい階段状のメサ構造を形成し、更に、n型電極層103とp型電極層112上に、n電極113、p電極114を各々形成した構造である。
FIG. 1 is a diagram showing an example of an embodiment of an APD according to the present invention.
FIG. 1 (a) is a schematic diagram thereof, and FIG. 1 (b) is a band structure diagram along line E1-E2 of FIG. 1 (a).
As shown in FIG. 1A, the APD of this example includes a high-concentration n-type semiconductor electrode layer 103 on a semi-insulating InP substrate 101 via a semi-insulating buffer layer 102 made of an undoped semiconductor, An avalanche multiplication layer 104 made of an undoped semiconductor, a p-type electric field control layer 105, a first electric field relaxation layer 106 made of an undoped semiconductor, an etch stop layer 107, and a second electric field made of an undoped semiconductor having a hollow portion. The relaxation layer 108, the band gap inclined layer 109, the p-type semiconductor light absorption layer 110, the high-concentration p-type semiconductor diffusion barrier layer 111, and the high-concentration p-type semiconductor electrode layer 112 are sequentially laminated to be semi-insulating. A stepwise mesa structure with a large outer peripheral width of the layer on the InP substrate 101 side is formed, and an n electrode 113 and a p electrode 114 are formed on the n type electrode layer 103 and the p type electrode layer 112, respectively. is there.

第2の電界緩和層108は、その中空部がバンドギャップ傾斜層109、p型半導体光吸収層110の外周より内側に形成されており、又、第2の電界緩和層108の外周の幅がバンドギャップ傾斜層109、p型半導体光吸収層110の外周の幅より大きく形成されている。つまり、第2の電界緩和層108はリング状の形状となっており、そのリング状の第2の電界緩和層108の内側の位置は、p型半導体光吸収層110を含むメサ構造側の外周の位置より内側であり、リング状の第2の電界緩和層108の外側の位置は、p型半導体光吸収層110を含むメサ構造側の外周の位置より外側であるように配置される。   The hollow portion of the second electric field relaxation layer 108 is formed inside the outer periphery of the band gap inclined layer 109 and the p-type semiconductor light absorption layer 110, and the width of the outer periphery of the second electric field relaxation layer 108 is The band gap gradient layer 109 and the p-type semiconductor light absorption layer 110 are formed to be larger than the outer peripheral width. That is, the second electric field relaxation layer 108 has a ring shape, and the position inside the ring-shaped second electric field relaxation layer 108 is the outer periphery on the mesa structure side including the p-type semiconductor light absorption layer 110. The position outside the ring-shaped second electric field relaxation layer 108 is located outside the position of the outer periphery on the mesa structure side including the p-type semiconductor light absorption layer 110.

上記構造のAPDは、例えば、以下の方法で作製する。
まず、半絶縁性InP基板101上に、半絶縁性バッファ層102から第2の電界緩和層108までの各層を、順次エピタキシャル成長し、その後、第2の電界緩和層108の中央部をエッチストップ層107までエッチングにより取り除き、中央部に中空部を有するリング形状とする。次に、バンドギャップ傾斜層109、p型半導体光吸収層110、高濃度p型半導体拡散バリア層111、高濃度p型半導体電極層112をエピタキシャル再成長させる。再成長後に、光吸収層109、電界緩和層108及びなだれ増倍層104を含む各層をエッチングし、図1(a)に示すような階段状のメサ構造を作製する。n電極113の及びp電極114は、各工程間の適宜なときに、或いは工程の最後に形成する。
The APD having the above structure is produced by the following method, for example.
First, each layer from the semi-insulating buffer layer 102 to the second electric field relaxation layer 108 is epitaxially grown sequentially on the semi-insulating InP substrate 101, and then the central portion of the second electric field relaxation layer 108 is formed as an etch stop layer. It removes to 107 by etching, and makes it a ring shape which has a hollow part in the center part. Next, the band gap inclined layer 109, the p-type semiconductor light absorption layer 110, the high-concentration p-type semiconductor diffusion barrier layer 111, and the high-concentration p-type semiconductor electrode layer 112 are epitaxially regrown. After the regrowth, each layer including the light absorption layer 109, the electric field relaxation layer 108, and the avalanche multiplication layer 104 is etched to produce a stepped mesa structure as shown in FIG. The n-electrode 113 and the p-electrode 114 are formed at an appropriate time between processes or at the end of the process.

上記メサ構造のAPDでは、素子表面の暗電流や電界強度を、更に抑制することを考慮して、階段状のメサ構造に形成して、n電極113とp電極114との距離(道のり)ができるだけ離れるように配置している。なお、メサ構造を階段状としない場合でも、本実施例は適用可能であり、例えば、垂直な側壁面を有するメサ構造の場合には、第2の電界緩和層108の外側の位置は、メサ構造の側壁面の位置までとしてもよい。   In the mesa structure APD, in consideration of further suppressing the dark current and the electric field intensity on the element surface, the mesa structure is formed in a stepped mesa structure, and the distance (path) between the n electrode 113 and the p electrode 114 is increased. They are placed as far away as possible. Note that this embodiment can be applied even when the mesa structure is not stepped. For example, in the case of a mesa structure having a vertical side wall surface, the position outside the second electric field relaxation layer 108 is mesa. It may be up to the position of the side wall surface of the structure.

又、エッチストップ層107を使用しない構造の場合には、第2の電界緩和層108も無くし、その代わりに、第1の電界緩和層106を2倍程度の膜厚に形成した後、第1の電界緩和層106の中央部のみを半分程度の膜厚にエッチングし、その後、バンドギャップ傾斜層109、p型半導体光吸収層110、高濃度p型半導体拡散バリア層111をエピタキシャル再成長させたメサ構造のAPDでもよく、図1(a)に示したメサ構造のAPDと同等のものを作製することができる。
つまり、上記メサ構造のAPDでは、光吸収層110の下層側であり、メサ構造の周縁部である電界緩和層106の外周側の膜厚が、電界緩和層106の中央部の膜厚に対して、2倍程度厚く形成された構造となっている。
In the case of a structure that does not use the etch stop layer 107, the second electric field relaxation layer 108 is also eliminated. Instead, the first electric field relaxation layer 106 is formed to a thickness of about twice, and then the first electric field relaxation layer 106 is formed. Only the central portion of the electric field relaxation layer 106 is etched to a thickness of about half, and then the band gap inclined layer 109, the p-type semiconductor light absorption layer 110, and the high-concentration p-type semiconductor diffusion barrier layer 111 are epitaxially regrown. A mesa-structured APD may be used, and an equivalent to the mesa-structured APD shown in FIG.
That is, in the APD having the mesa structure, the film thickness on the lower layer side of the light absorption layer 110 and on the outer peripheral side of the electric field relaxation layer 106 that is the peripheral portion of the mesa structure is smaller than the film thickness of the central portion of the electric field relaxation layer 106. Thus, the structure is formed about twice as thick.

本実施例のAPDの動作状態は、メサ構造の中央部では、光吸収層110の下層側であるなだれ増倍層104、電界制御層105、第1の電界緩和層106、エッチストップ層107、バンドギャップ傾斜層109は空乏化し、アバランシェ動作の可能な状態になり、又、この時の光吸収層110はほとんど中性を保つため、APDの低電圧駆動が可能となる。つまり、メサ構造の中央部(例えば、図1(a)のS1−S2線の部分)は、図4(b)に示したバンド構造と同等のバンド構造となる。   In the central part of the mesa structure, the operating state of the APD of this example is the avalanche multiplication layer 104, the electric field control layer 105, the first electric field relaxation layer 106, the etch stop layer 107, which are on the lower layer side of the light absorption layer 110, The band gap gradient layer 109 is depleted and is in a state where avalanche operation is possible, and the light absorption layer 110 at this time is almost neutral, so that the APD can be driven at a low voltage. That is, the central portion of the mesa structure (for example, the portion of the S1-S2 line in FIG. 1A) has a band structure equivalent to the band structure shown in FIG.

ここで、比較のため、本実施例のAPDのメサ構造周縁部のバンド構造を図1(b)に示す。これは、図1(a)のE1−E2線の部分に該当する。
なお、図1(b)において、高さ方向の電位差Vbは、p型光吸収層110側のフェルミ準位とn型電極層103のフェルミ準位の差を示したものであり、横方向は、図1(a)におけるE1−E2線に沿って、各層を、その厚さに相関するスケールで図示したものである。
Here, for comparison, the band structure of the peripheral portion of the mesa structure of the APD of this embodiment is shown in FIG. This corresponds to the portion of line E1-E2 in FIG.
In FIG. 1B, the potential difference Vb in the height direction indicates the difference between the Fermi level on the p-type light absorption layer 110 side and the Fermi level of the n-type electrode layer 103. Each layer is illustrated on a scale correlating with its thickness along line E1-E2 in FIG.

図1(b)に示すように、メサ構造周縁部では、光吸収層110の下層側であり、メサ構造周縁部である光吸収層110−電界制御層105間に、第1の電界緩和層106に加え、第2の電界緩和層108が挿入されているため、電界緩和領域A(図1(a)参照)が、メサ構造周縁部に形成されていることとなり、電位差Vbに対するメサ構造周縁部の電界強度が、挿入された第2の電界緩和層108の厚さの分、メサ構造の中央部と比較して、小さくなることとなる。   As shown in FIG. 1B, the first electric field relaxation layer is located on the lower side of the light absorption layer 110 at the periphery of the mesa structure and between the light absorption layer 110 and the electric field control layer 105, which is the periphery of the mesa structure. Since the second electric field relaxation layer 108 is inserted in addition to 106, the electric field relaxation region A (see FIG. 1A) is formed at the peripheral edge of the mesa structure, and the peripheral edge of the mesa structure with respect to the potential difference Vb. The electric field strength of the portion becomes smaller than the central portion of the mesa structure by the thickness of the inserted second electric field relaxation layer 108.

第2の半導体電界緩和層108の挿入によるメサ構造周縁部の電界強度の低下は、光吸収層110を含むメサ構造近傍の表面及びメサ構造直近のテラス領域部の電界強度を下げるため、メサ構造近傍の表面を流れる暗電流を減少させることになり、そして、表面を流れる暗電流の減少により、メサ構造近傍の表面結晶欠陥の発生割合が減少することになる。この結果、表面暗電流に起因する劣化が緩和し、信頼性を向上させることができる。又、第2の電界緩和層108の挿入によるメサ構造周縁部の電界強度の低下により、メサ構造周縁部の内部を流れる暗電流も減少し、これも結晶の劣化を緩和し、信頼性の向上に寄与することになる。メサ構造周縁部の電界の緩和は、第2の電界緩和層108の層厚が増大するほど大きい。   The decrease in the electric field intensity at the peripheral edge of the mesa structure due to the insertion of the second semiconductor electric field relaxation layer 108 decreases the electric field intensity at the surface in the vicinity of the mesa structure including the light absorption layer 110 and at the terrace region immediately adjacent to the mesa structure. The dark current flowing on the surface in the vicinity is reduced, and the generation rate of surface crystal defects in the vicinity of the mesa structure is reduced due to the decrease in the dark current flowing on the surface. As a result, the deterioration due to the surface dark current is alleviated and the reliability can be improved. In addition, due to the decrease in the electric field strength at the peripheral edge of the mesa structure due to the insertion of the second electric field relaxation layer 108, the dark current flowing inside the peripheral edge of the mesa structure is also reduced, which also alleviates the deterioration of the crystal and improves the reliability. Will contribute. The relaxation of the electric field at the periphery of the mesa structure increases as the layer thickness of the second electric field relaxation layer 108 increases.

以上説明したように、本実施例のAPDによれば、光吸収層を含むメサ構造周縁部の光吸収層−電界制御層間の電界強度の緩和により、信頼性試験での劣化の主な要因であるメサ構造周縁部近傍を流れる表面の暗電流を減少させ得るため、信頼性の向上が可能となる。   As described above, according to the APD of the present embodiment, the main factor of deterioration in the reliability test is due to the relaxation of the electric field strength between the light absorption layer and the electric field control layer at the periphery of the mesa structure including the light absorption layer. Since the dark current on the surface flowing in the vicinity of a peripheral portion of a certain mesa structure can be reduced, the reliability can be improved.

図2は、本発明に係るAPDの実施形態の他の一例を示す図である。
図2(a)は、その概略図であり、図2(b)は、図2(a)のE1−E2線におけるバンド構造図である。
図2(a)に示すように、本実施例のAPDは、半絶縁性InP基板201上に、アンドープ半導体からなる半絶縁性バッファ層202を介して、高濃度n型半導体電極層203と、アンドープ半導体からなるなだれ増倍層204と、第1のp型電界制御層205と、エッチストップ層206と、中空部を有する第2のp型電界制御層207と、アンドープ半導体からなる電界緩和層208と、バンドギャップ傾斜層209と、p型半導体光吸収層210と、高濃度p型半導体拡散バリア層211と、高濃度p型半導体電極層212とを順次積層して、半絶縁性InP基板201側の層の外周の幅が大きい階段状のメサ構造を形成し、更に、n型電極層203とp型電極層212上に、n電極213、p電極214を各々形成した構造である。実施例1(図1参照)との差異は、第2の電界緩和層108が第2の電界制御層207に置き換わった点にある。
FIG. 2 is a diagram showing another example of the embodiment of the APD according to the present invention.
FIG. 2A is a schematic view thereof, and FIG. 2B is a band structure diagram taken along line E1-E2 of FIG.
As shown in FIG. 2A, the APD of this example includes a high-concentration n-type semiconductor electrode layer 203 on a semi-insulating InP substrate 201 via a semi-insulating buffer layer 202 made of an undoped semiconductor. An avalanche multiplication layer 204 made of an undoped semiconductor, a first p-type electric field control layer 205, an etch stop layer 206, a second p-type electric field control layer 207 having a hollow portion, and an electric field relaxation layer made of an undoped semiconductor 208, a band gap inclined layer 209, a p-type semiconductor light absorption layer 210, a high-concentration p-type semiconductor diffusion barrier layer 211, and a high-concentration p-type semiconductor electrode layer 212 are sequentially laminated to form a semi-insulating InP substrate. In this structure, a stepwise mesa structure having a large outer peripheral width of the 201 side layer is formed, and an n electrode 213 and a p electrode 214 are formed on the n type electrode layer 203 and the p type electrode layer 212, respectively. The difference from the first embodiment (see FIG. 1) is that the second electric field relaxation layer 108 is replaced with the second electric field control layer 207.

第2のp型電界制御層207は、その中空部がバンドギャップ傾斜層209、p型半導体光吸収層210の外周より内側に形成されており、又、第2のp型電界制御層207の外周の幅がバンドギャップ傾斜層209、p型半導体光吸収層210の外周の幅より大きく形成されている。つまり、第2のp型電界制御層207はリング状の形状となっており、そのリング状の第2のp型電界制御層207の内側の位置は、p型半導体光吸収層210を含むメサ構造側の外周の位置より内側であり、リング状の第2のp型電界制御層207の外側の位置は、p型半導体光吸収層210を含むメサ構造側の外周の位置より外側であるように配置される。   The hollow portion of the second p-type electric field control layer 207 is formed inside the outer periphery of the band gap gradient layer 209 and the p-type semiconductor light absorption layer 210. The outer peripheral width is formed larger than the outer peripheral width of the band gap inclined layer 209 and the p-type semiconductor light absorbing layer 210. In other words, the second p-type electric field control layer 207 has a ring shape, and a position inside the ring-shaped second p-type electric field control layer 207 is a mesa including the p-type semiconductor light absorption layer 210. It is inside the outer peripheral position on the structure side, and the outer position of the ring-shaped second p-type electric field control layer 207 is outer than the outer peripheral position on the mesa structure side including the p-type semiconductor light absorption layer 210. Placed in.

上記構造のAPDは、例えば、実施例1と同様の方法で作製する。
具体的には、半絶縁性InP基板201上に、半絶縁性バッファ層202から第2の電界制御層207までの各層を、順次エピタキシャル成長し、その後、第2の電界制御層207の中央部をエッチストップ層208までエッチングにより取り除き、中央部に中空部を有するリング形状とする。次に、バンドギャップ傾斜層209、p型半導体光吸収層210、高濃度p型半導体拡散バリア層211をエピタキシャル再成長させ、エピタキシャル再成長後のメサ構造及び電極の作製は、実施例1と同様に行うことで作製できる。
The APD having the above structure is produced by the same method as in Example 1, for example.
Specifically, the layers from the semi-insulating buffer layer 202 to the second electric field control layer 207 are sequentially epitaxially grown on the semi-insulating InP substrate 201, and then the central portion of the second electric field control layer 207 is formed. The etch stop layer 208 is removed by etching to form a ring shape having a hollow portion at the center. Next, the band gap inclined layer 209, the p-type semiconductor light absorption layer 210, and the high-concentration p-type semiconductor diffusion barrier layer 211 are epitaxially regrown, and the mesa structure and the electrode after the epitaxial regrowth are produced in the same manner as in the first embodiment. It can produce by performing to.

上記メサ構造のAPDでも、素子表面の暗電流や電界強度を、更に抑制することを考慮して、階段状のメサ構造に形成して、n電極213とp電極214との距離ができるだけ離れるように配置している。なお、メサ構造を階段状としない場合でも、本実施例は適用可能であり、例えば、垂直な側壁面を有するメサ構造の場合には、第2のp型電界制御層207の外側の位置は、メサ構造の側壁面の位置までとしてもよい。   The APD having the mesa structure is also formed in a stepped mesa structure in consideration of further suppressing the dark current and electric field intensity on the element surface so that the distance between the n electrode 213 and the p electrode 214 is as far as possible. Is arranged. Even when the mesa structure is not stepped, this embodiment can be applied. For example, in the case of a mesa structure having a vertical side wall surface, the position outside the second p-type electric field control layer 207 is Further, it may be up to the position of the side wall surface of the mesa structure.

又、エッチストップ層206を使用しない構造の場合には、第2の電界制御層207も無くし、その代わりに、実施例1と同様に、第1の電界制御層205を2倍程度の膜厚に形成した後、中央部のみを半分程度の膜厚にエッチングし、その後、電界緩和層208、バンドギャップ傾斜層209、p型半導体光吸収層210、高濃度p型半導体拡散バリア層211をエピタキシャル再成長させたメサ構造のAPDでもよく、図2(a)に示したメサ構造のAPDと同等のものを作製することができる。
つまり、上記メサ構造のAPDでは、光吸収層210の下層側であり、メサ構造の周縁部である電界制御層205の外周側の膜厚が、電界制御層205の中央部の膜厚に対して、2倍程度厚く形成された構造となっている。
In the case where the etch stop layer 206 is not used, the second electric field control layer 207 is also eliminated, and instead, the first electric field control layer 205 is about twice as thick as in the first embodiment. After that, only the central portion is etched to a thickness of about half, and then the electric field relaxation layer 208, the band gap inclined layer 209, the p-type semiconductor light absorption layer 210, and the high-concentration p-type semiconductor diffusion barrier layer 211 are epitaxially formed. A regrown mesa APD may be used, and an APD having the mesa structure shown in FIG. 2A can be produced.
That is, in the APD having the mesa structure, the film thickness on the lower side of the light absorption layer 210 and on the outer peripheral side of the electric field control layer 205 that is the peripheral part of the mesa structure is smaller than the film thickness of the central part of the electric field control layer 205. Thus, the structure is formed about twice as thick.

本実施例のAPDの動作状態は、実施例1と同様に、メサ構造の中央部では、光吸収層210の下層側であるなだれ増倍層204、第1の電界制御層205、エッチストップ層206、電界緩和層208、バンドギャップ傾斜層209は空乏化し、アバランシェ動作の可能な状態になる(図4(b)参照)。   The operating state of the APD of this embodiment is the same as that of the first embodiment. In the central portion of the mesa structure, the avalanche multiplication layer 204, the first electric field control layer 205, the etch stop layer, which are on the lower layer side of the light absorption layer 210. 206, the electric field relaxation layer 208, and the band gap gradient layer 209 are depleted, and an avalanche operation is possible (see FIG. 4B).

一方、メサ構造周縁部では、図2(b)に示した本実施例のAPDのメサ構造周縁部のバンド構造から明らかなように、第1の電界制御層205に加え、第2の電界制御層207があり、実質的な電界制御層の層厚が増大するため、メサ構造周縁部において、中性化領域B(図2(a)参照)が、光吸収層110から第2の電界制御層207近傍まで広げられたようになっている。このため、メサ構造周縁部では、光吸収層110より電子が引き出され難く、電界制御層205,207−n電極層203間の電界強度が増大してもアバランシェ状態とならない。   On the other hand, in the peripheral portion of the mesa structure, as is apparent from the band structure of the peripheral portion of the mesa structure of the APD of this embodiment shown in FIG. 2B, in addition to the first electric field control layer 205, the second electric field control is performed. Since the layer 207 is present and the substantial thickness of the electric field control layer is increased, the neutralization region B (see FIG. 2A) extends from the light absorption layer 110 to the second electric field control at the periphery of the mesa structure. It is expanded to the vicinity of the layer 207. For this reason, at the peripheral edge of the mesa structure, it is difficult for electrons to be extracted from the light absorption layer 110, and even if the electric field strength between the electric field control layers 205 and 207 and the n-electrode layer 203 increases, an avalanche state does not occur.

メサ構造周縁部の中性化領域Bは、電界緩和層208のメサ構造周縁部の電界強度を低下させるため、メサ構造周縁部の表面を流れる暗電流も減少する。又、光吸収層210は略中性を保ち、光吸収層210−電界制御層205,207間の電界強度も緩和されるため、メサ構造周縁部の内部を流れる暗電流も減少させることができる。これらの暗電流の減少は、実施例1と同様に暗電流に起因する素子表面の劣化を緩和し、APDの信頼性の向上に寄与する。   Since the neutralization region B of the mesa structure peripheral portion reduces the electric field strength of the mesa structure peripheral portion of the electric field relaxation layer 208, the dark current flowing on the surface of the mesa structure peripheral portion also decreases. Further, since the light absorption layer 210 is substantially neutral and the electric field strength between the light absorption layer 210 and the electric field control layers 205 and 207 is relaxed, the dark current flowing inside the peripheral portion of the mesa structure can also be reduced. These reductions in dark current alleviate the deterioration of the element surface caused by dark current, as in Example 1, and contribute to improving the reliability of APD.

図3は、本発明に係るAPDの実施形態の更なる他の一例を示す図である。
図3(a)は、その概略図であり、図3(b)は、図3(a)のE1−E2線におけるバンド構造図である。
図3(a)に示すように、本発明に係るAPDは、半絶縁性InP基板301上に、アンドープ半導体からなる半絶縁性バッファ層302介して、高濃度n型半導体電極層303と、アンドープ半導体からなるなだれ増倍層304と、リング状の高濃度のp型電界制御領域306を有するp型電界制御層305と、アンドープ半導体からなる電界緩和層307と、バンドギャップ傾斜層308と、p型半導体光吸収層309と、高濃度p型半導体拡散バリア層310と、高濃度p型半導体電極層311とを順次積層して、半絶縁性InP基板301側の層の外周の幅が大きい階段状のメサ構造を形成し、更に、n型電極層303とp型電極層311上に、n電極312、p電極313を各々形成した構造である。
FIG. 3 is a diagram showing still another example of the embodiment of the APD according to the present invention.
FIG. 3A is a schematic diagram thereof, and FIG. 3B is a band structure diagram taken along line E1-E2 of FIG.
As shown in FIG. 3A, the APD according to the present invention includes a high-concentration n-type semiconductor electrode layer 303 and an undoped semiconductor layer on a semi-insulating InP substrate 301 via a semi-insulating buffer layer 302 made of an undoped semiconductor. An avalanche multiplication layer 304 made of a semiconductor, a p-type electric field control layer 305 having a ring-shaped high-concentration p-type electric field control region 306, an electric field relaxation layer 307 made of an undoped semiconductor, a band gap inclined layer 308, Type semiconductor light absorption layer 309, high-concentration p-type semiconductor diffusion barrier layer 310, and high-concentration p-type semiconductor electrode layer 311 are sequentially stacked, and the step width of the outer periphery of the layer on the semi-insulating InP substrate 301 side is large. A mesa structure is formed, and an n-electrode 312 and a p-electrode 313 are formed on the n-type electrode layer 303 and the p-type electrode layer 311, respectively.

本実施例のAPDでは、電界制御層305の外周の幅をバンドギャップ傾斜層308、p型半導体光吸収層309の外周の幅より大きくし、p型電界制御領域306の内側の位置を、バンドギャップ傾斜層308、p型半導体光吸収層309の外周より内側に配置し、p型電界制御領域306の外側の位置を、バンドギャップ傾斜層308、p型半導体光吸収層309の外周より外側に配置した。つまり、電界制御層305内の高濃度のp型電界制御領域306を、バンドギャップ層308の周縁部に沿って、その下層側に、リング状の中空形状に形成した。この電界制御領域306は、電界制御層305よりも高濃度のp型にドープされている。   In the APD of the present embodiment, the width of the outer periphery of the electric field control layer 305 is made larger than the width of the outer periphery of the band gap inclined layer 308 and the p-type semiconductor light absorption layer 309, and the position inside the p-type electric field control region 306 is The gap gradient layer 308 and the p-type semiconductor light absorption layer 309 are arranged inside the outer periphery, and the position outside the p-type electric field control region 306 is outside the band gap gradient layer 308 and the p-type semiconductor light absorption layer 309 outer periphery. Arranged. That is, the high-concentration p-type electric field control region 306 in the electric field control layer 305 is formed in a ring-shaped hollow shape along the peripheral edge of the band gap layer 308 on the lower layer side. The electric field control region 306 is doped with a higher concentration of p-type than the electric field control layer 305.

上記構造のAPDの作製方法としては、例えば、半絶縁性InP基板301上に、半絶縁性バッファ層302から電界制御層305まで、基板側から各層を順次エピタキシャル成長し、その後、電界制御層305中のメサ構造周縁部に選択的にZn等を熱拡散して、高濃度の電界制御領域306とし、次に、電界制御層307、バンドギャップ傾斜層308、p型半導体光吸収層309、高濃度p型半導体拡散バリア層310をエピタキシャル再成長させることで作製される。   As a method for manufacturing the APD having the above-described structure, for example, each layer is sequentially epitaxially grown from the substrate side from the semi-insulating buffer layer 302 to the electric field control layer 305 on the semi-insulating InP substrate 301, and thereafter, in the electric field control layer 305 Zn is selectively thermally diffused at the periphery of the mesa structure to form a high-concentration electric field control region 306, followed by an electric field control layer 307, a band gap inclined layer 308, a p-type semiconductor light absorption layer 309, a high concentration The p-type semiconductor diffusion barrier layer 310 is produced by epitaxial regrowth.

又、上記メサ構造のAPDでは、素子表面の暗電流や電界強度を、更に抑制することを考慮して、n電極312とp電極313との距離ができるだけ離れるように配置している。   Further, in the APD having the mesa structure, the n-electrode 312 and the p-electrode 313 are arranged such that the distance between the n-electrode 312 and the p-electrode 313 is as far as possible in consideration of further suppressing the dark current and electric field intensity on the element surface.

実施例2では、メサ構造周縁部に第2の電界制御層207を設け、電界制御層の層厚を実質的に増大させているが、本実施例では、第2の電界制御層207の代わりに、メサ構造周縁部に、より高濃度の電界制御領域306を設けることで、メサ構造周縁部に中性化領域Bが形成されるように構成している。   In the second embodiment, the second electric field control layer 207 is provided on the periphery of the mesa structure, and the thickness of the electric field control layer is substantially increased. However, in this embodiment, instead of the second electric field control layer 207, In addition, the neutralization region B is formed in the peripheral portion of the mesa structure by providing a higher concentration electric field control region 306 in the peripheral portion of the mesa structure.

従って、本実施例のAPDの動作状態は、実施例2と同様に、メサ構造中央部がアバランシェ状態に達していても、メサ構造周縁部は中性化領域Bによりアバランシェ状態に達しない。その結果、実施例2と同様に、メサ構造周縁部の暗電流の低下及び暗電流の低下に伴う信頼性の向上が可能である。なお、参考のため、図3(a)のE1−E2線のバンド構造を、図3(b)に示した。これからも明らかなように、中性化領域Bが、光吸収層309から電界制御層305まで拡大している。   Therefore, the operating state of the APD of the present embodiment does not reach the avalanche state due to the neutralization region B even if the mesa structure central portion reaches the avalanche state as in the second embodiment. As a result, as in the second embodiment, it is possible to improve the dark current at the peripheral edge of the mesa structure and the reliability associated with the dark current. For reference, the band structure of the E1-E2 line in FIG. 3A is shown in FIG. As is clear from this, the neutralized region B extends from the light absorption layer 309 to the electric field control layer 305.

上記実施例1、2、3で説明したように、本発明では、光吸収層を含むメサ構造の周縁部内部を流れる電流及びメサ構造の周縁部の表面を流れる暗電流を減少させる方法として、以下の構造を各々示した。
1.メサ構造周縁部にのみ新たな電界緩和層を挿入して、又は、メサ構造周縁部にのみ電界緩和層の膜厚を厚くして、メサ構造周縁部における光吸収層−電界制御層間の電界強度を低下させ、電界緩和領域を形成する構造(実施例1)。
2.メサ構造周縁部にのみ新たな電界制御層を挿入して、実質的な電界制御層の層厚を増大させて、又は、メサ構造周縁部にのみ電界制御層の膜厚を厚くして、メサ構造周縁部における中性化領域を広げる構造(実施例2)。
3.メサ構造周縁部にのみ高濃度の電界制御層を設けて、メサ構造周縁部における中性化領域を広げる構造(実施例3)
As described in the first, second, and third embodiments, in the present invention, as a method for reducing the current flowing inside the peripheral portion of the mesa structure including the light absorption layer and the dark current flowing on the surface of the peripheral portion of the mesa structure, The following structures are shown respectively.
1. The electric field strength between the light absorption layer and the electric field control layer at the mesa structure periphery is increased by inserting a new electric field relaxation layer only at the periphery of the mesa structure or by increasing the thickness of the electric field relaxation layer only at the periphery of the mesa structure. (Embodiment 1) in which an electric field relaxation region is formed.
2. A new electric field control layer is inserted only at the peripheral edge of the mesa structure to increase the layer thickness of the substantial electric field control layer, or the thickness of the electric field control layer is increased only at the peripheral edge of the mesa structure. A structure (Example 2) in which a neutralized region is widened at the peripheral edge of the structure.
3. Example 3 in which a high-concentration electric field control layer is provided only at the periphery of the mesa structure to widen the neutralization region at the periphery of the mesa structure

なお、本発明は、各実施例1、2、3を単独で用いる場合に限らず、これらの各実施例を組み合わせて、光吸収層−電界制御層間の電界をより緩和したり、p型電界制御層をより中性化し易くしたりしてもよい。例えば、実施例2において、第2のp型電界制御層207のドーピング濃度を第1のp型電界制御層205より高くすることで、高濃度のp型電界制御領域を造り込むことも可能である。この場合、層厚及びp型ドーピング濃度の増大により、中性化領域が実施例2、3よりも容易に形成され、メサ構造周縁部の暗電流下を、より一層減少させることができる。   The present invention is not limited to the case where each of the first, second, and third embodiments is used alone, but by combining these embodiments, the electric field between the light absorption layer and the electric field control layer can be further relaxed, The control layer may be more easily neutralized. For example, in Example 2, it is possible to build a high-concentration p-type electric field control region by making the doping concentration of the second p-type electric field control layer 207 higher than that of the first p-type electric field control layer 205. is there. In this case, due to the increase in the layer thickness and the p-type doping concentration, the neutralized region can be formed more easily than in the second and third embodiments, and the dark current at the periphery of the mesa structure can be further reduced.

本発明に係るAPDの実施形態の一例を示し、(a)は、その構成の概略図であり、(b)は、(a)のE1−E2線(メサ周縁部)のバンド構成図である。An example of embodiment of APD which concerns on this invention is shown, (a) is the schematic of the structure, (b) is a band block diagram of the E1-E2 line (mesa peripheral part) of (a). . 本発明に係るAPDの実施形態の他の一例を示し、(a)は、その構成の概略図であり、(b)は、(a)のE1−E2線(メサ周縁部)のバンド構成図である。The other example of embodiment of APD which concerns on this invention is shown, (a) is the schematic of the structure, (b) is a band block diagram of the E1-E2 line (mesa peripheral part) of (a). It is. 本発明に係るAPDの実施形態の更なる他の一例を示し、(a)は、その構成の概略図であり、(b)は、(a)のE1−E2線(メサ周縁部)のバンド構成図である。The further another example of embodiment of APD which concerns on this invention is shown, (a) is the schematic of the structure, (b) is the band of E1-E2 line (mesa peripheral part) of (a). It is a block diagram. (a)は、従来のAPDの構成を示す概略図であり、(b)は、(a)のS1−S2線(メサ中央部)のバンド構成図である。(A) is the schematic which shows the structure of the conventional APD, (b) is a band block diagram of the S1-S2 line (mesa center part) of (a).

符号の説明Explanation of symbols

101 半絶縁性InP基板、102 アンドープ半導体からなるバッファ層、103 n電極層、104 アンドープ半導体からなるなだれ増倍層、105 電界制御層、106 アンドープ半導体からなる第1の電界緩和層、107 エッチストップ層、108 アンドープ半基体からなる第2の電界緩和層、109 バンドギャップ緩和層、110 光吸収層、111 拡散バリア層、112 p電極層、113 n型電極、114 p型電極
201 半絶縁性InP基板、202 アンドープ半導体からなるバッファ層、203 n電極層、204 アンドープ半導体からなるなだれ増倍層、205 第1の電界制御層、206 エッチストップ層、207 第2の電界制御層、208 アンドープ半導体からなる電界緩和層、209 バンドギャップ緩和層、210 光吸収層、211 拡散バリア層、212 p電極層、213 n型電極、214 p型電極
301 半絶縁性InP基板、302 アンドープ半導体からなるバッファ層、303 n電極層、304 アンドープ半導体からなるなだれ増倍層、305 電界制御層、306 高濃度の電界制御層、307 アンドープ半導体からなる電界緩和層、308 バンドギャップ緩和層、309 光吸収層、310 拡散バリア層、311 p電極層、312 n型電極、313 p型電極
401 半絶縁性InP基板、402 アンドープ半導体からなるバッファ層、403 n電極層、404 アンドープ半導体からなるなだれ増倍層、405 電界制御層、406 アンドープ半導体からなる電界緩和層、407 バンドギャップ緩和層、408 光吸収層、409 拡散バリア層、410 p電極層、411 n型電極、412 p型電極
101 semi-insulating InP substrate, 102 buffer layer made of undoped semiconductor, 103 n electrode layer, avalanche multiplication layer made of 104 undoped semiconductor, 105 electric field control layer, first electric field relaxation layer made of 106 undoped semiconductor, 107 etch stop Layer, 108 second electric field relaxation layer made of undoped semi-base, 109 band gap relaxation layer, 110 light absorption layer, 111 diffusion barrier layer, 112 p electrode layer, 113 n-type electrode, 114 p-type electrode
201 semi-insulating InP substrate, 202 buffer layer made of undoped semiconductor, 203 n electrode layer, 204 avalanche multiplication layer made of undoped semiconductor, 205 first electric field control layer, 206 etch stop layer, 207 second electric field control layer , 208 Electric field relaxation layer made of undoped semiconductor, 209 band gap relaxation layer, 210 light absorption layer, 211 diffusion barrier layer, 212 p electrode layer, 213 n-type electrode, 214 p-type electrode
301 Semi-insulating InP substrate, 302 buffer layer made of undoped semiconductor, 303 n electrode layer, 304 avalanche multiplication layer made of undoped semiconductor, 305 electric field control layer, 306 high concentration electric field control layer, electric field relaxation made of 307 undoped semiconductor Layer, 308 band gap relaxation layer, 309 light absorption layer, 310 diffusion barrier layer, 311 p electrode layer, 312 n-type electrode, 313 p-type electrode
401 semi-insulating InP substrate, 402 undoped semiconductor buffer layer, 403 n electrode layer, 404 undoped semiconductor avalanche multiplication layer, 405 electric field control layer, 406 undoped semiconductor electric field relaxation layer, 407 band gap relaxation layer, 408 light absorption layer, 409 diffusion barrier layer, 410 p electrode layer, 411 n-type electrode, 412 p-type electrode

Claims (8)

半絶縁性基板上に、アンドープ半導体からなるバッファ層を介して、
高濃度n型半導体電極層と、アンドープ半導体からなるなだれ増倍層と、p型電界制御層と、アンドープ半導体からなる電界緩和層と、バンドギャップ傾斜層と、p型半導体光吸収層と、高濃度p型半導体拡散バリア層と、高濃度p型半導体電極層とを順次積層して、メサ構造とすると共に、
前記電界緩和層の外周側の膜厚を、前記電界緩和層の中央部の膜厚に対して厚く形成したことを特徴とするアバランシェフォトダイオード。
Through a buffer layer made of an undoped semiconductor on a semi-insulating substrate,
A high-concentration n-type semiconductor electrode layer, an avalanche multiplication layer made of an undoped semiconductor, a p-type electric field control layer, an electric field relaxation layer made of an undoped semiconductor, a band gap inclined layer, a p-type semiconductor light absorption layer, A concentration p-type semiconductor diffusion barrier layer and a high concentration p-type semiconductor electrode layer are sequentially stacked to form a mesa structure,
The avalanche photodiode is characterized in that the film thickness on the outer peripheral side of the electric field relaxation layer is thicker than the film thickness of the central portion of the electric field relaxation layer.
半絶縁性基板上に、アンドープ半導体からなるバッファ層を介して、
高濃度n型半導体電極層と、アンドープ半導体からなるなだれ増倍層と、p型電界制御層と、アンドープ半導体からなる第1の電界緩和層と、中空部を有するアンドープ半導体からなる第2の電界緩和層と、バンドギャップ傾斜層と、p型半導体光吸収層と、高濃度p型半導体拡散バリア層と、高濃度p型半導体電極層とを順次積層して、メサ構造とすると共に、
前記第2の電界緩和層の前記中空部を、前記p型半導体光吸収層の外周より内側に形成したことを特徴とするアバランシェフォトダイオード。
Through a buffer layer made of an undoped semiconductor on a semi-insulating substrate,
High-concentration n-type semiconductor electrode layer, avalanche multiplication layer made of undoped semiconductor, p-type electric field control layer, first electric field relaxation layer made of undoped semiconductor, and second electric field made of undoped semiconductor having a hollow portion A relaxation layer, a band gap inclined layer, a p-type semiconductor light absorption layer, a high-concentration p-type semiconductor diffusion barrier layer, and a high-concentration p-type semiconductor electrode layer are sequentially stacked to form a mesa structure.
The avalanche photodiode, wherein the hollow portion of the second electric field relaxation layer is formed inside the outer periphery of the p-type semiconductor light absorption layer.
請求項1又は請求項2記載のアバランシェフォトダイオードにおいて、
前記メサ構造を、前記半絶縁性基板側の層の外周の幅が大きくなる階段状にすると共に、
前記電界緩和層又は第2の電界緩和層の外周の幅を、前記p型半導体光吸収層の外周の幅より大きくしたことを特徴とするアバランシェフォトダイオード。
The avalanche photodiode according to claim 1 or 2,
The mesa structure is stepped so that the width of the outer periphery of the layer on the semi-insulating substrate side is increased,
An avalanche photodiode, wherein the outer peripheral width of the electric field relaxation layer or the second electric field relaxation layer is larger than the outer peripheral width of the p-type semiconductor light absorption layer.
半絶縁性基板上に、アンドープ半導体からなるバッファ層を介して、
高濃度n型半導体電極層と、アンドープ半導体からなるなだれ増倍層と、p型電界制御層と、アンドープ半導体からなる電界緩和層と、バンドギャップ傾斜層と、p型半導体光吸収層と、高濃度p型半導体拡散バリア層と、高濃度p型半導体電極層とを順次積層して、メサ構造とすると共に、
前記p型電界制御層の外周側の膜厚を、前記p型電界制御層の中央部の膜厚に対して厚く形成したことを特徴とするアバランシェフォトダイオード。
Through a buffer layer made of an undoped semiconductor on a semi-insulating substrate,
A high-concentration n-type semiconductor electrode layer, an avalanche multiplication layer made of an undoped semiconductor, a p-type electric field control layer, an electric field relaxation layer made of an undoped semiconductor, a band gap inclined layer, a p-type semiconductor light absorption layer, A concentration p-type semiconductor diffusion barrier layer and a high concentration p-type semiconductor electrode layer are sequentially stacked to form a mesa structure,
The avalanche photodiode is characterized in that the film thickness on the outer peripheral side of the p-type electric field control layer is thicker than the film thickness of the central part of the p-type electric field control layer.
半絶縁性基板上に、アンドープ半導体からなるバッファ層を介して、
高濃度n型半導体電極層と、アンドープ半導体からなるなだれ増倍層と、第1のp型電界制御層と、中空部を有する第2のp型電界制御層と、アンドープ半導体からなる電界緩和層と、バンドギャップ傾斜層と、p型半導体光吸収層と、高濃度p型半導体拡散バリア層と、高濃度p型半導体電極層とを順次積層して、メサ構造とすると共に、
前記第2のp型電界制御層の前記中空部を、前記p型半導体光吸収層の外周より内側に形成したことを特徴とするアバランシェフォトダイオード。
Through a buffer layer made of an undoped semiconductor on a semi-insulating substrate,
High-concentration n-type semiconductor electrode layer, avalanche multiplication layer made of undoped semiconductor, first p-type electric field control layer, second p-type electric field control layer having a hollow portion, and electric field relaxation layer made of undoped semiconductor And a mesa structure by sequentially stacking a band gap inclined layer, a p-type semiconductor light absorption layer, a high-concentration p-type semiconductor diffusion barrier layer, and a high-concentration p-type semiconductor electrode layer,
The avalanche photodiode, wherein the hollow portion of the second p-type electric field control layer is formed inside the outer periphery of the p-type semiconductor light absorption layer.
請求項4又は請求項5記載のアバランシェフォトダイオードにおいて、
前記メサ構造を、前記半絶縁性基板側の層の外周の幅が大きくなる階段状にすると共に、
前記p型電界制御層又は第2のp型電界制御層の外周の幅を、前記p型半導体光吸収層の外周の幅より大きくしたことを特徴とするアバランシェフォトダイオード。
The avalanche photodiode according to claim 4 or 5,
The mesa structure is stepped so that the width of the outer periphery of the layer on the semi-insulating substrate side is increased,
An avalanche photodiode, wherein the outer peripheral width of the p-type electric field control layer or the second p-type electric field control layer is larger than the outer peripheral width of the p-type semiconductor light absorption layer.
半絶縁性基板上に、アンドープ半導体からなるバッファ層を介して、
高濃度n型半導体電極層と、アンドープ半導体からなるなだれ増倍層と、p型電界制御層と、アンドープ半導体からなる電界緩和層と、バンドギャップ傾斜層と、p型半導体光吸収層と、高濃度p型半導体拡散バリア層と、高濃度p型半導体電極層とを順次積層して、メサ構造とすると共に、
前記p型電界制御層中に、前記p型電界制御層より高濃度のp型電界制御領域を、前記p型半導体光吸収層の周縁部に沿って中空形状に形成し、
前記高濃度のp型電界制御領域の内側の位置を、前記p型半導体光吸収層の外周より内側に配置したことを特徴とするアバランシェフォトダイオード。
Through a buffer layer made of an undoped semiconductor on a semi-insulating substrate,
A high-concentration n-type semiconductor electrode layer, an avalanche multiplication layer made of an undoped semiconductor, a p-type electric field control layer, an electric field relaxation layer made of an undoped semiconductor, a band gap inclined layer, a p-type semiconductor light absorption layer, A concentration p-type semiconductor diffusion barrier layer and a high concentration p-type semiconductor electrode layer are sequentially stacked to form a mesa structure,
In the p-type electric field control layer, a p-type electric field control region having a higher concentration than the p-type electric field control layer is formed in a hollow shape along the peripheral edge of the p-type semiconductor light absorption layer,
An avalanche photodiode characterized in that a position inside the high-concentration p-type electric field control region is arranged inside the outer periphery of the p-type semiconductor light absorption layer.
請求項7記載のアバランシェフォトダイオードにおいて、
前記メサ構造を、前記半絶縁性基板側の層の外周の幅が大きくなる階段状にすると共に、
前記p型電界制御層の外周の幅を、前記p型半導体光吸収層の外周の幅より大きくし、前記高濃度のp型電界制御領域の外側の位置を、前記p型半導体光吸収層の外周より外側に配置したことを特徴とするアバランシェフォトダイオード。
The avalanche photodiode according to claim 7,
The mesa structure is stepped so that the width of the outer periphery of the layer on the semi-insulating substrate side is increased,
The width of the outer periphery of the p-type electric field control layer is made larger than the width of the outer periphery of the p-type semiconductor light absorption layer, and the position outside the high-concentration p-type electric field control region is positioned on the p-type semiconductor light absorption layer. An avalanche photodiode characterized in that it is arranged outside the outer periphery.
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