WO2019220514A1 - Optical semiconductor device and method of manufacturing same - Google Patents
Optical semiconductor device and method of manufacturing same Download PDFInfo
- Publication number
- WO2019220514A1 WO2019220514A1 PCT/JP2018/018602 JP2018018602W WO2019220514A1 WO 2019220514 A1 WO2019220514 A1 WO 2019220514A1 JP 2018018602 W JP2018018602 W JP 2018018602W WO 2019220514 A1 WO2019220514 A1 WO 2019220514A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- semiconductor device
- type
- optical semiconductor
- manufacturing
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/223—Buried stripe structure
Definitions
- the present invention relates to an optical semiconductor device and a method for manufacturing the same.
- a semi-insulating buried layer is used for the purpose of current confinement to the active layer and heat dissipation from the active layer.
- current injection efficiency into the active layer is reduced due to carrier leakage into the semi-insulating layer.
- Patent Document 1 a structure that suppresses carrier leakage by using a p-type layer as the first buried layer is used (see, for example, Patent Document 1).
- the active layer itself becomes p-type by diffusing the dopant of the p-type layer into the active layer. For this reason, there is a problem in that absorption between valence bands increases, optical loss increases, and threshold current increases. Further, when the doping concentration of the p-type layer is increased, the effect of suppressing carrier leakage is increased, but there is a trade-off problem that light loss due to the diffusion of the p-type dopant into the active layer also increases.
- the present invention has been made to solve the above-described problems, and an object thereof is to obtain an optical semiconductor device capable of suppressing the diffusion of p-type dopants into an active layer and a method for manufacturing the same.
- An optical semiconductor device includes a semiconductor substrate, a first conductivity type cladding layer, an active layer, and a second conductivity type cladding layer sequentially stacked on the semiconductor substrate, and is processed into a mesa shape.
- the first layer of the buried layer does not contain a p-type dopant. Therefore, even if the doping concentration of the p-type layer of the buried layer is increased in order to suppress carrier leakage, the diffusion of the p-type dopant from the p-type layer to the active layer can be suppressed.
- FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment.
- 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
- FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
- FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
- FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
- FIG. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.
- This semiconductor device is a semiconductor laser.
- an n-type InP clad layer 2 On the n-type InP substrate 1, an n-type InP clad layer 2, an InGaAsP active layer 3, and a p-type InP clad layer 4 are laminated in order to form a laminate 5.
- the laminated body 5 is processed into a mesa shape.
- Embedded layers 6 are embedded on both sides of the laminate 5.
- the buried layer 6 includes a first layer 7, a p-type InP layer 8, and an Fe-doped InP layer 9 that are sequentially stacked from the side surface of the stacked body 5.
- the first layer 7 is an undoped InP layer and is in direct contact with the side wall of the InGaAsP active layer 3.
- a p-type InP cladding layer 10 and a p-type InGaAs contact layer 11 are sequentially stacked on the stacked body 5 and the buried layer 6.
- An insulating film 12 made of SiO 2 having an opening is provided on the p-type InGaAs contact layer 11.
- An upper surface electrode 13 in which Ti, Pt, and Au are sequentially laminated is provided on the insulating film 12, and is connected to the p-type InGaAs contact layer 11 through an opening.
- a lower surface electrode 14 in which Ti, Pt, and Au are sequentially laminated is provided on the lower surface of the n-type InP substrate 1.
- FIG. 2 to 4 are cross-sectional views showing the manufacturing steps of the semiconductor device according to the first embodiment.
- an n-type InP clad layer 2 an InGaAsP active layer 3, and a p-type InP clad layer 4 are sequentially laminated on an n-type InP substrate 1 to form a laminate 5.
- a striped SiO 2 film 15 is formed on the stacked body 5.
- the stacked body 5 is processed into a mesa shape by performing RIE etching using the SiO 2 film 15 as a mask.
- the first layer 7, the p-type InP layer 8, and the Fe-doped InP layer 9 are sequentially stacked on both sides of the mesa-shaped stacked body 5.
- the SiO 2 film 15 is removed with hydrofluoric acid, and the p-type InP cladding layer 10, the p-type InGaAs contact layer 11, the insulating film 12, the upper surface electrode 13 and the lower surface electrode 14 are formed.
- the first layer 7 of the buried layer 6 does not contain a p-type dopant. Therefore, even if the doping concentration of the p-type InP layer 8 of the buried layer 6 is increased in order to suppress carrier leakage, the diffusion of the p-type dopant from the p-type InP layer 8 to the InGaAsP active layer 3 can be suppressed.
- the semi-insulating Fe-doped InP layer 9 blocks current by trapping electrons. Instead of the Fe-doped InP layer 9, a semi-insulating layer with Ru as a dopant may be used. In place of the InGaAsP active layer 3, an active layer containing AlGaInAs may be used.
- the first layer 7 of the buried layer 6 is an n-type InP layer.
- the diffusion of the p-type dopant from the p-type InP layer 8 to the InGaAsP active layer 3 can be further suppressed.
- the resistance of the n-type InP layer is low, a low-resistance current leak path is formed beside the InGaAsP active layer 3. Therefore, the carrier concentration of the n-type InP layer and the p-type InP layer 8 and the film thickness of the n-type InP layer are set so that the n-type InP layer is completely depleted beside the InGaAsP active layer 3.
- the longitudinal resistance of the first layer 7 on the side of the InGaAsP active layer 3 can be made sufficiently large with respect to the resistance of the InGaAsP active layer 3, thereby suppressing current leakage through the first layer 7.
- the thickness W of the depletion layer is expressed by the following equation.
- epsilon s dielectric constant of InP the acceptor density of the N A p-type layer, the donor density of N D n-type layer
- q is the electron elementary charge
- V D -V is the voltage across the pn junction .
- the depletion layer width xn on the n-type layer side is expressed by the following formula.
- the first layer 7 of the buried layer 6 is an Fe-doped InP layer.
- the diffusion of the p-type dopant into the InGaAsP active layer 3 can be suppressed.
- the Fe-doped InP layer has a trapping effect on electrons from the n-type InP substrate 1 or the n-type InP clad layer 2, current leakage can be suppressed as compared with the first embodiment.
- the first layer 7 of the buried layer 6 is a Ru-doped InP layer. Since the Ru-doped InP layer has a hole trap effect, the diffusion of the p-type dopant from the p-type InP layer 8 to the InGaAsP active layer 3 can be further suppressed.
- n-type InP substrate semiconductor substrate
- 2 n-type InP clad layer first conductivity type clad layer
- 3 InGaAsP active layer active layer
- 4 p-type InP clad layer second conductivity type clad layer
- 5 Laminated body 6 buried layer (buried layer), 7 first layer, 8 p-type InP layer (p-type layer), 9 Fe-doped InP layer (semi-insulating layer)
Abstract
A stack (5) is composed of a first conductivity type cladding layer (2), an active layer (3), and a second conductivity type cladding layer (4) stacked in this order on a semiconductor substrate (1). The stack (5) is fabricated into a mesa shape. Filling layers (6) fill in the space on both sides of the stack (5). The filling layers (6) each have a first layer (7), a p-type layer (8), and a semi-insulating layer (9) that are stacked in this order from the side surface of the stack (5). The first layer (7) is in contact with a side wall of the active layer (3) and does not contain a p-type dopant.
Description
本発明は、光半導体装置及びその製造方法に関する。
The present invention relates to an optical semiconductor device and a method for manufacturing the same.
半導体レーザを代表とする光半導体装置では、活性層への電流狭窄と活性層からの放熱を目的として半絶縁性の埋め込み層が用いられている。しかし、半絶縁層へのキャリアのリークにより活性層への電流注入効率が低下するという問題があった。これに対して、埋め込み層の第一層をｐ型層にすることでキャリアのリークを抑制する構造が用いられている（例えば、特許文献１参照）。
In an optical semiconductor device typified by a semiconductor laser, a semi-insulating buried layer is used for the purpose of current confinement to the active layer and heat dissipation from the active layer. However, there is a problem in that current injection efficiency into the active layer is reduced due to carrier leakage into the semi-insulating layer. On the other hand, a structure that suppresses carrier leakage by using a p-type layer as the first buried layer is used (see, for example, Patent Document 1).
しかし、ｐ型層のドーパントが活性層に拡散することで活性層自体がｐ型化されてしまう。このため、価電子帯間吸収が増加し、光損失が増加し、閾値電流が増加するという問題があった。また、ｐ型層のドーピング濃度を高くすると、キャリアリーク抑制効果は増えるが、活性層へのｐ型ドーパントの拡散による光損失も増えてしまうというトレードオフの問題があった。
However, the active layer itself becomes p-type by diffusing the dopant of the p-type layer into the active layer. For this reason, there is a problem in that absorption between valence bands increases, optical loss increases, and threshold current increases. Further, when the doping concentration of the p-type layer is increased, the effect of suppressing carrier leakage is increased, but there is a trade-off problem that light loss due to the diffusion of the p-type dopant into the active layer also increases.
本発明は、上述のような課題を解決するためになされたもので、その目的は活性層へのｐ型ドーパントの拡散を抑制できる光半導体装置及びその製造方法を得るものである。
The present invention has been made to solve the above-described problems, and an object thereof is to obtain an optical semiconductor device capable of suppressing the diffusion of p-type dopants into an active layer and a method for manufacturing the same.
本発明に係る光半導体装置は、半導体基板と、前記半導体基板の上に順に積層された第一導電型クラッド層、活性層、及び第二導電型クラッド層を有し、メサ状に加工された積層体と、前記積層体の両側を埋め込む埋め込み層とを備え、前記埋め込み層は、前記積層体の側面から順に積層された第一層、ｐ型層、及び半絶縁層を有し、前記第一層は、前記活性層の側壁に接し、ｐ型ドーパントを含まないことを特徴とする。
An optical semiconductor device according to the present invention includes a semiconductor substrate, a first conductivity type cladding layer, an active layer, and a second conductivity type cladding layer sequentially stacked on the semiconductor substrate, and is processed into a mesa shape. A laminated body and a buried layer embedded on both sides of the laminated body, the buried layer including a first layer, a p-type layer, and a semi-insulating layer laminated in order from a side surface of the laminated body, One layer is in contact with the side wall of the active layer and does not contain a p-type dopant.
本発明では、埋め込み層の第一層がｐ型ドーパントを含まない。これにより、キャリアリークを抑制するために埋め込み層のｐ型層のドーピング濃度を高くしても、ｐ型層から活性層へのｐ型ドーパントの拡散を抑制できる。
In the present invention, the first layer of the buried layer does not contain a p-type dopant. Thereby, even if the doping concentration of the p-type layer of the buried layer is increased in order to suppress carrier leakage, the diffusion of the p-type dopant from the p-type layer to the active layer can be suppressed.
実施の形態に係る光半導体装置及びその製造方法について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
An optical semiconductor device according to an embodiment and a manufacturing method thereof will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.
実施の形態１．
図１は、実施の形態１に係る半導体装置を示す断面図である。この半導体装置は半導体レーザである。Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment. This semiconductor device is a semiconductor laser.
図１は、実施の形態１に係る半導体装置を示す断面図である。この半導体装置は半導体レーザである。
FIG. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment. This semiconductor device is a semiconductor laser.
ｎ型ＩｎＰ基板１の上に順にｎ型ＩｎＰクラッド層２、ＩｎＧａＡｓＰ活性層３、及びｐ型ＩｎＰクラッド層４が積層されて積層体５が構成されている。積層体５はメサ状に加工されている。積層体５の両側を埋め込み層６が埋め込んでいる。埋め込み層６は、積層体５の側面から順に積層された第一層７、ｐ型ＩｎＰ層８、及びＦｅドープＩｎＰ層９を有する。第一層７はアンドープＩｎＰ層であり、ＩｎＧａＡｓＰ活性層３の側壁に直接的に接している。
On the n-type InP substrate 1, an n-type InP clad layer 2, an InGaAsP active layer 3, and a p-type InP clad layer 4 are laminated in order to form a laminate 5. The laminated body 5 is processed into a mesa shape. Embedded layers 6 are embedded on both sides of the laminate 5. The buried layer 6 includes a first layer 7, a p-type InP layer 8, and an Fe-doped InP layer 9 that are sequentially stacked from the side surface of the stacked body 5. The first layer 7 is an undoped InP layer and is in direct contact with the side wall of the InGaAsP active layer 3.
積層体５及び埋め込み層６の上にｐ型ＩｎＰクラッド層１０及びｐ型ＩｎＧａＡｓコンタクト層１１が順に積層されている。ｐ型ＩｎＧａＡｓコンタクト層１１の上に開口を有するＳｉＯ２からなる絶縁膜１２が設けられている。絶縁膜１２の上にＴｉ、Ｐｔ、Ａｕを順に積層した上面電極１３が設けられ、開口を介してｐ型ＩｎＧａＡｓコンタクト層１１に接続されている。ｎ型ＩｎＰ基板１の下面にＴｉ、Ｐｔ、Ａｕを順に積層した下面電極１４が設けられている。
A p-type InP cladding layer 10 and a p-type InGaAs contact layer 11 are sequentially stacked on the stacked body 5 and the buried layer 6. An insulating film 12 made of SiO 2 having an opening is provided on the p-type InGaAs contact layer 11. An upper surface electrode 13 in which Ti, Pt, and Au are sequentially laminated is provided on the insulating film 12, and is connected to the p-type InGaAs contact layer 11 through an opening. A lower surface electrode 14 in which Ti, Pt, and Au are sequentially laminated is provided on the lower surface of the n-type InP substrate 1.
続いて、本実施の形態に係る光半導体装置の製造方法を説明する。図２から図４は、実施の形態１に係る半導体装置の製造工程を示す断面図である。まず、図２に示すように、ｎ型ＩｎＰ基板１の上に順にｎ型ＩｎＰクラッド層２、ＩｎＧａＡｓＰ活性層３、及びｐ型ＩｎＰクラッド層４を積層して積層体５を形成する。
Subsequently, a method for manufacturing the optical semiconductor device according to the present embodiment will be described. 2 to 4 are cross-sectional views showing the manufacturing steps of the semiconductor device according to the first embodiment. First, as shown in FIG. 2, an n-type InP clad layer 2, an InGaAsP active layer 3, and a p-type InP clad layer 4 are sequentially laminated on an n-type InP substrate 1 to form a laminate 5.
次に、図３に示すように、積層体５の上にストライプ状のＳｉＯ２膜１５を形成する。ＳｉＯ２膜１５をマスクとしてＲＩＥエッチングを行うことで積層体５をメサ状に加工する。次に、図４に示すように、メサ状の積層体５の両側に順に第一層７、ｐ型ＩｎＰ層８、及びＦｅドープＩｎＰ層９を積層する。その後、フッ酸でＳｉＯ２膜１５を除去し、ｐ型ＩｎＰクラッド層１０、ｐ型ＩｎＧａＡｓコンタクト層１１、絶縁膜１２、上面電極１３及び下面電極１４を形成する。
Next, as shown in FIG. 3, a striped SiO 2 film 15 is formed on the stacked body 5. The stacked body 5 is processed into a mesa shape by performing RIE etching using the SiO 2 film 15 as a mask. Next, as shown in FIG. 4, the first layer 7, the p-type InP layer 8, and the Fe-doped InP layer 9 are sequentially stacked on both sides of the mesa-shaped stacked body 5. Thereafter, the SiO 2 film 15 is removed with hydrofluoric acid, and the p-type InP cladding layer 10, the p-type InGaAs contact layer 11, the insulating film 12, the upper surface electrode 13 and the lower surface electrode 14 are formed.
本実施の形態では、埋め込み層６の第一層７がｐ型ドーパントを含まない。これにより、キャリアリークを抑制するために埋め込み層６のｐ型ＩｎＰ層８のドーピング濃度を高くしても、ｐ型ＩｎＰ層８からＩｎＧａＡｓＰ活性層３へのｐ型ドーパントの拡散を抑制できる。
In the present embodiment, the first layer 7 of the buried layer 6 does not contain a p-type dopant. Thereby, even if the doping concentration of the p-type InP layer 8 of the buried layer 6 is increased in order to suppress carrier leakage, the diffusion of the p-type dopant from the p-type InP layer 8 to the InGaAsP active layer 3 can be suppressed.
ｐ型ＩｎＰ層８は伝導帯のエネルギーレベルが高いため、電子がＩｎＧａＡｓＰ活性層３から溢れ出すのを抑制する。半絶縁性のＦｅドープＩｎＰ層９は電子をトラップすることにより電流を阻止する。ＦｅドープＩｎＰ層９の代わりに、ドーパントがＲｕの半絶縁層を用いてもよい。なお、ＩｎＧａＡｓＰ活性層３の代わりにＡｌＧａＩｎＡｓを含む活性層を用いてもよい。
Since the p-type InP layer 8 has a high energy level in the conduction band, it prevents the electrons from overflowing from the InGaAsP active layer 3. The semi-insulating Fe-doped InP layer 9 blocks current by trapping electrons. Instead of the Fe-doped InP layer 9, a semi-insulating layer with Ru as a dopant may be used. In place of the InGaAsP active layer 3, an active layer containing AlGaInAs may be used.
実施の形態２．
本実施の形態では埋め込み層６の第一層７がｎ型ＩｎＰ層である。これにより、ｐ型ＩｎＰ層８からＩｎＧａＡｓＰ活性層３へのｐ型ドーパントの拡散を更に抑制することができる。ただし、ｎ型ＩｎＰ層の抵抗が低いとＩｎＧａＡｓＰ活性層３の横に低抵抗の電流リーク経路ができてしまう。そこで、ＩｎＧａＡｓＰ活性層３の横においてｎ型ＩｎＰ層が全て空乏化されるように、ｎ型ＩｎＰ層とｐ型ＩｎＰ層８のキャリア濃度、ｎ型ＩｎＰ層の膜厚を設定する。これにより、ＩｎＧａＡｓＰ活性層３の横における第一層７の縦方向の抵抗をＩｎＧａＡｓＰ活性層３の抵抗に対して十分に大きくとることができるため、第一層７を経由する電流リークを抑えることができる。なお、空乏層の厚さＷは以下の式で表される。
ここで、εｓはＩｎＰの誘電率、ＮＡはｐ型層のアクセプター密度、ＮＤはｎ型層のドナー密度、ｑは電子素量、ＶＤ－Ｖはｐｎ接合部にかかる電圧である。また、ｎ型層側の空乏層幅ｘｎは以下の式で表される。
Embodiment 2. FIG.
In the present embodiment, thefirst layer 7 of the buried layer 6 is an n-type InP layer. Thereby, the diffusion of the p-type dopant from the p-type InP layer 8 to the InGaAsP active layer 3 can be further suppressed. However, if the resistance of the n-type InP layer is low, a low-resistance current leak path is formed beside the InGaAsP active layer 3. Therefore, the carrier concentration of the n-type InP layer and the p-type InP layer 8 and the film thickness of the n-type InP layer are set so that the n-type InP layer is completely depleted beside the InGaAsP active layer 3. As a result, the longitudinal resistance of the first layer 7 on the side of the InGaAsP active layer 3 can be made sufficiently large with respect to the resistance of the InGaAsP active layer 3, thereby suppressing current leakage through the first layer 7. Can do. Note that the thickness W of the depletion layer is expressed by the following equation.
Here, epsilon s dielectric constant of InP, the acceptor density of the N A p-type layer, the donor density of N D n-type layer, q is the electron elementary charge, V D -V is the voltage across the pn junction . The depletion layer width xn on the n-type layer side is expressed by the following formula.
本実施の形態では埋め込み層６の第一層７がｎ型ＩｎＰ層である。これにより、ｐ型ＩｎＰ層８からＩｎＧａＡｓＰ活性層３へのｐ型ドーパントの拡散を更に抑制することができる。ただし、ｎ型ＩｎＰ層の抵抗が低いとＩｎＧａＡｓＰ活性層３の横に低抵抗の電流リーク経路ができてしまう。そこで、ＩｎＧａＡｓＰ活性層３の横においてｎ型ＩｎＰ層が全て空乏化されるように、ｎ型ＩｎＰ層とｐ型ＩｎＰ層８のキャリア濃度、ｎ型ＩｎＰ層の膜厚を設定する。これにより、ＩｎＧａＡｓＰ活性層３の横における第一層７の縦方向の抵抗をＩｎＧａＡｓＰ活性層３の抵抗に対して十分に大きくとることができるため、第一層７を経由する電流リークを抑えることができる。なお、空乏層の厚さＷは以下の式で表される。
In the present embodiment, the
実施の形態３．
本実施の形態では埋め込み層６の第一層７がＦｅドープＩｎＰ層である。これにより、同様にＩｎＧａＡｓＰ活性層３へのｐ型ドーパントの拡散を抑制することができる。また、ＦｅドープＩｎＰ層がｎ型ＩｎＰ基板１又はｎ型ＩｎＰクラッド層２からの電子に対してトラップ効果を持つことから、実施の形態１よりも電流リークを抑制できる。Embodiment 3 FIG.
In the present embodiment, thefirst layer 7 of the buried layer 6 is an Fe-doped InP layer. Thereby, similarly, the diffusion of the p-type dopant into the InGaAsP active layer 3 can be suppressed. In addition, since the Fe-doped InP layer has a trapping effect on electrons from the n-type InP substrate 1 or the n-type InP clad layer 2, current leakage can be suppressed as compared with the first embodiment.
本実施の形態では埋め込み層６の第一層７がＦｅドープＩｎＰ層である。これにより、同様にＩｎＧａＡｓＰ活性層３へのｐ型ドーパントの拡散を抑制することができる。また、ＦｅドープＩｎＰ層がｎ型ＩｎＰ基板１又はｎ型ＩｎＰクラッド層２からの電子に対してトラップ効果を持つことから、実施の形態１よりも電流リークを抑制できる。
In the present embodiment, the
実施の形態４．
本実施の形態では埋め込み層６の第一層７がＲｕドープＩｎＰ層である。ＲｕドープＩｎＰ層がホールトラップ効果を持つことから、ｐ型ＩｎＰ層８からＩｎＧａＡｓＰ活性層３へのｐ型ドーパントの拡散を更に抑制することができる。Embodiment 4 FIG.
In the present embodiment, thefirst layer 7 of the buried layer 6 is a Ru-doped InP layer. Since the Ru-doped InP layer has a hole trap effect, the diffusion of the p-type dopant from the p-type InP layer 8 to the InGaAsP active layer 3 can be further suppressed.
本実施の形態では埋め込み層６の第一層７がＲｕドープＩｎＰ層である。ＲｕドープＩｎＰ層がホールトラップ効果を持つことから、ｐ型ＩｎＰ層８からＩｎＧａＡｓＰ活性層３へのｐ型ドーパントの拡散を更に抑制することができる。
In the present embodiment, the
１ ｎ型ＩｎＰ基板（半導体基板）、２ ｎ型ＩｎＰクラッド層（第一導電型クラッド層）、３ ＩｎＧａＡｓＰ活性層（活性層）、４ ｐ型ＩｎＰクラッド層（第二導電型クラッド層）、５ 積層体、６ 埋め込み層（埋め込み層）、７ 第一層、８ ｐ型ＩｎＰ層（ｐ型層）、９ ＦｅドープＩｎＰ層（半絶縁層）
1 n-type InP substrate (semiconductor substrate), 2 n-type InP clad layer (first conductivity type clad layer), 3 InGaAsP active layer (active layer), 4 p-type InP clad layer (second conductivity type clad layer), 5 Laminated body, 6 buried layer (buried layer), 7 first layer, 8 p-type InP layer (p-type layer), 9 Fe-doped InP layer (semi-insulating layer)
Claims (12)
- 半導体基板と、
前記半導体基板の上に順に積層された第一導電型クラッド層、活性層、及び第二導電型クラッド層を有し、メサ状に加工された積層体と、
前記積層体の両側を埋め込む埋め込み層とを備え、
前記埋め込み層は、前記積層体の側面から順に積層された第一層、ｐ型層、及び半絶縁層を有し、
前記第一層は、前記活性層の側壁に接し、ｐ型ドーパントを含まないことを特徴とする光半導体装置。 A semiconductor substrate;
A first conductive type clad layer, an active layer, and a second conductive type clad layer sequentially laminated on the semiconductor substrate, and a laminated body processed into a mesa shape;
An embedded layer embedded on both sides of the laminate,
The buried layer includes a first layer, a p-type layer, and a semi-insulating layer that are sequentially stacked from the side surface of the stacked body,
The first semiconductor layer is in contact with the side wall of the active layer and does not contain a p-type dopant. - 前記第一層はアンドープ層であることを特徴とする請求項１に記載の光半導体装置。 The optical semiconductor device according to claim 1, wherein the first layer is an undoped layer.
- 前記第一層はｎ型層であることを特徴とする請求項１に記載の光半導体装置。 The optical semiconductor device according to claim 1, wherein the first layer is an n-type layer.
- 前記活性層の横において前記ｎ型層が全て空乏化されることを特徴とする請求項３に記載の光半導体装置。 4. The optical semiconductor device according to claim 3, wherein the n-type layer is all depleted beside the active layer.
- 前記第一層はＦｅドープ層であることを特徴とする請求項１に記載の光半導体装置。 The optical semiconductor device according to claim 1, wherein the first layer is an Fe-doped layer.
- 前記第一層はＲｕドープ層であることを特徴とする請求項１に記載の光半導体装置。 The optical semiconductor device according to claim 1, wherein the first layer is a Ru-doped layer.
- 前記半導体基板、前記第一導電型クラッド層、及び前記第二導電型クラッド層はＩｎＰであり、
前記活性層はＩｎＧａＡｓＰ又はＡｌＧａＩｎＡｓを含み、
前記埋め込み層はＩｎＰであり、
前記半絶縁層のドーパントがＦｅ又はＲｕであることを特徴とする請求項１～６の何れか１項に記載の光半導体装置。 The semiconductor substrate, the first conductivity type cladding layer, and the second conductivity type cladding layer are InP;
The active layer includes InGaAsP or AlGaInAs,
The buried layer is InP;
7. The optical semiconductor device according to claim 1, wherein the dopant of the semi-insulating layer is Fe or Ru. - 半導体基板の上に順に第一導電型クラッド層、活性層、及び第二導電型クラッド層を積層して積層体を形成する工程と、
前記積層体をエッチングによりメサ状に加工する工程と、
メサ状の前記積層体の両側に順に第一層、ｐ型層、及び半絶縁層を積層する工程とを備え、
前記第一層は、前記活性層の側壁に接し、ｐ型ドーパントを含まないことを特徴とする光半導体装置の製造方法。 Laminating a first conductivity type cladding layer, an active layer, and a second conductivity type cladding layer in order on a semiconductor substrate;
Processing the laminate into a mesa shape by etching;
Laminating a first layer, a p-type layer, and a semi-insulating layer in order on both sides of the mesa-shaped laminate,
The method of manufacturing an optical semiconductor device, wherein the first layer is in contact with a side wall of the active layer and does not include a p-type dopant. - 前記第一層はアンドープ層であることを特徴とする請求項８に記載の光半導体装置の製造方法。 The method for manufacturing an optical semiconductor device according to claim 8, wherein the first layer is an undoped layer.
- 前記第一層はｎ型層であることを特徴とする請求項８に記載の光半導体装置の製造方法。 The method for manufacturing an optical semiconductor device according to claim 8, wherein the first layer is an n-type layer.
- 前記第一層はＦｅドープ層であることを特徴とする請求項８に記載の光半導体装置の製造方法。 9. The method of manufacturing an optical semiconductor device according to claim 8, wherein the first layer is an Fe-doped layer.
- 前記第一層はＲｕドープ層であることを特徴とする請求項８に記載の光半導体装置の製造方法。 The method of manufacturing an optical semiconductor device according to claim 8, wherein the first layer is a Ru-doped layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2018/018602 WO2019220514A1 (en) | 2018-05-14 | 2018-05-14 | Optical semiconductor device and method of manufacturing same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2018/018602 WO2019220514A1 (en) | 2018-05-14 | 2018-05-14 | Optical semiconductor device and method of manufacturing same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2019220514A1 true WO2019220514A1 (en) | 2019-11-21 |
Family
ID=68539675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2018/018602 WO2019220514A1 (en) | 2018-05-14 | 2018-05-14 | Optical semiconductor device and method of manufacturing same |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO2019220514A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7080414B1 (en) * | 2021-06-17 | 2022-06-03 | 三菱電機株式会社 | Optical semiconductor device and its manufacturing method |
| WO2023228234A1 (en) * | 2022-05-23 | 2023-11-30 | 三菱電機株式会社 | Semiconductor laser, semiconductor laser device, and semiconductor laser production method |
| TWI836984B (en) | 2022-05-23 | 2024-03-21 | 日商三菱電機股份有限公司 | Semiconductor laser, semiconductor laser device, and semiconductor laser manufacturing method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0449691A (en) * | 1990-06-18 | 1992-02-19 | Mitsubishi Electric Corp | Visible-ray laser diode |
| JPH05218585A (en) * | 1992-02-04 | 1993-08-27 | Fujitsu Ltd | Semiconductor light emitting device |
| JPH0685390A (en) * | 1992-09-04 | 1994-03-25 | Fujitsu Ltd | Fabrication of semiconductor laser |
| JPH09148669A (en) * | 1995-11-28 | 1997-06-06 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor laser of buried-structure |
| JP2003078212A (en) * | 2001-09-06 | 2003-03-14 | Nippon Telegr & Teleph Corp <Ntt> | Buried semiconductor optical device |
| US20110032964A1 (en) * | 2009-03-04 | 2011-02-10 | Alcatel-Lucent Usa, Incorporated | Fabricating electronic-photonic devices having an active layer with spherical quantum dots |
| JP2013182976A (en) * | 2012-03-01 | 2013-09-12 | Mitsubishi Electric Corp | Buried type optical semiconductor element |
-
2018
- 2018-05-14 WO PCT/JP2018/018602 patent/WO2019220514A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0449691A (en) * | 1990-06-18 | 1992-02-19 | Mitsubishi Electric Corp | Visible-ray laser diode |
| JPH05218585A (en) * | 1992-02-04 | 1993-08-27 | Fujitsu Ltd | Semiconductor light emitting device |
| JPH0685390A (en) * | 1992-09-04 | 1994-03-25 | Fujitsu Ltd | Fabrication of semiconductor laser |
| JPH09148669A (en) * | 1995-11-28 | 1997-06-06 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor laser of buried-structure |
| JP2003078212A (en) * | 2001-09-06 | 2003-03-14 | Nippon Telegr & Teleph Corp <Ntt> | Buried semiconductor optical device |
| US20110032964A1 (en) * | 2009-03-04 | 2011-02-10 | Alcatel-Lucent Usa, Incorporated | Fabricating electronic-photonic devices having an active layer with spherical quantum dots |
| JP2013182976A (en) * | 2012-03-01 | 2013-09-12 | Mitsubishi Electric Corp | Buried type optical semiconductor element |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7080414B1 (en) * | 2021-06-17 | 2022-06-03 | 三菱電機株式会社 | Optical semiconductor device and its manufacturing method |
| WO2022264347A1 (en) * | 2021-06-17 | 2022-12-22 | 三菱電機株式会社 | Optical semiconductor element and manufacturing method therefor |
| WO2023228234A1 (en) * | 2022-05-23 | 2023-11-30 | 三菱電機株式会社 | Semiconductor laser, semiconductor laser device, and semiconductor laser production method |
| TWI836984B (en) | 2022-05-23 | 2024-03-21 | 日商三菱電機股份有限公司 | Semiconductor laser, semiconductor laser device, and semiconductor laser manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9312377B2 (en) | Semiconductor devices and methods of manufacturing the same | |
| JP2009283822A (en) | Semiconductor laser and manufacturing method thereof | |
| JP2009059918A (en) | Optical semiconductor device | |
| JP5327892B2 (en) | Avalanche photodiode | |
| US6584130B2 (en) | Multiple semiconductor laser structure with narrow wavelength distribution | |
| JP2016031970A (en) | Optical semiconductor device | |
| US8340147B2 (en) | Laser diode | |
| WO2019220514A1 (en) | Optical semiconductor device and method of manufacturing same | |
| JP4127815B2 (en) | Avalanche photodiode | |
| JP2008198942A (en) | Semiconductor photo element | |
| JP5920043B2 (en) | Semiconductor laser and manufacturing method thereof | |
| CN115023869A (en) | Optical semiconductor device and method for manufacturing the same | |
| JP2017017282A (en) | Semiconductor optical element and manufacturing method of the same | |
| TWI836984B (en) | Semiconductor laser, semiconductor laser device, and semiconductor laser manufacturing method | |
| WO2022264347A1 (en) | Optical semiconductor element and manufacturing method therefor | |
| JP6702523B1 (en) | Semiconductor device | |
| JP4430961B2 (en) | Electroabsorption type light modulation element and method for manufacturing the same | |
| JP2010027923A (en) | Semiconductor optical element | |
| WO2023228234A1 (en) | Semiconductor laser, semiconductor laser device, and semiconductor laser production method | |
| WO2020090078A1 (en) | Optical semiconductor device and method for manufacturing optical semiconductor device | |
| JP2007013100A (en) | Semiconductor laser | |
| WO2020084687A1 (en) | Semiconductor integrated optical device | |
| JP4508174B2 (en) | Vertical resonant surface light emitting device | |
| JP2008270435A (en) | Semiconductor optical element | |
| JP4634847B2 (en) | Optical semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 18919095 Country of ref document: EP Kind code of ref document: A1 |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 18919095 Country of ref document: EP Kind code of ref document: A1 |
|
| NENP | Non-entry into the national phase |
Ref country code: JP |