JP4125531B2 - Microprocessor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microprocessor having a mechanism that efficiently uses a bank function.
[0002]
[Prior art]
When creating a program using multiple banks, it is necessary to ensure the consistency of the bank that was switched at the time of interrupt. Conventionally, as a method for ensuring the consistency of a bank, a method of disabling interrupts while switching banks to access another bank has been used.
[0003]
FIG. 12 shows a technique for ensuring the consistency of bank values at the time of interruption in a conventional microprocessor. In FIG. 12, reference numeral 1 indicates an overall view of a bank access sequence showing data access using a bank.
[0004]
In the bank access sequence 1, reference numeral 11 denotes an interrupt prohibiting process, and by preventing execution of the interrupt processing program, a problem of interrupt processing due to setting a bank number in the subsequent processes is avoided.
[0005]
Reference numeral 12 denotes a bank number setting step, which is a step for storing a bank number in which data is placed in a bank number setting register.
[0006]
Reference numeral 13 denotes a bank validation step. The bank number set in the bank number setting step 12 is validated, and subsequent data access is determined to access the memory of the bank number set in the bank number setting step 12. is doing.
[0007]
Reference numeral 14 denotes a bank data access process, which performs data access to the memory indicated by the bank number set in the bank number setting process 12.
[0008]
Reference numeral 15 denotes a bank invalidation step, which invalidates access to the bank memory and returns to normal memory access.
[0009]
Reference numeral 16 denotes an interrupt permission process, which permits interrupt processing in subsequent programs.
[0010]
With the processing as described above, problems due to interrupt processing at the time of data access to the bank memory are avoided.
[0011]
[Problems to be solved by the invention]
However, the method of disabling interrupts while switching banks requires setting the value in the bank number setting register and disabling and enabling interrupts every time data in another bank is accessed. There is a problem that the response time of the interrupt processing program becomes long by increasing the size and execution time and prohibiting the interrupt.
[0012]
[Means for Solving the Problems]
In the present invention, the code size and execution time of the program can be reduced by providing a mechanism for simultaneously setting the bank function (valid / invalid, bank number, saving / returning bank number, etc.) and interrupt permission prohibition. In addition, the responsiveness of interrupt processing can be improved.
[0013]
Hereinafter, each claim will be described.
[0014]
The microprocessor according to claim 1 has first and second flags arranged in a setting register having the same address, and the interrupt becomes valid when a predetermined value is set in the first flag. The bank is invalidated when a predetermined value is set in the flag.
[0015]
According to this configuration, it becomes possible to simultaneously perform the bank valid / invalid setting and the interrupt permission prohibiting operation, and the code size and execution time of the program can be reduced. In addition, the responsiveness of interrupt processing can be improved.
[0016]
According to a second aspect of the present invention, in the microprocessor according to the first aspect, a value set in the first flag when the interrupt is enabled and a value set in the second flag when the bank is disabled. Are the same value.
[0017]
According to this configuration, the operation is the same as that of the microprocessor according to the first aspect.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0036]
FIG. 1 shows a bank access method of a microprocessor according to the first embodiment of the present invention. In FIG. 1, reference numeral 2 denotes a bank access sequence, which shows the entire bank access method.
[0037]
Reference numeral 21 denotes a bank valid and interrupt prohibition process, and the bank number validation process and the interrupt prohibition setting process are simultaneously performed by this process.
[0038]
Reference numeral 22 denotes a bank number setting step, which is a step for storing a bank number in which data is placed in a bank number setting register.
[0039]
Reference numeral 23 denotes a bank data access process, which performs data access to the memory indicated by the bank number set in the bank number setting process 22.
[0040]
Reference numeral 24 denotes a bank invalidation / interrupt permission process. The bank number invalidation process and the interrupt permission setting process set in this process are performed simultaneously.
[0041]
FIG. 3A shows the simultaneous processing of the bank number enabling process and the interrupt prohibition setting process in the bank valid and interrupt prohibiting process 21, and the bank invalidating and interrupt disabling process 24 in the bank invalidating and interrupt disabling process 24. An example of a microprocessor bank / interrupt setting register, which is a hardware configuration for realizing simultaneous processing with interrupt permission setting processing, is shown. In FIG. 3A, reference numeral 4 denotes a setting register, which stores flags for setting interrupt enable processing and bank invalidation processing. Reference numeral 41 denotes an interrupt valid flag that switches between valid and invalid interrupts. Reference numeral 42 denotes a bank invalidation flag, which switches between valid and invalid banks. That is, the interrupt valid flag 41 and the bank invalidation flag 42 are arranged in the setting register 4 having the same address.
[0042]
FIG. 3B shows the coding state of the interrupt valid flag 41 and the bank invalidation flag 42. With respect to the interrupt valid flag 41, in the present embodiment, setting the value 1 enables the interrupt, and setting the value 0 disables the interrupt. With respect to the bank invalidation flag 42, in the present embodiment, setting the value 1 invalidates the bank number setting, and setting the value 0 validates the bank number setting.
[0043]
Contrary to the above description, with respect to the interrupt valid flag 41, setting the value 0 enables the interrupt, setting the value 1 disables the interrupt, and setting the bank invalidation flag 42 with the value 0. Then, the bank number setting may be invalidated, and if the value 1 is set, the bank number setting may be validated.
[0044]
By providing the setting register 4 as described above and performing encoding as shown in FIG. 3B, simultaneous processing of bank valid and interrupt disable, such as bank valid and interrupt disable step 21, and bank invalid and interrupt enable Simultaneous processing of bank invalidation and interrupt permission as in step 24 can be easily performed by one instruction of a general processor instruction such as an AND instruction and an OR instruction.
[0045]
For example, for the interrupt enable flag 41, setting the value 1 enables the interrupt, setting the value 0 disables the interrupt, and for the bank disabling flag 42, setting the value 1 disables the bank number setting. When the value 0 is set to enable the bank number setting, the AND instruction and the OR instruction are as follows. That is, when the interrupt is enabled and the bank is invalidated, when the setting is changed without affecting other bits of the register, it can be executed by the “OR 0xc0, R” instruction. In the above OR instruction, R is a setting register, and its meaning means that the OR of the value of the setting register R and the hexadecimal number c0 is taken and substituted into the setting register R.
[0046]
Further, it is possible to disable the interrupt and enable the bank by executing the “AND 0x3f, R” instruction. The meaning of this AND instruction means that the AND of the value of the setting register R and the hexadecimal number 3f is taken and substituted into the setting register R.
[0047]
That is, by setting the value as described above, it is possible to change both settings with a single instruction without affecting other bits of the setting register 4 that sets the flag.
[0048]
It should be noted that, in the form of encoding in which the interrupt valid flag 41 is enabled by the value 1 and the bank invalidation flag 42 is enabled by the value 1, the general microprocessor is provided as described above. It is not possible to perform processing such as interrupt enable and bank invalidation as described above with one general instruction such as an AND instruction or an OR instruction. However, if the other bits of the register are not used, the above processing can be performed. In the following embodiment, there is no restriction as described above.
[0049]
FIG. 4 shows an example of a microprocessor bank / interrupt setting circuit, which is another hardware configuration for realizing the simultaneous processing in the bank valid and interrupt prohibiting step 21 and the simultaneous processing in the bank invalid and interrupt permitting step 24. ing. In FIG. 4, reference numeral 51 denotes an instruction register, which stores an instruction code fetched from the memory. Reference numeral 52 denotes an instruction decoder, which is a circuit that decodes an instruction code stored in the instruction register 51 and transmits a control signal corresponding to the instruction code stored in the instruction register 51.
[0050]
Reference numeral 53 denotes a bank invalidation register, which switches the validity of the bank according to the value set in this register. Reference numeral 531 denotes a bank invalidation register set signal. When this signal is a value 1, the bank invalidation register 53 is set. Reference numeral 532 denotes a bank invalidation register clear signal. When this signal is a value 1, the bank invalidation register 53 is cleared.
[0051]
Reference numeral 54 denotes an interrupt valid register, which switches between valid and invalid interrupts according to the value set in this register. Reference numeral 541 denotes an interrupt valid register set signal. When this signal is a value 1, the interrupt valid register 54 is set. Reference numeral 542 denotes an interrupt valid register clear signal. When this signal is a value 1, the interrupt valid register 54 is cleared.
[0052]
FIG. 5 is a truth table showing a part of the operation of the instruction decoder 52, and shows the operation of the control signal lines 531, 532, 541, and 542 in response to the instruction code stored in the instruction register 51 as an input. . In this embodiment, the instruction code assigned to the bank invalidation interrupt enable instruction (DBEI) is “10”, and the bank enable interrupt disable instruction (EBDI) is “20”.
[0053]
By providing the hardware as shown in FIGS. 4 and 5, the simultaneous processing in the bank valid / interrupt prohibiting step 21 and the bank invalid / interrupt permitting step 24 can be assigned to a special small instruction code. Accordingly, it is possible to simultaneously perform the bank valid / invalid setting and the interrupt permission prohibiting operation, and the code size and execution time of the program can be reduced. In addition, the responsiveness of interrupt processing can be improved.
[0054]
In the above embodiment, the instruction decoder 52 decodes the two instruction codes of the bank invalidation interrupt enable instruction (DBEI) and the bank enable interrupt disable instruction (EBDI). A circuit that decodes only one instruction code that inverts the set values of the generalization register 53 and the interrupt valid register 54 may be used.
[0055]
FIG. 2 shows a bank access method of the microprocessor according to the second embodiment of the present invention. In FIG. 2, reference numeral 3 denotes a bank access sequence, which shows the entire bank access method.
[0056]
Reference numeral 31 denotes a bank number setting and interrupt prohibiting step, and bank number setting processing, bank validation and interrupt prohibition setting are simultaneously performed by this step.
[0057]
Reference numeral 32 denotes a bank data access process, which performs data access to the memory indicated by the bank number set in the bank number setting and interrupt prohibition process 31.
[0058]
Reference numeral 33 denotes a bank number return and interrupt permission process, which simultaneously performs bank number recovery processing, bank invalidation, and interrupt permission processing set before the bank access sequence 3.
[0059]
FIG. 6 shows an example of a bank / interrupt setting circuit of a microprocessor, which is a hardware configuration for realizing the simultaneous processing in the bank number setting and interrupt prohibition step 31 and the bank number return and interrupt permission step 33. Yes. In FIG. 6, reference numeral 61 denotes an instruction register, which stores an instruction code fetched from the memory.
[0060]
Reference numeral 62 denotes an instruction decoder, which is a circuit that decodes the instruction code stored in the instruction register 61 and transmits a control signal corresponding to the stored instruction code.
[0061]
Reference numeral 63 denotes a bank invalidation register, which switches the validity of the bank according to the value set in this register. Reference numeral 631 denotes a bank invalidation register set signal. When this signal is a value 1, the bank invalidation register 63 is set. Reference numeral 632 denotes a bank invalidation register clear signal. When this signal is a value 1, the bank invalidation register 63 is cleared.
[0062]
Reference numeral 64 denotes an interrupt valid register, which switches between valid and invalid interrupts according to the value set in this register. Reference numeral 641 denotes an interrupt valid register set signal. When this signal is a value 1, the interrupt valid register 64 is set. Reference numeral 642 denotes an interrupt valid register clear signal. When this signal is a value 1, the interrupt valid register 64 is cleared.
[0063]
Reference numeral 65 denotes a bank number setting register which stores a bank number for data access. Reference numeral 651 denotes a bank number data bus, which is a signal line for transmitting a bank number set in the bank number setting register 65. Reference numeral 652 denotes a bank number setting register write enable signal. When this signal is 1, the bank number of the bank number data bus 651 is stored in the bank number setting register 65.
[0064]
Reference numeral 66 denotes a bank number decoder. The bank invalidation register set signal 631, the bank invalidation register clear signal 632, and the interrupt valid register set, which are control signals, are determined from the values of the bank number data bus 651 and the bank number setting register write enable signal 652. A signal 641 and an interrupt valid register clear signal 642 are generated.
[0065]
FIG. 7 is a truth table showing the operation of the bank number decoder 66. In the present embodiment, the data bus 651 has 2 bits, of which the values 1, 2, and 3 are used for bank switching, and the value 0 is used as a code indicating bank invalidation.
[0066]
With this configuration, bank number setting, bank invalid / effective switching, and interrupt valid / invalid switching can be executed simultaneously, and the code size, execution time, and interrupt response time can be reduced.
[0067]
FIG. 8 shows another hardware configuration for realizing the simultaneous processing in the bank number setting and interrupt prohibition step 31 and the simultaneous processing in the bank number return and interrupt permission step 33. An example of a setting circuit is shown. In FIG. 8, reference numeral 71 denotes an instruction register, which stores an instruction code fetched from the memory.
[0068]
Reference numeral 72 denotes an instruction decoder, which is a circuit that decodes the instruction code stored in the instruction register 71 and transmits a control signal corresponding to the stored instruction code.
[0069]
Reference numeral 73 denotes a bank number saving memory (register), which is a memory for temporarily saving the set value of the bank number setting register 75. Reference numeral 731 denotes a bank number saving memory write enable signal. When the value is 1, the bank number to be saved is stored in the bank number saving memory 73.
[0070]
Reference numeral 74 denotes an interrupt valid register, which switches between valid and invalid interrupts according to the value set in this register. Reference numeral 741 denotes an interrupt valid register set signal. When this signal is a value 1, the interrupt valid register 74 is set. Reference numeral 742 denotes an interrupt valid register clear signal. When this signal is a value 1, the interrupt valid register 74 is cleared.
[0071]
The bank number setting register 75 stores a bank number for data access. Reference numeral 751 denotes a bank number setting register write enable signal. When this signal is 1, the bank number is stored in the bank number setting register 75.
[0072]
Reference numeral 76 denotes a bank number decoder. The bank number setting signal write enable signal 751, the bank number setting data bus 772, and the bank number selection signal 771, which is a control signal, the bank number save memory write enable signal 731 and the interrupt valid register are indicated. A set signal 741 and an interrupt valid register clear signal 742 are generated.
[0073]
Reference numeral 77 denotes a selector which selects setting of the bank number stored in the bank number setting register 75 or restoration of the saved value. Reference numeral 771 denotes a bank number selection signal. When the value is 0, the bank number setting data bus 772 is selected. Therefore, the bank number sent through the bank number setting data bus 772 is selected. The number saving data bus 773 is selected, and therefore the bank number saved in the bank number saving memory 73 is selected.
[0074]
The bank number setting data bus 772 is a signal line for transmitting the bank number set in the bank number setting register 75. The bank number saving data bus 773 is a signal line for transmitting the bank number saved in the bank number saving memory 73 to the selector 77. Reference numeral 774 denotes a bank number selection result, and a value obtained by selecting the bank number by the selector 77 is output.
[0075]
FIG. 9 is a truth table showing the operation of the bank number decoder 76. In the present embodiment, the bank number setting register 75 has 2 bits, of which the values 0, 1, and 2 are used for specifying the bank number, and the value 3 is restored to the previous bank setting value. It is used as a code to be made.
[0076]
Here, the relationship between bank validity / invalidity and saving / restoring of bank numbers will be described. If the bank number can be saved / restored, there is no need to enable / disable the bank. In the case of the bank valid / invalid flag, if data is accessed when the bank is invalid, the default value of the bank number determined in advance by hardware is used. However, when using save / restore, the user arbitrarily determines the default value. be able to. Return to the previously set value by return processing.
[0077]
Even when the bank number decoder 76 changes the setting of any bank 0, 1, or 2 to another bank, the bank number 3 can be set to return to the previous bank number.
[0078]
According to this configuration, it is possible to simultaneously perform bank function settings such as bank number setting and saving / restoring of previous bank numbers, and interrupt permission prohibition operations, and the code size and execution time of the program can be reduced. In addition, the responsiveness of interrupt processing can be improved.
[0079]
FIG. 10 shows another hardware configuration for realizing the simultaneous processing in the bank number setting and interrupt prohibition step 31 and the simultaneous processing in the bank number return and interrupt permission step 33. 2 shows an example of an interrupt setting circuit. In FIG. 10, reference numeral 81 denotes an instruction register, which stores an instruction code fetched from the memory.
[0080]
Reference numeral 82 denotes an instruction decoder, which is a circuit that decodes the instruction code stored in the instruction register 81 and transmits a control signal corresponding to the stored instruction code.
[0081]
Reference numeral 83 denotes a bank number saving memory, which is a memory for temporarily saving the set value of the bank number setting register 85. This memory can be addressed (0, 1, 2, 3) so that a plurality of, for example, four set values can be stored. Reference numeral 831 denotes a bank number saving memory write enable signal. When the value is 1, the bank number saved in the bank number saving memory 83 is stored. Reference numeral 832 denotes a bank number saving memory address signal, which can specify the memory address of the bank number saving memory 83.
[0082]
Reference numeral 84 denotes an interrupt valid register, which switches between valid and invalid interrupts according to the value set in this register. Reference numeral 841 denotes an interrupt valid register set signal. When this signal is a value 1, the interrupt valid register 84 is set. Reference numeral 842 denotes an interrupt valid register clear signal. When this signal is a value 1, the interrupt valid register 84 is cleared.
[0083]
The bank number setting register 85 is a register for storing a bank number for data access. Reference numeral 851 denotes a bank number setting register write enable signal. When this signal is 1, the bank number is stored in the bank number setting register 85.
[0084]
Reference numeral 86 denotes a bank number decoder, and a bank number selection signal 871 which is a control signal based on the bank number setting register write enable signal 851, the value of the bank number setting data bus 872, and the address value 861 output from the address register 88. A bank number saving memory write enable signal 831, an addition / subtraction selection signal 891, an interrupt valid register set signal 841, and an interrupt valid register clear signal 842 are generated. Reference numeral 861 denotes an address value, and the value of the address register 88 is transmitted to the decoder 86.
[0085]
Reference numeral 87 denotes a bank number selector, which selects setting of a bank number stored in the bank number setting register 85 or restoration of a saved value. When the bank number selection signal 871 is 0, the bank number setting data bus 872 is selected. Therefore, the bank number sent through the bank number setting data bus 872 is selected. The bus 873 is selected, and therefore the bank number saved in the bank number saving memory 83 and designated by the address is selected. The bank number setting data bus 872 is a signal line for transmitting the bank number set in the bank number setting register 85. The bank number saving data bus 873 is a signal line for transmitting the bank number saved in the bank number saving memory 83 to the selector 87. Reference numeral 874 denotes a bank number selection result, and the value of the result selected by the bank number selector 87 is output.
[0086]
The address register 88 holds the address of the bank number saving memory 83.
[0087]
Reference numeral 89 denotes an adder / subtracter constituting an arithmetic unit, which calculates the value of the address register 88. The adder / subtractor 89 can switch between addition and subtraction by an addition / subtraction selection signal 891 which is a control signal. The adder / subtracter 89 performs addition when the addition / subtraction selection signal 891 is 0, and performs subtraction when the value is 1. A similar function can be realized by using a decoder instead of the adder / subtractor 89. Such a circuit is called a circuit means for changing an address value.
[0088]
Reference numeral 8 a denotes an address selector that selects an address to be given to the bank save memory 83. When the addition / subtraction selection signal 89 as the control signal is 0, the value of the adder / subtractor 89 is selected, and when the value is 1, the value of the address register 88 is selected.
[0089]
FIG. 11 is a truth table showing the operation of the decoder 86.
[0090]
In the present embodiment, the bank number setting register 85 has 2 bits, of which the values 0, 1, and 2 are used for specifying the bank number, and the value 3 is restored to the previous bank setting value. It is used as a code to be made. In this example, the address value 861 is input to the bank number decoder 86, and the interrupt valid register set signal 841 is not output until the address value of the address register 88 returns to the initial value 0. That is, the interrupt valid register set signal 841 is output for the first time when all the saved bank numbers are restored, and the interrupt becomes valid. This is the difference from the configuration of the embodiment shown in FIGS.
[0091]
In the present embodiment, by providing a plurality of bank number saving memories 83, it is possible to switch the bank a plurality of times, and to disable the interrupt until the original bank is restored.
[0092]
Here, operations related to the address register 88, the adder / subtractor 89, and the selector 8a will be described. The adder / subtracter selection signal 891 is added when the bank number is set, that is, when the bank number values 0, 1, and 2 are written, and is subtracted when the bank number is restored, that is, when the bank number 3 is written. This is a signal for selecting an operation. When setting the bank number, an address value indicating the bank number saving memory is selected by the selector 8a by adding 1 to the value of the address register 88. The saved bank number is saved in the bank number saving memory address indicated by the added address value. In the next cycle, a value obtained by adding 1 is stored in the address 88.
[0093]
When restoring the bank number, the selector 8a selects the output of the address register 88, and the bank number stored in the bank save memory indicated by the address value stored in the address register 88 is stored in the bank number save data bus 873. The bank number setting register 85 is restored. In the next cycle, a value obtained by subtracting 1 from the value of the adder / subtractor 89 is stored in the address register 88.
[0094]
A plurality of bank number saving processes are realized by the above operation. The above circuit is equivalent to a circuit that performs a post-increment pre-decrement stack operation, and the address register 88 can also be called a stack pointer.
[0095]
According to this configuration, it is possible to simultaneously perform bank function settings such as bank number setting and saving / restoring of previous bank numbers, and interrupt permission prohibition operations, and the code size and execution time of the program can be reduced. In addition, the responsiveness of interrupt processing can be improved. Further, a plurality of previous bank numbers can be saved and restored, and bank switching can be performed a plurality of times before returning to the original bank.
[0096]
【The invention's effect】
Claim 1 of the present invention 2 According to the described microprocessor, it is possible to simultaneously perform the bank valid / invalid setting and the interrupt permission prohibiting operation, and the code size and execution time of the program can be reduced. In addition, the responsiveness of interrupt processing can be improved.
[Brief description of the drawings]
FIG. 1 is a flowchart illustrating a bank access method in a microprocessor according to a first embodiment of this invention.
FIG. 2 is a flowchart showing a bank access method in a microprocessor according to a second embodiment of the present invention.
3A is a schematic diagram illustrating an example of a bank / interrupt setting register in the microprocessor according to the first embodiment of the present invention, and FIG. 3B is a schematic diagram illustrating register setting values.
FIG. 4 is a block diagram showing an example of a bank / interrupt setting circuit in the microprocessor according to the first embodiment of the present invention;
FIG. 5 is an explanatory diagram showing a decoder truth table of FIG. 4;
FIG. 6 is a block diagram showing an example of a bank / interrupt setting circuit in the microprocessor according to the second embodiment of the present invention;
7 is an explanatory diagram showing a decoder truth table of FIG. 6; FIG.
FIG. 8 is a block diagram showing an example of a bank / interrupt setting circuit with a bank number saving register in the microprocessor according to the second embodiment of the present invention;
9 is an explanatory diagram showing a decoder truth table of FIG. 8. FIG.
FIG. 10 is a block diagram showing an example of a bank / interrupt setting circuit with bank number saving memory in the microprocessor according to the second embodiment of the present invention;
FIG. 11 is an explanatory diagram showing a decoder truth table of FIG. 10;
FIG. 12 is a flowchart showing a bank access method in a conventional microprocessor.
[Explanation of symbols]
1 Bank access sequence
11 Interrupt disable process
12 Bank number setting process
13 Bank validation process
14 Bank data access process
15 Bank invalidation process
16 Interrupt enable process
2 Bank access sequence
21 Bank enabled and interrupt disabled process
22 Bank number setting process
23 Bank data access process
24 Bank invalid and interrupt enable process
3 Bank access sequence
31 Bank number setting and interrupt disable process
32 Bank data access process
33 Bank number return and interrupt enable process
4 Setting register
41 Interrupt enable flag
42 Bank invalidation flag
51 Instruction Register
52 Instruction decoder
53 Bank Invalidation Register
531 Bank invalidation register set signal
532 Bank invalidation register clear signal
54 Interrupt enable register
541 Interrupt enable register set signal
542 Interrupt enable register clear signal
61 Instruction Register
62 Instruction decoder
63 Bank invalidation register
631 Bank invalidation register set signal
632 Bank invalidation register clear signal
64 Interrupt enable register
641 Interrupt enable register set signal
642 Interrupt valid register clear signal
65 Bank number setting register
651 Bank number data bus
652 Bank number setting register write enable signal
66 Bank number decoder
71 Instruction Register
72 Instruction decoder
73 Bank number saving memory
731 Bank number saving memory write enable signal
74 Interrupt enable register
741 Interrupt enable register set signal
742 Interrupt valid register clear signal
75 Bank number setting register
751 Bank number setting register write enable signal
76 Bank number decoder
77 Selector
771 Bank number selection signal
772 Bank number setting data bus
773 Bank number saving data bus
774 Bank number selection result
81 Instruction register
82 Instruction decoder
83 Bank number save memory
831 Bank number save memory write enable signal
832 Bank number save memory address signal
84 Interrupt enable register
841 Interrupt enable register set signal
842 Interrupt enable register clear signal
85 Bank number setting register
851 Bank number setting register write enable signal
86 Bank number decoder
861 Address value
87 Bank number selector
871 Bank number selection signal
872 Bank number setting data bus
873 Bank number saving data bus
874 Bank number selection result
88 Address register
89 Adder / Subtractor
891 Addition / subtraction selection signal
8a Address selector

Claims (2)

  It has first and second flags arranged in the setting register of the same address, interrupt is enabled when a predetermined value is set in the first flag, and a predetermined value is set in the second flag A microprocessor that is disabled when banked. 2. The microprocessor according to claim 1, wherein the value set in the first flag when the interrupt is enabled is the same as the value set in the second flag when the bank is disabled .

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