JP4498705B2 - Cash system - Google Patents

Description

  The present invention relates to a cache system including a cache memory, and more particularly to a cache system having an access mode for operating a cache memory at low speed and low power consumption and an access mode for operating a cache memory at high speed and high power consumption.

  A first example of a cache system having two access modes is disclosed in Patent Document 1 below. In the first access mode (all access mode), the index operation for all ways is performed in parallel with the hit / miss determination operation for the address memory. Thereby, the speed of data output from the cache memory to the outside can be increased. On the other hand, in the second access mode (unique access mode), hit / miss determination operation regarding the address memory is performed prior to the index operation, and only for the way selected by the way selection signal obtained by the determination operation. An index operation is performed. As a result, only the minimum necessary data memory area operates, and the power consumption can be reduced.

  A second example of a cache system having two access modes is disclosed in Patent Document 2 below. The cache system includes a CPU and a cache memory, and the CPU includes a processor core and a prefetch device. The prefetch device includes an instruction buffer, a buffer occupancy detector, and a branch instruction predictor. In the first access mode (parallel access mode), index operations for all data RAM units are performed in parallel with the hit / miss determination operation for the address memory. On the other hand, in the second access mode (serial access mode), hit / miss determination operation related to the tag RAM is performed prior to the index operation, and one data RAM unit selected by the coincidence signal obtained by the determination operation is stored. Only the index operation is performed.

Japanese Patent Laid-Open No. 11-39216 JP-A-8-221324

  However, the conventional cache systems disclosed in Patent Documents 1 and 2 have the following problems.

  In the above-mentioned Patent Document 1, an example in which all access mode and only access mode are selected is described only in the case of burst access such as continuous reading. That is, Patent Document 1 describes that in the case of burst access, the cache memory is operated in the entire access mode in the first access, and the only access mode is operated in the second and subsequent accesses.

  However, the selection of the two access modes is not limited to the first access and the second and subsequent accesses in burst access.

  For example, in a semiconductor device equipped with a plurality of cache systems, high-speed processing from other cache systems in a situation where one cache system is operating in the power consumption priority access mode (second access mode). If there is an access request that requires a high-speed operation, it is desirable to switch to the access mode prioritizing high-speed operation (the first access mode) and to immediately start processing for access requests from other cache systems.

  Also, if the cache system becomes unable to accept a new access request due to snoop processing, write back processing, etc., the processing at the later stage of pipeline processing is clogged, so that the register between multiple instructions Dependencies are likely to occur, and as a result, there is a high possibility of causing a decrease in performance. Therefore, in such a state, it is desirable to operate the cache memory in an access mode that prioritizes high-speed operation.

  In addition, when the cache system receives a plurality of access requests at the same time, the processing start for the low priority access request is waited until the processing for the high priority access request is completed. cause. Therefore, when a plurality of access requests are received at the same time, it is desirable to operate the cache memory in an access mode giving priority to high-speed operation.

  In addition, when a branch instruction is executed, high-speed operation may be required for processing after branching. For example, an interrupt process in an embedded application often requires a response within real time. Therefore, when an interrupt routine is specified for the branch destination address, it is desirable to operate the cache memory in an access mode that prioritizes high-speed operation.

  In Patent Documents 1 and 2, the access mode cannot be switched depending on the type of issued command. Moreover, the above-mentioned Patent Document 2 cannot deal with a device that does not have a prefetch device, and requires a branch instruction predictor, which increases the circuit scale.

  In addition, when data required by the processor is not stored in the cache memory, data exchange with the external memory occurs, resulting in performance degradation. In addition, since the subsequent processing of the pipeline processing is clogged, register dependency is likely to occur between a plurality of instructions, and as a result, there is a high possibility that the performance will be further deteriorated. Therefore, in such a case, it is desirable to operate the cache memory in an access mode that prioritizes high-speed operation.

  In addition, as will be described in detail later, when switching from an access mode that prioritizes power consumption to an access mode that prioritizes high-speed operation, in some cases it is not possible to achieve high-speed operation and reduce power consumption. Can occur.

  The present invention has been made to solve these problems, and the processor determines the internal state of the entire system so that the processing speed of the entire semiconductor device on which the cache system is mounted is not reduced. An object of the present invention is to obtain a cache system capable of appropriately selecting an access mode so as to operate with as low power consumption as possible.

  It is another object of the present invention to provide a cache system that can appropriately select an access mode according to the type of instruction code executed by a processor.

  According to the first invention, the cache system includes a cache memory, a cache control unit that controls the cache memory, and a processor that can access the cache memory via the cache control unit. The cache memory can be accessed from a functional block different from the processor via the cache control unit, and the cache control unit can switch between each other at a first speed with respect to the access to the cache memory from the processor, and A first mode for accessing at a first power consumption, and a second mode for accessing at a second speed higher than the first speed and at a second power consumption higher than the first power consumption. The cache control unit switches between the first mode and the second mode according to the state of access from the functional block to the cache memory.

  According to the second invention, the cache system includes a cache memory, a cache control unit that controls the cache memory, and a processor that can access the cache memory via the cache control unit. Regarding the access from the processor to the cache memory, the cache control unit can switch between the first mode and the first mode for accessing at the first power consumption and the second speed that is faster than the first speed. And whether or not the cache control unit can accept an access request to the cache memory from the processor, and has a second mode of accessing with a second power consumption higher than the first power consumption. The first mode and the second mode are switched according to the above.

  According to the third invention, the cache system includes a cache memory, a cache control unit that controls the cache memory, and a processor that can access the cache memory via the cache control unit. The cache memory can be accessed from a functional block different from the processor via the cache control unit, and each access to the cache memory from the processor and the functional block can be switched to each other. A first mode that is accessed at a first speed and a second power consumption that is higher than the first speed and a second power that is higher than the first power consumption. When the cache control unit receives an access request from the processor to the cache memory and an access request from the functional block to the cache memory in duplicate, the cache control unit transfers the cache memory from the processor and the functional block to the cache memory. Each access is executed in the second mode.

  According to the fourth invention, a cache system includes a cache memory, a cache control unit that controls the cache memory, and a processor that can access the cache memory via the cache control unit. Regarding the access from the processor to the cache memory, the cache control unit can switch between the first mode and the first mode for accessing at the first power consumption and the second speed that is faster than the first speed. And a second mode for accessing with a second power consumption higher than the first power consumption, and the cache control unit is configured to allow the processor to access the cache memory based on the execution of the branch instruction. In the case of reading specific branch destination data from the memory, the processor accesses the cache memory in the second mode.

  According to the fifth invention, the cache system includes a cache memory, a cache control unit that controls the cache memory, and a processor that can access the cache memory via the cache control unit. Regarding the access from the processor to the cache memory, the cache control unit can switch between the first mode and the first mode for accessing at the first power consumption and the second speed that is faster than the first speed. And a second mode for accessing with a second power consumption higher than the first power consumption, and the cache control unit determines an instruction code fetched by the processor or a decoding result of the instruction code As a result, the processor accesses the cache memory in the first mode or the second mode.

  According to the sixth invention, a cache system includes a cache memory, a cache control unit that controls the cache memory, and a processor that can access the cache memory via the cache control unit. Regarding the access from the processor to the cache memory, the cache control unit can switch between the first mode and the first mode for accessing at the first power consumption and the second speed that is faster than the first speed. And the second mode for accessing with a second power consumption higher than the first power consumption, and the cache control unit accesses the cache memory from the processor, but the data required by the processor Is not stored in the cache memory, the next access from the processor to the cache memory is executed in the second mode.

  According to the seventh invention, a cache system includes a cache memory, a cache control unit that controls the cache memory, and a processor that can access the cache memory via the cache control unit. Regarding the access from the processor to the cache memory, the cache control unit can switch between the first mode and the first mode for accessing at the first power consumption and the second speed that is faster than the first speed. And a second mode for accessing with a second power consumption higher than the first power consumption, and the cache control unit continues to the second mode following the access request in the first mode. If the second access period accessed in the second mode overlaps with a part of the first access period accessed in the first mode due to the occurrence of the access request in The access in the second access period is changed to the first mode.

  According to the first to seventh inventions, the cache memory can be operated with as low power consumption as possible without reducing the processing speed of the entire semiconductor device on which the cache system is mounted.

  In particular, according to the fifth aspect, the access mode can be appropriately selected according to the type of instruction code executed by the processor.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a semiconductor device in which a cache system according to Embodiment 1 of the present invention is mounted. As shown in FIG. 1, the semiconductor device includes a CPU (processor) 1, a functional block different from CPU 1 (CPU 80 in the example of the first embodiment), a cache unit 100, a bus arbitration circuit 60, and an external bus. 3 and an external memory 70. The cache unit 100 includes a cache control unit 2 and a cache memory 50. The cache control unit 2 controls the operation of the cache memory 50. The CPU 1 can access the cache memory 50 via the cache control unit 2. The cache memory 50 can also be accessed from the CPU 80 via the cache control unit 2.

  The CPU 1 receives a cache access acceptance signal S5 and a cache data ready signal S6 from the cache control unit 2. For example, 32-bit output data D2 is input from the cache memory 50 to the CPU 1. The CPU 1 outputs a cache access request signal S4 and, for example, a 27-bit cache address A2.

  A cache access request signal S4 and a cache address A2 are input from the CPU 1 to the cache control unit 2. Further, the snoop request signal S1 and, for example, a 27-bit snoop address A1 are input from the CPU 80 to the cache control unit 2. Further, the output data D 2 and the Miss signal S 11 are input from the cache memory 50 to the cache control unit 2. The cache control unit 2 also receives a bus access acceptance signal S8 from the bus arbitration circuit 60. The cache control unit 2 includes a cache access acceptance signal S5, a cache data ready signal S6, a snoop request acceptance signal S2, a snoop data ready signal S3, a bus access request signal S7, for example, 128-bit write back data D1, a tag enable signal S9, For example, a 27-bit access address A3 and a cache access mode switching signal S10 are output.

  The CPU 80 receives a snoop request acceptance signal S2 and a snoop data ready signal S3 from the cache control unit 2. Further, the CPU 80 receives output data D2 from the cache memory 50. The CPU 80 outputs a snoop request signal S1 and a snoop address A1.

  A tag enable signal S9, an access address A3, and a cache access mode switching signal S10 are input from the cache control unit 2 to the cache memory 50. The cache memory 50 outputs a Miss signal S11 and output data D2.

  A bus access request signal S 7 is input from the cache control unit 2 to the bus arbitration circuit 60. The bus arbitration circuit 60 outputs a bus access acceptance signal S8.

  Write-back data D1 is input from the cache control unit 2 to the external memory 70 via the external bus 3.

  When reading data stored in the cache memory 50, the CPU 1 outputs a cache access request signal S4 and a cache address A2. The cache access request signal S4 and the cache address A2 are input to the cache control unit 2.

  When there are a plurality of access requests to the cache memory 50 within the same cycle period, the cache control unit 2 has a function of arbitrating them. Since such an arbitration function is well known, detailed description is omitted.

  When the cache control unit 2 receives the cache access request signal S4, if the cache memory 50 is in an accessible state, the cache control unit 2 outputs the cache access acceptance signal S5, the tag enable signal S9, and the access address A3 based on the cache address A2. Output. The cache access acceptance signal S5 is input to the CPU1. The tag enable signal S9 and the access address A3 are input to the cache memory 50.

  When reading data stored in the cache memory 50, the CPU 80 outputs a snoop request signal S1 and a snoop address A1. The snoop request signal S1 and the snoop address A1 are input to the cache control unit 2.

  When the cache control unit 2 receives the snoop request signal S1, if the cache memory 50 is in an accessible state, the cache control unit 2 outputs the snoop request reception signal S2, the tag enable signal S9, and the access address A3 based on the snoop address A1. To do. The snoop request acceptance signal S2 is input to the CPU 80. The tag enable signal S9 and the access address A3 are input to the cache memory 50.

  For each access from the CPU 1 and the CPU 80 to the cache memory 50, the cache control unit 2 has a first speed and a first power consumption mode (hereinafter referred to as “two-cycle access mode”), a first And a mode of accessing at a second speed higher than the speed and a second power consumption higher than the first power consumption (“one-cycle access mode” in this specification).

  The cache control unit 2 switches between the 2-cycle access mode and the 1-cycle access mode according to the status of access from the CPU 80 to the cache memory 50. Specifically, the cache control unit 2 outputs the cache access mode switching signal S10 of “H” level during the “H (High)” period in which the snoop request signal S1 is asserted, and “L” during other periods. (Low) "level cache access mode switching signal S10 is output. The cache access mode switching signal S10 is input to the cache memory 50. When the cache access mode switching signal S10 is at "H" level, the one cycle access mode is selected, and when the cache access mode switching signal S10 is at "L" level, the two cycle access mode is selected.

  Alternatively, the cache control unit 2 outputs an “H” level cache access mode switching signal S10 in the case of cache access based on the snoop request signal S1, while in the case of cache access based on the cache access request signal S4, The “L” level cache access mode switching signal S10 may be output.

  When the cache memory 50 receives the tag enable signal S9, the cache memory 50 starts data read processing based on the access address A3 and the cache access mode switching signal S10, and outputs the Miss signal S11 and the output data D2.

  When the cache access is based on the cache access request signal S4, the cache control unit 2 determines that the data required by the CPU 1 is stored in the cache memory 50 based on the Miss signal S11. A cache data ready signal S6 is output in synchronization with the output timing. The cache data ready signal S6 is input to the CPU1.

  When the cache access is based on the snoop request signal S1, the cache control unit 2 determines that the data required by the CPU 80 is stored in the cache memory 50 based on the Miss signal S11, and outputs the output data D2. A snoop data ready signal S3 is output in synchronization with the timing. The snoop data ready signal S3 is input to the CPU 80.

  When the output data D2 read from the cache memory 50 is written back to the external memory 70, the cache control unit 2 outputs a bus access request signal S7. The bus access request signal S7 is input to the bus arbitration circuit 60. The bus arbitration circuit 60 outputs a bus access acceptance signal S8 when the external bus 3 connected to the external memory 70 is usable. The bus access acceptance signal S8 is input to the cache control unit 2. When the cache control unit 2 receives the bus access acceptance signal S8, the cache control unit 2 outputs the write back data D1. The write back data D1 is input to the external memory 70 via the external bus 3.

  2 and 3 are block diagrams respectively showing a part of the configuration of the cache control unit 2. Referring to FIG. 2, the cache control unit 2 includes a switching signal generation circuit 2a. The switching signal generation circuit 2a outputs the snoop request signal S1 as the cache access mode switching signal S10.

  Alternatively, as shown in FIG. 3, the cache control unit 2 includes a switching signal generation circuit 2b. The switching signal generation circuit 2b outputs the snoop request acceptance signal S2 as the cache access mode switching signal S10.

  FIG. 4 is a block diagram showing a specific configuration of the cache memory 50. The cache memory 50 has a 2-way set associative configuration. The cache memory 50 includes a tag memory 101, a latch circuit 106, comparators 92a and 92b, a miss determination device 103, a cache access mode switching device 109, a data memory 104, selectors 105 and 111, and a flip-flop 110. And have.

  The tag memory 101 is an address memory, and includes a tag Way0 and a tag Way1 that are both address arrays. The tag Way0 and the tag Way1 each store a tag address corresponding to the index address.

  An index address A3b (for example, 8 bits) which is a lower part of the access address A3 shown in FIG. 1 is input to the tag Way0 and the tag Way1. The tag Way0 and the tag Way1 each output a tag address (for example, 17 bits) corresponding to the input index address A3b.

  The tag address of the tag Way0 specified by the index address A3b is an address related to data of data Way0 (described later) specified by the same index address A3b. Similarly, the tag address of the tag Way1 specified by the index address A3b is an address related to data of data Way1 (described later) specified by the same index address A3b.

  A tag enable signal S9 is input to each of the tag Way0 and the tag Way1. The tag Way0 and the tag Way1 operate when the tag enable signal S9 is at “H” level, and do not operate when the tag enable signal S9 is at “L” level.

  A tag address A3a (for example, 17 bits), which is the upper part of the access address A3 shown in FIG. 1, is input to the comparators 92a and 92b via the latch circuit 106, respectively. The latch circuit 106 outputs the input tag address A3a with a delay of ½ cycle.

  The comparator 92a compares the tag address input from the tag Way0 with the tag address A3a input from the latch circuit 106. Then, when the two match, that is, when the data of the designated address exists in the data Way0 (that is, in the case of hit), the comparator 92a outputs the “H” level Tag hit Way0 signal. S20 is output. On the other hand, if the two do not match, that is, if the data at the designated address does not exist in the data Way0 (that is, in the case of a miss hit), the “L” level Tag hit Way0 signal S20 is output. . The Tag hit Way 0 signal S20 is input to the miss determination device 103 and the cache access mode switching device 109.

  The comparator 92b compares the tag address input from the tag Way1 with the tag address A3a input from the latch circuit 106. Then, when the two match, that is, when the data at the designated address exists in the data Way1 (that is, in the case of a hit), the comparator 92b outputs an “H” level Tag hit Way1 signal. S21 is output. On the other hand, if the two do not match, that is, if the data at the designated address does not exist in the data Way1 (that is, in the case of a miss hit), an “L” level Tag hit Way1 signal S21 is output. . The Tag hit Way1 signal S21 is input to the miss determination device 103 and the cache access mode switching device 109.

  When both the tag hit way 0 signal S20 and the tag hit way 1 signal S21 are at the “L” level, the miss determination device 103 has no data at the designated address in the data Way 0 or the data Way 1. A Miss signal S11 having a content indicating that is output.

  The data memory 104 includes data Way0 and data Way1, which are data arrays. Data Way0 and Data Way1 store data in association with index addresses, respectively. In this specification, the term “data” includes both an instruction code and operand data.

  The data stored in the data Way0 is data having the index address A3b as a lower address and the tag address stored in the tag Way0 as an upper address corresponding to the same index address A3b. Similarly, the data stored in the data Way1 is data having the index address A3b as the lower address and the tag address stored in the tag Way1 corresponding to the same index address A3b as the upper address.

  The flip-flop 110 outputs the input index address A3b with a delay of one cycle period. The output of the flip-flop 110 is input to the first input terminal of the selector 111.

  The index address A3b is input to the second input terminal of the selector 111.

  The selector 111 receives a cache access mode switching signal S10 from the cache control unit 2 shown in FIG. The selector 111 selects the first input terminal when the cache access mode switching signal S10 is at the “L” level, and selects the second input terminal when the cache access mode switching signal S10 is at the “H” level.

  The output of the selector 111 is input to the data Way0 and the data Way1, respectively, and the Way0 enable signal S22 and the Way1 enable signal S23 are input from the cache access mode switching device 109, respectively.

  When the Way 0 enable signal S 22 is at “H” level, the data Way 0 outputs data corresponding to the output of the selector 111. Data output from the data Way 0 is input to the first input terminal of the selector 105. When the Way0 enable signal S22 is at “L” level, the data Way0 does not operate.

  When the Way 1 enable signal S 23 is at “H” level, the data Way 1 outputs data corresponding to the output of the selector 111. Data output from the data Way 1 is input to the second input terminal of the selector 105. When the Way1 enable signal S23 is at “L” level, the data Way1 does not operate.

  The selector 105 receives the way select signal S24 from the cache access mode switching device 109. The selector 105 selects the first input terminal when the Way select signal S24 is “L” level, and selects the second input terminal when the Way select signal S24 is “H” level.

  The cache access mode switching device 109 receives a cache access mode switching signal S10 from the cache control unit 2 shown in FIG. When the cache access mode switching signal S10 is at “H” level by the switching control by the cache access mode switching device 109, the cache memory 50 operates in the one-cycle access mode, and the cache access mode switching signal S10 is at “L” level. In some cases, the cache memory 50 operates in the 2-cycle access mode.

  FIG. 5 is a block diagram showing a specific configuration of the cache access mode switching device 109. The cache access mode switching device 109 has latch circuits 910, 911, 920, 921 and selectors 930, 931, 94.

  To the latch circuit 910, the Tag hit Way 0 signal S20 is input from the comparator 92a shown in FIG. The latch circuit 910 outputs the inputted Tag hit Way 0 signal S20 with a delay of ½ cycle period. The Tag hit Way 0 signal S20 output from the latch circuit 910 is input to the first input terminal of the selector 930.

  To the latch circuit 911, the Tag hit Way1 signal S21 is input from the comparator 92b shown in FIG. The latch circuit 911 delays the input Tag hit Way1 signal S21 by a ½ cycle period and outputs the delayed signal. The Tag hit Way1 signal S21 output from the latch circuit 911 is input to the first input terminal of the selector 931.

  A power supply potential giving an “H” level is input to each of the second input terminals of the selectors 930 and 931. Further, the cache access mode switching signal S10 is input to the selectors 930 and 931 from the cache control unit 2 shown in FIG.

  When the cache access mode switching signal S10 is at “H” level, the selector 930 outputs an “H” level signal as the Way0 enable signal S22. Accordingly, in the one cycle access mode, data is output from the cache memory 50 using one cycle period.

  On the other hand, when the cache access mode switching signal S10 is at "L" level, the selector 930 outputs the Tag hit Way0 signal S20 input from the latch circuit 910 as the Way0 enable signal S22. The Tag hit Way 0 signal S20 input to the selector 930 is delayed by a half cycle period by the latch circuit 910 than the Tag hit Way 0 signal S20 output from the comparator 92a shown in FIG. Therefore, the cycle period in which the data Way0 operates is one cycle period after the cycle period in which the tag Way0 operates. Accordingly, in the 2-cycle access mode, data is output from the cache memory 50 using a 2-cycle period.

  When the cache access mode switching signal S10 is at “H” level, the selector 931 outputs an “H” level signal as the Way1 enable signal S23. Accordingly, in the one cycle access mode, data is output from the cache memory 50 using one cycle period.

  On the other hand, when the cache access mode switching signal S10 is at “L” level, the selector 931 outputs the Tag hit Way1 signal S21 input from the latch circuit 911 as the Way1 enable signal S23. The Tag hit Way1 signal S21 input to the selector 931 is delayed by a half cycle period by the latch circuit 911 from the Tag hit Way1 signal S21 output from the comparator 92b shown in FIG. Therefore, the cycle period in which the data Way1 operates is one cycle period after the cycle period in which the tag Way1 operates. Accordingly, in the 2-cycle access mode, data is output from the cache memory 50 using a 2-cycle period.

  The latch circuit 920 outputs the cache access mode switching signal S10 input from the cache control unit 2 shown in FIG. The cache access mode switching signal S10 output from the latch circuit 920 is input to the selector 94.

  The latch circuit 921 delays the Way1 enable signal S23 input from the selector 931 and outputs the delayed signal by a ½ cycle period. The Way1 enable signal S23 output from the latch circuit 921 is input to the first input terminal of the selector 94. A Tag hit Way1 signal S21 is input to the second input terminal of the selector 94 from the comparator 92b shown in FIG.

  When the cache access mode switching signal S10 input from the latch circuit 920 is at “L” level, the selector 94 outputs the Way1 enable signal S23 input from the latch circuit 921 as the Way select signal S24. This is because, when the data Way1 is selected when the cache access mode switching signal S10 is at the “L” level, the Way1 enable signal S23 is after the ½ cycle period of the cycle period in which the tag memory 101 is accessed, that is, the data This is because it becomes “H” level 1/2 cycle before the cycle in which the memory 104 is accessed.

  On the other hand, when the cache access mode switching signal S10 input from the latch circuit 920 is at “H” level, the selector 94 outputs the Tag hit Way1 signal S21 as the Way select signal S24. This is because, when the data Way1 is selected when the cache access mode switching signal S10 is at the “H” level, the Tag hit Way1 signal S21 is accessed by the data memory 104 that is the same as the cycle period in which the tag memory 101 is accessed. This is because it becomes “H” level during the cycle period.

  With reference to FIG. 4, the Way select signal S <b> 24 is input to the selector 105. When the way select signal S24 is at "L" level, the selector 105 selects the data input from the data Way0 and outputs it as the output data D2 shown in FIG. On the other hand, when the way select signal S24 is at “H” level, the selector 105 selects the data input from the data Way1 and outputs it as the output data D2 shown in FIG.

  FIG. 6 is a timing chart showing waveforms of respective parts of the cache memory 50 when operating in the 2-cycle access mode. Hereinafter, the operation of the cache memory 50 in the 2-cycle access mode will be described in detail with reference to FIGS. Referring to FIG. 6, in the 2-cycle access mode, data is output from cache memory 50 using a 2-cycle period of a tag access cycle and a data access cycle.

  4 and 6, first, in the first half of the tag access cycle, access to the tag memory 101 is executed, and tag addresses are output from the tag Way0 and the tag Way1, respectively.

  Next, the comparator 92a compares the tag address input from the tag Way0 with the tag address A3a input from the latch circuit 106. If the two match, the “H” level Tag hit Way0. A signal S20 is output, and if they do not match, an “L” level tag hit way 0 signal S20 is output. The comparator 92b compares the tag address input from the tag Way1 with the tag address A3a input from the latch circuit 106. If the two match, the comparator 92b generates the “H” level Tag hit Way1 signal S21. If the two do not match, an “L” level Tag Hit Way 1 signal S21 is output. Therefore, when the data of the designated address exists in the cache memory 50, either the Tag hit Way 0 signal S20 or the Tag hit Way 1 signal S21 is set to the “H” level, while the designated data If the address data does not exist in the cache memory 50, both the Tag hit Way 0 signal S20 and the Tag hit Way 1 signal S21 are set to the “L” level.

  Next, in the latter half of the tag access cycle, if the Tag hit Way 0 signal S20 is at “H” level, the Way 0 enable signal S22 is set to “H” level, and if the Tag hit Way 1 signal S21 is at “H” level, Way 1 is set. The enable signal S23 is set to the “H” level.

  Next, in the first half of the data access cycle, if the Way0 enable signal S22 is “H” level, access to the data Way0 is executed and data is output, and if the Way1 enable signal S23 is “H” level, the data Way1 Is accessed and data is output.

  As described above, in the two-cycle access mode, the tag memory 101 is accessed in the tag access cycle, and the data memory 104 is accessed in the subsequent data access cycle. In the data access cycle, only one of data Way0 and data Way1 operates, and the other does not operate. Therefore, power consumption is smaller than when both data Way0 and data Way1 operate (one-cycle access mode). .

  FIG. 7 is a timing chart showing waveforms at various parts of the cache memory 50 when operating in the 1-cycle access mode. Hereinafter, the operation of the cache memory 50 in the one-cycle access mode will be described in detail with reference to FIGS. Referring to FIG. 7, in the 1-cycle access mode, data is output from cache memory 50 using a tag and data access cycle which is a 1-cycle period.

  4 and 7, first, in the first half of the tag and data access cycle, access to the tag memory 101 is executed, and tag addresses are output from the tag Way0 and the tag Way1, respectively.

  Next, the comparator 92a compares the tag address input from the tag Way0 with the tag address A3a input from the latch circuit 106. If the two match, the “H” level Tag hit Way0. A signal S20 is output, and if they do not match, an “L” level tag hit way 0 signal S20 is output. The comparator 92b compares the tag address input from the tag Way1 with the tag address A3a input from the latch circuit 106. If the two match, the comparator 92b generates the “H” level Tag hit Way1 signal S21. If the two do not match, an “L” level Tag Hit Way 1 signal S21 is output. Therefore, when the data of the designated address exists in the cache memory 50, either the Tag hit Way 0 signal S20 or the Tag hit Way 1 signal S21 is set to the “H” level, while the designated data If the address data does not exist in the cache memory 50, both the Tag hit Way 0 signal S20 and the Tag hit Way 1 signal S21 are set to the “L” level.

  In parallel with the above-described processing by the comparators 92a and 92b, the Way0 enable signal S22 and the Way1 enable signal S23 are both set to the “H” level in the same cycle period.

  Next, in the second half of the tag and data access cycle, each access to the data Way0 and the data Way1 is executed, and data is output from the data Way0 and the data Way1, respectively.

  Then, the selector 105 selects and outputs one of the data output from the data Way0 and the data Way1 based on the Way select signal S24.

  As described above, in the one-cycle access mode, access to the tag memory 101 and access to the data memory 104 are executed during one cycle period. Therefore, data can be output from the cache memory 50 earlier than when the data memory 104 is accessed after the access to the tag memory 101 (two-cycle access mode).

  Thus, according to the cache system according to the first embodiment, the cache control unit 2 outputs the cache access mode switching signal S10 at the “H” level during the “H” period when the snoop request signal S1 is asserted. Thus, the one-cycle access mode is set. When an access request from the CPU 80 to the cache memory 50 is generated while the CPU 1 is accessing the cache memory 50 in the two-cycle access mode, if the priority of the access request from the CPU 1 is high, the access request from the CPU 1 Until the remaining processing is completed, the start of processing based on the access request from the CPU 80 is awaited. However, according to the cache system according to the first embodiment, in such a case, the access from the CPU 1 to the cache memory 50 is switched from the 2-cycle access mode to the 1-cycle access mode. The remaining processing can be executed at high speed. Therefore, the process based on the access request from the CPU 80 can be started at an early stage, and as a result, it is possible to suppress the performance of the CPU 80 from being deteriorated. This is particularly effective when the CPU 80 gives priority to high-speed operation.

  In the above description, the CPU 80 that executes the snoop process is described as an element that can access the cache unit 100 in addition to the CPU 1. However, a CPU other than the CPU 80 may be used. In addition to the CPU 1, the elements that can access the cache unit 100 are not limited to the CPU 80 or a CPU other than the CPU 80, and may be any functional block. The same applies to all embodiments described later.

Embodiment 2. FIG.
FIG. 8 is a block diagram showing a configuration of a semiconductor device in which the cache system according to the second embodiment of the present invention is mounted. Of the plurality of components shown in FIG. 8, the same components as those in the first embodiment are given the same reference numerals as those in FIG. Hereinafter, the difference from the first embodiment will be mainly described.

  As shown in FIG. 8, the semiconductor device includes a CPU 201, a CPU 80, a cache unit 200, a bus arbitration circuit 60, an external bus 3, and an external memory 70. The cache unit 200 includes a cache control unit 202 and a cache memory 50. The cache control unit 202 controls the operation of the cache memory 50. The CPU 201 can access the cache memory 50 via the cache control unit 202. The cache memory 50 can also be accessed from the CPU 80 via the cache control unit 202.

  The CPU 201 receives a cache access acceptance signal S5 and a cache data ready signal S6 from the cache control unit 202. Further, output data D <b> 2 is input from the cache memory 50 to the CPU 201. The CPU 201 outputs a cache access request signal S4 and a cache address A2.

  A cache access request signal S4 and a cache address A2 are input from the CPU 201 to the cache control unit 202. Further, the snoop request signal S1 and the snoop address A1 are input from the CPU 80 to the cache control unit 202. Further, the output data D2 and the Miss signal S11 are input from the cache memory 50 to the cache control unit 202. The cache control unit 202 also receives a bus access acceptance signal S8 from the bus arbitration circuit 60. The cache control unit 202 includes a cache access acceptance signal S5, a cache data ready signal S6, a snoop request acceptance signal S2, a snoop data ready signal S3, a bus access request signal S7, a write back data D1, a tag enable signal S9, an access address A3, And the cache access mode switching signal S10 is output.

  The CPU 80 receives a snoop request acceptance signal S 2 and a snoop data ready signal S 3 from the cache control unit 202. Further, the CPU 80 receives output data D2 from the cache memory 50. The CPU 80 outputs a snoop request signal S1 and a snoop address A1.

  A tag enable signal S9, an access address A3, and a cache access mode switching signal S10 are input from the cache control unit 202 to the cache memory 50. The cache memory 50 outputs a Miss signal S11 and output data D2.

  When reading data stored in the cache memory 50, the CPU 201 outputs a cache access request signal S4 and a cache address A2. The cache access request signal S4 and the cache address A2 are input to the cache control unit 202.

  When the cache control unit 202 receives the cache access request signal S4, if the cache memory 50 is in an accessible state, the cache control unit 202 outputs the cache access acceptance signal S5, the tag enable signal S9, and the access address A3 based on the cache address A2. Output. The cache access acceptance signal S5 is input to the CPU 201. The tag enable signal S9 and the access address A3 are input to the cache memory 50.

  When reading data stored in the cache memory 50, the CPU 80 outputs a snoop request signal S1 and a snoop address A1. The snoop request signal S1 and the snoop address A1 are input to the cache control unit 202.

  When the cache control unit 202 receives the snoop request signal S1, if the cache memory 50 is accessible, the cache control unit 202 outputs the snoop request reception signal S2, the tag enable signal S9, and the access address A3 based on the snoop address A1. To do. The snoop request acceptance signal S2 is input to the CPU 80. The tag enable signal S9 and the access address A3 are input to the cache memory 50.

  For each access from the CPU 201 and the CPU 80 to the cache memory 50, the cache control unit 202 has a two-cycle access mode and a one-cycle access mode similar to those in the first embodiment.

  The cache control unit 202 switches between the 2-cycle access mode and the 1-cycle access mode depending on whether or not an access request to the cache memory 50 can be received from the CPU 201.

  Specifically, when the CPU 201 is accessing the cache memory 50 in the two-cycle access mode, the cache control unit 202 requests a new access request from the CPU 201 to the cache memory 50 due to a cache miss or a write back process. In the next access or subsequent access, the cache access mode switching signal S10 at the “H” level is output. That is, the 2-cycle access mode is switched to the 1-cycle access mode.

  Alternatively, when the CPU 80 is accessing the cache memory 50 in the 2-cycle access mode and the cache control unit 202 cannot accept an access request to the cache memory from the CPU 201 due to a reason such as a snoop process, the next time In an access or subsequent access, an “H” level cache access mode switching signal S10 is output. That is, the 2-cycle access mode is switched to the 1-cycle access mode.

  FIG. 9 is a block diagram illustrating a part of the configuration of the cache control unit 202. The cache control unit 202 includes a state monitoring circuit 10 and a switching signal generation circuit 11. The switching signal generation circuit 11 has a clear circuit 12, and the clear circuit 12 includes a plurality of counters 13.

  When the status monitoring circuit 10 detects an access request to the cache memory 50, the status monitoring circuit 10 outputs an access generation signal S30. In addition, when the state monitoring circuit 10 cannot accept a new access request to the cache memory 50, the state monitoring circuit 10 outputs a cache busy signal S31. The access generation signal S30 and the cache busy signal S31 are input to the switching signal generation circuit 11.

  When the cache busy signal S31 is input, the switching signal generation circuit 11 outputs an “H” level cache access mode switching signal S10. Thereby, the operation of the cache memory 50 is set to the one-cycle access mode.

  As described above, the switching signal generation circuit 11 has the clear circuit 12, and the clear circuit 12 includes a plurality of counters 13. Therefore, the switching signal generation circuit 11 can grasp the cycle period and the number of accesses after the cache access mode switching signal S10 is set to the “H” level based on the access generation signal S30 and the cache busy signal S31. . The clear circuit 12 is notified of the completion of the next access, the fact that a predetermined number of cycle periods have elapsed since the cache access mode switching signal S10 was set to the “H” level, and the cache for the subsequent and subsequent accesses. The fact that access to the memory 50 is interrupted is set as a clear condition. When the clear condition is satisfied, the clear circuit 12 switches the cache access mode switching signal S10 to “L” level.

  As described above, according to the cache system according to the second embodiment, when the cache control unit 202 cannot accept a new access request to the cache memory 50, the cache control unit 202 outputs the cache access mode switching signal S10 of “H” level. By outputting, one cycle access mode is set. For example, when the CPU 201 is accessing the cache memory 50 in the 2-cycle access mode, a new access request from the CPU 201 to the cache memory 50 is generated, and the cache memory 50 is in an access prohibited state. Since the subsequent processing is clogged, register dependency is likely to occur between a plurality of instructions, and as a result, there is a high possibility of causing performance degradation. However, according to the cache system according to the second embodiment, in such a case, the access from the CPU 201 to the cache memory 50 is switched from the 2-cycle access mode to the 1-cycle access mode, so that the penalty for performance degradation is minimized. It becomes possible to suppress to the limit.

Embodiment 3 FIG.
FIG. 10 is a block diagram showing a configuration of a semiconductor device in which the cache system according to the third embodiment of the present invention is mounted. Of the plurality of components shown in FIG. 10, the same components as those in the first embodiment are given the same reference numerals as those in FIG. Hereinafter, the difference from the first embodiment will be mainly described.

  As shown in FIG. 10, the semiconductor device includes a CPU 301, a CPU 80, a cache unit 300, a bus arbitration circuit 60, an external bus 3, and an external memory 70. The cache unit 300 includes a cache control unit 302 and a cache memory 50. The cache control unit 302 controls the operation of the cache memory 50. The CPU 301 can access the cache memory 50 via the cache control unit 302. The cache memory 50 can also be accessed from the CPU 80 via the cache control unit 302.

  The CPU 301 receives a cache access acceptance signal S5 and a cache data ready signal S6 from the cache control unit 302. In addition, output data D <b> 2 is input from the cache memory 50 to the CPU 301. The CPU 301 outputs a cache access request signal S4 and a cache address A2.

  A cache access request signal S4 and a cache address A2 are input from the CPU 301 to the cache control unit 302. Further, the snoop request signal S1 and the snoop address A1 are input from the CPU 80 to the cache control unit 302. Further, the output data D 2 and the Miss signal S 11 are input from the cache memory 50 to the cache control unit 302. The cache control unit 302 also receives a bus access acceptance signal S8 from the bus arbitration circuit 60. The cache control unit 302 includes a cache access acceptance signal S5, a cache data ready signal S6, a snoop request acceptance signal S2, a snoop data ready signal S3, a bus access request signal S7, a write back data D1, a tag enable signal S9, an access address A3, And the cache access mode switching signal S10 is output.

  The CPU 80 receives a snoop request acceptance signal S 2 and a snoop data ready signal S 3 from the cache control unit 302. Further, the CPU 80 receives output data D2 from the cache memory 50. The CPU 80 outputs a snoop request signal S1 and a snoop address A1.

  A tag enable signal S9, an access address A3, and a cache access mode switching signal S10 are input from the cache control unit 302 to the cache memory 50. The cache memory 50 outputs a Miss signal S11 and output data D2.

  When reading data stored in the cache memory 50, the CPU 301 outputs a cache access request signal S4 and a cache address A2. The cache access request signal S4 and the cache address A2 are input to the cache control unit 302.

  When the cache control unit 302 receives the cache access request signal S4, if the cache memory 50 is in an accessible state, the cache control unit 302 outputs the cache access acceptance signal S5, the tag enable signal S9, and the access address A3 based on the cache address A2. Output. The cache access acceptance signal S5 is input to the CPU 301. The tag enable signal S9 and the access address A3 are input to the cache memory 50.

  When reading data stored in the cache memory 50, the CPU 80 outputs a snoop request signal S1 and a snoop address A1. The snoop request signal S1 and the snoop address A1 are input to the cache control unit 302.

  When the cache control unit 302 receives the snoop request signal S1, if the cache memory 50 is in an accessible state, the cache control unit 302 outputs the snoop request reception signal S2, the tag enable signal S9, and the access address A3 based on the snoop address A1. To do. The snoop request acceptance signal S2 is input to the CPU 80. The tag enable signal S9 and the access address A3 are input to the cache memory 50.

  For each access from the CPU 301 and the CPU 80 to the cache memory 50, the cache control unit 302 has the same 2-cycle access mode and 1-cycle access mode as in the first embodiment.

  When the cache control unit 302 receives the access request from the CPU 301 to the cache memory 50 and the access request from the CPU 80 to the cache memory 50 in duplicate, all of the accesses from the CPU 301 and the CPU 80 to the cache memory 50 are performed. An “H” level cache access mode switching signal S10 is output. That is, each access from the CPU 301 and the CPU 80 to the cache memory 50 is executed in the one-cycle access mode.

  FIG. 11 is a block diagram illustrating a part of the configuration of the cache control unit 302. The cache control unit 302 includes an arbitration circuit 15 and a switching signal generation circuit 16.

  When the arbitration circuit 15 detects that an access request from the CPU 301 to the cache memory 50 and an access request from the CPU 80 to the cache memory 50 are received within the same cycle period, it outputs an access request simultaneous generation signal S40. The access request simultaneous generation signal S40 is input to the switching signal generation circuit 16.

  When the access request simultaneous generation signal S40 is input, the switching signal generation circuit 16 receives the cache access of “H” level in the cycle period in which the access request simultaneous generation signal S40 is input and in one cycle period following the cycle period. A mode switching signal S10 is output. Thus, the operation of the cache memory 50 is set to the one-cycle access mode in both the access period based on the cache access request signal S4 and the access period based on the snoop request signal S1.

  As described above, according to the cache system according to the third embodiment, the cache control unit 302 receives the access request from the CPU 301 to the cache memory 50 and the access request from the CPU 80 to the cache memory 50 in duplicate. Each access from the CPU 301 and the CPU 80 to the cache memory 50 is executed in the one-cycle access mode. When the cache system receives a plurality of access requests at the same time, the start of processing for an access request with a low priority waits for the processing for an access request with a high priority to be completed, resulting in performance degradation. . However, according to the cache system according to the third embodiment, in this case, each access from the CPU 301 and the CPU 80 to the cache memory 50 is switched to the 1-cycle access mode, so that the penalty for performance degradation is minimized. It becomes possible to suppress to the limit.

Embodiment 4 FIG.
FIG. 12 is a block diagram showing a configuration of a semiconductor device in which the cache system according to the fourth embodiment of the present invention is mounted. Of the plurality of components shown in FIG. 12, the same components as those in the first embodiment are given the same reference numerals as those in FIG. Hereinafter, the difference from the first embodiment will be mainly described.

  As illustrated in FIG. 12, the semiconductor device includes a CPU 401, a CPU 80, a cache unit 400, a bus arbitration circuit 60, an external bus 3, and an external memory 70. The cache unit 400 includes a cache control unit 402 and a cache memory 50. The cache control unit 402 controls the operation of the cache memory 50. The CPU 401 can access the cache memory 50 via the cache control unit 402. The cache memory 50 can also be accessed from the CPU 80 via the cache control unit 402. However, with respect to the fourth embodiment, the CPU 80 is not necessarily provided.

  The CPU 401 receives a cache access acceptance signal S5 and a cache data ready signal S6 from the cache control unit 402. Further, output data D <b> 2 is input from the cache memory 50 to the CPU 401. The CPU 401 outputs a cache access request signal S4, a cache address A2, a branch request signal S50, and a 27-bit branch destination address A50, for example.

  A cache access request signal S4, a cache address A2, a branch request signal S50, and a branch destination address A50 are input from the CPU 401 to the cache control unit 402. In addition, the snoop request signal S1 and the snoop address A1 are input from the CPU 80 to the cache control unit 402. Further, the output data D 2 and the Miss signal S 11 are input from the cache memory 50 to the cache control unit 402. In addition, the bus access acceptance signal S8 is input from the bus arbitration circuit 60 to the cache control unit 402. The cache control unit 402 includes a cache access acceptance signal S5, a cache data ready signal S6, a snoop request acceptance signal S2, a snoop data ready signal S3, a bus access request signal S7, a write back data D1, a tag enable signal S9, an access address A3, And the cache access mode switching signal S10 is output.

  The CPU 80 receives a snoop request acceptance signal S 2 and a snoop data ready signal S 3 from the cache control unit 402. Further, the CPU 80 receives output data D2 from the cache memory 50. The CPU 80 outputs a snoop request signal S1 and a snoop address A1.

  A tag enable signal S9, an access address A3, and a cache access mode switching signal S10 are input from the cache control unit 402 to the cache memory 50. The cache memory 50 outputs a Miss signal S11 and output data D2.

  When reading data stored in the cache memory 50, the CPU 401 outputs a cache access request signal S4 and a cache address A2. The cache access request signal S4 and the cache address A2 are input to the cache control unit 402.

  When the cache control unit 402 receives the cache access request signal S4, if the cache memory 50 is in an accessible state, the cache control unit 402 outputs the cache access acceptance signal S5, the tag enable signal S9, and the access address A3 based on the cache address A2. Output. The cache access acceptance signal S5 is input to the CPU 401. The tag enable signal S9 and the access address A3 are input to the cache memory 50.

  When reading data stored in the cache memory 50, the CPU 80 outputs a snoop request signal S1 and a snoop address A1. The snoop request signal S1 and the snoop address A1 are input to the cache control unit 402.

  When the cache control unit 402 receives the snoop request signal S1, if the cache memory 50 is in an accessible state, the cache control unit 402 outputs the snoop request reception signal S2, the tag enable signal S9, and the access address A3 based on the snoop address A1. To do. The snoop request acceptance signal S2 is input to the CPU 80. The tag enable signal S9 and the access address A3 are input to the cache memory 50.

  Regarding the access from the CPU 401 to the cache memory 50, the cache control unit 402 has the same 2-cycle access mode and 1-cycle access mode as in the first embodiment.

  When the access from the CPU 401 to the cache memory 50 based on the execution of the branch instruction is the reading of specific branch destination data from the cache memory 50, the cache control unit 402 regards the access from the CPU 401 to the cache memory 50 as “H ”Level cache access mode switching signal S10 is output. That is, access from the CPU 401 to the cache memory 50 is executed in the one-cycle access mode.

  Specifically, the CPU 401 inputs the branch request signal S50 and the branch destination address A50 to the cache control unit 402 when executing the branch instruction. When the branch request signal S50 and the branch destination address A50 are input, the cache control unit 402 determines whether or not the branch destination address A50 matches any of preset specific addresses (plural). . Then, when the branch destination address A50 matches any of the specific addresses, the cache control unit 402 outputs an “H” level cache access mode switching signal S10, while the branch destination address A50 is the specific address. If the address does not match any of the addresses, an “L” level cache access mode switching signal S10 is output.

  The specific address is preset in the cache unit 400 as a hardware configuration by the system designer. Alternatively, the specific address may be set by a program in a storage element (not shown) in the cache unit 400 by a system user. Further, only one specific address may be set.

FIG. 13 is a block diagram illustrating a part of the configuration of the cache control unit 402. The cache control unit 402 has a switching signal generation circuit 20. The switching signal generation circuit 20 includes a plurality of comparators 21 _{1 to} 21 _n (n is a natural number of 2 or more), an OR circuit 22, a selector 23, and latch circuits 24 and 25.

The specific addresses are input as set values K _{1 to} K _{n to} the first input terminals of the comparators 21 _{1 to} 21 _n , respectively. The branch destination address A50 is input to each of the second input terminals of the comparators 21 _{1 to} 21 _n . Each output terminal of the comparators 21 _{1 to} 21 _n is connected to a plurality of input terminals of the OR circuit 22. The output terminal of the OR circuit 22 is connected to the first input terminal of the selector 23. The output terminal of the selector 23 is connected to the input terminal of the latch circuit 24, and the output terminal of the latch circuit 24 is connected to the input terminal of the latch circuit 25. A cache access mode switching signal S10 is output from the latch circuit 24. The output terminal of the latch circuit 25 is connected to the second input terminal of the selector 23. A branch request signal S50 is input to the selector 23.

The selector 23 selects the first input terminal during the period in which the branch request signal S50 is input, and selects the second input terminal during the other periods. When the branch request signal S50 and the branch destination address A50 are input from the CPU 401 illustrated in FIG. 12 to the cache control unit 402, when the branch destination address A50 matches any of the set values K _{1 to} K _n , An “H” level signal is input to the input terminal 1. This “H” level signal is output from the selector 23 and input to the latch circuit 24. Therefore, the latch circuit 24 outputs an “H” level cache access mode switching signal S10. Thereby, the operation of the cache memory 50 shown in FIG. 12 is set to the one-cycle access mode.

  As described above, according to the cache system according to the fourth embodiment, the cache control unit 402 accesses the cache memory 50 from the CPU 401 based on the execution of the branch instruction, and reads specific branch destination data from the cache memory 50. In this case, the CPU 401 accesses the cache memory 50 in the one cycle access mode. Therefore, for example, when an interrupt routine is specified for the branch destination address, the cache memory 50 can be operated in the one-cycle access mode. Interrupt processing in embedded applications often requires a response within real time. According to the cache system of the fourth embodiment, it is possible to increase the possibility that the interrupt process is completed in real time by switching the operation of the cache memory 50 to the one-cycle access mode.

  Note that the branch instruction to be executed includes not only a branch instruction that is executed after the branch condition is determined but also a branch instruction that is executed in advance in anticipation of the occurrence of a branch (branch prediction). .

Embodiment 5 FIG.
FIG. 14 is a block diagram showing a configuration of a semiconductor device in which the cache system according to the fifth embodiment of the present invention is mounted. Of the plurality of components shown in FIG. 15, the same components as those in the first embodiment are given the same reference numerals as those in FIG. Hereinafter, the difference from the first embodiment will be mainly described.

  As illustrated in FIG. 14, the semiconductor device includes a CPU 501, a CPU 80, a cache unit 500, a bus arbitration circuit 60, an external bus 3, and an external memory 70. The cache unit 500 includes a cache control unit 502 and a cache memory 50. The cache control unit 502 controls the operation of the cache memory 50. The CPU 501 can access the cache memory 50 via the cache control unit 502. The cache memory 50 can also be accessed from the CPU 80 via the cache control unit 502. However, with respect to the fifth embodiment, the CPU 80 is not necessarily provided.

  A cache access acceptance signal S5 and a cache data ready signal S6 are input from the cache control unit 502 to the CPU 501. Further, the CPU 501 receives output data D2 from the cache memory 50. The CPU 501 outputs a cache access request signal S4, a cache address A2, and a 32-bit instruction code C1, for example.

  A cache access request signal S4, a cache address A2, and an instruction code C1 are input from the CPU 501 to the cache control unit 502. Further, the snoop request signal S1 and the snoop address A1 are input from the CPU 80 to the cache control unit 502. In addition, the output data D2 and the Miss signal S11 are input from the cache memory 50 to the cache control unit 502. The cache control unit 502 also receives a bus access acceptance signal S8 from the bus arbitration circuit 60. The cache control unit 502 includes a cache access acceptance signal S5, a cache data ready signal S6, a snoop request acceptance signal S2, a snoop data ready signal S3, a bus access request signal S7, a write back data D1, a tag enable signal S9, an access address A3, And the cache access mode switching signal S10 is output.

  The CPU 80 receives a snoop request acceptance signal S2 and a snoop data ready signal S3 from the cache control unit 502. Further, the CPU 80 receives output data D2 from the cache memory 50. The CPU 80 outputs a snoop request signal S1 and a snoop address A1.

  A tag enable signal S9, an access address A3, and a cache access mode switching signal S10 are input from the cache control unit 502 to the cache memory 50. The cache memory 50 outputs a Miss signal S11 and output data D2.

  When reading data stored in the cache memory 50, the CPU 501 outputs a cache access request signal S4 and a cache address A2. The cache access request signal S4 and the cache address A2 are input to the cache control unit 502.

  When the cache control unit 502 receives the cache access request signal S4, if the cache memory 50 is in an accessible state, the cache control unit 502 outputs the cache access reception signal S5, the tag enable signal S9, and the access address A3 based on the cache address A2. Output. The cache access acceptance signal S5 is input to the CPU 501. The tag enable signal S9 and the access address A3 are input to the cache memory 50.

  When reading data stored in the cache memory 50, the CPU 80 outputs a snoop request signal S1 and a snoop address A1. The snoop request signal S1 and the snoop address A1 are input to the cache control unit 502.

  When the cache control unit 502 receives the snoop request signal S1, if the cache memory 50 is in an accessible state, the cache control unit 502 outputs the snoop request reception signal S2, the tag enable signal S9, and the access address A3 based on the snoop address A1. To do. The snoop request acceptance signal S2 is input to the CPU 80. The tag enable signal S9 and the access address A3 are input to the cache memory 50.

  Regarding the access from the CPU 501 to the cache memory 50, the cache control unit 502 has the same 2-cycle access mode and 1-cycle access mode as in the first embodiment.

  The cache control unit 502 determines an instruction code C1 fetched by the CPU 501 or a decoding result of the instruction code C1, and thereby accesses the cache memory 50 from the CPU 501 at “H” level or “L” level. A mode switching signal S10 is output. That is, the CPU 501 accesses the cache memory 50 in the one-cycle access mode when the cache access mode switching signal S10 is at “H” level, and for two cycles when the cache access mode switching signal S10 is at “L” level. Run in access mode.

  Specifically, the CPU 501 inputs the fetched instruction code C1 to the cache control unit 502. The cache control unit 502 determines whether the input instruction code C1 matches or does not match any of specific values (plurality) set in advance according to the type of instruction code. Then, the cache control unit 502 determines whether to set the one-cycle access mode, the two-cycle access mode, or keep the previous access mode according to the determination result, and the corresponding cache An access mode switching signal S10 is output.

  The specific value is preset in the cache unit 500 as a hardware configuration by the system designer. Alternatively, the specific value may be set by a system user in a register (not shown) in the cache unit 500 by a program.

  15 to 17 are block diagrams respectively showing a part of the configuration of the cache system according to the fifth embodiment. The cache unit 500 illustrated in FIG. 14 includes the determination devices 31 and 33 and the decoding circuits 30, 32, and 34 illustrated in FIGS.

  Referring to FIG. 15, instruction code C <b> 1 fetched by CPU 501 shown in FIG. 14 is input to decode circuit 30. The decode circuit 30 decodes the instruction code C1 and outputs a decode result D10. The determination device 31 receives the instruction code C1 (or a part thereof). The determination device 31 determines whether the input instruction code C1 matches any of the specific values or does not match any of them. Then, the corresponding cache access mode switching signal S10 is output according to the determination result.

  Referring to FIG. 16, instruction code C <b> 1 fetched by CPU 501 shown in FIG. 14 is input to decode circuit 32. The decode circuit 32 decodes the instruction code C1 and outputs a decode result D10. A part of the decoding result D10 is input to the determination device 33. Based on the input decoding result D10, the determination device 33 determines whether the instruction code C1 matches any of the specific values or does not match any of them. Then, the corresponding cache access mode switching signal S10 is output according to the determination result.

  Referring to FIG. 17, instruction code C <b> 1 fetched by CPU 501 shown in FIG. 14 is input to decode circuit 34. The decode circuit 34 decodes the instruction code C1 and outputs a decode result D10. The decode circuit 34 has a determination function similar to that of the determination devices 31 and 33 shown in FIGS. 15 and 16, respectively, and which of the specific values the input instruction code C1 matches. Or, it is determined whether they do not match any of them. Then, according to the determination result, the corresponding cache access mode switching signal S10 is output as a part of the decoding result D10.

FIG. 18 is a block diagram showing a part of the configuration of the cache control unit 502 shown in FIG. In the example illustrated in FIG. 18, the cache control unit 502 includes the determination device 31 illustrated in FIG. The determination device 31 includes a plurality of comparators 35 _{1 to} 35 ₄ , OR circuits 36 to 38, a selector 39, and latch circuits 40 and 41.

The specific values are input as set values L _{1 to} L _{4 to} the first input terminals of the comparators 35 _{1 to} 35 ₄ , respectively. The comparator 35 _{1-35 4} each second input terminal of the instruction code C1 (or portions thereof) are input, respectively. Each output terminal of the comparators 35 ₁ and 35 ₂ is connected to two input terminals of the OR circuit 36, and each output terminal of the comparators 35 ₃ and 35 ₄ is connected to two input terminals of the OR circuit 37, respectively. Has been. The output terminals of the OR circuits 36 and 37 are connected to two input terminals of the OR circuit 38, respectively. The output terminal of the OR circuit 37 is also connected to the first input terminal of the selector 39. A signal output from the OR circuit 38 is input to the selector 39.

  The output terminal of the selector 39 is connected to the input terminal of the latch circuit 40, and the output terminal of the latch circuit 40 is connected to the input terminal of the latch circuit 41. A cache access mode switching signal S10 is output from the latch circuit 40. The output terminal of the latch circuit 41 is connected to the second input terminal of the selector 39.

  The selector 39 selects the first input terminal when the “H” level signal is input from the OR circuit 38 and the second input terminal when the “L” level signal is input. To do.

When the instruction code C1 input from the CPU 501 shown in FIG. 14 to the cache control unit 502 matches one of the setting values L ₃ and L ₄ , the first input terminal of the selector 39 has an “H” level. Signal is input. This “H” level signal is output from the selector 39 and input to the latch circuit 40. Accordingly, the latch circuit 40 outputs the cache access mode switching signal S10 at “H” level. Thereby, the operation of the cache memory 50 shown in FIG. 14 is set to the one-cycle access mode.

When the instruction code C1 input from the CPU 501 shown in FIG. 14 to the cache control unit 502 matches either of the set values L ₁ and L ₂ , the first input terminal of the selector 39 has an “L” level. Signal is input. This “L” level signal is output from the selector 39 and input to the latch circuit 40. Accordingly, the latch circuit 40 outputs the “L” level cache access mode switching signal S10. Thereby, the operation of the cache memory 50 shown in FIG. 14 is set to the two-cycle access mode.

When the instruction code C1 input from the CPU 501 shown in FIG. 14 to the cache control unit 502 does not match any of the setting values L _{1 to} L _4, an “L” level signal is output from the OR circuit 38. Therefore, the second input terminal of the selector 39 is selected. A cache access mode switching signal S10 for determining the previous access mode is input from the latch circuit 41 to the second input terminal of the selector 39. The cache access mode switching signal S10 is output from the latch circuit 40 via the selector 39. Thereby, the operation of the cache memory 50 shown in FIG. 14 is set to be the same as the access mode in the previous state.

The determination device 33 shown in FIG. 16, only the signal inputted to each second input terminal of the comparator 35 _{1-35 4} becomes a part of the instruction code C1, not the decoded result D10, other The circuit configuration is the same as that of the determination device 31 shown in FIG.

  As described above, according to the cache system according to the fifth embodiment, the cache control unit 502 switches between the 1-cycle access mode and the 2-cycle access mode according to the type of instruction executed by the CPU 501. Accordingly, it is possible to use the access mode by selecting the compile option of the software. Also, a high-speed instruction set mainly for the 1-cycle access mode and a low-power consumption instruction set mainly for the 2-cycle access mode are prepared, and the access mode can be selected according to the instruction set to be used. It becomes like.

  Moreover, the cache control unit 502 selects the access mode by determining the instruction code C1 fetched by the CPU 501 or the decoding result D10 of the instruction code C1. Therefore, unlike the cache system disclosed in Patent Document 2, the cache system according to the fifth embodiment is compatible with a device that does not have a prefetch device, and a branch instruction predictor is unnecessary. The circuit scale does not increase.

  Further, in the example shown in FIGS. 16 and 17, since all or part of the decoding circuit is also used as an access mode determination device, an increase in circuit scale is suppressed as compared with the example shown in FIG. be able to.

Embodiment 6 FIG.
FIG. 19 is a block diagram showing a configuration of a semiconductor device in which the cache system according to the sixth embodiment of the present invention is mounted. Of the plurality of components shown in FIG. 19, the same components as those in the first embodiment are given the same reference numerals as those in FIG. Hereinafter, the difference from the first embodiment will be mainly described.

  As shown in FIG. 19, the semiconductor device includes a CPU 601, a CPU 80, a cache unit 600, a bus arbitration circuit 60, an external bus 3, and an external memory 70. The cache unit 600 includes a cache control unit 602 and a cache memory 50. The cache control unit 602 controls the operation of the cache memory 50. The CPU 601 can access the cache memory 50 via the cache control unit 602. The cache memory 50 can also be accessed from the CPU 80 via the cache control unit 602. However, regarding the sixth embodiment, the CPU 80 is not necessarily provided.

  The CPU 601 receives a cache access acceptance signal S5 and a cache data ready signal S6 from the cache control unit 602. Further, output data D <b> 2 is input from the cache memory 50 to the CPU 601. The CPU 601 outputs a cache access request signal S4 and a cache address A2.

  The cache control unit 602 receives a cache access request signal S4 and a cache address A2 from the CPU 601. Further, the snoop request signal S1 and the snoop address A1 are input from the CPU 80 to the cache control unit 602. In addition, the output data D2 and the Miss signal S11 are input from the cache memory 50 to the cache control unit 602. Further, the bus access acceptance signal S <b> 8 is input from the bus arbitration circuit 60 to the cache control unit 602. The cache control unit 602 includes a cache access acceptance signal S5, a cache data ready signal S6, a snoop request acceptance signal S2, a snoop data ready signal S3, a bus access request signal S7, a write back data D1, a tag enable signal S9, an access address A3, And the cache access mode switching signal S10 is output.

  The CPU 80 receives a snoop request acceptance signal S 2 and a snoop data ready signal S 3 from the cache control unit 602. Further, the CPU 80 receives output data D2 from the cache memory 50. The CPU 80 outputs a snoop request signal S1 and a snoop address A1.

  A tag enable signal S9, an access address A3, and a cache access mode switching signal S10 are input from the cache control unit 602 to the cache memory 50. The cache memory 50 outputs a Miss signal S11 and output data D2.

  When reading data stored in the cache memory 50, the CPU 201 outputs a cache access request signal S4 and a cache address A2. The cache access request signal S4 and the cache address A2 are input to the cache control unit 602.

  When the cache control unit 602 receives the cache access request signal S4, if the cache memory 50 is in an accessible state, the cache control unit 602 generates the cache access acceptance signal S5, the tag enable signal S9, and the access address A3 based on the cache address A2. Output. The cache access acceptance signal S5 is input to the CPU 601. The tag enable signal S9 and the access address A3 are input to the cache memory 50.

  When reading data stored in the cache memory 50, the CPU 80 outputs a snoop request signal S1 and a snoop address A1. The snoop request signal S1 and the snoop address A1 are input to the cache control unit 602.

  When the cache control unit 602 receives the snoop request signal S1, if the cache memory 50 is accessible, the cache control unit 602 outputs the snoop request reception signal S2, the tag enable signal S9, and the access address A3 based on the snoop address A1. To do. The snoop request acceptance signal S2 is input to the CPU 80. The tag enable signal S9 and the access address A3 are input to the cache memory 50.

  Regarding the access from the CPU 601 to the cache memory 50, the cache control unit 602 has a two-cycle access mode and a one-cycle access mode similar to those in the first embodiment.

  The cache control unit 602 accesses the cache memory 50 from the CPU 601, but when the data required by the CPU 601 is not stored in the cache memory 50, the CPU 601 accesses the cache memory 50 next time or after the next time. In access, the cache access mode switching signal S10 of “H” level is output. That is, the operation of the cache memory 50 is set to the one cycle access mode.

  FIG. 20 is a block diagram illustrating a part of the configuration of the cache control unit 602. The cache control unit 602 includes a state monitoring circuit 51 and a switching signal generation circuit 52. The switching signal generation circuit 52 has a clear circuit 53, and the clear circuit 53 includes a plurality of counters 54.

  When the status monitoring circuit 51 detects an access request to the cache memory 50, it outputs an access generation signal S51. The access generation signal S51 is input to the switching signal generation circuit 52. Further, the Miss signal S11 is input from the cache memory 50 shown in FIG.

  When the Miss signal S11 indicating that the designated data is not stored in the cache memory 50 is input, the switching signal generation circuit 11 outputs an “H” level cache access mode switching signal S10. Thereby, the operation of the cache memory 50 is set to the one-cycle access mode.

  As described above, the switching signal generation circuit 52 has the clear circuit 53, and the clear circuit 53 includes a plurality of counters 54. Therefore, the switching signal generation circuit 52 can grasp the cycle period and the number of accesses after the cache access mode switching signal S10 is set to the “H” level based on the access generation signal S51 and the Miss signal S11. In the clear circuit 53, the above-mentioned next access is completed, the cache access mode switching signal S10 is set to the “H” level, a predetermined number of cycle periods have elapsed, and the above-mentioned next and subsequent accesses are cached. The fact that access to the memory 50 is interrupted is set as a clear condition. When the clear condition is satisfied, the clear circuit 53 switches the cache access mode switching signal S10 to the “L” level.

  As described above, according to the cache system according to the sixth embodiment, the cache control unit 602 allows the data required by the CPU 601 to be stored in the cache memory even when the cache memory 50 is operating in the two-cycle access mode. If it is not stored in 50, the cache access mode switching signal S10 at "H" level is output to set the one cycle access mode. When the necessary data is not stored in the cache memory 50, it is necessary to read the data from the external memory 70, which may cause a decrease in performance. In addition, since the subsequent processing of the pipeline processing is clogged, register dependency is likely to occur between a plurality of instructions, and as a result, the possibility of causing performance degradation is further increased. However, according to the cache system according to the sixth embodiment, in such a case, the access from the CPU 601 to the cache memory 50 is set to the one-cycle access mode, so that the penalty for performance degradation is minimized. It becomes possible.

Embodiment 7 FIG.
FIGS. 21 and 22 are timing charts respectively showing the situation in which the access mode is switched in the cache systems according to the first to sixth embodiments. In the example shown in FIG. 21, an access request (access AC1) in the 2-cycle access mode is generated in the cycle period P1, an access request is not generated in the cycle period P2, and an access request in the 1-cycle access mode in the cycle period P3. (Access AC3) has occurred. The data memory access of access AC1 is completed in the first half of the cycle period P3. Therefore, access AC3 tag and data memory access is started from the latter half of the cycle period P3, and high-speed operation is realized for access AC3.

  In the example shown in FIG. 22, an access request (access AC1) in the 2-cycle access mode is generated in the cycle period P1, and an access request (access AC2) in the 2-cycle access mode is also generated in the cycle period P2. , An access request (access AC3) is generated in the 1-cycle access mode. In this case, even if it is attempted to start the access AC3 tag and data memory access from the latter half of the cycle period P3, the access AC2 data memory access is not yet completed. Therefore, the start of access AC3 tag and data memory access must wait until the second half of the cycle period P4. As a result, the access AC3 has higher power consumption than the access AC1 and AC2, and a high-speed operation is not realized. Such a situation is not limited to the cache systems according to Embodiments 1 to 6 described above, but in any cache system having two low-speed and high-speed access modes (including the cache systems disclosed in Patent Documents 1 and 2). appear.

  In the seventh embodiment, a cache system that can avoid such a situation will be described.

  FIG. 23 is a block diagram showing a configuration of a semiconductor device in which the cache system according to the seventh embodiment of the present invention is mounted. Of the plurality of components shown in FIG. 23, the same components as those in the first embodiment are given the same reference numerals as those in FIG. Hereinafter, the difference from the first embodiment will be mainly described.

  As shown in FIG. 23, the semiconductor device includes a CPU 701, a CPU 80, a cache unit 700, a bus arbitration circuit 60, an external bus 3, and an external memory 70. The cache unit 700 includes a cache control unit 702 and a cache memory 50. The cache control unit 702 controls the operation of the cache memory 50. The CPU 701 can access the cache memory 50 via the cache control unit 702. The cache memory 50 can also be accessed from the CPU 80 via the cache control unit 702.

  The CPU 701 receives a cache access acceptance signal S5 and a cache data ready signal S6 from the cache control unit 702. Further, output data D <b> 2 is input from the cache memory 50 to the CPU 701. The CPU 701 outputs a cache access request signal S4 and a cache address A2.

  The cache control unit 702 receives a cache access request signal S4 and a cache address A2 from the CPU 701. In addition, the snoop request signal S1 and the snoop address A1 are input from the CPU 80 to the cache control unit 702. In addition, the output data D 2 and the Miss signal S 11 are input from the cache memory 50 to the cache control unit 702. Further, the bus access acceptance signal S8 is input from the bus arbitration circuit 60 to the cache control unit 702. The cache control unit 702 includes a cache access acceptance signal S5, a cache data ready signal S6, a snoop request acceptance signal S2, a snoop data ready signal S3, a bus access request signal S7, a write back data D1, a tag enable signal S9, an access address A3, And the cache access mode switching signal S10 is output.

  The CPU 80 receives a snoop request acceptance signal S2 and a snoop data ready signal S3 from the cache control unit 702. Further, the CPU 80 receives output data D2 from the cache memory 50. The CPU 80 outputs a snoop request signal S1 and a snoop address A1.

  A tag enable signal S9, an access address A3, and a cache access mode switching signal S10 are input from the cache control unit 702 to the cache memory 50. The cache memory 50 outputs a Miss signal S11 and output data D2.

  When reading data stored in the cache memory 50, the CPU 701 outputs a cache access request signal S4 and a cache address A2. The cache access request signal S4 and the cache address A2 are input to the cache control unit 702.

  When the cache control unit 702 receives the cache access request signal S4, if the cache memory 50 is in an accessible state, the cache control unit 702 outputs the cache access acceptance signal S5, the tag enable signal S9, and the access address A3 based on the cache address A2. Output. The cache access acceptance signal S5 is input to the CPU 701. The tag enable signal S9 and the access address A3 are input to the cache memory 50.

  When reading data stored in the cache memory 50, the CPU 80 outputs a snoop request signal S1 and a snoop address A1. The snoop request signal S1 and the snoop address A1 are input to the cache control unit 702.

  When the cache control unit 702 receives the snoop request signal S1, if the cache memory 50 is accessible, the cache control unit 702 outputs the snoop request reception signal S2, the tag enable signal S9, and the access address A3 based on the snoop address A1. To do. The snoop request acceptance signal S2 is input to the CPU 80. The tag enable signal S9 and the access address A3 are input to the cache memory 50.

  With respect to each access from the CPU 701 and CPU 80 to the cache memory 50, the cache control unit 702 has a two-cycle access mode and a one-cycle access mode similar to those in the first embodiment.

  The cache control unit 702 accesses in the 2-cycle access mode due to the occurrence of the access request in the 1-cycle access mode following the access request in the 2-cycle access mode (first access period). If a period (second access period) for accessing a part of the second access period overlaps, the access in the second access period is changed to the two-cycle access mode. For example, referring to the example shown in FIG. 22, the second access to the second half of the first access period (the second half of the cycle period P2 to the first half of the cycle period P4) to be accessed in the two-cycle access mode. Access periods (the second half of the cycle period P3 to the first half of the cycle period P4) overlap. Accordingly, the cache control unit 702 changes the access AC3 in the second access period from the 1-cycle access mode to the 2-cycle access mode.

  FIG. 24 is a timing chart illustrating a situation where the access mode is switched in the cache system according to the seventh embodiment. Similar to the example shown in FIG. 22, in the cycle period P1, an access request (access AC1) in the 2-cycle access mode is generated because the determination condition for the 2-cycle access mode is satisfied. Also, in the cycle period P2 that is continuous with the cycle period P1, the access request (access AC2) in the 2-cycle access mode is generated because the determination condition for the 2-cycle access mode is satisfied. Further, in the cycle period P3 continuous to the cycle period P2, the access request (access AC3) in the one-cycle access mode is generated because the determination condition for the one-cycle access mode is satisfied.

  When the cache control unit 702 determines that the access AC3 in the one-cycle access mode is continuous with the access AC2 in the two-cycle access mode, the cache control unit 702 sets the cache access mode switching signal S10 corresponding to the access AC3 to the “H” level. To “L” level. Thereby, the access mode of the access AC3 is changed from the 1-cycle access mode to the 2-cycle access mode.

  In addition, even when the access in the 1 cycle access mode is executed after the access in the 2 cycle access mode, the access in the 1 cycle access mode is not continuous with the access in the 2 cycle access mode. The same operation as in FIG. 21 is performed.

  FIG. 25 is a block diagram illustrating a part of the configuration of the cache control unit 702. The cache control unit 702 has a switching signal generation circuit 60. The switching signal generation circuit 60 includes an access cycle determination circuit 61, AND circuits 62, 63 and 65, and a flip-flop 64. The output terminal of the access cycle determination circuit 61 is connected to each first input terminal of the AND circuits 63 and 65. The output terminal of the AND circuit 63 is connected to the input terminal of the flip-flop 64. The output terminal of the flip-flop 64 is connected to the first input terminal of the AND circuit 62 and the second input terminal of the AND circuit 65. A cache access mode switching signal S10 is output from the AND circuit 65. A tag enable signal S9 is input to the second input terminal of the AND circuit 62. The output terminal of the AND circuit 62 is connected to the second input terminal of the AND circuit 63.

  The access cycle determination circuit 61 normally outputs an “H” level signal, and outputs an “L” level signal only for one cycle period when accessing the cache memory 50 in the two-cycle access mode.

  When the access cycle determination circuit 61 outputs an “L” level signal for only one cycle period, an “L” level cache access mode switching signal is output during this one cycle period and the next one cycle period following this one cycle period. S10 is output.

  On the other hand, when the access cycle determination circuit 61 outputs an “H” level signal, there is an access to the tag memory within the same cycle period, and there is an access to the data memory in the 2-cycle access mode. , “L” level signals are input to the flip-flop 64. In other cases, an “H” level signal is input to the flip-flop 64. The AND circuit 65 takes a logical product of the signal input from the flip-flop 64 and the signal input from the access cycle determination circuit 61 and outputs the logical product as the cache access mode switching signal S10.

  In the cache system according to the seventh embodiment, the determination conditions for the one-cycle access mode and the two-cycle access mode are not limited to the determination conditions described in the first to sixth embodiments. It may be anything.

  As described above, according to the cache system according to the seventh embodiment, when the cache control unit 702 determines that the access AC3 in the one-cycle access mode is continuous with the access AC2 in the two-cycle access mode, The AC3 access mode is changed from the 1-cycle access mode to the 2-cycle access mode. Therefore, when the high-speed operation cannot be realized even when the mode is switched to the 1-cycle access mode, the 2-cycle access mode is maintained, so that the power consumption can be suppressed.

1 is a block diagram illustrating a configuration of a semiconductor device in which a cache system according to a first embodiment of the present invention is mounted. It is a block diagram which shows a part of structure of a cache control part regarding the cache system which concerns on Embodiment 1 of this invention. It is a block diagram which shows a part of structure of a cache control part regarding the cache system which concerns on Embodiment 1 of this invention. 1 is a block diagram showing a specific configuration of a cache memory in the cache system according to Embodiment 1 of the present invention. 1 is a block diagram showing a specific configuration of a cache access mode switching device in the cache system according to Embodiment 1 of the present invention. 4 is a timing chart showing waveforms of respective parts of the cache memory when operating in the two-cycle access mode with respect to the cache system according to the first embodiment of the present invention. 5 is a timing chart showing waveforms of respective parts of the cache memory when operating in the one-cycle access mode with respect to the cache system according to the first embodiment of the present invention. It is a block diagram which shows the structure of the semiconductor device with which the cache system which concerns on Embodiment 2 of this invention is mounted. It is a block diagram which shows a part of structure of a cache control part regarding the cache system which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the semiconductor device with which the cache system which concerns on Embodiment 3 of this invention is mounted. It is a block diagram which shows a part of structure of a cache control part regarding the cache system which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structure of the semiconductor device with which the cache system based on Embodiment 4 of this invention is mounted. It is a block diagram which shows a part of structure of a cache control part regarding the cache system which concerns on Embodiment 4 of this invention. It is a block diagram which shows the structure of the semiconductor device with which the cache system based on Embodiment 5 of this invention is mounted. It is a block diagram which shows a part of structure of the cache system which concerns on Embodiment 5 of this invention. It is a block diagram which shows a part of structure of the cache system which concerns on Embodiment 5 of this invention. It is a block diagram which shows a part of structure of the cache system which concerns on Embodiment 5 of this invention. It is a block diagram which shows a part of structure of a cache control part regarding the cache system which concerns on Embodiment 5 of this invention. It is a block diagram which shows the structure of the semiconductor device with which the cache system which concerns on Embodiment 6 of this invention is mounted. It is a block diagram which shows a part of structure of a cache control part regarding the cache system which concerns on Embodiment 6 of this invention. It is a timing chart which shows the condition where an access mode switches regarding the cache system which concerns on Embodiment 1-6 of this invention. It is a timing chart which shows the condition where an access mode switches regarding the cache system which concerns on Embodiment 1-6 of this invention. It is a block diagram which shows the structure of the semiconductor device with which the cache system based on Embodiment 7 of this invention is mounted. It is a timing chart which shows the condition where an access mode switches regarding the cache system which concerns on Embodiment 7 of this invention. It is a block diagram which shows a part of structure of a cache control part regarding the cache system which concerns on Embodiment 7 of this invention.

Explanation of symbols

1, 80, 201, 301, 401, 501, 601, 701 CPU, 2, 202, 302, 402, 502, 602, 702 Cache control unit, 50 cache memory.

Claims (10)

Cache memory,
A cache control unit for controlling the cache memory;
A processor accessible to the cache memory via the cache control unit,
The cache memory can be accessed from the functional block different from the processor via the cache control unit,
Regarding the access to the cache memory from the processor, the cache control unit can switch to each other at a first speed and a first mode that is accessed at a first power consumption, and is faster than the first speed. And a second mode for accessing at a second speed and a second power consumption higher than the first power consumption,
The cache control unit, wherein the cache control unit switches between the first mode and the second mode according to a state of access from the functional block to the cache memory.   When the cache controller receives an access request to the cache memory from the functional block while the processor is accessing the cache memory in the first mode, the cache control unit changes the first mode to the first mode. The cache system according to claim 1, wherein the mode is switched to a second mode. Cache memory,
A cache control unit for controlling the cache memory;
A processor accessible to the cache memory via the cache control unit,
Regarding the access from the processor to the cache memory, the cache control unit can switch to each other at a first speed and a first mode that is accessed at a first power consumption, and is faster than the first speed. And a second mode for accessing at a second speed and a second power consumption higher than the first power consumption,
The cache system, wherein the cache control unit switches between the first mode and the second mode depending on whether or not an access request to the cache memory can be received from the processor. When the processor is accessing the cache memory in the first mode and the cache control unit cannot accept a new access request to the cache memory from the processor, The cache system according to claim 3, wherein the cache system is switched to the second mode.
The cache memory can be accessed from the functional block different from the processor via the cache control unit,
Regarding the access from the functional block to the cache memory, the cache control unit has the first mode and the second mode that can be switched to each other,
In the state where the functional block is accessing the cache memory in the first mode, the cache control unit is configured to change the first mode when the processor cannot accept an access request to the cache memory. The cache system according to claim 3, wherein the cache system is switched to the second mode. Cache memory,
A cache control unit for controlling the cache memory;
A processor accessible to the cache memory via the cache control unit,
The cache memory can be accessed from the functional block different from the processor via the cache control unit,
With respect to each access from the processor and the functional block to the cache memory, the cache control unit can switch between each other at a first speed and at a first power consumption, and the first mode. And a second mode for accessing at a second speed higher than the first power consumption and at a second power consumption higher than the first power consumption,
When the cache control unit receives an access request from the processor to the cache memory and an access request from the functional block to the cache memory, the cache control unit transfers the cache memory from the processor and the functional block to the cache memory. A cache system that executes each access in the second mode. Cache memory,
A cache control unit for controlling the cache memory;
A processor accessible to the cache memory via the cache control unit,
Regarding the access from the processor to the cache memory, the cache control unit can switch to each other at a first speed and a first mode that is accessed at a first power consumption, and is faster than the first speed. And a second mode for accessing at a second speed and a second power consumption higher than the first power consumption,
When the access from the processor to the cache memory based on execution of a branch instruction is a read of specific branch destination data from the cache memory, the cache control unit controls the access from the processor to the cache memory. A cache system that executes in the second mode. Cache memory,
A cache control unit for controlling the cache memory;
A processor accessible to the cache memory via the cache control unit,
Regarding the access to the cache memory from the processor, the cache control unit can switch to each other at a first speed and a first mode that is accessed at a first power consumption, and is faster than the first speed. And a second mode for accessing at a second speed and a second power consumption higher than the first power consumption,
The cache control unit determines access to the cache memory from the processor in the first mode or the second mode by determining an instruction code fetched by the processor or a decoding result of the instruction code. The cache system to execute. Cache memory,
A cache control unit for controlling the cache memory;
A processor accessible to the cache memory via the cache control unit,
Regarding the access from the processor to the cache memory, the cache control unit can switch to each other at a first speed and a first mode that is accessed at a first power consumption, and is faster than the first speed. And a second mode for accessing at a second speed and a second power consumption higher than the first power consumption,
When the cache control unit is accessed from the processor to the cache memory, but the data required by the processor is not stored in the cache memory, the cache control unit performs the next access from the processor to the cache memory. A cache system that executes in the second mode. Cache memory,
A cache control unit for controlling the cache memory;
A processor accessible to the cache memory via the cache control unit,
Regarding the access from the processor to the cache memory, the cache control unit can switch to each other at a first speed and a first mode that is accessed at a first power consumption, and is faster than the first speed. And a second mode for accessing at a second speed and a second power consumption higher than the first power consumption,
The cache control unit has a first access period in which access is made in the first mode because an access request in the second mode is generated following an access request in the first mode. A cache system that changes access in the second access period to the first mode when a second access period for accessing a part of the second access period overlaps in part in the second mode.

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