JP4119907B2 - 2-layer wiring board - Google Patents

Description

  The present invention relates to a two-layer wiring board having a wiring pattern on both surfaces of an insulating substrate such as a two-layer wiring TAB tape, and in particular, improves the reliability of a connection without causing a decrease in productivity due to a complicated configuration. It is related with the made two-layer wiring board.

  Two-layer wiring TAB (Tape Automated Bonding) for TCP (Tape Carrier Package) as a two-layer wiring board in which wiring patterns are formed on both sides of an insulating substrate and the wiring patterns on both sides are connected through through holes or via holes There is a tape.

  FIG. 6 shows a conventional two-layer wiring TAB tape for TCP. This two-layer wiring TAB tape includes a polyimide tape 1 having device holes 1A and blind via holes 1B, a signal wiring pattern 2A made of Cu foil formed on one surface of the polyimide tape 1, A power / ground wiring pattern 3A made of Cu foil formed on the surface, and a Cu vapor deposition layer 3B formed in the blind via hole 1B and electrically connecting the signal wiring pattern 2A and the power / ground wiring pattern 3A, The solder resist 4 is applied to a predetermined region of the signal wiring pattern 2A, and protects and insulates between the patterns, and the IC chip 6 is connected to the inner lead of the signal wiring pattern 2A via the bump 5 A semiconductor device is used.

  FIG. 7 shows the connection structure of the two-layer wiring through the blind via hole 1B. The signal wiring pattern 2A and the power / ground wiring pattern 3A are formed on the inner wall of the blind via hole 1B by vapor deposition together with the power / ground wiring pattern 3A. The Cu vapor deposition layer 3B is connected. This Cu vapor deposition layer 3B is formed by vapor-depositing Cu having a thickness of 3 μm on a Ni or Cr base metal having a thickness of 500 mm.

  On the other hand, there is one in which wiring patterns on both surfaces of a two-layer wiring board are connected by forming a Cu plating layer on the inner wall of a blind via hole. 8 (a) to 8 (d) show a method for forming a Cu plating layer, which penetrates the insulating substrate 7 and the wiring pattern 9 on one surface thereof and is formed on the back surface of the wiring pattern 8 on the other surface of the insulating substrate 7. The carbon black 10 is adsorbed on the inner wall of the reaching blind via hole 7A and its vicinity, the carbon black 10 other than the inner wall of the blind via hole 7A is removed by microetching, and finally the electroplating is performed on the carbon black 10 in the blind via hole 7A. By doing this, the Cu plating layer 11 is formed.

9 (a) to 9 (d) show other methods for forming a Cu plating layer. The wiring pattern on the other surface of the insulating substrate 7 passes through the insulating substrate 7 and the wiring pattern 9 on one surface thereof. A MnO ₂ layer 12 is formed on the inner wall of the blind via hole 7A reaching the back surface of the substrate 8 by permanganese hydrochloric acid treatment, and the MnO ₂ layer 12 and a pyrrole dielectric monomer are oxidatively polymerized under acidic conditions to form a conductive polymer 13. Finally, the Cu plating layer 11 is formed by performing electroplating on the conductive polymer 13 in the through hole 7A.

  However, in the above-described two-layer wiring board in which the two-layer wiring is connected by the Cu vapor-deposited layer formed in the blind via hole, the productivity is lowered unless an expensive apparatus for continuously vapor-depositing with a coil is used. There is a problem, and in the case where two-layer wiring is connected by the Cu plating layer formed in the blind via hole, the conductive film must be formed on the inner wall of the blind via hole before Cu plating, so the structure is complicated and produced. There is a problem that the performance is lowered.

  Therefore, the present applicant has proposed a two-layer wiring board for solving such a problem as shown in FIG. This two-layer wiring board performs an electrical Cu plating process by stacking with a separately provided anode 14 and a cathode using a signal wiring pattern 2A on a TCP two-layer wiring TAB tape, thereby forming a blind via hole. A Cu plating layer 15 is grown in 1B to connect the signal wiring pattern 2A and the power / ground wiring pattern 3A (quoting numerals are the same as those in FIG. 7).

  However, according to the proposed two-layer wiring board, the blind via hole has a dead end, and therefore the flow of the Cu plating solution is bad, and the Cu plating solution does not enter the bottom of the blind via hole, as shown in FIG. Entrainment of bubbles 16 occurs. For this reason, it becomes difficult to make Cu plating securely adhere to the inner wall of the blind via hole and stack it, and there is a risk of poor conduction.

  Accordingly, an object of the present invention is to provide a two-layer wiring board capable of improving the reliability of a connection portion without causing a reduction in productivity due to a complicated configuration.

In view of the above problems, the present invention provides first and second wiring patterns formed on the first and second surfaces of the insulating substrate, and a blind formed on the insulating substrate and the second wiring pattern. and via-hole, opens into the blind via hole, the by the said having a diameter smaller than the diameter of the blind via hole first through holes formed in the wiring pattern, the plating solution flowing through the said through hole and in said blind via hole The present invention provides a two-layer wiring board having an electroplating layer formed by closing a through hole and the blind via hole and connecting the first and second wiring patterns.

  As described above, according to the two-layer wiring board of the present invention, it is possible to improve the reliability of the connection portion without causing a decrease in productivity due to the complicated configuration.

Embodiment of the present invention
Hereinafter, a two-layer wiring board of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings.

  FIG. 1 shows a two-layer wiring TAB tape for TCP as a first embodiment of the present invention. This two-layer wiring TAB tape includes a polyimide tape 1 having device holes 1A and blind via holes 1B, a signal wiring pattern 2A made of Cu foil formed on one surface of the polyimide tape 1, A power / ground wiring pattern 3A made of Cu foil formed on the surface, and a Cu plating layer 15 formed in the blind via hole 1B and electrically connecting the signal wiring pattern 2A and the power / ground wiring pattern 3A; Solder resists 4A and 4B which are applied to predetermined regions of the signal wiring pattern 2A and the power / ground wiring pattern 3A and protect and insulate between the patterns, and the signal wiring pattern 2A which is the bottom of the blind via hole 1B. Of the signal wiring pattern 2A Is a semiconductor device by connecting the IC chip 6 via the bumps 5 to over de.

  The polyimide tape 1 has a thickness of 20 to 75 μm, and the blind via hole 1B has a diameter of 30 to 500 μm.

  The signal wiring pattern 2A and the power / ground wiring pattern 3A have a thickness of 2 to 25 μm or less and a pitch between wirings of 100 μm or less, and the through hole 17 has a diameter of 20 μm or more.

FIG. 2 shows the blind via 1B of the two-layer wiring TAB tape, in which a through hole 17 is formed in the signal wiring pattern 2A constituting the bottom of the blind via hole 1B, and the signal wiring pattern 2A and the power / ground wiring pattern 3A is connected by a Cu plating layer 15 grown in the blind via hole 1B by electric Cu plating by a method of stacking using the signal wiring pattern 2A as a cathode. Cu electroplating, for example, using a gloss Cu and matte Cu shown in Table 1, carried out at 3A / dm 2 higher current density.

  In the above configuration, when a two-layer wiring TAB tape is manufactured, first, as shown in FIG. 3A, a Cu foil having a thickness of 25 μm or less is formed on one surface of a polyimide tape 1 having a thickness of 20 to 75 μm. A two-layer CCL (Copper Clad Laminate) material having 2 is prepared, and a Cu foil 3 having a thickness of 25 μm or less is laminated on the surface of the polyimide tape 1 opposite to the Cu foil 2.

  Next, as shown in FIG. 3B, a hole 3C having a predetermined area is formed at the device hole forming position of the Cu foil 3, and a hole 3D having a diameter of 30 to 500 μm is formed at the blind via hole forming position. It is formed by etching.

Subsequently, as shown in FIG. 3C, a through hole 17 having a diameter of 20 μm or more is formed at a position that becomes the bottom of the blind via hole of the Cu foil 2.

  Further, as shown in FIG. 3D, laser processing is performed on portions exposed from the holes 3C and 3D of the polyimide tape 1 using the Cu foil 3 as a mask to form device holes 1A and blind via holes 1B.

  Thereafter, as shown in FIG. 3E, a solder resist 4B is applied to a predetermined region of the Cu foil 3 so as to leave a predetermined region around the blind via hole 1B.

  Then, as shown in FIG. 4 (a), an electrical Cu plating process is performed in a Cu plating solution in which the anode 14 is disposed, and the Cu foil 2 is used as a cathode to perform Cu plating in the blind via hole 1B. The layer 15 is grown and the Cu foil 2 and the Cu foil 3 are connected.

  Finally, as shown in FIG. 4 (b), the Cu foils 2 and 3 are subjected to photo application and etching to form a signal wiring pattern 2A having a pitch between wirings of 100 μm or less, and a power / ground wiring pattern 3A. After forming each, as shown in FIG. 1, a solder resist 4A is applied to a predetermined region on the signal wiring pattern 2A.

  According to such a two-layer wiring TAB tape, since the through hole 17 is formed at the bottom of the blind via hole 1B, the flow of the Cu plating solution in the blind via hole 1B in the electric Cu plating process is good, and the inner wall of the blind via hole 1B Cu plating is surely stacked. For this reason, the reliability of a connection part can be improved, without causing the productivity fall by complication of a structure.

In the first embodiment, the reason why the thickness of the Cu foils 2 and 3 is 25 μm or less is that the pitch between the wiring patterns can be etched up to 80 μm, and the thickness of the Cu foil can be etched up to 35 μm. This is because if the pitch is set to 80 μm or less, the Cu foils 2 and 3 cannot be etched unless the thickness is 25 μm or less. Further, the reason for setting the thickness of the polyimide tape 1 to 20 to 75 μm is that the thickness is preferably 75 μm or less for the limitation of the polyimide casting method, and the minimum is 20 μm to ensure the electrical insulation and the strength of the tape conveyance. This is because thickness is required. Further, the reason for setting the diameter of the blind via hole 1B to 30 to 500 μm is to cope with the miniaturization of the wiring pattern. Furthermore, the reason why the electric Cu plating is performed at a current density higher than 3 A / dm 2 is to ensure the electrical connection between the signal wiring pattern 2 A and the power / ground wiring pattern 3 A. That is, when the current density is larger than 3 A / dm 2 , the inner wall of the blind via hole 1B is in an unprocessed state, that is, the signal wiring pattern 2A and the power / ground wiring pattern 3A are formed without forming a conductive film. Cu plating can be grown. Furthermore, the reason why the diameter of the through-hole 17 is 20 μm or more is that the effect of improving the flow of the Cu plating solution cannot be obtained unless it is more than this.

  FIG. 5 shows a two-layer wiring TAB tape according to the second embodiment of the present invention. In this two-layer wiring TAB tape, a through hole 17 is formed in the signal wiring pattern 2A constituting the bottom of the blind via hole 1B, and the signal wiring pattern 2A and the power / ground wiring pattern 3A are electroplated on the blind via hole 1B. Are connected by a Cu plating layer 15 grown by the above method. There is no device hole in the polyimide tape 1, and an IC chip is mounted on the signal wiring pattern 2A via bumps 6. In such a two-layer wiring TAB tape, the same effect as that of the first embodiment can be obtained, and since there is no device hole, the configuration can be simplified.

  In the above embodiment, a Cu adhesive material in which a Cu foil is provided on a polyimide tape without using an adhesive is used. However, a material with an adhesive may be used.

An inner lead of a 18 μm thick Cu foil provided with a 25 μm thick Cu foil on the other side of the polyimide tape of a two-layer CCL material in which a 18 μm thick Cu foil was provided on one side of a 50 μm thick polyimide tape 64 holes each having a diameter of 30 μm were formed in the blind via hole forming positions on the side and the input lead side, and 6 mm square holes were formed in the device hole forming positions by photo application and etching, respectively. Next, 64 holes each having a diameter of 20 μm were formed by photo application and etching at the positions corresponding to the bottoms of the blind via holes on the inner lead side and the input lead side of the 25 μm thick Cu foil. Furthermore, laser processing was performed using a 18 μm thick Cu foil as a mask, and 64 blind via holes each having a diameter of 30 μm were formed on the inner lead side and the input lead side of the polyimide tape, and a 6 mm square device hole was formed in the center. . Then, a solder resist was applied with a thickness of 15 μm, leaving a peripheral diameter of 130 μm of the blind via hole. Next, using a Cu foil having a thickness of 25 μm as a cathode, electro Cu plating was performed at a current density of 3 A / dm 2 by a method of stacking using glossy Cu, and a 7 μm Cu plating layer was grown in the blind via hole. The Cu foil was made conductive. Thereafter, a signal wiring layer having an inner lead and an input lead with a wiring pitch of 80 μm from a 25 μm thick Cu foil, and a square power source / ground layer from a 18 μm thick Cu foil by photo application and etching, respectively. Created. Finally, a solder resist was applied to a predetermined region on the signal wiring layer with a thickness of 15 μm.

  Here, in order to evaluate the reliability of the conductive portion of the two-layer wiring, a temperature cycle test with one cycle of −55 ° C. × 30 minutes and 150 ° C. × 30 minutes was performed for 1000 cycles, and the change in conduction resistance was measured. When measured every 200, 500, and 1000 cycles, it was found that there was no increase in resistance, and the reliability due to thermal stress of the conductive portion of the two-layer wiring, that is, the Cu plating layer was obtained. In addition, when a migration test was performed for 1000 hours at 85 ° C. and 85% humidity and a DC bias of 50 V, there was no conduction breakdown of the conductive layer of the two-layer wiring, that is, Cu plating layer, and no dielectric breakdown of the two-layer wiring layer. I found out.

A hole with a diameter of 50 μm is formed at the position where a blind via hole is formed on the inner lead side and the input lead side of one Cu foil of a three-layer CCL material in which a 18 μm thick Cu foil is laminated on both sides of a polyimide tape of 50 μm thickness. 64 pieces were formed by etching. Next, 64 holes each having a diameter of 30 μm were formed by photo application and etching at the bottoms of the blind via holes on the inner lead side and the input lead side of the other Cu foil. Further, laser processing was performed using a Cu foil layer having a hole with a diameter of 50 μm as a mask to form 64 blind via holes with a diameter of 50 μm on the inner lead side and the input lead side of the polyimide tape. Then, from Cu foil having a hole with a diameter of 30 μm, a signal wiring layer having an inner lead and an input lead with an inter-wiring pitch of 80 μm, and from the Cu foil having a hole with a diameter of 50 μm to a rectangular power supply / ground layer, respectively. And created by etching. Next, a solder resist was applied with a thickness of 15 μm, leaving a peripheral diameter of 130 μm of the blind via hole. Further, a solder resist was applied at a thickness of 15 μm in addition to the flip chip-connected lead on the signal wiring layer. Finally, electric Cu plating was performed at a current density of 3 A / dm 2 by a method of stacking using bright Cu plating, a 7 μm Cu plating layer was grown in the blind via hole, and the two-layer wiring was made conductive.

  Here, in order to evaluate the reliability of the conductive portion of the two-layer wiring, a temperature cycle test with one cycle of −55 ° C. × 30 minutes and 150 ° C. × 30 minutes was performed for 1000 cycles, and the change in conduction resistance was measured. When measured every 200, 500, and 1000 cycles, it was found that there was no increase in resistance, and the reliability due to thermal stress of the conductive portion of the two-layer wiring, that is, the Cu plating layer was obtained. In addition, when a migration test was performed for 1000 hours at 85 ° C. and 85% humidity and a DC bias of 50 V, there was no conduction breakdown of the conductive layer of the two-layer wiring, that is, Cu plating layer, and no dielectric breakdown of the two-layer wiring layer. I found out.

Sectional drawing which shows the 1st Embodiment of this invention. Sectional drawing of the blind via hole in 1st Embodiment. Sectional drawing which shows the manufacturing process in 1st Embodiment. Sectional drawing which shows the manufacturing process in 1st Embodiment. Sectional drawing which shows the 2nd Embodiment of this invention. Sectional drawing which shows the conventional 2 layer wiring TAB tape. Sectional drawing of the blind via hole in the conventional two-layer wiring TAB tape. Sectional drawing which shows the conduction structure of the 2 layer wiring of the conventional 2 layer wiring board. Sectional drawing which shows the conduction structure of the 2 layer wiring of the conventional 2 layer wiring board. Sectional drawing which shows the conduction | electrical_connection structure of the two-layer wiring of the proposed two-layer wiring board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Polyimide tape 1A Device hole 1B Blind via hole 2 Cu foil 2A Signal wiring pattern 3 Cu foil 3A Power supply / ground wiring pattern 3B Cu vapor deposition layer 3C, 3D Hole 4, 4A, 4B Solder resist 5 Bump 6 IC chip 7 Insulation Substrate 8, 9 Wiring pattern 10 Carbon black 11 Cu plating layer 12 MnO ₂ layer 13 Conductive polymer 14 Anode 15 Cu plating layer 16 Air bubble 17 Through hole

Claims (1)

First and second wiring patterns formed on the first and second surfaces of the insulating substrate;
Blind via holes formed in the insulating substrate and the second wiring pattern;
A through hole formed in the first wiring pattern having a diameter smaller than the diameter of the blind via hole, leading to the blind via hole;
The formed by the through-hole and the plating solution flowing through the said blind via hole plugging the through hole and the blind via hole, and characterized in that it has an electroplated layer for connecting said first and second wiring patterns 2-layer wiring board.

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