JP4114988B2 - Data processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data processing apparatus and a system construction method suitable for application to an image processing apparatus such as a copying machine, a printer, and a facsimile. Specifically, a three-way interface unit is connected to a data memory and a data bus divided into two, and an external device connected to one data bus transfers data to and from the data memory. When writing / reading, the other data bus can be opened to other external devices, and the memory for data can be shared in time series or simultaneously by the external devices connected to each data bus. It is a thing.
[0002]
[Prior art]
In recent years, digital copying machines that perform image formation based on image data acquired from a document image have been used. In this type of copying machine, image information of an original is read by a scanner or the like, and the image information of the original is temporarily stored in an image memory. The image information stored in the image memory is subjected to image processing such as image reduction, enlargement, and rotation in response to a user request. As a result, the image of the original can be copied onto a predetermined transfer sheet based on the image data subjected to the image processing.
[0003]
By the way, in this type of digital copying machine, a large-capacity memory is provided to temporarily store image information of a document, and a technique for efficiently transferring the image information is required.
[0004]
FIG. 7 is a block diagram showing a configuration example of a conventional image forming apparatus 500 using this type of image memory. The image forming apparatus 500 has a CPU bus 1 shown in FIG. Connected to the CPU bus 1 are a system control means 2, an image memory 3, a direct memory access controller (hereinafter simply referred to as DMAC) 4, an image acquisition means 5 and an image reproduction means 6.
[0005]
The system control means 2 connected to the CPU bus 1 has a CPU 2a, a ROM 2b, a RAM 2c, and an operation unit 2d. The CPU 2a is an IC that performs overall control of the image forming apparatus 500, and the control program is stored in the ROM 2b. The RAM 2c is a memory that is temporarily used when the CPU 2a performs calculations, and is necessary for execution of the control program.
[0006]
For example, when a control command such as a start instruction is output to the image acquisition unit 5 or the image playback unit 6, the control command is written in the RAM 2c by the CPU 2a, and then there is a notification of completion of writing of image data. It is verified whether it is for a control command.
[0007]
The operation unit 2d is necessary for an interface between the user and the apparatus, and the CPU 2a executes predetermined data processing according to this instruction. The image memory 3 connected to the CPU bus 1 is a relatively large memory having a capacity for a plurality of pages, and the code data is also accumulated by performing an encoding process (not shown). The DMAC 4 performs data transfer between devices without the intervention of the CPU 2a, and can perform data transfer at a higher speed than the CPU 2a.
[0008]
The image acquisition means 5 connected to the CPU bus 1 includes a scanner interface 5a, a scanner unit 5b, and a page memory 5c. The scanner interface 5a performs drive control of the scanner unit 5b and image data (DATA) writing / reading control in the page memory 5c. The page memory 5c is a memory for storing one page of image data from the scanner unit 5b, and is necessary for matching the data transfer speed between the scanner unit 5b and the CPU 2a and improving the use efficiency of the CPU bus 1.
[0009]
Further, the image reproducing means 6 connected to the CPU bus 1 has a printer interface 6a, a page memory 6b, and a printer unit 6c. The printer interface 6a performs drive control of the printer unit 6c and image data write / read control in the page memory 6b. The page memory 6b is a memory for storing data to be written to the printer unit 6c for one page, and is necessary for matching the data transfer speed between the printer 6c and the CPU 2a and improving the use efficiency of the CPU bus 1.
[0010]
Next, the operation of the image forming apparatus 500 will be described. First, a copy operation for a single document will be described. First, when a one-page copy instruction is received from the operation unit 2d, the CPU 2a instructs the image acquisition unit 5 to drive the scanner. In response to this instruction, the scanner interface 5a drives the scanner unit 5b, acquires image data of the original from the scanner unit 5b, and sequentially stores the image data in the page memory 5c. When the image data for one page is stored in the page memory 5c, the scanner interface 5a notifies the CPU 2a of the end of reading the image data.
[0011]
Upon receiving this notification, the CPU 2a instructs the DMAC 4 to transfer image data from the scanner interface 5a to the printer interface 6a. Then, one page of image data is transferred from the scanner page memory 5c to the printer page memory 6b. When the transfer of the image data for one page is completed, the DMAC 4 notifies the CPU 2a of the transfer end. Upon receiving this notification, the CPU 2a instructs the image reproducing means 6 to drive the printer. Upon receiving this instruction, the printer interface 6a reads the image data from the page memory 6b and outputs the image data to the printer unit 6c. The printer unit 6c can copy an image of a document on transfer paper or the like based on one page of image data.
[0012]
Next, the operation when a plurality of copies of a plurality of documents are copied will be described. First, the CPU 2a receiving the instruction from the operation unit 2d instructs the image acquisition means 5 to drive the scanner. In response to this instruction, when one page of image data acquired by the scanner unit 5b is stored in the page memory 5c, the scanner interface 5a stores the image data for one page from the scanner interface 5a to the CPU 2a. The end of reading is notified. Upon receiving this notification, the CPU 2a instructs the DMAC 4 to transfer data, so that the image data stored in the page memory 5c is transferred to the image memory 3.
[0013]
This series of operations is repeated for the number of documents, and all image data is stored in the image memory 3. Thereafter, the stored image data is transferred to the printer interface 6a in accordance with an instruction from the CPU 2a. At this time, when image data for one page is stored from the image memory 3 to the printer page memory 6d by the DMAC 4, the CPU 2a instructs the printer interface 6a to start the printer.
[0014]
When one page of image data is output to the printer unit 6c by the printer interface 6a receiving this instruction, the CPU 2a is notified of the end of printing. Upon receiving this notification, the CPU 2a instructs the DMAC 4 to transfer the image data of the next page, and the printing is started.
[0015]
Since this series of operations is repeated for the number of documents, the first copy is completed. In this example, since the CPU 2a is instructed to copy a plurality of copies, the DMAC 4 is instructed to transfer the image data of the first page from the image memory 3 to the printer interface 6a again. Thereafter, a plurality of copies can be made by repeating the same operation for the set number of copies.
[0016]
[Problems to be solved by the invention]
By the way, according to the conventional image forming apparatus 10, there is a demand for a data processing apparatus in which a printer and a facsimile function are combined with a copying function by adding a communication means to this apparatus. In response to this request, the image memory 3 must be used efficiently in order to perform so-called memory communication or broadcast communication. However, in the conventional system, the image memory 3, DMCA 4, image acquisition means 5 and image reproduction means 6 are connected to one CPU bus 1, and page memories 5 c and 6 b are connected to each means 5 and 6. Yes.
[0017]
Accordingly, since the scanner and printer page memories 5c and 6b are not used except during the operation of the scanner unit 5c and the printer unit 6c, there is a problem in system construction that the memory use efficiency is deteriorated. Incidentally, the page memories 5c and 6b have a capacity capable of recording image data of the largest document size (for example, A3 size). As a result, when a document smaller than the A3 size is copied, a memory area that is not used is generated, and the memory use efficiency is lowered.
[0018]
Also, when a plurality of originals are copied, that is, when a plurality of copies are simultaneously made while printing out the original of the first page after reading one page of image data, the DMAC 4 is used for the scanner. Image data must be transferred from the page memory 5c to both the image memory 3 and the printer page memory 6b. Therefore, the image data must be transferred twice, which is about twice the data transfer time for a single document.
[0019]
Furthermore, since the transfer speed of the DMAC 4 connected to the CPU bus 1 changes depending on the bus occupancy rate of the CPU 2a, the image data of the next page may be overwritten by the DMAC 4 on the image data of the previous page. This is because the image data of the next page is transferred before all the image data for one page is transferred from the page memory 5a to the image memory 3 when the transfer speed of the DMAC 4 decreases due to the change in the bus occupation ratio of the CPU 2a. Occurs when the loading of starts.
[0020]
Similarly, if the printer is instructed before the image data for one page is stored in the page memory 6b, an underflow of the image data may occur and the upper part of the document may not be copied. In order to avoid such a state, if the CPU bus 1 is exclusively used by the DMAC (hereinafter also referred to as an external device) 4 in preference to the CPU 2a, the processing speed of the CPU 2a is reduced, or the CPU bus (hereinafter also referred to as the data bus). There is a problem that it is difficult to cause the CPU (hereinafter also referred to as an external device) 2a to execute a fax process using the 1 or image memory (hereinafter also referred to as a data memory) 3 or the like.
[0021]
Therefore, the present invention solves the above-described problem, and even when one external device occupies a data bus, the other external device uses the other data bus to execute other data processing. It is an object of the present invention to provide a data processing apparatus and a system construction method that enable data memory to be shared in time series by external devices connected to each data bus.
[0022]
[Means for Solving the Problems]
  In order to solve the above problems, a data processing device according to the present invention provides:imageMemory,A first data bus, a second data bus, and the imageMemory andSaidRead / write data to / from the first data busShi,The imageMemory andSaidRead / write data to / from the second data busShi,as well as,SaidWith the first data busSaidA three-way interface means for transferring data to and from the second data bus,SaidThe three-way interface meansA bidirectional first interface unit connected to the first data bus for inputting / outputting data and a bidirectional second interface unit connected to the second data bus for inputting / outputting data An internal data bus connected between the first and second interface units, a branch data bus branched from the internal data bus, and data between the image memory connected to the branch data bus Memory control means for controlling writing / reading of data, and a first FIFO memory provided between the first interface section and the memory control means for temporarily storing data input from the first interface section; , Provided between the memory control means and the second interface unit, for temporarily storing data input from the second interface unit. FIFO memory, a third FIFO memory for temporarily storing data to be written controlled by the memory control means, a fourth FIFO memory for temporarily storing data to be read controlled by the memory control means, and the first A control memory for temporarily recording a control command for input / output control of the interface unit, the second interface unit, the internal data bus, and the memory control means, and the control command recorded in the control memory Based on the first, second, third and fourth FIFO memories, and controls the image memory toA first data bus andSaidInput / output control of the second data bus in time seriesBecomeIt is characterized by that.
[0023]
According to the data processing device of the present invention, data transfer control can be performed by dividing one data bus into two. For example, an external device connected to the first data bus is connected to a data memory. Data read / write between the second data bus and the data memory, the same data read from the data memory is stopped. Or transfer to the second data bus.
[0024]
  Therefore, when the external device connected to the first data bus is writing data to and reading data from the data memory, the second data bus can be opened to other external devices. . In addition, the data memory can be shared in time series or simultaneously between the external device connected to the first data bus and the external device connected to the second data bus.In addition, it is possible to construct a data processing system that does not place an excessive control burden on the host control device.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, a data processing device as an embodiment of the present invention will be described with reference to the drawings.In placeExplain about it.
[0028]
(1) Configuration example of interface device
FIG. 1 is a diagram showing a configuration example of an interface apparatus applied to the data processing apparatus as this embodiment.
[0029]
In this embodiment, a three-way interface means is connected to a data memory and a data bus divided into two, and an external device connected to one data bus is connected to the data memory. When data is being read and written, the other data bus can be opened to other external devices, and the memory for data can be opened in time series or simultaneously by the external device connected to each data bus. It can be shared.
[0030]
  The interface device 100 is used by being connected between the first data bus 11 and the second data bus 12 shown in FIG. A bidirectional first interface unit 13 is connected to the data bus 11, and data is input to and output from the data bus 11. The output stage to the inside of the interface unit 13 is the first for data.FThe IFO memory 14a is connected, and data input from the data bus 11 is temporarily recorded. The FIFO memory 14a is necessary for matching the data transfer rate between the two data buses. The data from the FIFO memory 14a is output first from the first input.
[0031]
A second interface unit 16 is connected to the output stage of the FIFO memory 14a via an internal data bus 15a. A data bus 12 is connected to an output stage to the outside of the interface unit 16, and data from the data bus 11 is output to the data bus 12.
[0032]
  Further, the output stage to the inside of the interface unit 16 has a second for data.FThe IFO memory 14b is connected, and data input from the data bus 12 is temporarily recorded for the reason described above. This data is output first from the first input. An interface unit 13 is connected to the output stage of the FIFO memory 14b via an internal data bus 15b. A data bus 11 is connected to an output stage to the outside of the interface unit 13, and data from the data bus 12 is output to the data bus 11.
[0033]
Further, a control memory 17 is connected between the two interface units 13 and 16 described above. For example, when a data processing system including the interface device 100 is constructed, control from a control device or the like at the higher level of the system is performed. Instruction D1 is temporarily recorded. In this example, the control memory 17 has a command register 17a and a status register 17b. The control instruction D1 is recorded in the command register 17a.
[0034]
As a method for accessing the interface device 100, a method using a uniquely selected chip select signal, a method using an address decoding method, or the like can be considered. In the address decoding method, an address Add mapped in advance in a ROM or the like is driven on the data bus 11 by a control device or the like when accessed. This is a method of accepting access by decoding the address in the interface device 100 by setting the address register in the interface device 100. In the following description, the latter case is assumed.
[0035]
For example, the interface control unit 18 is provided in the interface unit 13 or the interface unit 16, and the data write / read control of the FIFO memories 14a and 14b is performed based on the control instruction D1 recorded in the command register 17a. The inputs and outputs of the units 13 and 16 and the internal data buses 15a and 15b are controlled.
[0036]
The interface control unit 18 is provided with an address register 18a, a decoder 18b, a timing generation circuit 18c and the like shown in FIG. An address addressed to the interface device 100 is set in the address register 18a when accessed. Whether the access is to the interface apparatus 100 is determined by the address being decoded by the decoder 18b. The decoder 18b is also used for decoding the control instruction D1. Based on the decoding result of the control instruction D1, the timing generation circuit 18c generates switch control signals S1 to S4.
[0037]
The switch control signal S1 is used for bus switching of the interface unit 13, and the switch control signal S2 is used for bus switching of the interface unit 16. The memory control signal S3 is used for writing / reading of the FIFO memory 14a, and the memory control signal S4 is used for writing / reading of the FIFO memory 14b.
[0038]
Control notification information is temporarily recorded in the status register 17b. This control notification information is like the end status data D2 indicating the data transfer result executed with respect to the control command D1, and the control device or the like of the system receives the end status data D2 so that the interface is first connected. It can be determined whether or not the data processing for the control instruction D1 given to the device 100 is completed.
[0039]
Next, the operation of the interface device 100 will be described with reference to FIG. In this example, when data is transferred between the data buses 11 and 12, the control instruction D1 is written to the command register 17a.
[0040]
For example, when data is transferred from the data bus 11 to the data bus 12, a control instruction D1 to that effect is written to the command register 17a. When the control command D1 is received by the interface control unit 18, the control command D1 is decoded by the interface control unit 18, and the data bus 11 is transferred to the internal data in the interface unit 13 based on the switch control signal S1 as a result of the decoding. The interface unit 16 is connected to the bus 15a, and the internal data bus 15a is connected to the data bus 12 based on the switch control signal S2.
[0041]
The data input from the data bus 11 is temporarily recorded in the FIFO memory 14a based on the memory control signal S3. This is because the data transfer speed on the data bus 11 and the data transfer speed on the data bus 12 are matched. The data first recorded in the FIFO memory 14a is read based on the memory control signal S3 in order, and is output to the data bus 12 through the interface unit 16.
[0042]
When data is transferred from the data bus 12 to the data bus 11, a control instruction D1 to that effect is written to the command register 17a. When the control command D1 is received by the interface control unit 18, the data bus 11 is connected to the internal data bus 15b in the interface unit 13 based on the switch control signal S1 decoded by the interface control unit 18, and the interface unit 16 The internal data bus 15b is connected to the data bus 12 based on the switch control signal S2.
[0043]
The data input from the data bus 12 is temporarily recorded in the FIFO memory 14b based on the memory control signal S4, and the data transfer rates of the data buses 11 and 12 are matched. The data recorded first in the FIFO memory 14b is read based on the memory control signal S4 in order, and is output to the data bus 11 through the interface unit 13.
[0044]
When this data transfer ends, the end status data D2 is written in the status register 17b. The status register 17b is not only written with the end status data D2 of the interface device 100 itself, but also a data processing system is constructed by arranging a large number of this type of interface device 100 at nodes and nodes that divide the data bus. In this case, the end status data D2 from the other interface device 100 is also recorded.
[0045]
In this way, by confirming the recorded contents of the status register 17b of the interface device 100 arranged at the closest position to the control device of the system, the control given to the interface device 100 close to the terminal device in the data processing system. It is possible to easily determine whether the data processing for the instruction D1 is completed.
[0046]
As described above, according to the interface device 100 according to the present embodiment, after the control instruction D1 is once written in the command register 17a, the interface units 13 and 16 and the internal data bus 15a are based on the control instruction D1. 15b input / output control and FIFO memory 14a, 14b write / read control, so that data can be transferred between the data buses 11 and 12 independently of the control device of the host system connected to the interface device 100. can do.
[0047]
Therefore, after writing the control command D1, the control device itself does not have to manage the input / output of the interface device 100, so the data processing burden on the control device can be reduced.
[0048]
In this embodiment, the end status data D2 indicating the data transfer result executed with respect to the control instruction D1 is temporarily recorded in the status register 17b. Therefore, by reading the data D2 from the command register 17b, the control instruction D1 It is possible to easily confirm the data transfer result executed for. Therefore, data processing by handshake can be performed between the control device and the interface device 100, and data processing by handshaking can be performed between the plurality of interface devices 100.
[0049]
Next, the three-way interface device 200 according to this embodiment will be described. FIG. 3 is a block diagram showing a configuration example of the three-way interface device 200 according to the present embodiment.
[0050]
In this embodiment, a branch data bus branched from the internal data buses 15a and 15b is connected, a memory control means is connected to the branch data bus, and data input / output by the interface units 13 and 16 is based on the control instruction D1. Thus, read / write control is performed. In addition, since the same code | symbol and the same name as the interface apparatus 100 have the same function, the description is abbreviate | omitted.
[0051]
The three-way interface device 200 is provided with an internal bus selector 21 shown in FIG. The internal bus selector 21 has a switch circuit 21a for selecting two circuits 1 and single switch circuits 21b and 21c shown in FIG. Of course, these switch circuits 21a to 21c may use transistor circuits integrated by field effect transistors or bipolar transistors.
[0052]
  The point a of the switch circuit 21a is connected to the internal data bus 15a of the output stage of the FIFO memory 14a, and the point b is connected to the internal data bus 15b of the output stage of the FIFO memory 14b. The neutral point n of the switch circuit 21a is connected to a memory bus 22a for writing as a branch data bus. The memory bus 22a has a third data bus.FConnected to the IFO memory 23a, the write data branched from the internal data bus 15a or 15b is temporarily stored. The memory control means 24 is connected to the output stage of the FIFO memory 23a, and data read / write control from the internal data bus 15a or 15b is performed. A data memory such as the image memory 3 is connected to the output stage of the memory control means 24 to the outside.
[0053]
  Also, the output stage to the inside of the memory control means 244thA FIFO memory 23b is connected to temporarily store read data for output to the internal data bus 15a or 15b. A memory bus 22b for reading is connected to the output stage of the FIFO memory 23b. The memory bus 22b is connected to a contact n of the switch circuits 21b and 21c. The point a of the switch circuit 21b is connected to the input stage of the interface unit 16 through the internal data bus 15a, and the point b of the switch circuit 21c is connected to the input stage of the interface unit 13 through the internal data bus 15b.
[0054]
An interface control unit 28 is provided in place of the interface control unit 18 in the interface unit 13 or the interface unit 16 described above. The interface control unit 28 includes an address register 28a, a decoder 28b, and a timing generation circuit 28c, and these functions are substantially the same as those of the address register 18a, the decoder 18b, and the timing generation circuit 18c of the interface control unit 18. In the interface control unit 28, the data write / read control of the FIFO memories 14a, 14b and 23a, 23b, the input of the interface units 13, 16, and the internal data buses 15a, 15b based on the control instruction D1 recorded in the command register 17a. Output control, switch control of the switch circuits 21a to 21c, and the like are performed.
[0055]
The interface control unit 28 decodes the control command D1 and generates the switch control signals S1 to S4 in the same manner as the interface control unit 18, and also uses the timing generation circuit 28c to switch the switch control signal used for switching the bus of the switch circuit 21a. S5, a switch control signal S6 used for switching the bus of the switch circuit 21b, a memory control signal S7 used for writing / reading of the FIFO memory 23a, and a memory control signal S8 used for writing / reading of the FIFO memory 23b A switch control signal S9 used for short-circuiting the bus of the switch circuit 21c is generated.
[0056]
Next, the operation of the interface apparatus 200 will be described with reference to FIG. In this example, the control instruction D1 relating to the following nine data transfer events is written in the command register 17a. This data transfer event is
(1) When transferring data from the data bus 11 to the data bus 12 (data through),
(2) When writing data from the data bus 11 to the image memory 3,
(3) When writing the data from the data bus 11 to the image memory 3 and simultaneously transferring the same data to the data bus 12,
(4) When transferring data from the data bus 12 to the data bus 11 (data through),
(5) When writing data from the data bus 12 to the image memory 3,
(6) When writing the data from the data bus 12 to the image memory 3 and transferring the same data to the data bus 11 at the same time,
(7) When reading data from the image memory 3 to the data bus 11,
(8) When reading data from the image memory 3 to the data bus 12, and
(9) This is a case where the same data is read from the image memory 3 to the data bus 11 and the data bus 12.
[0057]
For example, when the control instruction D1 related to the data transfer event (1) is written in the command register 17a, when the control instruction D1 is received by the interface control unit 28, the control instruction D1 is decoded by the interface control unit 28. The data bus 11 is connected to the internal data bus 15a in the interface unit 13 based on the switch control signal S1 that is the decoding result, and the internal data bus 15a is connected to the data bus 12 in the interface unit 16 based on the switch control signal S2. Connected.
[0058]
In the switch circuit 21a, the memory bus 22a is disconnected from the internal data bus 15a based on the switch control signal S5. Similarly, in the switch circuit 21a, the memory bus 22b is disconnected from the internal data bus 15b based on the switch control signal S6. The data input from the data bus 11 is temporarily recorded in the FIFO memory 14a based on the memory control signal S3. The data first recorded in the FIFO memory 14a is read based on the memory control signal S3 in order, and is output to the data bus 12 through the interface unit 16. As a result, data can be transferred from the data bus 11 to the data bus 12 (data through).
[0059]
When the control instruction D1 related to the data transfer event (2) is written to the command register 17a, the data bus 11 is connected to the internal data bus 15a based on the switch control signal S1 decoded by the interface control unit 28. In the switch circuit 21a, the memory bus 22a and the internal data bus 15a are connected based on the switch control signal S5.
[0060]
The data input from the data bus 11 is temporarily recorded in the FIFO memory 14a based on the memory control signal S3. The first data recorded in the FIFO memory 14a is sequentially recorded in the FIFO memory 23a. The data recorded in the FIFO memory 23a is read based on the memory control signal S7 and written into the image memory 3.
[0061]
At this time, the memory bus 22b remains disconnected from the internal data bus 15b. In this case, the data bus 12 and the internal data buses 15a and 15b may be connected in any way. Thereby, data can be written from the data bus 11 to the image memory 3.
[0062]
Further, when the control instruction D1 related to the data transfer event (3) is written to the command register 17a, the data bus 11 is connected to the internal data bus 15a based on the switch control signal S1 decoded by the interface control unit 28. The internal data bus 15a is connected to the data bus 12 based on the switch control signal S2. In the switch circuit 21a, the memory bus 22a and the internal data bus 15a are connected based on the switch control signal S5.
[0063]
The data input from the data bus 11 is temporarily recorded in the FIFO memory 14a based on the memory control signal S3. The first data recorded in the FIFO memory 14a is sequentially recorded in the FIFO memory 23a. At the same time, the data recorded in the FIFO memory 14 a is output to the data bus 12. The data recorded in the FIFO memory 23a is read based on the memory control signal S7 and written into the image memory 3. Thus, the same data can be transferred to the data bus 12 at the same time as the data is written from the data bus 11 to the image memory 3.
[0064]
When the control instruction D1 related to the data transfer event (4) is written to the command register 17a, the data bus 11 is connected to the internal data bus 15b based on the switch control signal S1 decoded by the interface control unit 28. The internal data bus 15b is connected to the data bus 12 based on the switch control signal S2.
[0065]
In the switch circuit 21a, the memory bus 22a is disconnected from the internal data bus 15a based on the switch control signal S5. Similarly, in the switch circuit 21a, the memory bus 22b is disconnected from the internal data bus 15b based on the switch control signal S6. The data input from the data bus 12 is temporarily recorded in the FIFO memory 14b based on the memory control signal S4. The data recorded first in the FIFO memory 14b are read out in order based on the memory control signal S4, passed through the interface unit 13, and output to the data bus 11. As a result, data can be transferred from the data bus 12 to the data bus 11 (data through).
[0066]
Next, when the control instruction D1 related to the data transfer event (5) is written to the command register 17a, the data bus 12 is connected to the internal data bus 15b based on the switch control signal S2 decoded by the interface control unit 28. In the switch circuit 21a, the memory bus 22a and the internal data bus 15a are connected based on the switch control signal S5.
[0067]
The data input from the data bus 12 is temporarily recorded in the FIFO memory 14b based on the memory control signal S4. The first data recorded in the FIFO memory 14b is recorded in the FIFO memory 23a in order. The data recorded in the FIFO memory 23a is read based on the memory control signal S7 and written into the image memory 3.
[0068]
At this time, the memory bus 22b remains disconnected from the internal data bus 15b. In this case, the data bus 11 and the internal data buses 15a and 15b may be connected in any way. Thereby, data can be written from the data bus 12 to the image memory 3.
[0069]
When the control instruction D1 related to the data transfer event (6) is written to the command register 17a, the data bus 11 is connected to the internal data bus 15b based on the switch control signal S1 decoded by the interface control unit 28, and the switch The internal data bus 15b is connected to the data bus 12 based on the control signal S2. In the switch circuit 21a, the memory bus 22a and the internal data bus 15a are connected based on the switch control signal S5.
[0070]
The data input from the data bus 12 is temporarily recorded in the FIFO memory 14b based on the memory control signal S4. The first data recorded in the FIFO memory 14b is recorded in the FIFO memory 23a in order. At the same time, the data recorded in the FIFO memory 14 b is output to the data bus 11. The data recorded in the FIFO memory 23a is read based on the memory control signal S7 and written into the image memory 3. Thereby, the same data can be transferred to the data bus 11 at the same time as the data is written from the data bus 12 to the image memory 3.
[0071]
When the control instruction D1 related to the data transfer event (7) is written to the command register 17a, the data bus 11 is connected to the internal data bus 15b based on the switch control signal S1 decoded by the interface control unit 28, and the switch In the circuit 21b, the memory bus 22b and the internal data bus 15b are connected based on the switch control signal S6. In this example, the switch circuit 21c is turned on by the switch control signal S9.
[0072]
The data read from the image memory 3 is temporarily recorded in the FIFO memory 23b based on the memory control signal S8. The data first recorded in the FIFO memory 23b is output to the data bus 11 through the interface unit 13 in order. At this time, the memory bus 22a is disconnected from the internal data bus 15b. In this case, the internal data bus 15b is disconnected from the data bus 12 based on the switch control signal S2. As a result, data can be read from the image memory 3 to the data bus 11.
[0073]
When the control instruction D1 related to the data transfer event (8) is written to the command register 17a, the data bus 11 is disconnected from the internal data bus 15a based on the switch control signal S1 decoded by the interface control unit 28, and the switch In the circuit 21b, the memory bus 22b and the internal data bus 15a are connected based on the switch control signal S6.
[0074]
The data read from the image memory 3 is temporarily recorded in the FIFO memory 23b based on the memory control signal S8. The data first recorded in the FIFO memory 23b is output to the data bus 12 through the interface unit 16 in order. At this time, the memory bus 22a is disconnected from the internal data bus 15b. In this case, the internal data bus 15a is disconnected from the data bus 11 based on the switch control signal S1. Thereby, data can be read from the image memory 3 to the data bus 12. When the control command D1 related to the data transfer events (1) to (6) and (8) is executed, the switch circuit 21c is kept off by the switch control signal S9.
[0075]
When the control instruction D1 related to {circle around (9)} is written to the command register 17a, the data bus 11 is connected to the internal data bus 15b based on the switch control signal S1 decoded by the interface control unit 28, and switch control is performed. Based on the signal S2, the data bus 12 is connected to the internal data bus 15a. Moreover, in the switch circuit 21b, the memory bus 22b and the internal data bus 15a are connected based on the switch control signal S6, the switch circuit 21c is turned on based on the switch control signal S9, and the internal data buses 15a and 15b are short-circuited. .
[0076]
The data read from the image memory 3 is temporarily recorded in the FIFO memory 23b based on the memory control signal S8. The data first recorded in the FIFO memory 23b is sequentially output to the data bus 11 through the interface unit 13 and output to the data bus 12 through the interface unit 16. At this time, the memory bus 22a is disconnected from the internal data buses 15a and 15b. Thereby, the same data can be read from the image memory 3 to the data bus 11 and the data bus 12. When any one of these data transfer events {circle over (1)} to {circle over (9)} is completed, end status data D2 is written in the status register 17b to notify the data transfer result.
[0077]
Thus, according to the three-way interface device 200 as the present embodiment, after the control instruction D1 is written from the system control device to the command register 17a, the data bus 11 is independent of the control device. Data can be written to the image memory 3 or the like, or data can be read from the image memory 3 onto the data bus 12.
[0078]
Accordingly, when a data processing system such as an office computer system or an image forming apparatus is constructed, one data bus is divided into two and data is transferred between the two data buses 11 and 12. The bidirectional interface device 100 according to this embodiment is designed to be disposed between the two data buses 11 and 12.
[0079]
In addition, data can be written and read between only the image memory 3 and the data bus 11, data can be written and read between the image memory 3 and the data bus 12, and the data bus 11 , 12, the three-way interface device 200 according to the present embodiment is arranged between the image memory 3 and the data buses 11 and 12. A command register 17a may be provided in the interface devices 100 and 200, and the control command D1 may be written in the command register 17a to control input / output of the interface devices 100 and 200.
[0080]
Next, a data processing device using the interface devices 100 and 200 will be described.
[0081]
(2) Configuration example of data processing device
FIG. 5 is a block diagram showing a configuration example of the data processing apparatus 300 as the present embodiment.
[0082]
In this embodiment, a terminal device connected to one data bus B by connecting a three-way interface device 200 between the main storage device 30 shown in FIG. When 40 is writing / reading data to / from the main storage device 30, the other data bus A can be opened to the main control device 10 and connected to each data bus A or B. The main storage device 30 can be shared in time series or simultaneously by the main control device 10, the sub control device 20, the terminal devices 40, 50, and the like.
[0083]
The data processing device 300 is provided with a main storage device 30 shown in FIG. 5 as a data memory. The main storage device 30 is connected to the above-described three-way interface device 200, and data is transferred between the main storage device 30 and the data bus A by a control instruction D1 written in the internal command register 17a. Writing and reading are performed, data is written and read between the main storage device 30 and the data bus B, and data transfer is performed between the two data buses A and B.
[0084]
In this example, the data bus A is provided with two bidirectional interface devices 101 and 102. One interface device 101 is connected to the data bus A and is connected to the other interface device 102 and the three-way interface device 200, and is also connected to the main control device 10 as an external device through the CPU bus 1a.
[0085]
Similarly, the other interface device 102 is connected to the data bus A and connected to the three-way interface device 200, and is also connected to the sub-control device 20 as an external device through the CPU bus 1b. Further, a bus arbitration unit 60 as a first arbitration unit is connected to the data bus A, and arbitration of the bus use right of the interface devices 101 and 102 is performed so that data collision does not occur.
[0086]
The data bus B is also provided with two bidirectional interface devices 103 and 104. One interface device 103 is connected to the data bus B, is connected to the other interface device 104 and the three-way interface device 200, and is connected to a terminal device 40 as an external device through a terminal bus 40a.
[0087]
Similarly, the other interface device 104 is connected to the data bus B to be connected to the three-way interface device 200, and is connected to the terminal device 50 as an external device through the terminal bus 50a. Further, a bus arbitration unit 70 as a second arbitration unit is connected to the data bus B, and arbitration of the bus use right of the interface devices 103 and 104 is performed.
[0088]
As the above-described interface devices 101 to 104, the bidirectional interface device 100 according to the present embodiment is used, and data transfer control is performed by a control instruction D1 written in a command register 17a provided therein. . In this example, at least when data transfer is performed between the data bus A and the main storage device 30, data transfer is performed between the main storage device 30 and the data bus B, or data is transferred between the data buses A and B. When the transfer is performed, the control instruction D1 is written to the command register 17a in the interface device 200. The control command D1 is written by the main control device 10 or the sub control device 20.
[0089]
Next, the operation of the data processing device 300 will be described. For example, description will be made assuming that data is written from the terminal device 40 to the main storage device 30. In this case, the control command D1 related to the above-described data transfer event (5) is written to the command register 17a of the interface device 200.
[0090]
Prior to this, first, the control instruction D1 related to the data transfer event (1) is written from the main control device 10 to a command register 17a (not shown) in the interface device 101 and a command register 17a (not shown) in the interface device 200. . Next, the control command D1 related to the data transfer event (4) is written from the main control device 10 to the interface device 103, and then the control command D1 related to the data transfer event (5) is written to the interface device 200.
[0091]
When each control command D1 is decoded by the interface devices 101, 200 and 103, the data bus B and the terminal bus 40a are connected in the interface device 103, and the data bus B and the memory bus 30a are connected in the interface device 200. Connected. The operation inside each of the interface devices 101, 200 and 103 is as described above. For example, data can be written from the terminal device 40 to the main storage device 30 via the data bus B by the connection operation of the interface devices 103 and 200.
[0092]
In this example, when data is written from the terminal device 40 to the main storage device 30 and when data is read from the main storage device 30 to the terminal device 50, the data bus A is transmitted by the three-way interface device 200. Is disconnected from the data bus B, the data bus A can be opened to the main controller 10 and the sub controller 20. As a result, the main control device 10 connected to the data bus A can exchange other data with the sub control device 20 through the interface devices 101 and 102.
[0093]
Further, the same data read from the main storage device 30 based on the control command D1 related to the data transfer event {circle over (9)} described above can be transferred to the main control device 10, the sub control device 20, the terminal device 50, and the like. it can. Accordingly, the main storage device 30 can be shared in time series or simultaneously by the main control device 10 and the sub control device 20 connected to the data bus A and the terminal devices 40 and 50 connected to the data bus B. .
[0094]
As described above, according to the data processing device 300 as the present embodiment, the two data buses A and B are input / output controlled in time series by the bidirectional interface devices 101 to 104 and the three-way interface device 200. Therefore, data transfer control can be performed by dividing one CPU bus 1 into two as in the conventional image forming apparatus 500.
[0095]
Next, an image forming apparatus to which the data processing apparatus 300 is applied will be described.
[0096]
(3) Application examples of data processing equipment
FIG. 6 is a block diagram illustrating a configuration example of an image forming apparatus 400 according to the present embodiment. In this embodiment, the memory bus bridge 201 is connected to the image memory 3 shown in FIG. 7 and the two data buses A and B, and the control instruction D1 is given to the bus bridge 201. The control unit D1 controls the scanner unit 42 and the printer unit 52 in time series independently of the CPU 2a so that the CPU 2a can execute other data processing during this time.
[0097]
The image forming apparatus 400 is provided with a bus bridge 201 shown in FIG. 6 as a three-way interface unit. The bus bridge 201 uses the three-way interface device 200 according to the present embodiment.
[0098]
An image memory 3 is connected to the bus bridge 201, and image data such as a document is temporarily stored. In this example, image data is written and read between the image memory 3 and the data bus A by the control instruction D1 written in the command register 17a in the bus bridge 201, and the image memory 3 and the data bus B The image data is written and read between the two data buses, and the image data is transferred between the two data buses A and B.
[0099]
In this example, the data bus A is provided with two bidirectional bus bridges 31 and 32. One bus bridge 31 is connected to the data bus A, is connected to the other bus bridge 32 and the memory bus bridge 201, and is also connected to the CPU 2a through the CPU bus 1a. As in the conventional method, the CPU 2a is connected to the ROM 2b, the RAM 2c, and the operation unit 2d, and performs overall control of the image forming apparatus 400. Description of these functions is omitted (see FIG. 7).
[0100]
The other bus bridge 32 is connected to the data bus A and connected to the bus bridge 201, and is also connected to the CPU 25 for controlling the communication modem and the like through the CPU bus 1b. The ROM 26 and the RAM 27 connected to the CPU bus 1b support the CPU 25. Further, a bus arbiter 61 as a first arbitration unit is connected to the data bus A, and arbitration of the bus use right of the bus bridge 31 and the bus bridge 32 is performed so that data collision does not occur.
[0101]
The data bus B is also provided with two bidirectional bus bridges 33 and 34. One bus bridge 33 is connected to the data bus B and is connected to the other bus bridge 34 and the bus bridge 201, and is also connected to a scanner unit 42 as an image acquisition unit through a scanner bus 41. The scanner unit 41 acquires an image of a document based on input control of the bus bridge 33 and outputs image data of the document.
[0102]
Similarly, the other bus bridge 34 is connected to the data bus B and connected to the bus bridge 201, and is also connected to a printer section 52 as an image reproducing means through a printer bus 51. The printer unit 52 is supplied with image data based on the output control of the bus bridge 34, and the original image is reproduced based on the image data. Further, a bus arbiter 71 as second arbitration means is connected to the data bus B, and arbitration of the bus use right of the bus bridges 33 and 34 is performed.
[0103]
The above-described bus bridges 101 to 104 use the bidirectional interface device 100 according to the present embodiment, and the data transfer is controlled by the control instruction D1 written in the command register 17a provided therein. . In this example, at least when data transfer is performed between the data bus A and the image memory 3, data transfer is performed between the image memory 3 and the data bus B, or data transfer is performed between the data buses A and B. When performing, the control instruction D1 is written to the command register 17a in the bus bridge 201.
[0104]
In this example, after the control command D1 is written to the bus bridge 201 by the CPU 2a or CPU 25, the scanner unit 42 and the printer unit 52 are input / output controlled in time series by the control command D1.
[0105]
Next, the operation of the image forming apparatus 400 as the present embodiment will be described. First, a case where a single (one page) document is copied will be described. In this example, it is assumed that the document image data acquired by the scanner unit 42 is once transferred to the image memory 3, and then the image data is read from the image memory 3 and supplied to the printer unit 52. To do.
[0106]
For example, when the operation unit 2d instructs the CPU 2a to copy one page, the CPU 2a instructs the bus bridge 33 to drive the scanner in order to drive the scanner unit 42. At this time, since the data buses A and B are not directly connected to the bus bridge 33 and the CPU 2a, a scanner drive instruction is sent via the bus bridge 31 and the bus bridge 201.
[0107]
In response to this scanner drive instruction, a control command D1 is sent from the CPU 2a to the bus bridge 31. At this time, the address generated by the CPU 2a indicates the bus bridge 31 mapped in advance. Accordingly, the bus bridge 31 drives this control command D1 and address to the data bus A. In the bus bridge 201 connected to the data bus A, since the address attached to the control instruction D1 designates the bus bridge 33 connected to the data bus B, the control instruction D1 and the address are transferred to the data bus B. Driven. As a result, the bus bridge 33 receives the control command D1 and the address from the bus bridge 201, and the drive control of the scanner unit 42 is performed.
[0108]
Next, the CPU 2a instructs the bus bridge 33 about the transfer destination of the image data output from the scanner unit 42, the number of transfer bytes, and the like. At this time, as described above, the CPU 2a drives the control instruction D1 for instructing the address of the bus bridge 33 and the storage location of the image data on the data bus A through the CPU bus 1a. As a result, the control command D 1 is transferred to the bus bridge 33 through the bus bridge 31 and the bus bridge 201. In the bus bridge 33 that has received the control command D1, preparation for writing the image data from the scanner unit 42 to the address of the instructed image memory 3 is started.
[0109]
In this writing, the bus bridge 33 requests the bus arbiter 71 to use the data bus B. The bus arbiter 71 permits the use of the data bus B in response to the highest priority bus use request at that time according to a built-in predetermined algorithm. In this case, since no bus use request is made from the bus bridge 201 and the bus bridge 34, the use of the data bus B is permitted to the bus bridge 33. In the bus bridge 33 that has received the permission, the address of the designated image memory 3 is driven to the data bus B.
[0110]
The bus bridge 201 that has received the address of the image memory 3 detects an access to the image memory 3 by decoding the control instruction D1. Accordingly, the image data driven on the data bus B is stored in the image memory 3 through the internal data bus 15b and the FIFO memory 23a of the bus bridge 201 (see FIG. 4).
[0111]
Here, if the address of the image memory 3 and the address of the bus bridge 34 are set to the same value on the address map of the CPU 2a, the image data from the scanner unit 42 is stored in the image memory 3, and the document is simultaneously written by the printer unit 52. Images can be printed out.
[0112]
While the image data of the transfer byte number designated by the CPU 2a is stored in the image memory 3 by the bus bridge 33, the CPU bus 1a and the data bus A are not used for transferring image data. The CPU 25 and the like can process jobs such as newly designated communication processing.
[0113]
When the transfer of image data for the designated number of bytes is completed, the bus bridge 33 notifies the CPU 2a of the end of data transfer. At this time, in the bus bridge 33, the data bus B is driven to indicate the address of the bus bridge 31 in order to record the end status data D2 in the status register 17b in the bus bridge 31.
[0114]
Since the data bus B is driven, the address is decoded in the bus bridge 201, and the address of the bus bridge 31 and the end status data D2 are driven to the data bus A. As a result, since the address addressed to the bus bridge 31 is driven in the bus bridge 31, the end status data D2 is stored in the status register 17b described above.
[0115]
Since the contents of the status register 17b change in the bus bridge 31, the contents are notified to the CPU 2a. Therefore, the CPU 2a can detect that the transfer of the image data from the scanner unit 42 to the image memory 3 is completed by reading the register 17b of the bus bridge 31.
[0116]
The CPU 2a that has received this data transfer end notification instructs the bus bridge 34 to start up the printer unit 52. At this time, the address driven to the CPU bus 1a instructs the bus bridge 34. Therefore, the control instruction D1 for the bus bridge 34 is stored in the command register 17a of the bus bridge 34 through the bus bridge 31 and the bus bridge 201. Thereafter, the CPU 2a is instructed to the bus bridge 34 about the storage source of the image data and the number of bytes thereof, and preparation for the start of printing is made.
[0117]
The bus bridge 34 requests the bus arbiter 71 to use the data bus B for data transfer. In response to this request, the bus arbiter 71 grants permission for the bus use request with the highest priority at that time according to a predetermined algorithm. In this case, since there is no bus use request from the bus bridge 201 and the bus bridge 33, permission to use the data bus B is given to the bus bridge 34. The bus bridge 34 that has received this permission drives the address of the image memory 3 to the data bus B.
[0118]
The bus bridge 201 that has received the address of the image memory 3 decodes this address, and it is detected that the access is to the image memory 3 based on the decoding result. As a result, the bus bridge 201 reads the image data from the image memory 3 at the address designated by the CPU 2 a and drives the image data onto the data bus B. The image data driven on the data bus B is taken in by the bus bridge 34, and the image data is output to the printer unit 52.
[0119]
In this bus bridge 34, when the printout for the designated byte is completed, the transfer end status is stored in the status register 17b in the bus bridge 31 described above. As described above, the CPU bus 1a and the data bus A can be used for the next job of the CPU 2a from the time when the start command is sent to the bus bridge 33 until the end of copying one page of the document.
[0120]
Next, a case where a plurality of originals are copied to a plurality of copies of transfer paper will be described. Also in this case, the CPU 2a sends a control command D1 for driving control of the scanner unit 42 to the bus bridge 33 according to an instruction from the operation unit 2d. Further, the storage destination address and the number of read bytes of the image data read by the scanner unit 42 are set, and reading of the image data is started. At this time, as described above, by setting the address of the bus bridge 34 to be the same as the address of the image memory 3, the read image data can be stored in the image memory 3 while being printed out.
[0121]
In this example, when the reading of the image data of the first page of the document is completed, the CPU 2a instructs the bus bridge 34 to activate the printer unit 52. At this time, if the image memory 3 has an empty memory area for one page, the CPU 2a instructs the bus bridge 33 to start reading the second page. Each bridge 33, 34 requests the bus arbiter 71 to use the data bus B. The bus bridge 33 or 34 having received this permission performs the data transfer as described above. When the same operation as described above is performed for the number of documents on the first page, one copy of the document on the first page is completed. In order to copy a plurality of copies, the bus bridge 34 is sequentially activated, and a predetermined number of copies are completed.
[0122]
As described above, according to the image forming apparatus 400 as the present embodiment, the input / output control of the image data can be performed by the bus bridge 201 dedicated to the memory independently of the CPU 2a. When image data is being written in the memory 3, an image of a document can be copied by the printer unit 42 based on the image data from the scanner unit 42 at the same time. Therefore, after the control command D1 is given from the CPU 2a to the bus bridge 201, the CPU 2a can execute other data processing such as communication processing.
[0123]
In this example, the communication means 38 is connected to the CPU 25, and the document image data from the scanner unit 42 is transmitted to the communication line 39, or the document image data sent using the communication line 39 is received. The document image data received by the communication unit 38 may be reproduced and output by the printer unit 52.
[0124]
Note that the CPU 2a and the CPU 25 may be the same. When the CPU 2a and the CPU 25 are the same, the bus bridge 31 and the bus bridge 32 can have the same configuration. The contents of the address map installed in the ROM 2b and the like are simplified.
[0125]
In the present embodiment, since the image memory 3 can be shared by the scanner unit 42, the printer unit 52, and the like, a page memory as in the conventional method becomes unnecessary and the use efficiency of the image memory 3 is improved.
[0126]
Further, since one data bus as in the conventional method can be divided into two, A and B, a DMAC can be introduced without worrying about the influence on the CPU 2a. Therefore, by providing the interface control unit 18 in the bus bridges 31 to 34 and the interface control unit 28 in the bus bridge 201 with a DMAC function, the transfer speed of image data and the like can be increased.
[0127]
【The invention's effect】
  As described above, according to the data processing apparatus of the present invention,Data is transferred between the first data bus and the second data busThree-way interface meansWith,The interface means connects the first data bus and the second data bus.Input / output control in time seriesHave FIFO memory forIs.
[0128]
With this configuration, data transfer control can be performed by dividing one data bus into two. For example, an external device connected to the first data bus can transfer data to and from a data memory. During writing / reading, data writing / reading between the second data bus and the data memory is stopped, or the same data read from the data memory is transferred to the second data bus. Can be transferred.
[0129]
  Therefore, when the external device connected to the first data bus is writing data to and reading data from the data memory, the second data bus can be opened to other external devices. . In addition, the data memory can be shared in time series or simultaneously between the external device connected to the first data bus and the external device connected to the second data bus.Moreover, it is possible to construct a data processing system that does not place an excessive control burden on the host control device..
[0132]
The present invention is extremely suitable when applied to an image processing apparatus such as a copying machine, a printer, or a facsimile.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of an interface apparatus 100 as an embodiment of the present invention.
FIG. 2 is a configuration diagram showing an operation example of the interface apparatus 100. FIG.
FIG. 3 is a block diagram showing a configuration example of a three-way interface device 200 as an embodiment of the present invention.
FIG. 4 is a configuration diagram illustrating an operation example of the interface apparatus 200;
FIG. 5 is a block diagram showing a configuration example of a data processing device 300 as an embodiment of the present invention.
FIG. 6 is a block diagram illustrating a configuration example of an image forming apparatus 400 as an embodiment of the present invention.
7 is a block diagram illustrating a configuration example of a conventional image forming apparatus 500. FIG.
[Explanation of symbols]
1 CPU bus
2 System control means
3 Image memory
5 Image acquisition means
6 Image playback means
10 Main controller
13,16 Interface part
17 Memory for control
17a Command register
17b Status register
20 Sub-control device
21 Internal bus selector
24 Memory control means
28 Interface controller
30 Main memory
31-34,201 Bus bridge
60, 70 Bus arbitration means
100,200 interface device

Claims (4)

Image memory,
A first data bus;
A second data bus;
The image memory and the Shi read out the write data between the first data bus, the Shi writing read out of the data between the image memory and the second data bus, and, and a 3 directional interface means for performing data transfer between said first data bus and said second data bus,
The three-way interface means includes:
A bidirectional first interface unit connected to the first data bus for inputting and outputting data;
A bidirectional second interface unit connected to the second data bus for inputting / outputting data;
An internal data bus connected between the first and second interface units;
A branched data bus branched from the internal data bus;
A memory control unit connected to the branch data bus for controlling the writing and reading of data to and from the image memory;
A first FIFO memory that is provided between the first interface unit and the memory control unit and temporarily stores data input from the first interface unit;
A second FIFO memory that is provided between the memory control means and the second interface unit and temporarily stores data input from the second interface unit;
A third FIFO memory for temporarily storing data to be written controlled by the memory control means;
A fourth FIFO memory for temporarily storing data to be read and controlled by the memory control means;
A control memory for temporarily recording a control command for input / output control of the first interface unit, the second interface unit, the internal data bus, and the memory control unit;
Based on the control command recorded in the control memory, performs data write / read control of the first, second, third and fourth FIFO memories,
The data processing apparatus characterized by comprising as time series input and output controls the first data bus and said second data bus to said image memory. 2. The data processing apparatus according to claim 1, wherein control notification information indicating a result of data transfer executed with respect to the control command is temporarily recorded in the control memory. Two or more bidirectional interface means disposed on the first data bus;
First arbitration means arranged for bus arbitration of two or more bidirectional interface means arranged on the first data bus;
Two or more bidirectional interface means disposed on the second data bus;
2. The data processing apparatus according to claim 1, further comprising: a second arbitration unit arranged to perform bus arbitration of two or more bidirectional interface units arranged on the second data bus. . Bi-directional interface means connected to the second data bus;
An external device connected to the bidirectional interface means is provided;
The bidirectional interface means includes:
A bidirectional first interface unit connected to the second data bus for inputting / outputting data;
A bidirectional second interface unit connected to the external device for inputting and outputting data;
An internal data bus connected between the first and second interface units;
A control memory for temporarily recording a control command for input / output control of the first interface unit, the second interface unit, and the internal data bus;
When transferring data between the external device and the second data bus,
2. The data processing apparatus according to claim 1, wherein a control command is written in the control memory.

Images