JP4112603B2 - Method and apparatus for controlling hierarchical cache memory - Google Patents

Description

  The present invention relates to a method and apparatus for controlling a hierarchical cache memory. More specifically, in the present invention, when data is stored in the cache line of the lower level cache memory, the data of the cache line already stored in the upper level cache memory is overwritten. The present invention relates to a control method for prohibiting the storage of data.

  In recent years, as the state of the art computer applications have become more and more complex, the need for improving the throughput of data processing by computers remains unavoidable and the demand for microprocessing systems continues to increase. In a conventional microprocessing system (a system using a microprocessor and a memory associated therewith), the cycle time (unit of time in which the microprocessor can process data) is very short, for example, 1 nanosecond. However, the time required to access the data stored in the main memory may be considerably longer than the microprocessor cycle time. For example, the access time when extracting 1 byte of data from a main memory mounted using dynamic random access memory (DRAM) technology is about 60 nanoseconds.

  Conventionally, a cache memory is used in order to improve a bottleneck caused by a relatively long access time of a DRAM memory. The cache memory assists the main memory and improves the system throughput. Main memory is often implemented using relatively inexpensive and slow DRAM memory technology, whereas cache memory is typically implemented using more expensive and faster static random access memory (SRAM) technology. . Since the cache memory is mounted using a high-cost technology, the capacity is usually much smaller than that of the main memory.

  Because cache memory is relatively small in capacity, conventional algorithms have been used to determine the data to be stored in the cache memory at various times during the operation of the microprocessing system. For example, these conventional algorithms are based on the concept of “locality of reference” and the fact that at a particular point in time, the microprocessor uses only a relatively limited portion of the executable program. Can be used. Thus, according to the concept of locality of reference, only a limited part of the executable program is stored in the cache memory at a certain point in time. Also, such algorithms and other algorithms can be used to control the storage of data in the cache memory and the retrieval of data from the cache memory (these data can be used by executable programs).

  Details of known algorithms and other concepts that use locality of reference to control the storage of executable programs and data in cache memory cannot be described here due to their large number. However, it may be sufficient to mention that no algorithm is suitable for any application, because the purpose of data processing can vary greatly from application to application.

  In the conventional algorithm for controlling the cache memory, the microprocessor gives a data access request to the cache memory. If the requested data is stored in the cache memory, a cache hit occurs and the microprocessor receives the data relatively quickly. If the data access request for the data is not satisfied even if the cache memory is accessed, that is, if a cache miss occurs, the data is acquired from the main memory and a data refill sequence stored in the cache memory is executed. It is desirable.

  The cache memory may be arranged “on-chip” in the microprocessor, and this configuration is referred to as a level 1 (L1) cache memory. Alternatively, the cache memory may be arranged separately from the microprocessor, that is, off-chip, and this configuration is referred to as a level 2 (L2) cache memory. Usually, the access time of the L1 cache memory is significantly shorter than that of the L2 cache memory. It is also possible to configure an L1 and L2 composite cache memory system that uses both an on-chip cache memory and an off-chip cache memory, and this configuration is sometimes referred to as a hierarchical cache memory. In this configuration, when the microprocessor makes an access request for data, the L1 cache memory is first accessed to satisfy the request. If the request is not satisfied, the L2 cache memory is accessed. When a miss of the L2 cache memory occurs, the main memory is accessed and the L1 cache memory and the L2 cache memory are refilled.

  In order to reduce the occurrence of contention between the L1 cache memory and the L2 cache memory and improve the access efficiency, the L2 cache memory may be an N-way set associative memory having more way sets than the L1 cache memory. According to the conventional technique, when the L2 cache memory is refilled (that is, after the occurrence of an L2 cache memory miss), a cache line for entering refill data from among the N cache lines of the L2 cache memory. Must be selected. If invalid data is stored in one or more of the N cache lines, the refill data is stored in one of these cache lines. However, if valid data is stored in all N cache lines, use a random selection approach, a known least frequently used (LRU) algorithm, or any other algorithm. Use to select the cache line that will contain the refill data. In any case, if valid data in the cache line of the L2 cache memory is overwritten and a copy of this valid data is also stored in the cache line of the L1 cache memory, the L1 cache memory and the L2 cache In order to match with the memory, it is necessary to invalidate the cache line of the L1 cache memory.

  However, if the data in the higher-level cache memory such as the L1 cache memory is invalidated as in the conventional control method, the throughput of the entire microprocessing system is reduced. For example, if data in the L1 cache memory is invalidated unnecessarily, the L1 cache memory cannot be used optimally. As a result, cached instructions and data that are accessed very frequently within the loop body may be unnecessarily invalidated. This situation is common when accessing very large data arrays.

  Accordingly, a cache memory that may comprise an L1 cache memory, an L2 cache memory, and / or a lower level cache memory to improve memory efficiency, improve processing throughput, and improve the quality of data processing performed throughout the system. There is a need in the art for new methods and apparatus for controlling the process.

  In accordance with one or more aspects of the present invention, an apparatus includes a first level cache memory having a plurality of cache lines each operable to store an address tag and data, each address tag status flag, And a next lower level cache memory with a plurality of cache lines operable to store data, the status flag for each cache line being And an L flag indicating that any one of the cache lines of the first level cache memory stores a copy of the data stored in the cache line of the next level cache memory.

  Preferably, the L flag of each cache line is 1 bit, and if the value is true, a copy of the data stored in the cache line of the cache memory at the next level is used as the first level cache. Indicates that the corresponding cache line of the memory is stored. If false, a copy of the data stored in the cache line of the next level cache memory is transferred to any cache of the first level cache memory. Indicates that no line is stored. For example, the true level of the L flag bit can be one of a logic high and a logic low, and the false level of the L flag bit can be the other of the logic high and the logic low.

  Preferably, the first level cache memory is an L1 cache memory, and the next level cache memory is an L2 cache memory.

  The apparatus sets the L flag of a predetermined cache line of the cache memory at the next level and copies the data stored in the predetermined cache line of the cache memory at the next level by the first cache line. There may further be a processor operable to indicate whether a corresponding cache line of the level cache memory is being refilled.

  Alternatively, (or in addition to) the apparatus may be configured such that an L flag of a predetermined cache line of the next-level cache memory stores a copy of the data stored in the predetermined cache line. Operates to prohibit overwriting of data to the predetermined cache line of the next level cache memory when the corresponding cache line of the level cache memory indicates that it is stored It can be. Preferably, when the valid flag of the status flag of the predetermined cache line in the next-level cache memory indicates that any of the data stored in the predetermined cache line is invalid, the processor And is further operable to allow overwriting of data to the predetermined cache line.

  Further, the valid flag of the status flag of the predetermined cache line of the cache memory at the next level indicates that the data stored in the predetermined cache line is valid, and the L bit of the predetermined cache line Indicates that the corresponding cache line of the cache lines of the first level cache memory does not store a copy of the data stored in the predetermined cache line; It may be further operable to allow overwriting of data to the cache line.

  The first level cache memory may be a direct mapped cache memory. The next level cache memory may be an N-way set associative cache memory.

  In accordance with one or more further aspects of the present invention, an apparatus includes: a first level cache memory having a plurality of M1 cache lines each operable to store an address tag and data; An N-way set associative unified cache memory, each N-way set having a plurality of M2 cache lines (M2 is greater than M1) each operable to store address tags, status flags and data; An additional memory associated with the next level cache memory and having a plurality of M1 memory lines, each memory line comprising a plurality of caches in each N-way set of the next level cache memory Each L bit corresponding to a line, and each L bit is a cache of the next level. Indicating whether a copy of the data stored in the predetermined cache lines of the memory, one of the cache lines of the first level cache memory is storing.

  Preferably, the number of L flags in each memory line of the additional memory is M2 / M1 × N. The L flag of each cache line may be 1 bit, and if the value is true, a copy of the data stored in the associated cache line of the next level cache memory is copied to the first level. Indicates that the cache line of the cache memory is stored, and if false, a copy of the data stored in the associated cache line of the next level cache memory is copied to the first level cache memory. Indicates that no cache line is stored. The true level of the L flag bit can be one of a logic high and a logic low, and the false level of the L flag bit can be the other of the logic high and the logic low.

  The apparatus preferably sets the L flag of each of the additional memories and corresponds to the first level cache memory according to the data stored in the cache line of the next level cache memory. Having a processor operable to indicate whether the cache line is being refilled; The processor is preferably further operable to set the L flag of a predetermined memory line of the additional memory substantially simultaneously.

  Alternatively, (or in addition to) the processor, the L flag of a predetermined cache line of the cache memory at the next level stores a copy of the data stored in the predetermined cache line. Operates to prohibit overwriting of data to the predetermined cache line of the next level cache memory when the corresponding cache line of the level cache memory indicates that it is stored It can be. Preferably, when the valid flag of the status flag of the predetermined cache line of the next-level cache memory indicates that any of the data stored in the predetermined cache line is invalid The processor may be further operable to allow overwriting of data to the predetermined cache line. Furthermore, the valid flag of the status flag of the predetermined cache line of the next-level cache memory indicates that the data stored in the predetermined cache line is valid, and the L flag of the predetermined cache line Indicates that the corresponding cache line of the cache lines of the first level cache memory does not store a copy of the data stored in the predetermined cache line, the processor preferably And is further operable to allow overwriting of data to the predetermined cache line.

  In accordance with one or more further aspects of the present invention, an apparatus includes a first level N-way set associative cache memory, and each N-way set of the first level cache memory, each comprising an address tag and A plurality of M1 cache lines operable to store data, each of the N-level set associative unified cache memory of the next level and each of the N-way sets of the next level cache memory A plurality of M2 cache lines (M2 is greater than M1) operable to store address tags, status flags and data, associated with the next level cache memory and having a plurality of M1 memory lines An additional memory, and each memory line of the additional memory is A bit group associated with each N-way set of one-level cache memory, whereby each bit group of the additional memory is a respective one of the cache lines of the first-level cache memory. Each bit group includes an index offset bit, a way set bit, and an L flag, and the combination of the index offset bit and the index is 1 in each N way set of the cache memory at the next level. A pointer to one cache line, the way set bit is a pointer to one of the N way sets of the next level cache memory, and the L flag is the index offset bit, the index, and the way A copy of the data stored in the next stage level cache memory of the cache line pointed to by Ttobitto indicates whether the associated cache line of the first level cache memory is storing.

  In accordance with one or more further aspects of the present invention, a method controls a first level cache memory comprising a plurality of cache lines each operable to store an address tag and data; Controlling a next level cache memory having a plurality of cache lines each operable to store an address tag, a status flag and data, wherein the status flag of each cache line has an L flag The first level by setting a L flag of a predetermined cache line of the cache memory at the next stage level and copying data stored in the predetermined cache line of the cache memory at the next stage level; The corresponding cache line of the cache lines of the cache memory is Having a step that determines whether the fill.

  Preferably, in the above method, a copy of data stored in the predetermined cache line of the L flag of the predetermined cache line of the cache memory at the next level is copied to the cache line of the first level cache memory. And a step of prohibiting overwriting of data to the predetermined cache line of the cache memory at the next level when the corresponding cache line indicates that it is stored. In the above method, when the valid flag of the status flag of the predetermined cache line of the next-level cache memory indicates that any of the data stored in the predetermined cache line is invalid, The method may include a step of permitting overwriting of data to the predetermined cache line. Further, in the method, the valid flag of the status flag of the predetermined cache line of the cache memory at the next level indicates that the data stored in the predetermined cache line is valid, and the predetermined cache line The predetermined bit if the L bit of the line indicates that the corresponding cache line of the cache lines of the first level cache memory does not store a copy of the data stored in the predetermined cache line; The method may further include the step of allowing data to be overwritten on the cache line.

  According to one or more further aspects of the present invention, a method controls a first level cache memory having a plurality of M1 cache lines each operable to store an address tag and data; Controlling a next level N-way set associative unified cache memory, each N-way set having a plurality of M2 cache lines each operable to store an address tag, a status flag and data ( M2 is greater than M1) and controlling an additional memory associated with the next level cache memory and having a plurality of M1 memory lines, each memory line including For multiple cache lines of each N-way set of level cache memory The first level cache memory in accordance with data stored in the cache line of the next level cache memory by setting each L flag of the additional memory and setting each L flag of the additional memory. Indicating whether the corresponding cache line is refilled.

  According to one or more further aspects of the present invention, a method controls a first level N-way set associative cache memory, wherein each N-way set of the first level cache memory is A plurality of M1 cache lines each operable to store an address tag and data, and controlling a next level N-way set associative unified cache memory, wherein the next level Each N-way set of the cache memory includes a plurality of M2 cache lines (M2 is greater than M1) each operable to store an address tag, a status flag, and data; Associated with cache memory and has multiple M1 memory lines (I) each memory line of the additional memory has a respective group of bits associated with each N-way set of the first level cache memory. Whereby each bit group of the additional memory is associated with a respective one of the cache lines of the first level cache memory, and (ii) each bit group includes an index offset bit, a wayset bit and (Iii) the combination of the index offset bit and the index becomes a pointer to one cache line of each N way set of the next level cache memory, and (iv) the way set bit is , The N way of the next level cache memory The next level cache pointed to by the index offset bit, the index and the wayset bit by setting a pointer to one of the set of bits and setting an L flag for each of the additional memories Indicating whether the corresponding cache line of the first level cache memory has been refilled with data stored in the cache line of the memory.

  In accordance with one or more further aspects of the present invention, the method and apparatus described above for controlling a cache memory, or the method and apparatus described later herein, are suitable hardware as shown in the following figures. Can be realized using hardware. This type of hardware can be implemented using any known technique. Examples include any known processor, programmable read only memory (PROM), programmable array logic device (PAL) operable to execute standard digital circuits, analog circuits, software programs and / or firmware programs. ), One or more programmable digital devices or systems, such as any combination thereof.

  Other aspects, features, advantages, etc. will become apparent to those skilled in the art after reading the description of the invention herein with reference to the accompanying drawings.

  For the purpose of illustrating the invention, there are shown in the drawings forms that are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.

  In the drawings, identical elements are referred to by the same reference numerals. FIG. 1 is a block diagram illustrating one or more aspects of the present invention. For the sake of brevity and clarity, the block diagram of FIG. 1 is referred to and described herein as an illustration of the apparatus 100. However, it should be understood that this description can be readily applied to various aspects of one or more methods having equivalent efficacy.

  The apparatus 100 is preferably a microprocessor system comprising a microprocessor 101, a first level cache memory 102, a lower level cache memory 103, and a further memory 104. Microprocessor 101 can be implemented using any currently available or later developed microprocessor device.

  The first level cache memory 102 is preferably an L1 cache memory, that is, a cache memory arranged on-chip in the microprocessor 101. However, although it is preferable that the first level cache memory 102 is disposed on-chip in the microprocessor 101, the first level cache memory 102 does not necessarily have to be mounted on-chip. In fact, the first level cache memory 102 may be arranged off-chip outside the microprocessor 101.

  Preferably, the first level cache memory 102 includes an instruction cache memory 102A and a separate data cache memory 102B, each of which includes a plurality of cache lines. Each cache line has an address tag, a status flag, and data. In order to avoid access contention, the instruction cache and the data cache are preferably separated. For example, the instruction cache memory 102A and the data cache memory 102B can each be implemented as a direct mapped configuration of 64 kilobytes. However, it should be noted that the sizes of the instruction cache memory 102A and the data cache memory 102B are arbitrary. It should also be noted that the first level cache memory 102 may have one direct mapped cache memory and store both instructions and data.

  The cache lines of instruction cache memory 102A and data cache memory 102B are addressed as valid addresses issued by microprocessor 101, each valid address including a tag bit and an index bit. The index bit becomes a pointer to a specific cache line of the instruction cache memory 102A and / or the data cache memory 102B of the first level cache memory 102. In the above example where the size of the cache memory is 64 kilobytes, the index bits can range from 0x0000 to 0xFFFF to point to all available cache lines (some of the least significant bits are used as offsets) ) As an example for illustration, assume that the pointer (or index) 110 obtained from the index bit of the effective address issued by the microprocessor 101 is 0xAFF0. This pointer points to the cache line storing the instruction A of the instruction cache memory 102A and also points to the cache line storing the data A of the data cache memory 102B.

  The lower level cache memory 103 is an L2 cache memory in this embodiment, and is preferably an N-way set associative memory with N = 4. Therefore, the lower level cache memory 103 includes a first way set 105, a second way set 106, a third way set 107, and a fourth way set 108. Each wayset of the lower level cache memory 103 preferably has a plurality of cache lines, and each cache line is operable to store address tags, status flags and data (which may include instructions). In this exemplary embodiment of the invention, the size of the lower level cache memory 103 is preferably 256 kilobytes and the size of each wayset is 64 kilobytes. Therefore, each cache line of the instruction cache memory 102 A and the data cache memory 102 B of the first level cache memory 102 corresponds to each cache line of the four way sets 105, 106, 107, 108 of the lower level cache memory 103. Yes. In the above example, the pointer 110 (index value 0xAFF0) points to four cache lines of the lower level cache memory 103, that is, one cache line for each way set 105, 106, 107, 108.

  The status flag of each cache line in the lower level cache memory 103 preferably stores an L flag 112, which is a copy of the data stored in that cache line in the next level cache memory 103. , Indicates whether any of the cache lines of the first level cache memory 102 is stored. Note that each L flag may be more than one bit, but one bit is most preferred. Any rule may be used in accordance with the present invention, for example if the L flag (or bit) 112 is "true", preferably the data stored in that cache line of the lower level cache memory 103 Indicates that the corresponding cache line of the first level cache memory 102 stores the copy. In contrast, when the L flag 112 is “false”, the cache line of the first level cache memory 102 preferably stores a copy of the data stored in the cache line of the lower level cache memory 103. Indicates no. If L flag 112 is 1 bit, preferably one of logic high and logic low represents a true state and the other of logic high and logic low represents a false state. .

For example, the cache line 109A (indexed by 0xAFF0) of the wayset 105 stores a logical low (false) L bit 112A, which causes the data (data C) on this cache line to be stored in the data cache This indicates that the cache line indexed by 0xAFF0 in the memory 102B is not stored. The cache line 109B of the lower level cache memory 103 stores a logical high (true) L bit 112B. This is because the data (data A) of this cache line is stored in the data cache memory of the first level cache memory 102. Indicates that the cache line indexed by 0xAFF0 of 102B is stored.
The cache line 109C of the lower level cache memory 103 stores a logical low (false) L bit 112C. This is because the data (data B) of this cache line is indexed by 0xAFF0 of the data cache memory 102B. Indicates that the cache line is not stored. Further, the cache line 109D stores a logical high (true) L bit 112D. This is because the cache line data (instruction A) is stored in the cache line indexed by 0xAFF0 in the instruction cache memory 102A. Indicates that it is stored.

  Still another memory 104 may be a next level cache memory or main memory. In fact, in the present invention, the number of layers existing between the microprocessor 101 and the main memory in the hierarchical cache memory may be any value.

  The structure and operation of the device 100 will be better understood with further reference to FIG. FIG. 2 is a flowchart illustrating certain actions performed by or associated with the device 100. For the sake of explanation, it is assumed that the first level cache memory 102 is an L1 cache memory, the lower level cache memory 103 is an L2 cache memory, and the further memory 104 is a main memory.

  In accordance with one or more aspects of the method and apparatus shown in FIGS. 1 and 2, each state of the L flag 112 is a function of data (or instructions) stored in the first level cache memory 102. Be controlled. The L flag 112 is used to determine whether to permit or prohibit storage of cache line data or instructions in the lower level cache memory 103. More specifically, preferably, to indicate whether a copy of data stored in a cache line in the lower level cache memory 103 is refilling the corresponding cache line in the first level cache memory 102, The L flag 112 of the cache line in the lower level cache memory 103 is set to true or false.

  FIG. 2 shows this general control in more detail. In action 150, it is determined whether an L1 cache hit or miss has occurred. If a cache hit occurs, the process flow proceeds to action 151 where the requested data is obtained from the first level cache memory 102 and provided to the microprocessor 101. If it is determined that a cache miss has occurred, the process flow proceeds to action 152. For example, it is assumed that the microprocessor 101 issues an access request for requesting data C from the cache line indexed by 0xAFF0 of the data cache memory 102B to the first level cache memory 102 (L1 cache memory). A cache miss occurs when one of the cache line status flags (eg, valid flag or bit) indicates that the data stored in this cache line is invalid, or this This is the case where the address tag of the cache line does not match the tag bit of the effective address (for example, the data stored in this cache line is not data C).

  In action 152, the cache lines 109A, 109B, 109C, 109D indexed by 0xAFF0 of the lower level cache memory 103 are accessed, and (i) one of these cache line address tags matches the tag bit of the effective address. And (ii) whether the valid flag of the cache line storing the address tag with the matching tag bit indicates that the data is valid. If none of the above conditions is satisfied, the L2 cache memory 103 cannot satisfy the access request and an L2 cache miss occurs (action 154). Since the cache line 109A stores valid data (that is, data C), the data requested by the L1 cache memory (and the microprocessor 101) becomes a hit of the L2 cache memory, and the processing flow changes from action 154 to action 156. Proceed to

  In action 156, the cache line of the data cache memory 102B of the L1 cache memory 102 is refilled with the data stored in the cache line 109A of the L2 cache memory 103. More specifically, the cache line indexed by 0xAFF0 in the data cache memory 102B and storing data A is overwritten by the refill data (data C) stored in the cache line 109A of the L2 cache memory 103. . The process flow then proceeds to action 158 where the L bit 112A of the cache line 109A of the L2 cache memory 103 is set to true. This indicates that a copy of the data in the cache line 109A is stored in the corresponding cache line in the data cache memory 102B. Further, when the L bit 112B of the cache line 109B is set to false, a copy of the data stored in the cache line 109B (ie, data A) is copied to the data stored in the corresponding cache line in the data cache memory 102B. To indicate that it is no longer stored.

  In the above example, the access request made by the microprocessor 101 results in a miss in the L1 cache memory 102. As a result, the access request made by the L1 cache memory 102 becomes a hit in the L2 cache memory 103. Hereinafter, a case will be described in which an access request made by the microprocessor 101 results in a miss in the L1 cache memory 102 and an access request made by the L1 cache memory 102 also results in a miss in the L2 cache memory 103. More specifically, it is assumed that the microprocessor 101 issues an access request for the data D indexed by 0xAFF0 to the L1 cache memory 102. In action 150, a L1 cache memory miss has occurred and processing proceeds to action 152. In action 152, the cache lines 109A-D indexed by 0xAFF0 are accessed and the process flow proceeds to action 154. In action 154, since none of the cache lines 109A-D indexed by 0xAFF0 stores data D, a miss in the L2 cache memory occurs. The process flow then proceeds to action 160. In action 160, the desired data (data D) is obtained from the cache memory or main memory at the next level. In this example, since it is assumed that another memory 104 is the main memory, desired data is acquired from the main memory. The process flow then proceeds to action 162 where the data refill sequence is started.

  Prior to discussing the details of action 162, according to one or more aspects of the present invention, the cache line of the L2 cache memory 103 that stores invalid data (ie, the validity of a cache line). It is desirable to allow overwriting of data for a flag (indicating that the data stored in the cache line is invalid). Assuming that all of the cache lines (cache lines 109A to 109D) indexed by the specific pointer 110 in the L2 cache memory 103 store valid data, the L of the cache line in which the L2 cache memory 103 is located If the flag indicates that the corresponding cache line of the cache lines of the L1 cache memory 102 stores a copy of the data stored in that cache line of the L2 cache memory 103, preferably Overwriting data in the cache line of the L2 cache memory 103 is prohibited. Details regarding this are shown in actions 162-168 of FIG.

  In action 162, it is determined whether all of the cache lines (indexed by 0xAFF0) of the L2 cache memory 103 store valid data. If one or more of the cache lines of the L2 cache memory 103 stores invalid data, the processing flow preferably branches to action 164 where the desired data (data D) is one of the cache lines. Will be overwritten. However, in this example, since it is assumed that any cache line in the L2 cache memory 103 stores valid data, the processing flow branches to action 166 as a result of the determination in action 162. In action 166, only one of the cache lines for which the corresponding L flag (or L bit) 112 is false is overwritten with the desired data (data D). In other words, the L flag 112 indicates that the corresponding cache line of the L1 cache memory 102 stores a copy of the data stored in the cache line corresponding to the L flag 112 of the L2 cache memory 103. If so, overwriting of the cache line in the L2 cache memory 103 is prohibited. Therefore, for example, since the corresponding L bits 112A and 112C of the cache lines 109A and 109C are false, desired data (data D) can be overwritten on the cache lines 109A and 109C. Assuming that the data in the cache line 109C in the L2 cache memory 103 is overwritten, the L bit 112C is set to true (action 168), and a copy of the data D corresponds to the data cache memory 102B in the L1 cache memory 102. Refilled to the cash line.

  When refilling the L2 cache memory 103, there is no need to invalidate any data in the L1 cache memory 102, which is advantageous. In this way, it is possible to improve memory use efficiency, improve processing throughput, and improve processing data quality.

  Reference is now made to FIG. 3, which is a block diagram illustrating another aspect and embodiment of the present invention. Again, for the sake of brevity and clarity, the block diagram of FIG. 3 is referred to and described herein as an illustration of the apparatus 200. However, it should be understood that this description is readily applicable to various aspects of one or more methods having the same force. The apparatus 200 is preferably a microprocessor system having a microprocessor device 201, a first level cache memory 202, a next level cache memory 203, and a further memory 104.

  Although the first level cache memory 202 preferably includes an instruction cache memory 202A and a separate data cache memory 202B, the present invention contemplates another embodiment in which the instruction cache memory and the data cache memory are integrated. I want you to understand that In any case, each of instruction cache memory 202A and data cache memory 202B is preferably implemented as an N = 2 N-way set associative cache memory. Therefore, the data cache memory 202B has a way set 204 and a way set 205, and the instruction cache memory 202A has a way set 206 and a way set 207. The size of each wayset 204-207 in the instruction cache memory 202A and data cache memory 202B is preferably 8 kilobytes, and each of these cache lines preferably stores address tags, status flags and data (which may include instructions). It is possible to operate. Therefore, the predetermined index (or pointer) 208 can take a value in the range of 0x0000 to 0x1FFF (13 bits) in order to index all the cache lines of the way sets 204, 205, 206, and 207. For the sake of explanation, it is assumed that the value of the pointer 208 is 0x0FF0 and points to one cache line for each way set 204, 205, 206, 207.

  The next level cache memory 203 is also preferably an N-way set associative cache memory with N = 8. Therefore, the next-level cache memory 203 includes a way set 209, a way set 210, a way set 211, a way set 212, a way set 213, a way set 214, a way set 215, and a way set 216. In this specification, these way sets are also referred to as set 0, set 1, set 2, set 3, set 4, set 5, set 6, and set 7. According to this embodiment of the present invention, each way set 209-216 of the next level cache memory 203 is preferably larger in size than each way set 204-207 of the first level cache memory 202. For example, the size of each way set 209 to 216 of the cache memory 203 at the next level is preferably 32 kilobytes. Therefore, the size of each way set 209 to 216 in the cache memory 203 at the next level is four times that of each way set 204 to 207 in the first level cache memory 202.

  Note that the index (or pointer) 208A requires 15 bits in the range of 0x0000 to 0x7FFF to be able to access all cache lines of the next level cache memory 203. However, it has been described that the size of the pointer 208 is 13 bits of 0x0000 to 0x1FFF is sufficient to access all the cache lines of the first level cache memory 202. In an actual system, this apparent inconsistency is resolved as follows. When a cache miss occurs in the first level cache memory 202, the effective address is transferred to the next level cache memory 203 on the address bus. This address bus may have 32 bits of [31: 0], for example. Therefore, when the address is issued by the first level cache memory 202, the address bus bits [31:13] store the valid address tag bits, and the address bus bits [12: 0] are valid. Stores the index bit of the address. The effective address is passed from the first level cache memory 202 to the next level cache memory 203 in this state.

  However, the cache memory 203 at the next level processes the bits [14: 0] of the address bus as bits storing the index bits of the pointer 208A indicating the target eight cache lines. Therefore, the bits [14:13] of the address bus (part of the bits processed by the first level cache memory 202 as tag bits) are used as index bits or part of the pointer 208A by the cache memory 203 at the next level. used. When bits [14:13] of the address bus are 00, the pointer 208A stores an index of 0x0FF0 and points to the lowest eight cache lines of the way sets 209 to 216. When bits [14:13] of the address bus are 01, the pointer 208A stores an index of 0x0FF0 + 0x2000, and points to the eight cache lines on one of the way sets 209 to 216. Similarly, when bits [14:13] of the address bus are 10, the pointer 208A stores an index of 0x0FF0 + 0x4000, and points to the upper eight cache lines next to the way sets 209 to 216. Finally, when bits [14:13] of the address bus are 11, the pointer 208A stores an index of 0x0FF0 + 0x6000 and points to the eight cache lines further above the way sets 209 to 216. For this reason, bits [14:13] of the address bus can be regarded as an index offset, and this index offset can be any of 0x0000, 0x2000, 0x4000, and 0x6000 in this example.

  Each cache line of the next level cache memory 203 is preferably operable to store address tags, status flags and data (which may include instructions). However, unlike the embodiment of FIG. 1 of the present invention, the apparatus 200 of FIG. 3 preferably has the next level cache memory 203 not having an L flag in each cache line. This is because, if each cache line has an L flag, it is impossible to control or change the value of each L flag present in the cache line indexed by a different index offset. In fact, only 8 cache lines indexed by the same index offset can be processed at a time.

  The apparatus 200 according to this embodiment of the present invention preferably includes an additional memory 203A, and the additional memory 203A is incorporated in the next-level cache memory 203, but is not included in the next-stage cache memory 203. It may be provided separately from the level cache memory 203. The additional memory 203A preferably has a plurality of memory lines, the number of which corresponds to the number of cache lines present in a given wayset of the first level cache memory 202. Thus, in the example of FIG. 3, the additional memory 203A preferably has an 8 kilobyte memory line. Each memory line of the additional memory 203A preferably has an L flag corresponding to each way set of the plurality of cache lines 209 to 216 of the cache memory 203 at the next level. In this example, each memory line has an L flag corresponding to each of the four cache lines of each way set 209 to 216, and the total of the L flags is 32. More generally, the number of L flags in each memory line of the additional memory 203A is as follows: N is the number of way sets in the first level cache memory 202, and M1 is the cache line in each way set in the first level cache memory 202. M2 / M1 × N, where M2 is the number of cache lines in each wayset of the cache memory 203 at the next level. In this way, all of the L flags corresponding to the value obtained by adding all the index offsets of the first level cache memory 202 to the predetermined index are included in one memory line of the additional memory 203A. For this reason, the L flag can be controlled or changed all at once.

  Next, the operation of the apparatus 200 of FIG. 3 will be described in more detail with an example. In this example in which the microprocessor 201 issues a valid address (or access request) to the first level cache memory 202 via, for example, a 32-bit address bus, it is assumed that the microprocessor 201 requests data C. . Data C is not stored in the first level cache memory 202 or the next level cache memory 203. Therefore, bits [31:13] of the address bus store tag bits corresponding to data (data C) requested by the microprocessor 201. Bits [12: 0] of the address bus store an index bit, and this index bit points to an individual cache line of the way sets 204 to 207 of the first level cache memory 202. In this example, the index bit is 0x0FF0. Therefore, the pointer 208 includes two cache lines storing the instruction A and the instruction B in the instruction cache memory 202A, and the data A and the data B in the data cache memory 202B. Are accessed. Since neither of the two cache lines of the accessed data cache memory 202B stores data C, a cache miss occurs.

  Due to a cache miss, the first level cache memory 202 passes a valid address to the lower level cache memory 203 and attempts to satisfy the data access request in this cache memory. The first level cache memory 202 uses the address bus bits [12: 0] as an effective address index, whereas the next level cache memory 203 uses the address bus bits [14: 0]. The index bit of the effective address is processed as a stored bit. In this example, it is assumed that the value of bits [14:13] of the address bus is 01. This value corresponds to an index offset of 0x2000. Therefore, the pointer 208A takes a value of 0x0FF0 + 0x2000, and points to the corresponding eight cache lines of the way sets 209 to 216 of the lower level cache memory 203.

  Since none of the eight cache lines of the accessed lower level cache memory 203 stores data C, a cache miss occurs. Thus, the lower level cache memory 203 passes the effective address to yet another memory 104 (which may be one or more further cache memories and / or main memory). Thereafter, data C is returned for refilling each of the cache memories 202 and 203.

  In the lower level cache memory 203, it is determined which of the cache lines indexed by 0x0FF0 + 0x2000 is to be filled with the refill data (data C). If one or more of the cache lines in the lower level cache memory 203 stores invalid data, the refill data is preferably overwritten on one such cache line. However, in this example, any cache line in the lower level cache memory 203 stores valid data (that is, each valid flag of the cache line indicates that all data is valid). Assumed. Therefore, preferably, it is determined whether one or more of the cache lines stores data that is not cached in the first level cache memory 202, and if there is a cache line storing uncached data, Refill data is stored in one such cache line.

  To do this, the memory line indexed by 0x0FF0 (no offset) in the additional memory 203A is accessed. As with all memory lines, this memory line stores 32 L flags, which in this example have 1 bit. A true bit (logic high) indicates that the data of the corresponding cache line in the lower level cache memory 203 is also cached in the first level cache memory 202. A false (logical low) level indicates that the data of the corresponding cache line in the lower level cache memory 203 is not cached in the first level cache memory 202.

  In this example, bits [15: 8] of the memory line indexed by 0x0FF0 store L bits corresponding to the eight cache lines indexed by 0x0FF0 + 0x2000 in the lower level cache memory 203. The values of these L bits are all false except for the L bit 222 ([13] bit of the memory line), and this false bit corresponds to the cache line 218 of the lower level cache memory 203. The cache line 218 stores data (instruction A), and this data is cached in the instruction cache memory 202 A of the first level cache memory 202. More specifically, the instruction A is stored in the cache line of the way set 207 of the instruction cache memory 202A indexed by 0x0FF0.

  According to the present invention, since the L bit 222 is true, the cache line 218 is protected, and overwriting of refill data (data C) to the cache line is prohibited. Therefore, the refill data (data C) is refilled to one of the other cache lines indexed by 0x0FF0 + 0x2000 in the lower level cache memory 203. For example, the refill data can be overwritten on the cache line of the way set 212. Further, the refill data (data C) is written into one of the cache lines indexed by 0x0FF0 (such as the cache line of the way set 204) in the data cache memory 202B of the first level cache memory 202. For this reason, the data (data B) stored in the cache line of the way set 204 is overwritten by the refill data (data C). Bit [11] of the memory line indexed by 0x0FF0 in the additional memory 203A is set to true so that the data in the corresponding cache line in the wayset 212 of the lower level cache memory 203 is in the first level cache It is shown that the memory 202 is cached. Since the cache line indexed by 0x0FF0 in the wayset 204 of the data cache memory 202B no longer stores data B, an additional L bit change in the memory 203A must also be made. More specifically, a copy of data B is stored in the cache line 221 of the way set 209 of the lower level cache memory 203. This cache line 221 is indexed by 0x0FF0 + 0x6000, so it is necessary to update the L bit 225 corresponding to this cache line. This L bit 225 is present in bit [24] of the memory line indexed by 0x0FF0 in the additional memory 203A. Specifically, the L bit 225 is set from a false (logic low) state to a true (logic high) state. Note that the L bits 222, 225 are changed simultaneously.

  When refilling the lower level cache memory 203, it is advantageous because no data in the first level cache memory 202 need be invalidated. In this way, it is possible to improve memory use efficiency, improve processing throughput, and improve processing data quality.

  Reference is now made to FIG. 4, which is a block diagram illustrating yet another aspect and embodiment of the present invention. Again, for the sake of brevity and clarity, the block diagram of FIG. 4 is referred to and described herein as an illustration of the apparatus 300. However, it should be understood that this description is readily applicable to various aspects of one or more methods having the same force.

  The apparatus 300 is preferably a microprocessor system having a microprocessor device 301, a first level cache memory 202, a next level cache memory 303, and a further memory 104. The first level cache memory 202 is preferably substantially the same as the first level cache memory 202 described above and shown in FIG. For this reason, the first level cache memory 202 preferably has an instruction cache memory 202A and a data cache memory 202B, and each is implemented as an N = 2 set of associative cache memory. Each wayset 204-207 in the instruction cache memory 202A is preferably 8 kilobytes in size, and each of these cache lines is preferably operable to store address tags, status flags and data (which may include instructions). It is. Therefore, the pointer 208 takes a value in the range of 0x0000 to 0x1FFF (13 bits) in order to index each cache line of the way sets 204 to 207. For the sake of explanation, it is assumed that the value of the pointer 208 is 0x0FF0 and points to one cache line for each way set 204-207.

  The next level cache memory 303 is preferably substantially the same as the cache memory 203 described above and shown in FIG. 3 except for the additional memory 303A (this will be described in detail later in this specification). . For this reason, the lower level cache memory 303 is preferably an N-way set associative cache memory, which has eight way sets 209-216. These can also be referred to herein as set 0 to set 7, respectively. Furthermore, the size of each way set 209 to 216 of the cache memory 303 at the next level is preferably 32 kilobytes. That is, the size of each way set 209 to 216 is four times that of each way set 204 to 207 of the first level cache memory 202. Therefore, 15 bits in the range of 0x0000 to 0x7FFF are required for the index 208A to access any cache line in the cache memory 303 at the next level.

  As with the device 200 of FIG. 3, 13 bits with a size of the pointer 208 of 0x0000 to 0x1FFF are sufficient to access all the cache lines of the first level cache memory 202. However, the lower level cache memory 303 uses the 13 bits provided from the first level cache memory 202 and the least significant 2 bits of the tag bits of the effective address as 15 index bits. In this way, the index for the cache line of the lower level cache memory 303 is obtained by adding the index offset obtained from the additional 2 bits from the tag bit to the 13 index bits received from the first level cache memory 202. It is done. In this example, the index offset can take any value of 0x0000, 0x2000, 0x4000, and 0x6000.

  Each cache line of the lower level cache memory 303 is preferably operable to store address tags, status flags and data (which may include instructions). Similar to the cache memory 203 of FIG. 3, the lower level cache memory 303 of FIG. 4 preferably does not have an L flag in each cache shrine. Instead, the additional memory 303A has the L flag. Even if the additional memory 303A is built in the lower level cache memory 303, it is provided separately from the lower level cache memory 303. Also good.

  More specifically, the additional memory 303A preferably has a plurality of memory lines, and the number of memory lines is equal to the number of cache lines included in each wayset 204-207 of the first level cache memory 202. It corresponds. Thus, in the example of FIG. 4, the additional memory 303A preferably has an 8 kilobyte memory line. Each memory line of the additional memory 303A preferably has a respective bit group associated with each wayset 204-207 of the first level cache memory 202. For this reason, each bit group of each memory line of the additional memory 303 </ b> A is associated with one of the cache lines of the first level cache memory 202. Each bit group preferably has an L flag 350, an offset bit 352 and a way set bit 354. Similar to the above embodiment of the present invention, the L flag 350 stores a copy of data stored in a predetermined cache line of the lower level cache memory 303 in a corresponding cache line of the first level cache memory 202. Indicates whether or not In this embodiment of the present invention, a particular cache line associated with an L flag 350 includes an index (provided by the first level cache memory 202) and its group of index offset bits 352 and wayset bits 354. Pointed by a combination of Therefore, the cache line of the lower level cache memory 303 associated with a certain bit group of the additional memory 303A uses the index provided from the first level cache memory 202 as the index offset bit 352 (each way set 209˜ This is determined by selecting the way sets 209 to 216 corresponding to the way set bits 354 after offsetting them by a value corresponding to a total of eight cache lines, one from 216 cache lines. In this example, the index offset bit 352 has four values of 00 (corresponding to the index offset 0x0000), 01 (corresponding to the index offset 0x2000), 10 (corresponding to the index offset 0x4000), and 11 (corresponding to the index offset 0x6000). Can take either. The way set bits 354 are 000 (corresponding to set 0), 001 (corresponding to set 1), 010 (corresponding to set 2), 011 (corresponding to set 3), ..., 111 (corresponding to set 7). It can take any one of the values.

  Therefore, each memory line of the additional memory 303A is a cache line corresponding to a plurality of cache lines of the lower level cache memory 303 (that is, each index and index offset bit 352 and way set bit 354 of each bit group). ) For each of the L flags 350. Further, each bit group of each memory line of the additional memory 303 </ b> A corresponds to a specific one of the way sets 204 to 207 of the first level cache memory 202. Considering the number of way sets in the first level cache memory 202, the number and size of way sets in the lower level cache memory 303, and the size (ie, 1 bit) of each L flag 350, each memory line of the additional memory 303A Has 24 bits [23: 0].

  Next, the operation of the apparatus 300 of FIG. 4 will be described in more detail with an example. In this example in which the microprocessor 301 issues a valid address (or access request) to the first level cache memory 202 via, for example, a 32-bit address bus, the data C existing in the index 0x0FF0 Assuming that This data (data C) is not stored in the first level cache memory 202 or the lower level cache memory 303. Therefore, bits [31:13] of the address bus store tag bits corresponding to data (data C) requested by the microprocessor 301. Bits [12: 0] of the address bus store an index bit, and this index bit points to an individual cache line of the way sets 204 to 207 of the first level cache memory 202. In this example, the index bit is 0x0FF0, so that the pointer 208 includes two cache lines storing instruction A and instruction B in the instruction cache memory 202A and / or data A in the data cache memory 202B. Two cache lines storing data B are accessed. Since neither of the two cache lines of the accessed data cache memory 202B stores data C, a cache miss occurs.

  Due to a cache miss, the first level cache memory 202 passes a valid address to the lower level cache memory 303 and attempts to satisfy the data access request in this cache memory. The cache memory 303 at the next level uses bits [14: 0] of the address bus as bits storing index bits of effective addresses. In this example, it is assumed that the value of bits [14:13] of the address bus is 01. This value corresponds to an index offset of 0x2000. Therefore, the pointer 208A takes a value of 0x0FF0 + 0x2000, and points to the corresponding eight cache lines of the way sets 209 to 216 of the lower level cache memory 203.

  Since none of the eight cache lines of the accessed lower level cache memory 303 stores data C, a cache miss occurs. Thus, the lower level cache memory 303 passes the effective address to yet another memory 104 (which may be one or more further cache memories and / or main memory). Thereafter, data C is returned for refilling each of the cache memories 202 and 303.

  In the lower level cache memory 303, it is determined which of the cache lines indexed by 0x0FF0 + 0x2000 is to be filled with the refill data (data C). If one or more of the cache lines in the lower level cache memory 303 stores invalid data, the refill data is preferably overwritten on one such cache line. However, in this example, it is assumed that any cache line in the lower level cache memory 303 stores valid data. Therefore, preferably, it is determined whether one or more of the cache lines stores data that is not cached in the first level cache memory 202, and if there is a cache line storing uncached data, Refill data is stored in one such cache line.

  To do this, the memory line indexed by 0x0FF0 (no offset) in the additional memory 303A is accessed. As with all memory lines, this memory line stores four L flags 350A-D. Each L flag is 1 bit and corresponds to four cache lines of the lower level cache memory 303. A true bit (logic high) indicates that the data of the corresponding cache line in the lower level cache memory 303 is also cached in the first level cache memory 202. A false (logical low) level indicates that the data of the corresponding cache line in the lower level cache memory 303 is not cached in the first level cache memory 202.

  In this example, the only index offset bit 352D is 01, which corresponds to an offset of 0x2000. This bit group is associated with the cache line 321 of the lower level cache memory 303 by the combination of the offset and the index provided from the first level cache memory 202 and the way set bit 354D (corresponding to the set 5). It is shown. The L bit 350D of this bit group is true, indicating that overwriting of the cache line 321 with refill data (data C) is prohibited. On the other hand, data can be refilled to any other cache line (cache line 358 or the like) indexed by 0x0FF0 + 0x2000 in the lower level cache memory 303.

  The refill data (data C) is written to one of the cache lines (such as the cache line 352 of the way set 204) indexed by 0x0FF0 in the data cache memory 202B of the first level cache memory 202. For this reason, the data (data B) originally stored in the cache line 352 is overwritten by the refill data (data C). Since cache line 352 indexed by 0x0FF0 in wayset 204 of data cache memory 202B no longer stores data B, an additional L bit 350 change in memory 303A must also be made. More specifically, a copy of data B is stored in the cache line 324 of the way set 209 of the lower level cache memory 303. This cache line 324 is indexed by 0x0FF0 + 0x6000, so it is necessary to update the L bit 350A corresponding to this cache line 324. This L bit 350A is present in bit [5] of the memory line indexed by 0x0FF0 in the additional memory 303A. In fact, the L bit 350A forms a group with an index offset bit 352A having a value of 11 and a way set bit 354A having a value of 000. That is, they point to the cache line 324 of the lower level cache memory 303. In order to properly update the L bit associated with the cache lines 358 and 324, the index offset bit 352 and the way set bit 354 associated with the way set 104 of the first level cache memory 202 are updated. More specifically, the index offset bit 352A is changed from 11 to 01, and the way set bit 354A is changed from 000 to 011. Thus, this bit group is associated with the cache line 358 instead of the cache line 324 of the lower level cache memory 303.

  When refilling the lower level cache memory 303, there is no need to invalidate any data in the first level cache memory 202. In this way, it is possible to improve memory use efficiency, improve processing throughput, and improve processing data quality.

  Although the invention has been described herein using specific embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. For this reason, it will be understood that these exemplary embodiments may be variously modified and other configurations may be devised without departing from the spirit and scope of the invention as set forth in the appended claims.

FIG. 2 is a block diagram illustrating aspects of one or more methods and apparatus suitable for controlling a hierarchical cache memory in accordance with one or more embodiments of the present invention. 6 is a flowchart illustrating certain operations / functions that may be performed and / or implemented by one or more of the embodiments of the present invention. FIG. 6 is a block diagram illustrating another aspect of one or more alternative methods and apparatus suitable for controlling a hierarchical cache memory, in accordance with one or more alternative embodiments of the present invention. FIG. 5 is a block diagram illustrating another aspect of one or more methods and apparatus suitable for controlling a hierarchical cache memory, in accordance with one or more alternative embodiments of the present invention.

Explanation of symbols

101 Microprocessor 102, 103 Cache memory 104-107 Wayset 109A-D Cache line 110 Pointer 112 Flag 202 Level cache memory 203 Cache memory 301 Microprocessor 303 Cache memory 303A Additional memory 324 Cache line 350 Bit 350 Flag 352 Offset bit 352 cache line 354 way set bit 358 cache line

Claims (20)

A plurality of way sets and a plurality of cache lines are associated, each of the plurality of cache lines having a first level cache memory operable to store address tags and data;
A plurality of way sets and a plurality of cache lines are associated, each of the plurality of cache lines having a next level cache memory operable to store address tags, status flags and data; ,
An additional memory associated with the next level cache memory and having a plurality of memory lines, wherein the number of memory lines is the number of cache lines included in a given set of the first level cache memory Corresponding to
An index is associated with each cache line of the first level cache memory, and each memory line of the additional memory is associated with a plurality of cache lines of each way set of the cache memory at the next level. All of the L flags corresponding to the value obtained by adding the index offset of the first level cache memory to a predetermined index are included in one memory line of the additional memory, and the next level The cache memory does not include an L flag corresponding to each cache line.   The apparatus of claim 1, wherein the number of memory lines of the additional memory is equal to the number of cache lines included in a predetermined wayset of the first level cache memory.   2. The apparatus of claim 1, wherein the first level cache memory includes N way sets, the next level cache memory includes M way sets, and M is greater than N.   The apparatus of claim 3 wherein N is 2 and M is 8.   The apparatus of claim 1, wherein all L flags associated with the predetermined index can be controlled at one time.   The apparatus of claim 1, wherein all L flags associated with the predetermined index can be changed at a time. Whether one of the cache lines of the first level cache memory has been refilled by the data stored in the cache line of the next level cache memory corresponding to each L flag of the additional memory The apparatus of claim 1, further comprising a processor operable to indicate whether.   The apparatus of claim 7, wherein the processor is further operable to set the L flag of each predetermined memory line of the additional memory substantially simultaneously.   2. The apparatus of claim 1, wherein each way set in the next level cache memory is larger than each way set in the first level cache memory.   10. The apparatus of claim 9, wherein each wayset in the next level cache memory is at least four times greater than each wayset in the first level cache memory.   A first index for accessing the first level cache memory; and a second index for accessing the next level cache memory; and the first index for accessing the first level cache memory. 10. The apparatus of claim 9, wherein the number of bits required by the second index is less than the number of bits required by the second index to access the next level cache memory. An address bus logically associated with the first level cache memory and the next level cache memory;
Said cache miss in first level cache memory is valid address is passed through the address bus to the next stage level cache memory when they occur, the first bit set in said address bus comprises a tag bit of the effective address The apparatus of claim 1, wherein a second set of bits in the address bus includes an index bit of the effective address. The next-level cache memory has at least one of the second bit set and the first bit set to access a selected one of the cache lines in at least one selected one of the way sets. And the next level cache memory treats at least a portion of the first bit set as index bits to extend an index bit of the second bit set. . A plurality of way sets and a plurality of cache lines are associated, each of the plurality of cache lines is operable to store an address tag and data, and an index is associated with each cache line. Having a first level cache memory;
A plurality of way sets and a plurality of cache lines are associated, each of the plurality of cache lines having a next level cache memory operable to store address tags, status flags and data; ,
An additional memory associated with the next level cache memory and having a plurality of memory lines, each memory line of the additional memory having a plurality of waysets of the next level cache memory; All of the L flags corresponding to a value obtained by adding the index offset of the first level cache memory to a predetermined index are included in one memory line of the additional memory. And the next level cache memory does not include a corresponding L flag in each cache line.   The apparatus of claim 14, wherein the first level cache memory is a direct map cache.   15. The apparatus of claim 14, wherein the first level cache memory is an L1 cache memory and the next level cache memory is an L2 cache memory. 15. The apparatus of claim 14, wherein all of the L flags associated with the predetermined one of the indexes can be controlled or changed simultaneously. A plurality of way sets and a plurality of cache lines are associated, each of the plurality of cache lines is operable to store an address tag and data, and an index is associated with each cache line. Controlling the first level cache memory;
Controlling a next level cache memory associated with a plurality of way sets and a plurality of cache lines, each of the plurality of cache lines being operable to store an address tag, a status flag and data. Have
Controlling an additional memory associated with the next level cache memory and having a plurality of memory lines, wherein each memory line of the additional memory is associated with each of the next level cache memories. All of the L flags corresponding to a value obtained by adding the index offset of the first level cache memory to a predetermined index are included in one memory of the additional memory. Included in the line, and
Whether one of the cache lines of the first level cache memory has been refilled with the data stored in the cache line of the next level cache memory corresponding to the L flag of each of the additional memories. Has a step of setting to indicate whether
A method wherein the next level cache memory does not include an L flag corresponding to each cache line. Passing a valid address through an address bus to the next level cache memory when a cache miss occurs in the first level cache memory, the first bit set in the address bus being a tag of the valid address 19. The method of claim 18, comprising a bit, wherein a second set of bits in the address bus includes an index bit of the effective address.   Identifying a selected one of the cache lines in at least one wayset in the next level cache memory from the second bit set and at least a portion of the first bit set. Item 20. The method according to Item 19.

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