JPH01199251A - Access control system for cache memory - Google Patents

Abstract

PURPOSE:To prevent the address having the highest access frequency from vanishing out of a high-order or low-order cache by giving the access control to the exchange of the low-order caches with consideration taken into a fact that the exchange of the low-order caches exists on the high-order caches, as well. CONSTITUTION:Some of those lines are first exchanged based on the LRUs which are updated with accesses received from a means A which updates the LRUs of both internal and external caches and a line selection means B which drives out the contents of the oldest line. The LRUs are updated so as to decide that the accesses are also given to those lines existing in the low-order caches in the blocks to be exchanged during the progress of a means which updates the LRUs of the low-order caches. Otherwise the exchange line of the low-order caches is decided by selecting the oldest line via a low-order cache out of those lines which are not included in the high-order caches and included in the low- order caches.

Description

[Detailed Description of the Invention] (Summary) The present invention relates to an access control method for a cache memory provided between a central processing unit and a main storage device, and aims to improve the accuracy of access to the cache memory. An access control method for a cache memory provided between a device and a main storage device, the LRU of each of an upper cache memory that may be provided inside the central processing unit and a lower cache memory that may be provided externally, based on hit information. an LRU updating means for updating the LRU;
and a line selection means for selectively replacing the contents of the oldest line based on the RU, and the line selection means exists in the upper cache in the block to be replaced during the step 11j of updating the LRU of the lower cache. Either update the LRU so that the line is considered to have been accessed, or select the oldest one from the lower cache among those that exist in the lower cache but not in the upper cache when determining a replacement line. The configuration is such that the replacement line is determined by doing this.

[Industrial application field]

The present invention relates to an access control method for a cache memory provided between a central processing unit and a main storage device.

In data processing equipment, in order to eliminate the difference in processing speed between the high-speed processing of the central processing unit (CPU) and the slow processing speed of the main storage unit (MSU), a high-speed cache memory is installed between them.
(hereinafter referred to as cache) is provided. The same is true for microprocessors; as the degree of integration increases, small-capacity caches are installed inside the chip, and additional caches are installed externally to supplement the capacity, increasing the hit rate and improving processing performance. ing. Cache is usually managed in units called lines, which consist of multiple bytes, and when registering a new line in the cache,
If there is no free line, one of the lines already registered in the cache will be evicted.

[Conventional technology]

FIG. 1O is a diagram illustrating a cache access control method based on the set associative method.
Data exchange is controlled by the U (Least Recently Used) method. In this method, the order of access up to the present moment among lines in the same set is stored, and the oldest lines that have not been accessed recently are replaced.

For example, “00” in the shaded part of the line of set 1 of MSU
If ``101χ'' and ``FFFOIX'' are stored in WAYO and WAYI of set 1 of the cache, respectively, then they correspond to the same set 1, but ``0OIOI
When an address other than “X” and “FFFOIX” is accessed, in the LRU method, “0OIOIX” and “FFFOIX” are
FOIX" that has not been used recently.

FIG. 11 is a diagram showing a hierarchical cache configuration. As shown in FIG. 12, which shows the internal configuration in detail, the upper cache corresponds to the internal cache, and the lower cache corresponds to the external cache. The internal cache and external cache differ in capacity, but they have a tag section (TAG) that stores addresses and a data section (DAG) that stores data.
TA) and a control unit (TA) that controls these writes/reads.
The basic structure is CNT). Usually, an internal cache is provided inside the CPU, and an external cache is connected to the internal cache via an address bus (ADD), a data bus (D), and a control signal line (S), and is further connected to the MSU. In a hierarchical cache configuration as shown in FIG. 11, normally the upper cache is accessed more frequently and the lower cache is accessed less frequently. Therefore, for read access, the upper cache has a hint (
Since the lower cache L is not accessed while the bit is being accessed, the lower cache line corresponding to the most frequently accessed address may be evicted from the lower cache line because the access frequency is low. At this time, if by chance the access is evicted from the upper cache and also evicted from the lower cache, the next access will be from the upper cache,
This results in a miss in which the lower address disappears, resulting in a drop in access performance.

[Problem to be solved by the invention]

FIG. 13 is a diagram explaining the conventional problems.

In the figure, the left side shows the contents of the upper cache, and the right side shows the contents of the lower cache. With reference to this figure, a case will be described in which the above-mentioned lower line corresponding to the frequently accessed address is evicted and then the upper line is also evicted. The left end shows the access order, with addresses A, B, C, and D corresponding to the same set.

It is assumed that E is accessed in this order, and A has the highest access frequency. The contents of the upper and lower cache ° indicate the contents of each line after the access shown on the left, and the subscript number indicates the access order between each WAY (the younger the number, the older the content is and the content to be replaced. ). Further, a dash (-) in the figure indicates that a line does not exist. In the upper cache, after address A is accessed to WAYO in the third from the bottom,
When address E is accessed to WAYI, address D of -AYI is updated to E. Next, when address D is accessed to WAYO, address A of WAYO is updated to D. At this point, WAYO becomes address D and AYI becomes address E, and address A disappears from the upper cache. Similarly, in the lower cache, when the third -AYO from the bottom changes from the address A, the address A disappears from all WAYs in the lower cache at this point. In this way, a situation arises in which the most frequently occurring address A is evicted from both the upper and lower caches.

An object of the present invention is to perform access control in accessing a hierarchical cache configuration by controlling the replacement of lower-level caches by taking into consideration that not only lower-level caches are accessed but also higher-level caches. An object of the present invention is to provide an access control method that prevents high addresses from disappearing from upper and lower caches.

[Means and operations for solving the problems] FIG. 1 is a diagram showing the basic configuration of the present invention. A is a means for updating the LRU of internal and external caches, and B is a line selection means for evicting the contents of the oldest line. In such a configuration, the LR updated by accessing
In a hierarchical cache memory access control method in which lines to be replaced are replaced based on U, while the means for updating the LRU of the lower cache is in progress, the lines existing in the upper cache in the block to be replaced are in progress. Either update the LRU so that it is assumed that the line that has been accessed has been accessed, or when deciding which line to replace in the lower cache, the oldest line that exists in the lower cache but not in the upper cache. The replacement line is determined by selecting the item from the lower cache.

〔Example〕

FIG. 2 is a block diagram of an internal cache to which the cache memory access control method according to the present invention is applied. The tag section (TAG) has an -AYO line and a WAYI line as shown in detail in FIG. -4 selects the line, and further specifies write or read address A31-11
is input. The designated address A31-11 is also input to comparators COMP 1 and COMP 2 at the same time, and is compared with the outputs from -AYO and WAYI in these comparators, and if they match, it is output to the control unit CNT. The outputs of the comparators COMP 1 and COMP 2 are connected to the control section C.
LR with line selection address Ar0-4 via NT
It is input to an internal control circuit (LiLRIJ) that updates using the U method. The output of the control circuit (LiLRtl) is input to the control unit CNT, and is also output to an external cache to be described later as a fetch WayA.

Furthermore, the line selection address A to-2 from the instruction control unit INCl is input to -AYO and WAYI of the data unit (DATA) via the internal address bus IADB. The outputs of the comparators COMP 1 and COMP 2 are input to -AYO and WAYI of the data section, and data at the designated address is output. Output data DA
TA is connected to the instruction control unit INC via the internal data bus IDB.
2. 2 is an update signal for updating the line inputted from the control unit CNT to the TAG.

FIG. 3 is a block diagram of an external cache to which the present invention is applied. In the external cache, the external control circuit (LeLRU) that updates using the LRU method is connected to the internal control circuit (LeLRU) described above.
Comparator COMP 3 is provided in place of iLRU) and further compares the update signals l and W with the acquisition WayA.
and COMP 4 are added. From each comparator, the signal 1-(bit) and the update signal I are inputted to the control CNT, and simultaneously sent to each WAY of the data section (DATA). For simplicity, WAYI and WAY2 are omitted, and these have the same configuration as WAYO and WAY3.

FIGS. 4(a) and 4(b) show cache configuration diagrams, and (a)
) is an internal cache, and (b) is an external cache.

E indicates that an external cache line exists, and l indicates that an internal cache line exists. Li is WAY LRU control of internal cache, Le is W of external cache
Shows AY's LRUIJI. The upper and lower caches have a fixed correspondence as shown by the diagonal lines, and in the present invention, when accessing the lower level, it is made to appear as if the upper level is also accessed, or the cache does not exist in the upper level but exists in the lower level. control to drive out the oldest among those that

Figures 5(a) and (b) are the LRs shown in Figures 2 and 3.
2 is a block diagram of a U control circuit, in which (a) is applied to method 1, which will be described later, and (b) is applied to method 2, which will be described later. FIG. As mentioned above, the access control method of the present invention includes two methods. In one method, the LRU does not exist in the upper cache, but when the lower cache is accessed, the LRU does not exist in the upper cache. It also has a function to update it as if it had been accessed.
The LRU is updated only based on hints from the lower cache, and has a function of selecting an older one from among those existing in the lower cache but not in the upper cache when expelling one. In other words, in either method, items that exist in both the upper and lower caches are left without being evicted, and when a frequently occurring item happens to be evicted from the upper cache, it remains in the lower cache. This prevents addresses from disappearing frequently.

The LRU*[11 circuit shown in (a) is the RAM5 of the LRU.
1, an LRU update circuit 52, and a replacement determination circuit 53 that determines replacement, and the LRU shown in (b)
The RU control circuit includes a RAM 51, an update circuit 52, and a replacement WAY determining circuit 54. Details of these circuits are shown in FIG. 7(a).

As shown in detail in (b) and Figures 8(a) to (c),
The explanation will be given later.

FIG. 6 is a diagram illustrating the reference order of WAYs.

As shown in the figure, a 4-way LRU is shown, and the reference order relationship of each way is shown by six arrows aw f. in this case,
For example, when a is “0”, the WAYO with the smaller number is 1^
This indicates that the WAYO is older than Y1, and when it is "l", it indicates that the WAYO with the smaller number is newer than -AYI. Similarly, for example, when f is "0", -AY2
is older than WAY3, and when it is "1", it indicates that WAY2 is newer than -AY3.

FIGS. 7(a) and 7(b) are block diagrams showing details of FIG. 5(a), where (a) is a detailed block diagram of the LRU update circuit 52;
b) is a detailed block diagram of the replacement determination circuit 53. In (a), for example, "hito" indicates that the access was made using -AYO as a hint, and "hit3" indicates that the WA
This shows that the access was made by hitting Y3. signal! indicates that the line exists in the upper cache; for example, "IO" indicates that the contents of WAYO exist in the upper cache. MPX indicates a multiplexer, and normal LRU updates are performed using bit signals, but when it is regarded as if the upper cache has been accessed as in method 1, update information is controlled by an update signal (2). That is, first, after performing an update using the ■ signal, “
update by "hit".Also, a out to f
out is the output of the RAM 51 of the LRU, and this output is also input to the replacement determination circuit 53 as shown in (b). Roughly, ai, 1 to fifi are input to the RAM 51 and become the contents to rewrite the RAM. Blocks 71a-71f
all have the same configuration, for example, block 71a (
As shown in the truth table in c), for example, Hl6 and Hl among the signals H1 selected by the multiplexer MPX, Hl. and Hl.

When both are "0.0" or "1,1", aim outputs aout as is, and when Hl and HII are different, a! “0” or “l” is output from R. Reference numerals 72a to 72d in (b) indicate replacement determination circuits, which are logics that search for which WAY is the oldest when actually expelling. H! R of LRU according to the truth table of
The data is written to AM and the LRU is updated.

8(a) to 8(c) are circuit configurations applied to method 2, and (a) is the same as FIG. 7(a). (b) and (c) are detailed configuration diagrams of the replacement way determining circuit 54. Since the operation and the like are similar to those in FIG. 7, their explanation will be omitted.

FIG. 9 is an LRU update timing chart of the access control system according to the present invention, and is a timing chart for outputting the take-in Way from the CPU in the circuits shown in FIGS. 2 and 3. As shown in FIGS. 4(a) and 4(b), there are 16 external cache lines (shaded area) corresponding to one line (shaded area) of the internal cache.

Among these, there is at most one each that exists in -AYO and -AYI of the internal cache. When importing into WAYO in the internal cache, 1-1 and WO are used to search for other lines that have been imported into WAYO. If found, that line would have been kicked out of WAYO, making it 1-0.

The CPU outputs the address ADD in response to the clock CLK, and the internal cache takes in the address and stores the data DA.
Data is taken in by TA. The control circuit LiLRU of the internal cache 2 outputs the take-in way signal A to the external cache. Control of the external cache is controlled by the imported W
It is divided into cases where there is no ay and cases where there is an imported way, and after the LRU is updated by ■, the bit is updated, and as mentioned above, other lines are imported into WAYO as Search to see if there are any. In other words, there is no imported Way (mis
s), m1ss, +l1iss... On the other hand, there was a way that was captured (b it)
In this case, it becomes I-0.

〔Effect of the invention〕

As explained above, according to the present invention, in a hierarchical cache, replacement of lower caches is controlled by taking into consideration not only accesses to lower caches but also existence in upper caches. Access accuracy can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention. FIG. 2 is a diagram showing the internal cache block configuration of an embodiment of the present invention. FIG. 3 is a diagram of the external cache block configuration of an embodiment of the present invention. Figures (a) and (b) show detailed configuration examples of internal and external caches. Figures 5 (a) and (b) are LRU control circuit block diagrams, Figure 6 is a WAY reference order explanatory diagram, and Figure 7 (a) and (b) are LRU control circuit detailed diagrams (method 1). , (c) is the truth table, and Figures 8 (a) to (c) are detailed diagrams of the LRtJ control circuit (
Method 2), FIG. 9 is an access time chart of the present invention, FIG. 1O is an explanatory diagram of the set associative method, FIG. 11 is a hierarchical cache configuration diagram, and FIG. The control configuration diagram and FIG. 13 are diagrams for explaining conventional problems. (Explanation of symbols) A: LRU update means, B: line selection means,
lNCl, lNC2...instruction control unit, CNT...
・Control section, TAG...Tag section, DATA...
Data section, 51...LRU RAM, 52...
- LRU update circuit, 53... Replace decision circuit, 54... Replace Way decision circuit.

Claims (1)

[Claims] 1. An access control method for a cache memory provided between a central processing unit and a main storage device, comprising an upper cache memory provided inside the central processing unit and a lower cache memory provided externally. LRU update means (A) for updating each LRU based on hit information; and line selection means (B) for selectively replacing the contents of the oldest line based on the LRU; During the procedure for updating the LRU of the block to be replaced, the LRU is updated so that it is assumed that a line existing in the upper cache in the block to be replaced has also been accessed, or when determining the replacement line in the lower cache, A cache memory access control method that determines replacement lines by selecting the oldest line from the lower cache that exists in the lower cache but not in the upper cache.