JP4094437B2 - Method for manufacturing electro-optical device - Google Patents

Description

【００６７】
ここでＱはＮ又はＣ−Ｒ（炭素鎖）であり、Ｍは金属、金属酸化物又は金属ハロゲン化物であり、Ｒは水素、アルキル、アラルキル、アリル又はアルカリルであり、Ｔ１、Ｔ２は水素、アルキル又はハロゲンのような置換基を含む不飽和六員環である。
【００６８】
また、正孔輸送層としての有機材料は芳香族第三アミンを用いることができ、好ましくは次のような一般式で表されるテトラアリルジアミンを含む。
【００６９】
【化２】

【００７０】
ここでＡｒｅはアリレン群であり、ｎは１から４の整数であり、Ａｒ、Ｒ₇、Ｒ₈、Ｒ₉はそれぞれ選択されたアリル群である。
【００７１】
また、ＥＬ層、電子輸送層又は電子注入層としての有機材料は金属オキシノイド化合物を用いることができる。金属オキシノイド化合物としては以下のような一般式で表されるものを用いれば良い。
【００７２】
【化３】

【００７３】
ここでＲ₂−Ｒ₇は置き換え可能であり、次のような金属オキシノイド化合物を用いることもできる。
【００７４】
【化４】

【００７５】
ここでＲ₂−Ｒ₇は上述の定義によるものであり、Ｌ₁−Ｌ₅は１から１２の炭素元素を含む炭水化物群であり、Ｌ₁、Ｌ₂又はＬ₂、Ｌ₃は共にベンゾ環を形成することができる。また、次のような金属オキシノイド化合物でも良い。
【００７６】
【化５】

【００７７】
ここでＲ₂−Ｒ₆は置き換え可能である。このように有機ＥＬ材料としては有機リガンドを有する配位化合物を含む。但し、以上の例は本発明のＥＬ材料として用いることのできる有機ＥＬ材料の一例であって、これに限定する必要はまったくない。
【００７８】
また、本発明ではＥＬ層の形成方法としてインクジェット方式を用いるため、好ましいＥＬ材料としてはポリマー系材料が多い。代表的なポリマー系材料としては、ポリパラフェニレンビニレン（ＰＰＶ）系、ポリフルオレン系、ポリビニルカルバゾール（ＰＶＫ）系などの高分子材料が挙げられる。カラー化するには、例えば、赤色発光材料にはシアノポリフェニレンビニレン、緑色発光材料にはポリフェニレンビニレン、青色発光材料にはポリフェニレンビニレン及びポリアルキルフェニレンが好ましい。
【００７９】
なお、ＰＰＶ系有機ＥＬ材料としては様々な型のものがあるが、例えば以下のような分子式が発表されている。
（「H. Shenk,H.Becker,O.Gelsen,E.Kluge,W.Kreuder,and H.Spreitzer,“Polymers for Light Emitting Diodes”,Euro Display,Proceedings,1999,p.33-37」）
【００８０】
【化６】

【００８１】
【化７】

【００８２】
また、特開平１０−９２５７６号公報に記載された分子式のポリフェニルビニルを用いることもできる。分子式は以下のようになる。
【００８３】
【化８】

【００８４】
【化９】

【００８５】
また、ＰＶＫ系有機ＥＬ材料としては以下のような分子式がある。
【００８６】
【化１０】

【００８７】
ポリマー系有機ＥＬ材料はポリマーの状態で溶媒に溶かして塗布することもできるし、モノマーの状態で溶媒に溶かして塗布した後に重合することもできる。モノマーの状態で塗布した場合、まずポリマー前駆体が形成され、真空中で加熱することにより重合してポリマーになる。
【００８８】
具体的な発光層としては、赤色に発光する発光層にはシアノポリフェニレンビニレン、緑色に発光する発光層にはポリフェニレンビニレン、青色に発光する発光層にはポリフェニレンビニレン若しくはポリアルキルフェニレンを用いれば良い。膜厚は３０〜１５０ｎｍ（好ましくは４０〜１００ｎｍ）とすれば良い。
【００８９】
また、代表的な溶媒としてはトルエン、キシレン、シメン、クロロフォルム、ジクロロメタン、γブチルラクトン、ブチルセルソルブ又はＮＭＰ（Ｎ−メチル−２−ピロリドン）が挙げられる。また、塗布液の粘度を上げるための添加剤を加えることも有効である。
【００９０】
但し、以上の例は本発明のＥＬ材料として用いることのできる有機ＥＬ材料の一例であって、これに限定する必要はまったくない。インクジェット法に使用できる有機ＥＬ材料については、特開平１０−０１２３７７号公報に記載されている材料を全て引用することができる。
【００９１】
なお、インクジェット方式はバブルジェット（登録商標）方式（サーマルインクジェット方式ともいう）とピエゾ方式とに大別されるが、本発明を実施するにはピエゾ方式が望ましい。両者の違いについて図１９を用いて説明する。
【００９２】
図１９（Ａ）はピエゾ方式の例であり、１９０１はピエゾ素子（圧電素子）、１９０２は金属パイプ、１９０３はインク材料とＥＬ材料の混合液（以下、ＥＬ形成溶液という）である。電圧がかかるとピエゾ素子が変形し、金属パイプ１９０２も変形する。その結果、内部のＥＬ形成溶液１９０３は液滴１９０４として発射される。このようにピエゾ素子にかかる電圧を制御することでＥＬ形成溶液の塗布を行う。この場合、ＥＬ形成溶液１９０３は物理的な外圧によって押し出されるため、組成等になんら影響はない。
【００９３】
図１９（Ｂ）はバブルジェット（登録商標）方式の例であり、１９０５は発熱体、１９０６は金属パイプ、１９０７はＥＬ形成溶液である。通電されると発熱体１９０５が発熱し、ＥＬ形成溶液１９０７中に気泡１９０８が発生する。その結果、気泡によってＥＬ形成溶液１９０７は押し出され、液滴１９０９として発射される。このように発熱体への電流を制御することでＥＬ形成溶液の塗布を行う。この場合、ＥＬ形成溶液１９０７は発熱体によって熱せられるため、ＥＬ材料の組成によっては悪影響を与える可能性がある。
【００９４】
また、実際にデバイス上にインクジェット方式を用いてＥＬ材料を塗布形成すると図２０に示すような形でＥＬ層が形成される。図２０において、９１は画素部、９２、９３は駆動回路であり、画素部９１には複数の画素電極９４が形成されている。図示されないが、各画素電極はそれぞれ電流制御用ＴＦＴに接続されている。また、実際には画素電極９４を個々に分離するバンク（図１参照）が設けられているが、ここでは図示しない。
【００９５】
そして、インクジェット方式により赤色発光のＥＬ層９５、緑色発光のＥＬ層９６、青色発光のＥＬ層９７を形成する。このとき、まず赤色発光のＥＬ層９５を全て形成した後で、順次緑色発光のＥＬ層９６、青色発光のＥＬ層９７を形成すれば良い。また、ＥＬ形成溶液に含まれる溶媒を除去するためにベーク（焼成）処理が必要である。このベーク処理は全てのＥＬ層を形成した後で行っても良いし、各色のＥＬ層が形成し終えた時点で個別に行っても良い。
【００９６】
また、ＥＬ層を形成する際、図２０に示すように、赤色発光のＥＬ層９５が形成される画素（赤色に対応する画素）、緑色発光のＥＬ層９６が形成される画素（緑色に対応する画素）及び青色発光のＥＬ層９７が形成される画素（青色に対応する画素）が、常に各色が互いに接するような状態となるようにする。
【００９７】
このような配置はいわゆるデルタ配置と呼ばれるものであり、良好なカラー表示を行う上で有効である。インクジェット方式の利点は、各色のＥＬ層を個々に打ち分けることができる点にあるため、デルタ配置の画素部を有するＥＬ表示装置に用いることが最も好ましい実施形態と言える。
【００９８】
また、ＥＬ層４７を形成する際、処理雰囲気は極力水分の少ない乾燥雰囲気とし、不活性ガス中で行うことが望ましい。ＥＬ層は水分や酸素の存在によって容易に劣化してしまうため、形成する際は極力このような要因を排除しておく必要がある。例えば、ドライ窒素雰囲気、ドライアルゴン雰囲気等が好ましい。
【００９９】
以上のようにしてＥＬ層４７をインクジェット方式により形成したら、次に陰極４８、保護電極４９が形成される。また、本明細書中では、画素電極（陽極）、ＥＬ層及び陰極で形成される発光素子をＥＬ素子と呼ぶ。
【０１００】
陰極４８としては、仕事関数の小さいマグネシウム（Ｍｇ）、リチウム（Ｌｉ）、セシウム（Ｃｓ）、バリウム（Ｂａ）、カリウム（Ｋ）、ベリリウム（Ｂｅ）若しくはカルシウム（Ｃａ）を含む材料を用いる。好ましくはＭｇＡｇ（ＭｇとＡｌをＭｇ：Ａｇ＝１０：１で混合した材料）でなる電極を用いれば良い。他にもＭｇＡｇＡｌ電極、ＬｉＡｌ電極、また、ＬｉＦＡｌ電極が挙げられる。また、保護電極４９は陰極４８を外部の水分等から保護膜するために設けられる電極であり、アルミニウム（Ａｌ）若しくは銀（Ａｇ）を含む材料が用いられる。この保護電極４９には放熱効果もある。
【０１０１】
なお、ＥＬ層４７及び陰極４８は大気解放せずに乾燥された不活性雰囲気中にて連続的に形成することが望ましい。これはＥＬ層として有機材料を用いる場合、水分に非常に弱いため、大気解放した時の吸湿を避けるためである。さらに、ＥＬ層４７及び陰極４８だけでなく、その上の保護電極４９まで連続形成するとさらに良い。
【０１０２】
また、５０は第３パッシベーション膜であり、膜厚は１０ｎｍ〜１μm（好ましくは２００〜５００ｎｍ）とすれば良い。第３パッシベーション膜５０を設ける目的は、ＥＬ層４７を水分から保護する目的が主であるが、第２パッシベーション膜４５と同様に放熱効果をもたせても良い。従って、形成材料としては第１パッシベーション膜４１と同様のものを用いることができる。但し、ＥＬ層４７として有機材料を用いる場合、酸素との結合により劣化する可能性があるので、酸素を放出しやすい絶縁膜は用いないことが望ましい。
【０１０３】
また、上述のようにＥＬ層は熱に弱いので、なるべく低温（好ましくは室温から１２０℃までの温度範囲）で成膜するのが望ましい。従って、プラズマＣＶＤ法、スパッタ法、真空蒸着法、イオンプレーティング法又は溶液塗布法（スピンコーティング法）が望ましい成膜方法と言える。
【０１０４】
このように、第２パッシベーション膜４５を設けるだけでも十分にＥＬ素子の劣化を抑制することはできるが、さらに好ましくはＥＬ素子を第２パッシベーション膜４５及び第３パッシベーション膜５０というようにＥＬ素子を挟んで形成された二層の絶縁膜によって囲み、ＥＬ層への水分、酸素の侵入を防ぎ、ＥＬ層からのアルカリ金属の拡散を防ぎ、ＥＬ層への熱の蓄積を防ぐ。その結果、ＥＬ層の劣化がさらに抑制されて信頼性の高いＥＬ表示装置が得られる。
【０１０５】
また、本発明のＥＬ表示装置は図１のような構造の画素からなる画素部を有し、画素内において機能に応じて構造の異なるＴＦＴが配置されている。これによりオフ電流値の十分に低いスイッチング用ＴＦＴと、ホットキャリア注入に強い電流制御用ＴＦＴとが同じ画素内に形成でき、高い信頼性を有し、且つ、良好な画像表示が可能な（動作性能の高い）ＥＬ表示装置が得られる。
【０１０６】
なお、図１の画素構造においてスイッチング用ＴＦＴとしてマルチゲート構造のＴＦＴを用いているが、ＬＤＤ領域の配置等の構成に関しては図１の構成に限定する必要はない。
【０１０７】
以上の構成でなる本発明について、以下に示す実施例でもってさらに詳細な説明を行うこととする。
【０１０８】
〔実施例１〕
本発明の実施例について図３〜図５を用いて説明する。ここでは、画素部とその周辺に設けられる駆動回路部のＴＦＴを同時に作製する方法について説明する。但し、説明を簡単にするために、駆動回路に関しては基本回路であるＣＭＯＳ回路を図示することとする。
【０１０９】
まず、図３（Ａ）に示すように、ガラス基板３００上に下地膜３０１を３００ｎｍの厚さに形成する。本実施例では下地膜３０１として窒化酸化珪素膜を積層して用いる。この時、ガラス基板３００に接する方の窒素濃度を１０〜２５ｗｔ％としておくと良い。
【０１１０】
また、下地膜３０１の一部として、図１に示した第１パッシベーション膜４１と同様の材料からなる絶縁膜を設けることは有効である。電流制御用ＴＦＴは大電流を流すことになるので発熱しやすく、なるべく近いところに放熱効果のある絶縁膜を設けておくことは有効である。
【０１１１】
次に下地膜３０１の上に５０ｎｍの厚さの非晶質珪素膜（図示せず））を公知の成膜法で形成する。なお、非晶質珪素膜に限定する必要はなく、非晶質構造を含む半導体膜（微結晶半導体膜を含む）であれば良い。さらに非晶質シリコンゲルマニウム膜などの非晶質構造を含む化合物半導体膜でも良い。また、膜厚は２０〜１００ｎｍの厚さであれば良い。
【０１１２】
そして、公知の技術により非晶質珪素膜を結晶化し、結晶質珪素膜（多結晶シリコン膜若しくはポリシリコン膜ともいう）３０２を形成する。公知の結晶化方法としては、電熱炉を使用した熱結晶化方法、レーザー光を用いたレーザーアニール結晶化法、赤外光を用いたランプアニール結晶化法がある。本実施例では、ＸｅＣｌガスを用いたエキシマレーザー光を用いて結晶化する。
【０１１３】
なお、本実施例では線状に加工したパルス発振型のエキシマレーザー光を用いるが、矩形であっても良いし、連続発振型のアルゴンレーザー光や連続発振型のエキシマレーザー光を用いることもできる。
【０１１４】
本実施例では結晶質珪素膜をＴＦＴの活性層として用いるが、非晶質珪素膜を用いることも可能である。しかし、電流制御用ＴＦＴは大電流を流す必要性があるため、電流を流しやすい結晶質珪素膜を用いた方が有利である。
【０１１５】
なお、オフ電流を低減する必要のあるスイッチング用ＴＦＴの活性層を非晶質珪素膜で形成し、電流制御用ＴＦＴの活性層を結晶質珪素膜で形成することは有効である。非晶質珪素膜はキャリア移動度が低いため電流を流しにくくオフ電流が流れにくい。即ち、電流を流しにくい非晶質珪素膜と電流を流しやすい結晶質珪素膜の両者の利点を生かすことができる。
【０１１６】
次に、図３（Ｂ）に示すように、結晶質珪素膜３０２上に酸化珪素膜でなる保護膜３０３を１３０ｎｍの厚さに形成する。この厚さは１００〜２００ｎｍ（好ましくは１３０〜１７０ｎｍ）の範囲で選べば良い。また、珪素を含む絶縁膜であれば他の膜でも良い。この保護膜３０３は不純物を添加する際に結晶質珪素膜が直接プラズマに曝されないようにするためと、微妙な濃度制御を可能にするために設ける。
【０１１７】
そして、その上にレジストマスク３０４a、３０４bを形成し、保護膜３０３を介してｎ型を付与する不純物元素（以下、ｎ型不純物元素という）を添加する。なお、ｎ型不純物元素としては、代表的には１５族に属する元素、典型的にはリン又は砒素を用いることができる。なお、本実施例ではフォスフィン（ＰＨ₃）を質量分離しないでプラズマ励起したプラズマドーピング法を用い、リンを１×１０¹⁸atoms/cm³の濃度で添加する。勿論、質量分離を行うイオンインプランテーション法を用いても良い。
【０１１８】
この工程により形成されるｎ型不純物領域３０５、３０６には、ｎ型不純物元素が２×１０¹⁶〜５×１０¹⁹atoms/cm³（代表的には５×１０¹⁷〜５×１０¹⁸atoms/cm³）の濃度で含まれるようにドーズ量を調節する。
【０１１９】
次に、図３（Ｃ）に示すように、保護膜３０３を除去し、添加した１５族に属する元素の活性化を行う。活性化手段は公知の技術を用いれば良いが、本実施例ではエキシマレーザー光の照射により活性化する。勿論、パルス発振型でも連続発振型でも良いし、エキシマレーザー光に限定する必要はない。但し、添加された不純物元素の活性化が目的であるので、結晶質珪素膜が溶融しない程度のエネルギーで照射することが好ましい。なお、保護膜３０３をつけたままレーザー光を照射しても良い。
【０１２０】
なお、このレーザー光による不純物元素の活性化に際して、熱処理による活性化を併用しても構わない。熱処理による活性化を行う場合は、基板の耐熱性を考慮して４５０〜５５０℃程度の熱処理を行えば良い。
【０１２１】
この工程によりｎ型不純物領域３０５、３０６の端部、即ち、ｎ型不純物領域３０５、３０６の周囲に存在するｎ型不純物元素を添加していない領域との境界部（接合部）が明確になる。このことは、後にＴＦＴが完成した時点において、ＬＤＤ領域とチャネル形成領域とが非常に良好な接合部を形成しうることを意味する。
【０１２２】
次に、図３（Ｄ）に示すように、結晶質珪素膜の不要な部分を除去して、島状の半導体膜（以下、活性層という）３０７〜３１０を形成する。
【０１２３】
次に、図３（Ｅ）に示すように、活性層３０７〜３１０を覆ってゲート絶縁膜３１１を形成する。ゲート絶縁膜３１１としては、１０〜２００ｎｍ、好ましくは５０〜１５０ｎｍの厚さの珪素を含む絶縁膜を用いれば良い。これは単層構造でも積層構造でも良い。本実施例では１１０ｎｍ厚の窒化酸化珪素膜を用いる。
【０１２４】
次に、２００〜４００ｎｍ厚の導電膜を形成し、パターニングしてゲート電極３１２〜３１６を形成する。なお、本実施例ではゲート電極と、ゲート電極に電気的に接続された引き回しのための配線（以下、ゲート配線という）とを別の材料で形成する。具体的にはゲート電極よりも低抵抗な材料をゲート配線として用いる。これは、ゲート電極としては微細加工が可能な材料を用い、ゲート配線には微細加工はできなくとも配線抵抗が小さい材料を用いるためである。勿論、ゲート電極とゲート配線とを同一材料で形成してしまっても構わない。
【０１２５】
また、ゲート電極は単層の導電膜で形成しても良いが、必要に応じて二層、三層といった積層膜とすることが好ましい。ゲート電極の材料としては公知のあらゆる導電膜を用いることができる。ただし、上述のように微細加工が可能、具体的には２μm以下の線幅にパターニング可能な材料が好ましい。
【０１２６】
代表的には、タンタル（Ｔａ）、チタン（Ｔｉ）、モリブデン（Ｍｏ）、タングステン（Ｗ）もしくはクロム（Ｃｒ）から選ばれた元素でなる膜、または前記元素の窒化物膜（代表的には窒化タンタル膜、窒化タングステン膜、窒化チタン膜）、または前記元素を組み合わせた合金膜（代表的にはＭｏ−Ｗ合金、Ｍｏ−Ｔａ合金）、または前記元素のシリサイド膜（代表的にはタングステンシリサイド膜、チタンシリサイド膜）または導電性を持たせたシリコン膜を用いることができる。勿論、単層で用いても積層して用いても良い。
【０１２７】
本実施例では、５０ｎｍ厚の窒化タンタル（ＴａＮ）膜と、３５０ｎｍ厚のＴａ膜とでなる積層膜を用いる。これはスパッタ法で形成すれば良い。また、スパッタガスとしてＸｅ、Ｎｅ等の不活性ガスを添加すると応力による膜はがれを防止することができる。
【０１２８】
またこの時、ゲート電極３１３、３１６はそれぞれｎ型不純物領域３０５、３０６の一部とゲート絶縁膜３１１を介して重なるように形成する。この重なった部分が後にゲート電極と重なったＬＤＤ領域となる。
【０１２９】
次に、図４（Ａ）に示すように、ゲート電極３１２〜３１６をマスクとして自己整合的にｎ型不純物元素（本実施例ではリン）を添加する。こうして形成される不純物領域３１７〜３２３にはｎ型不純物領域３０５、３０６の１／２〜１／１０（代表的には１／３〜１／４）の濃度でリンが添加されるように調節する。具体的には、１×１０¹⁶〜５×１０¹⁸atoms/cm³（典型的には３×１０¹⁷〜３×１０¹⁸atoms/cm³）の濃度が好ましい。
【０１３０】
次に、図４（Ｂ）に示すように、ゲート電極等を覆う形でレジストマスク３２４a〜３２４dを形成し、ｎ型不純物元素（本実施例ではリン）を添加して高濃度にリンを含む不純物領域３２５〜３３１を形成する。ここでもフォスフィン（ＰＨ₃）を用いたイオンドープ法で行い、この領域のリンの濃度は１×１０²⁰〜１×１０²¹atoms/cm³（代表的には２×１０²⁰〜５×１０²⁰atoms/cm³）となるように調節する。
【０１３１】
この工程によってｎチャネル型ＴＦＴのソース領域若しくはドレイン領域が形成されるが、スイッチング用ＴＦＴでは、図４（Ａ）の工程で形成したｎ型不純物領域３２０〜３２２の一部を残す。この残された領域が、図１におけるスイッチング用ＴＦＴのＬＤＤ領域１５a〜１５dに対応する。
【０１３２】
次に、図４（Ｃ）に示すように、レジストマスク３２４a〜３２４dを除去し、新たにレジストマスク３３２を形成する。そして、ｐ型不純物元素（本実施例ではボロン）を添加し、高濃度にボロンを含む不純物領域３３３、３３４を形成する。ここではジボラン（Ｂ₂Ｈ₆）を用いたイオンドープ法により３×１０²⁰〜３×１０²¹atoms/cm³（代表的には５×１０²⁰〜１×１０²¹atoms/cm³）濃度となるようにボロンを添加する。
【０１３３】
なお、不純物領域３３３、３３４には既に１×１０¹⁶〜５×１０¹⁸atoms/cm³の濃度でリンが添加されているが、ここで添加されるボロンはその少なくとも３倍以上の濃度で添加される。そのため、予め形成されていたｎ型の不純物領域は完全にＰ型に反転し、Ｐ型の不純物領域として機能する。
【０１３４】
次に、レジストマスク３３２を除去した後、それぞれの濃度で添加されたｎ型またはｐ型不純物元素を活性化する。活性化手段としては、ファーネスアニール法、レーザーアニール法、またはランプアニール法で行うことができる。本実施例では電熱炉において窒素雰囲気中、５５０℃、４時間の熱処理を行う。
【０１３５】
このとき雰囲気中の酸素を極力排除することが重要である。なぜならば酸素が少しでも存在していると露呈したゲート電極の表面が酸化され、抵抗の増加を招くと共に後にオーミックコンタクトを取りにくくなるからである。従って、上記活性化工程における処理雰囲気中の酸素濃度は１ｐｐｍ以下、好ましくは０．１ｐｐｍ以下とすることが望ましい。
【０１３６】
次に、活性化工程が終了したら３００ｎｍ厚のゲート配線３３５を形成する。ゲート配線３３５の材料としては、アルミニウム（Ａｌ）又は銅（Ｃｕ）を主成分（組成として５０〜１００％を占める。）とする金属膜を用いれば良い。配置としては図２のゲート配線２１１のように、スイッチング用ＴＦＴのゲート電極３１４、３１５（図２のゲート電極１９a、１９bに相当する）を電気的に接続するように形成する。（図４（Ｄ））
【０１３７】
このような構造とすることでゲート配線の配線抵抗を非常に小さくすることができるため、面積の大きい画像表示領域（画素部）を形成することができる。即ち、画面の大きさが対角１０インチ以上（さらには３０インチ以上）のＥＬ表示装置を実現する上で、本実施例の画素構造は極めて有効である。
【０１３８】
次に、図５（Ａ）に示すように、第１層間絶縁膜３３６を形成する。第１層間絶縁膜３３６としては、珪素を含む絶縁膜を単層で用いるか、その中で組み合わせた積層膜を用いれば良い。また、膜厚は４００ｎｍ〜１．５μmとすれば良い。本実施例では、２００ｎｍ厚の窒化酸化珪素膜の上に８００ｎｍ厚の酸化珪素膜を積層した構造とする。
【０１３９】
さらに、３〜１００％の水素を含む雰囲気中で、３００〜４５０℃で１〜１２時間の熱処理を行い水素化処理を行う。この工程は熱的に励起された水素により半導体膜の不対結合手を水素終端する工程である。水素化の他の手段として、プラズマ水素化（プラズマにより励起された水素を用いる）を行っても良い。
【０１４０】
なお、水素化処理は第１層間絶縁膜３３６を形成する間に入れても良い。即ち、２００ｎｍ厚の窒化酸化珪素膜を形成した後で上記のように水素化処理を行い、その後で残り８００ｎｍ厚の酸化珪素膜を形成しても構わない。
【０１４１】
次に、第１層間絶縁膜３３６に対してコンタクトホールを形成し、ソース配線３３７〜３４０と、ドレイン配線３４１〜３４３を形成する。なお、本実施例ではこの電極を、チタン膜を１００ｎｍ、チタンを含むアルミニウム膜を３００ｎｍ、チタン膜１５０ｎｍをスパッタ法で連続形成した３層構造の積層膜とする。勿論他の導電膜でも良く、銀、パラジウム及び銅を含む合金膜を用いても良い。
【０１４２】
次に、５０〜５００ｎｍ（代表的には２００〜３００ｎｍ）の厚さで第１パッシベーション膜３４４を形成する。本実施例では第１パッシベーション膜３４４として３００ｎｍ厚の窒化酸化珪素膜を用いる。これは窒化珪素膜で代用しても良い。勿論、図１の第１パッシベーション膜４１と同様の材料を用いることが可能である。
【０１４３】
なお、窒化酸化珪素膜の形成に先立ってＨ₂、ＮＨ₃等水素を含むガスを用いてプラズマ処理を行うことは有効である。この前処理により励起された水素が第１層間絶縁膜３３６に供給され、熱処理を行うことで、第１パッシベーション膜３４４の膜質が改善される。それと同時に、第１層間絶縁膜３３６に添加された水素が下層側に拡散するため、効果的に活性層を水素化することができる。
【０１４４】
次に、有機樹脂からなる第２層間絶縁膜３４７を形成する。有機樹脂としてはポリイミド、ポリアミド、アクリル、ＢＣＢ（ベンゾシクロブテン）等を使用することができる。特に、第２層間絶縁膜３４７は平坦化の意味合いが強いので、平坦性に優れたアクリルが好ましい。本実施例ではＴＦＴによって形成される段差を十分に平坦化しうる膜厚でアクリル膜を形成する。好ましくは１〜５μm（さらに好ましくは２〜４μm）とすれば良い。
【０１４５】
次に、第２層間絶縁膜３４７上に１００ｎｍ厚の第２パッシベーション膜３４８を形成する。本実施例ではＳｉ、Ａｌ、Ｎ、Ｏ及びＬａを含む絶縁膜を用いるため、その上に設けられるＥＬ層からのアルカリ金属の拡散を防止することができる。また、同時にＥＬ層に水分を侵入させず、且つ、ＥＬ層で発生した熱を分散させて、熱によるＥＬ層の劣化や平坦化膜（第２層間絶縁膜）の劣化を抑制することができる。
【０１４６】
そして、第２パッシベーション膜３４８、第２層間絶縁膜３４７及び第１パッシベーション膜３４４にドレイン配線３４３に達するコンタクトホールを形成し、画素電極３４９を形成する。本実施例では酸化インジウムと酸化スズとの化合物（ＩＴＯ）膜を１１０ｎｍの厚さに形成し、パターニングを行って画素電極とする。この画素電極３４９がＥＬ素子の陽極となる。なお、他の材料として、酸化インジウムと酸化亜鉛との化合物膜や酸化ガリウムを含む酸化亜鉛膜を用いることも可能である。
【０１４７】
なお、本実施例では画素電極３４９がドレイン配線３４３を介して電流制御用ＴＦＴのドレイン領域３３１へと電気的に接続された構造となっている。この構造には次のような利点がある。
【０１４８】
画素電極３４９はＥＬ層（発光層）や電荷輸送層などの有機材料に直接接することになるため、ＥＬ層等に含まれた可動イオンが画素電極中を拡散する可能性がある。即ち、本実施例の構造は画素電極３４９を直接活性層の一部であるドレイン領域３３１へ接続せず、ドレイン配線３４３を中継することによって活性層中への可動イオンの侵入を防ぐことができる。
【０１４９】
次に、図５（Ｃ）に示すように、ＥＬ層３５０をインクジェット方式により形成し、さらに大気解放しないで陰極（ＭｇＡｇ電極）３５１、保護電極３５２を形成する。このときＥＬ層３５０及び陰極３５１を形成するに先立って画素電極３４９に対して熱処理を施し、水分を完全に除去しておくことが望ましい。なお、本実施例ではＥＬ素子の陰極としてＭｇＡｇ電極を用いるが、公知の他の材料であっても良い。
【０１５０】
なお、ＥＬ層３５０としては【発明の実施の形態】の欄で説明した材料を用いることができる。本実施例では図２１に示すように、正孔注入層（Hole injecting layer）、正孔輸送層（Hole transporting layer）、発光層（Emitting layer）及び電子輸送層（Electron transporting layer）でなる４層構造をＥＬ層とするが、電子輸送層を設けない場合もあるし、電子注入層を設ける場合もある。また、正孔注入層を省略する場合もある。このように組み合わせは既に様々な例が報告されており、そのいずれの構成を用いても構わない。
【０１５１】
正孔注入層又は正孔輸送層としてはアミン系のＴＰＤ（トリフェニルアミン誘導体）を用いればよく、他にもヒドラゾン系（代表的にはＤＥＨ）、スチルベン系（代表的にはＳＴＢ）、スターバスト系（代表的にはｍ−ＭＴＤＡＴＡ）等を用いることができる。特にガラス転移温度が高く結晶化しにくいスターバスト系材料が好ましい。また、ポリアニリン（ＰＡｎｉ）、ポリチオフェン（ＰＥＤＯＴ）もしくは銅フタロシアニン（ＣｕＰｃ）を用いても良い。
【０１５２】
また、本実施例で用いる発光層としては、赤色に発光する発光層にはシアノポリフェニレンビニレン、緑色に発光する発光層にはポリフェニレンビニレン、青色に発光する発光層にはポリフェニレンビニレン若しくはポリアルキルフェニレンを用いれば良い。膜厚は３０〜１５０ｎｍ（好ましくは４０〜１００ｎｍ）とすれば良い。また、本実施例では溶媒としてトルエンを用いる。
【０１５３】
また、保護電極３５２でもＥＬ層３５０を水分や酸素から保護することは可能であるが、さらに好ましくは第３パッシベーション膜３５３を設けると良い。本実施例では第３パッシベーション膜３５３として３００ｎｍ厚の窒化珪素膜を設ける。この第３パッシベーション膜も保護電極３５２の後に大気解放しないで連続的に形成しても構わない。勿論、第３パッシベーション膜３５３としては、図１の第３パッシベーション膜５０と同一の材料を用いることができる。
【０１５４】
また、保護電極３５２はＭｇＡｇ電極３５１の劣化を防ぐために設けられ、アルミニウムを主成分とする金属膜が代表的である。勿論、他の材料でも良い。また、ＥＬ層３５０、ＭｇＡｇ電極３５１は非常に水分に弱いので、保護電極３５２までを大気解放しないで連続的に形成し、外気からＥＬ層を保護することが望ましい。
【０１５５】
なお、ＥＬ層３５０の膜厚は１０〜４００ｎｍ（典型的には６０〜１６０ｎｍ）、ＭｇＡｇ電極３５１の厚さは１８０〜３００ｎｍ（典型的には２００〜２５０ｎｍ）とすれば良い。また、ＥＬ層３５０を積層構造とする場合、各層の膜厚は１０〜１００ｎｍの範囲とすれば良い。
【０１５６】
こうして図５（Ｃ）に示すような構造のアクティブマトリクス型ＥＬ表示装置が完成する。ところで、本実施例のアクティブマトリクス型ＥＬ表示装置は、画素部だけでなく駆動回路部にも最適な構造のＴＦＴを配置することにより、非常に高い信頼性を示し、動作特性も向上しうる。
【０１５７】
まず、極力動作速度を落とさないようにホットキャリア注入を低減させる構造を有するＴＦＴを、駆動回路を形成するＣＭＯＳ回路のｎチャネル型ＴＦＴ２０５として用いる。なお、ここでいう駆動回路としては、シフトレジスタ、バッファ、レベルシフタ、サンプリング回路（トランスファゲート）などが含まれる。デジタル駆動を行う場合には、Ｄ／Ａコンバータなどの信号変換回路も含まれうる。
【０１５８】
本実施例の場合、図５（Ｃ）に示すように、ｎチャネル型２０５の活性層は、ソース領域３５５、ドレイン領域３５６、ＬＤＤ領域３５７及びチャネル形成領域３５８を含み、ＬＤＤ領域３５７はゲート絶縁膜３１１を挟んでゲート電極３１３と重なっている。
【０１５９】
ドレイン領域側のみにＬＤＤ領域を形成しているのは、動作速度を落とさないための配慮である。また、このｎチャネル型ＴＦＴ２０５はオフ電流値をあまり気にする必要はなく、それよりも動作速度を重視した方が良い。従って、ＬＤＤ領域３５７は完全にゲート電極に重ねてしまい、極力抵抗成分を少なくすることが望ましい。即ち、いわゆるオフセットはなくした方がよい。
【０１６０】
また、ＣＭＯＳ回路のｐチャネル型ＴＦＴ２０６は、ホットキャリア注入による劣化が殆ど気にならないので、特にＬＤＤ領域を設けなくても良い。勿論、ｎチャネル型ＴＦＴ２０５と同様にＬＤＤ領域を設け、ホットキャリア対策を講じることも可能である。
【０１６１】
なお、駆動回路の中でもサンプリング回路は他の回路と比べて少し特殊であり、チャネル形成領域を双方向に大電流が流れる。即ち、ソース領域とドレイン領域の役割が入れ替わるのである。さらに、オフ電流値を極力低く抑える必要があり、そういった意味でスイッチング用ＴＦＴと電流制御用ＴＦＴの中間程度の機能を有するＴＦＴを配置することが望ましい。
【０１６２】
従って、サンプリング回路を形成するｎチャネル型ＴＦＴは、図９に示すような構造のＴＦＴを配置することが望ましい。図９に示すように、ＬＤＤ領域９０１a、９０１bの一部がゲート絶縁膜９０２を挟んでゲート電極９０３と重なる。この効果は電流制御用ＴＦＴ２０２の説明で述べた通りであり、サンプリング回路の場合はチャネル形成領域９０４を挟む形でＬＤＤ領域９０１a、９０１bを設ける点が異なる。
【０１６３】
また、図１に示したような構造の画素を形成して画素部を形成している。画素内に形成されるスイッチング用ＴＦＴ及び電流制御用ＴＦＴの構造については、図１で既に説明したのでここでの説明は省略する。
【０１６４】
なお、実際には図５（Ｃ）まで完成したら、さらに外気に曝されないように気密性の高い保護フィルム（ラミネートフィルム、紫外線硬化樹脂フィルム等）やセラミックス製シーリングカンなどのハウジング材でパッケージング（封入）することが好ましい。その際、ハウジング材の内部を不活性雰囲気にしたり、内部に吸湿剤（例えば酸化バリウム）や酸化防止剤を配置したりすることでＥＬ層の信頼性（寿命）が向上する。
【０１６５】
また、パッケージング等の処理により気密性を高めたら、基板上に形成された素子又は回路から引き回された端子と外部信号端子とを接続するためのコネクター（フレキシブルプリントサーキット：ＦＰＣ）を取り付けて製品として完成する。このような出荷できる状態にまでしたＥＬ表示装置を本明細書中ではＥＬモジュールという。
【０１６６】
ここで本実施例のアクティブマトリクス型ＥＬ表示装置の構成を図６の斜視図を用いて説明する。本実施例のアクティブマトリクス型ＥＬ表示装置は、ガラス基板６０１上に形成された、画素部６０２と、ゲート側駆動回路６０３と、ソース側駆動回路６０４で構成される。画素部のスイッチング用ＴＦＴ６０５はｎチャネル型ＴＦＴであり、ゲート側駆動回路６０３に接続されたゲート配線６０６、ソース側駆動回路６０４に接続されたソース配線６０７の交点に配置されている。また、スイッチング用ＴＦＴ６０５のドレインは電流制御用ＴＦＴ６０８のゲートに接続されている。
【０１６７】
さらに、電流制御用ＴＦＴ６０８のソースは電流供給線６０９に接続され、電流制御用ＴＦＴ６０８のドレインにはＥＬ素子６１０が電気的に接続されている。このとき、電流制御用ＴＦＴ６０８がｎチャネル型ＴＦＴであればそのドレインにはＥＬ素子６１０の陰極が接続されることが好ましい。また、電流制御用ＴＦＴ６０８がｐチャネル型ＴＦＴであればそのドレインにはＥＬ素子６１０の陽極が接続されることが好ましい。
【０１６８】
そして、外部入力端子となるＦＰＣ６１１には駆動回路まで信号を伝達するための入力配線（接続配線）６１２、６１３、及び電流供給線６０９に接続された入力配線６１４が設けられている。
【０１６９】
また、図６に示したＥＬ表示装置の回路構成の一例を図７に示す。本実施例のＥＬ表示装置は、ソース側駆動回路７０１、ゲート側駆動回路（Ａ）７０７、ゲート側駆動回路（Ｂ）７１１、画素部７０６を有している。なお、本明細書中において、駆動回路とはソース側処理回路およびゲート側駆動回路を含めた総称である。
【０１７０】
ソース側駆動回路７０１は、シフトレジスタ７０２、レベルシフタ７０３、バッファ７０４、サンプリング回路（トランスファゲート）７０５を備えている。また、ゲート側駆動回路（Ａ）７０７は、シフトレジスタ７０８、レベルシフタ７０９、バッファ７１０を備えている。ゲート側駆動回路（Ｂ）７１１も同様な構成である。
【０１７１】
ここでシフトレジスタ７０２、７０８は駆動電圧が５〜１６Ｖ（代表的には１０Ｖ）であり、回路を形成するＣＭＯＳ回路に使われるｎチャネル型ＴＦＴは図５（Ｃ）の２０５で示される構造が適している。
【０１７２】
また、レベルシフタ７０３、７０９、バッファ７０４、７１０は、駆動電圧は１４〜１６Ｖと高くなるが、シフトレジスタと同様に、図５（Ｃ）のｎチャネル型ＴＦＴ２０５を含むＣＭＯＳ回路が適している。なお、ゲート配線をダブルゲート構造、トリプルゲート構造といったマルチゲート構造とすることは、各回路の信頼性を向上させる上で有効である。
【０１７３】
また、サンプリング回路７０５は駆動電圧が１４〜１６Ｖであるが、ソース領域とドレイン領域が反転する上、オフ電流値を低減する必要があるので、図９のｎチャネル型ＴＦＴ２０８を含むＣＭＯＳ回路が適している。
【０１７４】
また、画素部７０６は駆動電圧が１４〜１６Ｖであり、図１に示した構造の画素を配置する。
【０１７５】
なお、上記構成は、図３〜５に示した作製工程に従ってＴＦＴを作製することによって容易に実現することができる。また、本実施例では画素部と駆動回路の構成のみ示しているが、本実施例の作製工程に従えば、その他にも信号分割回路、Ｄ／Ａコンバータ回路、オペアンプ回路、γ補正回路など駆動回路以外の論理回路を同一基板上に形成することが可能であり、さらにはメモリ部やマイクロプロセッサ等を形成しうると考えている。
【０１７６】
さらに、ハウジング材をも含めた本実施例のＥＬモジュールについて図１７（Ａ）、（Ｂ）を用いて説明する。なお、必要に応じて図６、図７で用いた符号を引用することにする。
【０１７７】
基板（ＴＦＴの下の下地膜を含む）１７００上には画素部１７０１、ソース側駆動回路１７０２、ゲート側駆動回路１７０３が形成されている。それぞれの駆動回路からの各種配線は、入力配線６１２〜６１４を経てＦＰＣ６１１に至り外部機器へと接続される。
【０１７８】
このとき少なくとも画素部、好ましくは駆動回路及び画素部を囲むようにしてハウジング材１７０４を設ける。なお、ハウジング材１７０４はＥＬ素子の外寸よりも内寸が大きい凹部を有する形状又はシート形状であり、接着剤１７０５によって、基板１７００と共同して密閉空間を形成するようにして基板１７００に固着される。このとき、ＥＬ素子は完全に前記密閉空間に封入された状態となり、外気から完全に遮断される。なお、ハウジング材１７０４は複数設けても構わない。
【０１７９】
また、ハウジング材１７０４の材質はガラス、ポリマー等の絶縁性物質が好ましい。例えば、非晶質ガラス（硼硅酸塩ガラス、石英等）、結晶化ガラス、セラミックスガラス、有機系樹脂（アクリル系樹脂、スチレン系樹脂、ポリカーボネート系樹脂、エポキシ系樹脂等）、シリコーン系樹脂が挙げられる。また、セラミックスを用いても良い。また、接着剤１７０５が絶縁性物質であるならステンレス合金等の金属材料を用いることも可能である。
【０１８０】
また、接着剤１７０５の材質は、エポキシ系樹脂、アクリレート系樹脂等の接着剤を用いることが可能である。さらに、熱硬化性樹脂や光硬化性樹脂を接着剤として用いることもできる。但し、可能な限り酸素、水分を透過しない材質であることが必要である。
【０１８１】
さらに、ハウジング材と基板１７００との間の空隙１７０６は不活性ガス（アルゴン、ヘリウム、窒素等）を充填しておくことが望ましい。また、ガスに限らず不活性液体（パーフルオロアルカンに代表される液状フッ素化炭素等）を用いることも可能である。不活性液体に関しては特開平８−７８１５９号で用いられているような材料で良い。また、樹脂を充填しても良い。
【０１８２】
また、空隙１７０６に乾燥剤を設けておくことも有効である。乾燥剤としては特開平９−１４８０６６号公報に記載されているような材料を用いることができる。典型的には酸化バリウムを用いれば良い。また、乾燥剤だけでなく酸化防止剤を設けることも有効である。
【０１８３】
また、図１７（Ｂ）に示すように、画素部には個々に孤立したＥＬ素子を有する複数の画素が設けられ、それらは全て保護電極１７０７を共通電極として有している。本実施例では、ＥＬ層、陰極（ＭｇＡｇ電極）及び保護電極を大気解０放しないで連続形成することが好ましいとしたが、ＥＬ層と陰極とを同じマスク材を用いて形成し、保護電極だけ別のマスク材で形成すれば図１７（Ｂ）の構造を実現することができる。
【０１８４】
このとき、ＥＬ層と陰極は画素部のみ設ければよく、駆動回路の上に設ける必要はない。勿論、駆動回路上に設けられていても問題とはならないが、ＥＬ層にアルカリ金属が含まれていることを考慮すると設けない方が好ましい。
【０１８５】
なお、保護電極１７０７は１７０８で示される領域において、入力配線１７０９に接続される。入力配線１７０９は保護電極１７０７に所定の電圧を与えるための配線であり、導電性ペースト材料（異方導電性膜）１７１０を介してＦＰＣ６１１に接続される。
【０１８６】
ここで領域１７０８におけるコンタクト構造を実現するための作製工程について図１８を用いて説明する。
【０１８７】
まず、本実施例の工程に従って図５（Ａ）の状態を得る。このとき、基板端部（図１７（Ｂ）において１７０８で示される領域）において第１層間絶縁膜３３６及びゲート絶縁膜３１１を除去し、その上に入力配線１７０９を形成する。勿論、図５（Ａ）のソース配線及びドレイン配線と同時に形成される。（図１８（Ａ））
【０１８８】
次に、図５（Ｂ）において第２パッシベーション膜３４８、第２層間絶縁膜３４７及び第１パッシベーション膜３４４をエッチングする際に、１８０１で示される領域を除去し、且つ開孔部１８０２を形成する。（図１８（Ｂ））
【０１８９】
この状態で画素部ではＥＬ素子の形成工程（画素電極、ＥＬ層及び陰極の形成工程）が行われる。この際、図１８に示される領域ではマスク材を用いてＥＬ素子が形成されないようにする。そして、陰極３５１を形成した後、別のマスク材を用いて保護電極３５２を形成する。これにより保護電極３５２と入力配線１７０９とが電気的に接続される。さらに、第３パッシベーション膜３５３を設けて図１８（Ｃ）の状態を得る。
【０１９０】
以上の工程により図１７（Ｂ）の１７０８で示される領域のコンタクト構造が実現される。そして、入力配線１７０９はハウジング材１７０４と基板１７００との間の隙間（但し接着剤１７０５で充填されている。即ち、接着剤１７０５は入力配線の段差を十分に平坦化しうる厚さが必要である。）を通ってＦＰＣ６１１に接続される。なお、ここでは入力配線１７０９について説明したが、他の出力配線６１２〜６１４も同様にしてハウジング材１７０４の下を通ってＦＰＣ６１１に接続される。
【０１９１】
〔実施例２〕
本実施例では、画素の構成を図２（Ｂ）に示した構成と異なるものとした例を図１０に示す。
【０１９２】
本実施例では、図２（Ｂ）に示した二つの画素を、電流供給線について対称となるように配置する。即ち、図１０に示すように、電流供給線２１３を隣接する二つの画素間で共通化することで、必要とする配線の本数を低減することができる。なお、画素内に配置されるＴＦＴ構造等はそのままで良い。
【０１９３】
このような構成とすれば、より高精細な画素部を作製することが可能となり、画像の品質が向上する。
【０１９４】
なお、本実施例の構成は実施例１の作製工程に従って容易に実現可能であり、ＴＦＴ構造等に関しては実施例１や図１の説明を参照すれば良い。
【０１９５】
〔実施例３〕
本実施例では、図１と異なる構造の画素部を形成する場合について図１１を用いて説明する。なお、第２層間絶縁膜４４を形成する工程までは実施例１に従えば良い。また、第２層間絶縁膜４４で覆われたスイッチング用ＴＦＴ２０１、電流制御用ＴＦＴ２０２は図１と同じ構造であるので、ここでの説明は省略する。
【０１９６】
本実施例の場合、第２パッシベーション膜４５、第２層間絶縁膜４４及び第１パッシベーション膜４１に対してコンタクトホールを形成したら、画素電極５１、バンク１０３a、１０３bを形成した後、陰極５２及びＥＬ層５３を形成する。本実施例では陰極５２を真空蒸着法で形成した後、大気解放しないで乾燥された不活性雰囲気を維持したままインクジェット方式によりＥＬ層５３を形成する。この際、バンク１０３a、１０３bにより選択的に赤色発光のＥＬ層、緑色発光のＥＬ層、青色発光のＥＬ層が別々の画素に形成される。なお、図１１には一つの画素しか図示していないが、同一構造の画素が赤、緑又は青のそれぞれの色に対応して形成され、これによりカラー表示を行うことができる。これら各色のＥＬ層は公知の材料を採用すれば良い。
【０１９７】
本実施例では画素電極５１として、１５０ｎｍ厚のアルミニウム合金膜（１wt%のチタンを含有したアルミニウム膜）を設ける。なお、画素電極の材料としては金属材料であれば如何なる材料でも良いが、反射率の高い材料であることが好ましい。また、陰極５２として２３０ｎｍ厚のＭｇＡｇ電極を用い、ＥＬ層５３の膜厚は９０ｎｍ（下から電子輸送層２０ｎｍ、発光層４０ｎｍ、正孔輸送層３０ｎｍ）とする。
【０１９８】
次に、透明導電膜（本実施例ではＩＴＯ膜）からなる陽極５４を１１０ｎｍの厚さに形成する。こうしてＥＬ素子２０９が形成され、実施例１に示した材料でもって第３パッシベーション膜５５を形成すれば図１１に示すような構造の画素が完成する。
【０１９９】
本実施例の構造とした場合、各画素で生成された赤色、緑色又は青色の光はＴＦＴが形成された基板とは反対側に放射される。そのため、画素内のほぼ全域、即ちＴＦＴが形成された領域をも有効な発光領域として用いることができる。その結果、画素の有効発光面積が大幅に向上し、画像の明るさやコントラスト比（明暗の比）が向上する。
【０２００】
なお、本実施例の構成は、実施例１、２のいずれの構成とも自由に組み合わせることが可能である。
【０２０１】
〔実施例４〕
本実施例では、実施例１の図２とは異なる構造の画素を形成する場合について図１２（Ａ）、（Ｂ）を用いて説明する。
【０２０２】
図１２（Ａ）において、１２０１はスイッチング用ＴＦＴであり、活性層５６、ゲート電極５７a、ゲート配線５７b、ソース配線５８及びドレイン配線５９を構成として含む。また、１２０２は電流制御用ＴＦＴであり、活性層６０、ゲート電極６１、ソース配線６２及びドレイン配線６３を構成として含む。そして、電流制御用ＴＦＴ１２０２のソース配線６２は電流供給線６４に接続され、ドレイン配線６３はＥＬ素子６５に接続される。この画素の回路構成を表したのが図１２（Ｂ）である。
【０２０３】
図１２（Ａ）と図２（Ａ）との相違点は、スイッチング用ＴＦＴの構造である。本実施例では線幅が０．１〜５μmと細いゲート電極５７aを形成し、その部分を横切るようにして活性層５６を形成する。そして各画素のゲート電極５７aを電気的に接続するようにゲート配線５７bが形成される。これにより面積をさほど専有することなくトリプルゲート構造を実現している。
【０２０４】
他の部分は図２（Ａ）と同様であるが、本実施例のような構造とするとスイッチング用ＴＦＴの専有する面積が小さくなるため有効発光面積が広くなる、即ち画像の明るさが向上する。また、オフ電流値を低減するための冗長性を高めたゲート構造を実現しうるため、さらなる画質の向上を図ることができる。
【０２０５】
なお、本実施例の構成は実施例２のように電流供給線６４を隣接する画素間で共通化しても良いし、実施例３のような構造としても良い。また、作製工程に関しては実施例１に従えば良い。
【０２０６】
〔実施例５〕
実施例１〜４ではトップゲート型ＴＦＴの場合について説明したが、本発明はボトムゲート型ＴＦＴを用いて実施しても構わない。本実施例では逆スタガ型ＴＦＴで本発明を実施した場合について図１３に示す。なお、ＴＦＴ構造以外は図１の構造と同様であるので必要に応じて図１と同じ符号を用いる。
【０２０７】
図１３において、基板１１、下地膜１２には実施例１と同様の材料を用いることができる。そして、下地膜１２上にはスイッチング用ＴＦＴ１３０１及び電流制御用ＴＦＴ１３０２が形成される。
【０２０８】
スイッチング用ＴＦＴ１３０１の構成は、ゲート電極７０a、７０b、ゲート配線７１、ゲート絶縁膜７２、ソース領域７３、ドレイン領域７４、ＬＤＤ領域７５a〜７５d、高濃度不純物領域７６、チャネル形成領域７７a、７７b、チャネル保護膜７８a、７８b、第１層間絶縁膜７９、ソース配線８０及びドレイン配線８１を含む。
【０２０９】
また、電流制御用ＴＦＴ１３０２の構成は、ゲート電極８２、ゲート絶縁膜７２、ソース領域８３、ドレイン領域８４、ＬＤＤ領域８５、チャネル形成領域８６、チャネル保護膜８７、第１層間絶縁膜７９、ソース配線８８及びドレイン配線８９を含む。この時、ゲート電極８２はスイッチング用ＴＦＴ１３０１のドレイン配線８４と電気的に接続される。
【０２１０】
なお、上記スイッチング用ＴＦＴ１３０１及び電流制御用ＴＦＴ１３０２は公知の逆スタガ型ＴＦＴの作製方法によって形成すれば良い。また、上記ＴＦＴを形成する各部位（配線、絶縁膜、活性層等）の材料は実施例１のトップゲート型ＴＦＴにおいて対応する各部位と同様の材料を用いることができる。但し、トップゲート型ＴＦＴの構成にはないチャネル保護膜７８a、７８b、８７に関しては、珪素を含む絶縁膜で形成すれば良い。また、ソース領域、ドレイン領域又はＬＤＤ領域等の不純物領域の形成については、フォトリソグラフィ技術を用いて個別に不純物濃度を変えて形成すれば良い。
【０２１１】
ＴＦＴが完成したら、第１パッシベーション膜４１、第２層間絶縁膜（平坦化膜）４４、第２パッシベーション膜４５、画素電極（陽極）４６、バンク１０１a、１０１b、ＥＬ層４７、ＭｇＡｇ電極（陰極）４８、アルミニウム電極（保護電極）４９、第３パッシベーション膜５０を順次形成してＥＬ素子１３０３を有する画素が完成する。これらの作製工程及び材料に関しては実施例１を参考にすれば良い。
【０２１２】
なお、本実施例の構成は、実施例２〜４のいずれの構成とも自由に組み合わせることが可能である。
【０２１３】
〔実施例６〕
実施例１の図５（Ｃ）又は図１の構造において、活性層と基板との間に設けられる下地膜として、第２パッシベーション膜４５と同様に放熱効果の高い材料を用いることは有効である。特に電流制御用ＴＦＴは多くの電流を流すことになるため発熱しやすく、自己発熱による劣化が問題となりうる。そのような場合に、本実施例のように下地膜が放熱効果を有することでＴＦＴの熱劣化を防ぐことができる。
【０２１４】
もちろん、基板から拡散する可動イオン等から防ぐ効果も重要であるので、第１パッシベーション膜４１と同様にＳｉ、Ａｌ、Ｎ、Ｏ、Ｍを含む化合物と珪素を含む絶縁膜との積層構造を用いることも好ましい。
【０２１５】
なお、本実施例の構成は、実施例１〜５のいずれの構成とも自由に組み合わせることが可能である。
【０２１６】
〔実施例７〕
実施例３に示した画素構造とした場合、ＥＬ層から発する光は基板とは反対側に放射されるため、基板と画素電極との間に存在する絶縁膜等の透過率を気にする必要がない。即ち、多少透過率の低い材料であっても用いることができる。
【０２１７】
従って、下地膜１２、第１パッシベーション膜４１又は第２パッシベーション膜４５としてダイヤモンド薄膜、ダイヤモンドライクカーボン膜又はアモルファスカーボン膜と呼ばれる炭素膜を用いる上で有利である。即ち、透過率の低下を気にする必要がないため、膜厚を１００〜５００ｎｍというように厚く設定することができ、放熱効果をより高めることが可能である。
【０２１８】
なお、第３パッシベーション膜５０に上記炭素膜を用いる場合に関しては、やはり透過率の低下は避けるべきであるので、膜厚は５〜１００ｎｍ程度にしておくことが好ましい。
【０２１９】
なお、本実施例においても下地膜１２、第１パッシベーション膜４１、第２パッシベーション膜４５又は第３パッシベーション膜５０のいずれに炭素膜を用いる場合においても、他の絶縁膜と積層して用いることは有効である。
【０２２０】
なお、本実施例は実施例３に示した画素構造とする場合において有効であり、その他の構成に関しては、実施例１〜６のいずれの構成とも自由に組み合わせることが可能である。
【０２２１】
〔実施例８〕
本発明ではＥＬ表示装置の画素においてスイッチング用ＴＦＴをマルチゲート構造とすることによりスイッチング用ＴＦＴのオフ電流値を低減し、保持容量の必要性を排除している。これは保持容量の専有する面積を発光領域として有効に活用するための工夫である。
【０２２２】
しかしながら、保持容量を完全になくせないまでも専有面積を小さくするだけで有効発光面積を広げるという効果は得られる。即ち、スイッチング用ＴＦＴをマルチゲート構造にすることによりオフ電流値を低減し、保持容量の専有面積を縮小化するだけでも十分である。
【０２２３】
従って、図１４に示すような画素構造とすることも可能である。なお、図１４では必要に応じて図１と同じ符号を引用している。
【０２２４】
図１４と図１との相違点は、スイッチング用ＴＦＴに接続された保持容量１４０１が存在する点である。保持容量１４０１はスイッチング用ＴＦＴ２０１のドレイン領域１４から延長された半導体領域（下部電極）１４０２とゲート絶縁膜１８と容量電極（上部電極）１４０３とで形成される。この容量電極１４０３はＴＦＴのゲート電極１９a、１９b、３５と同時に形成される。
【０２２５】
この上面図を図１５（Ａ）に示す。図１５（Ａ）の上面図をＡ−Ａ’で切った断面図が図１４に相当する。図１５（Ａ）示すように、容量電極１４０３は電気的に接続された接続配線１４０４を介して電流制御用ＴＦＴのソース領域３１と電気的に接続される。なお、接続配線１４０４はソース配線２１、３６及びドレイン配線２２、３７と同時に形成される。また、図１５（Ｂ）は図１５（Ａ）に示す上面図の回路構成を表している。
【０２２６】
なお、本実施例の構成は、実施例１〜７のいずれの構成とも自由に組み合わせることができる。即ち、画素内に保持容量が設けられるだけであって、ＴＦＴ構造やＥＬ層の材料等に限定を加えるものではない。
【０２２７】
〔実施例９〕
実施例１では、結晶質珪素膜３０２の形成手段としてレーザー結晶化を用いているが、本実施例では異なる結晶化手段を用いる場合について説明する。
【０２２８】
本実施例では、非晶質珪素膜を形成した後、特開平７−１３０６５２号公報に記載された技術を用いて結晶化を行う。同公報に記載された技術は、結晶化を促進（助長）する触媒として、ニッケル等の元素を用い、結晶性の高い結晶質珪素膜を得る技術である。
【０２２９】
また、結晶化工程が終了した後で、結晶化に用いた触媒を除去する工程を行っても良い。その場合、特開平１０−２７０３６３号若しくは特開平８−３３０６０２号に記載された技術により触媒をゲッタリングすれば良い。
【０２３０】
また、本出願人による特願平１１−０７６９６７の出願明細書に記載された技術を用いてＴＦＴを形成しても良い。
【０２３１】
以上のように、実施例１に示した作製工程は一実施例であって、図１又は実施例１の図５（Ｃ）の構造が実現できるのであれば、他の作製工程を用いても問題はない。
【０２３２】
なお、本実施例の構成は、実施例１〜８のいずれの構成とも自由に組み合わせることが可能である。
【０２３３】
〔実施例１０〕
本発明のＥＬ表示装置を駆動するにあたって、画像信号としてアナログ信号を用いたアナログ駆動を行うこともできるし、デジタル信号を用いたデジタル駆動を行うこともできる。
【０２３４】
アナログ駆動を行う場合、スイッチング用ＴＦＴのソース配線にはアナログ信号が送られ、その階調情報を含んだアナログ信号が電流制御用ＴＦＴのゲート電圧となる。そして、電流制御用ＴＦＴでＥＬ素子に流れる電流を制御し、ＥＬ素子の発光強度を制御して階調表示を行う。この場合、電流制御用ＴＦＴは飽和領域で動作させることが望ましい。即ち、｜Ｖds｜＞｜Ｖgs−Ｖth｜の条件内で動作させることが望ましい。なお、ここでＶdsはソース領域とドレイン領域との間の電圧、Ｖgsはソース領域とゲート電極との間の電圧、ＶthはＴＦＴのしきい値電圧である。
【０２３５】
一方、デジタル駆動を行う場合、アナログ的な階調表示とは異なり、時分割駆動（時間階調駆動）もしくは面積階調駆動と呼ばれる階調表示を行う。即ち、発光時間の長さや発光面積比率を調節することで、視覚的に色階調が変化しているように見せる。この場合、電流制御用ＴＦＴは線形領域で動作させることが望ましい。即ち、｜Ｖds｜＜｜Ｖgs−Ｖth｜の条件内で動作させることが望ましい。
【０２３６】
ＥＬ素子は液晶素子に比べて非常に応答速度が速いため、高速で駆動することが可能である。そのため、１フレームを複数のサブフレームに分割して階調表示を行う時分割駆動に適した素子であると言える。また、１フレーム期間が短いため電流制御用ＴＦＴのゲート電圧を保持しておく時間も短くて済み、保持容量を小さくする、もしくは省略する上で有利と言える。
【０２３７】
このように、本発明は素子構造に関する技術であるので、駆動方法は如何なるものであっても構わない。
【０２３８】
〔実施例１１〕
本実施例では、本発明に係るＥＬ表示装置の画素構造の例を図２３（Ａ）、（Ｂ）に示す。なお、本実施例において、４７０１はスイッチング用ＴＦＴ４７０２のソース配線、４７０３はスイッチング用ＴＦＴ４７０２のゲート配線、４７０４は電流制御用ＴＦＴ、４７０５は電流供給線、４７０６は電源制御用ＴＦＴ、４７０７は電源制御用ゲート配線、４７０８はＥＬ素子とする。電源制御用ＴＦＴ４７０６の動作については特願平１１−３４１２７２号を参照すると良い。
【０２３９】
また、本実施例では電源制御用ＴＦＴ４７０６を電流制御用ＴＦＴ４７０４とＥＬ素子４７０８との間に設けているが、電源制御用ＴＦＴ４７０６とＥＬ素子４７０８との間に電流制御用ＴＦＴ４７０４が設けられた構造としても良い。また、電源制御用ＴＦＴ４７０６は電流制御用ＴＦＴ４７０４と同一構造とするか、同一の活性層で直列させて形成するのが好ましい。
【０２４０】
また、図２３（Ａ）は、二つの画素間で電流供給線４７０５を共通とした場合の例である。即ち、二つの画素が電流供給線４７０５を中心に線対称となるように形成されている点に特徴がある。この場合、電流供給線の本数を減らすことができるため、画素部をさらに高精細化することができる。
【０２４１】
また、図２３（Ｂ）は、ゲート配線４７０３と平行に電流供給線４７１０を設け、ソース配線４７０１と平行に電源制御用ゲート配線４７１１を設けた場合の例である。なお、図２３（Ｂ）では電流供給線４７１０とゲート配線４７０３とが重ならないように設けた構造となっているが、両者が異なる層に形成される配線であれば、絶縁膜を挟んで重なるように設けることもできる。この場合、電流供給線４７１０とゲート配線４７０３とで専有面積を共有させることができるため、画素部をさらに高精細化することができる。
【０２４２】
〔実施例１２〕
本実施例では、本発明に係るＥＬ表示装置の画素構造の例を図２４（Ａ）、（Ｂ）に示す。なお、本実施例において、４８０１はスイッチング用ＴＦＴ４８０２のソース配線、４８０３はスイッチング用ＴＦＴ４８０２のゲート配線、４８０４は電流制御用ＴＦＴ、４８０５は電流供給線、４８０６は消去用ＴＦＴ、４８０７は消去用ゲート配線、４８０８はＥＬ素子とする。消去用ＴＦＴ４８０６の動作については特願平１１−３３８７８６号を参照すると良い。
【０２４３】
消去用ＴＦＴ４８０６のドレインは電流制御用ＴＦＴ４８０４のゲートに接続され、電流制御用ＴＦＴ４８０４のゲート電圧を強制的に変化させることができるようになっている。なお、消去用ＴＦＴ４８０６はｎチャネル型ＴＦＴとしてもｐチャネル型ＴＦＴとしても良いが、オフ電流を小さくできるようにスイッチング用ＴＦＴ４８０２と同一構造とすることが好ましい。
【０２４４】
また、図２４（Ａ）は、二つの画素間で電流供給線４８０５を共通とした場合の例である。即ち、二つの画素が電流供給線４８０５を中心に線対称となるように形成されている点に特徴がある。この場合、電流供給線の本数を減らすことができるため、画素部をさらに高精細化することができる。
【０２４５】
また、図２４（Ｂ）は、ゲート配線４８０３と平行に電流供給線４８１０を設け、ソース配線４８０１と平行に消去用ゲート配線４８１１を設けた場合の例である。なお、図２４（Ｂ）では電流供給線４８１０とゲート配線４８０３とが重ならないように設けた構造となっているが、両者が異なる層に形成される配線であれば、絶縁膜を挟んで重なるように設けることもできる。この場合、電流供給線４８１０とゲート配線４８０３とで専有面積を共有させることができるため、画素部をさらに高精細化することができる。
【０２４６】
〔実施例１３〕
本発明のＥＬ表示装置は画素内にいくつのＴＦＴを設けた構造としても良い。実施例１１、１２ではＴＦＴを三つ設けた例を示しているが、四つ乃至六つのＴＦＴを設けても構わない。本発明はＥＬ表示装置の画素構造に限定されずに実施することが可能である。
【０２４７】
〔実施例１４〕
本実施例では、図１の電流制御用ＴＦＴ２０２としてｐチャネル型ＴＦＴを用いた場合の例について説明する。なお、その他の部分は図１と同様であるので詳細な説明は省略する。
【０２４８】
本実施例の画素の断面構造を図２５に示す。本実施例で用いるｐチャネル型ＴＦＴの作製方法は実施例１を参考にすれば良い。ｐチャネル型ＴＦＴの活性層はソース領域２８０１、ドレイン領域２８０２およびチャネル形成領域２８０３を含み、ソース領域２８０１はソース配線３６に、ドレイン領域２８０２はドレイン配線３７に接続されている。
【０２４９】
このように、電流制御用ＴＦＴにＥＬ素子の陽極が接続される場合は、電流制御用ＴＦＴとしてｐチャネル型ＴＦＴを用いることが好ましい。
【０２５０】
なお、本実施例の構成は、実施例１〜１３のいずれの構成とも自由に組み合わせて実施することが可能である。
【０２５１】
〔実施例１５〕
本発明において、三重項励起子からの燐光を発光に利用できるＥＬ材料を用いることで、外部発光量子効率を飛躍的に向上させることができる。これにより、ＥＬ素子の低消費電力化、長寿命化、および軽量化が可能になる。
ここで、三重項励起子を利用し、外部発光量子効率を向上させた報告を示す。(T.Tsutsui, C.Adachi, S.Saito, Photochemical Processes in Organized Molecular Systems, ed.K.Honda, (Elsevier Sci.Pub., Tokyo,1991) p.437.)上記論文に報告されたＥＬ材料（クマリン色素）の分子式を以下に示す。
【０２５２】
【化１１】

【０２５３】
(M.A.Baldo, D.F.O'Brien, Y.You, A.Shoustikov, S.Sibley, M.E.Thompson, S.R.Forrest, Nature 395 (1998) p.151.)
上記論文に報告されたＥＬ材料（Ｐｔ錯体）の分子式を以下に示す。
【０２５４】
【化１２】

【０２５５】
(M.A.Baldo, S.Lamansky, P.E.Burrrows, M.E.Thompson, S.R.Forrest, Appl.Phys.Lett.,75 (1999) p.4.)
(T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamura, T.Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguchi, Jpn.Appl.Phys., 38 (12B) (1999) L1502.)上記論文に報告されたＥＬ材料（Ｉｒ錯体）の分子式を以下に示す。
【０２５６】
【化１３】

【０２５７】
以上のように三重項励起子からの燐光発光を利用できれば原理的には一重項励起子からの蛍光発光を用いる場合より３〜４倍の高い外部発光量子効率の実現が可能となる。なお、本実施例の構成は、実施例１〜実施例１３のいずれの構成とも自由に組み合わせて実施することが可能である。
【０２５８】
〔実施例１６〕
実施例１ではＥＬ層として有機ＥＬ材料を用いることが好ましいとしたが、本発明は無機ＥＬ材料を用いても実施できる。但し、現在の無機ＥＬ材料は非常に駆動電圧が高いため、アナログ駆動を行う場合には、そのような駆動電圧に耐えうる耐圧特性を有するＴＦＴを用いなければならない。
【０２５９】
または、将来的にさらに駆動電圧の低い無機ＥＬ材料が開発されれば、本発明に適用することは可能である。
【０２６０】
また、本実施例の構成は、実施例１〜１４のいずれの構成とも自由に組み合わせることが可能である。
【０２６１】
〔実施例１７〕
本発明を実施して形成されたアクティブマトリクス型ＥＬ表示装置（ＥＬモジュール）は、自発光型であるため液晶表示装置に比べて明るい場所での視認性に優れている。そのため直視型のＥＬディスプレイ（ＥＬモジュールを組み込んだ表示ディスプレイを指す）として用途は広い。
【０２６２】
なお、ＥＬディスプレイが液晶ディスプレイよりも有利な点の一つとして視野角の広さが挙げられる。従って、ＴＶ放送等を大画面で鑑賞するには対角３０インチ以上（典型的には４０インチ以上）の表示ディスプレイ（表示モニタ）として本発明のＥＬディスプレイを用いるとよい。
【０２６３】
また、ＥＬディスプレイ（パソコンモニタ、ＴＶ放送受信用モニタ、広告表示モニタ等）として用いるだけでなく、様々な電子装置の表示ディスプレイとして用いることができる。
【０２６４】
その様な電子装置としては、ビデオカメラ、デジタルカメラ、ゴーグル型ディスプレイ（ヘッドマウントディスプレイ）、カーナビゲーション、パーソナルコンピュータ、携帯情報端末（モバイルコンピュータ、携帯電話または電子書籍等）、記録媒体を備えた画像再生装置（具体的にはコンパクトディスク（ＣＤ）、レーザーディスク（ＬＤ）又はデジタルビデオディスク（ＤＶＤ）等の記録媒体を再生し、その画像を表示しうるディスプレイを備えた装置）などが挙げられる。それら電子装置の例を図１６に示す。
【０２６５】
図１６（Ａ）はパーソナルコンピュータであり、本体２００１、筐体２００２、表示部２００３、キーボード２００４を含む。本発明は表示部２００３に用いることができる。
【０２６６】
図１６（Ｂ）はビデオカメラであり、本体２１０１、表示部２１０２、音声入力部２１０３、操作スイッチ２１０４、バッテリー２１０５、受像部２１０６を含む。本発明を表示部２１０２に用いることができる。
【０２６７】
図１６（Ｃ）はゴーグル型ディスプレイであり、本体２２０１、表示部２２０２、アーム部２２０３を含む。本発明は表示部２２０２に用いることができる。
【０２６８】
図１６（Ｄ）は携帯型（モバイル）コンピュータであり、本体２３０１、カメラ部２３０２、受像部２３０３、操作スイッチ２３０４、表示部２３０５を含む。本発明は表示部２３０５に用いることができる。
【０２６９】
図１６（Ｅ）は記録媒体を備えた画像再生装置（具体的にはＤＶＤ再生装置）であり、本体２４０１、記録媒体（ＣＤ、ＬＤまたはＤＶＤ等）２４０２、操作スイッチ２４０３、表示部（ａ）２４０４、表示部（ｂ）２４０５を含む。表示部（ａ）は主として画像情報を表示し、表示部（ｂ）は主として文字情報を表示するが、本発明はこれら表示部（ａ）、（ｂ）に用いることができる。なお、記録媒体を備えた画像再生装置としては、ＣＤ再生装置、ゲーム機器などに本発明を用いることができる。
【０２７０】
図１６（Ｆ）はＥＬディスプレイであり、筐体２５０１、支持台２５０２、表示部２５０３を含む。本発明は表示部２５０３に用いることができる。本発明のＥＬディスプレイは特に大画面化した場合において有利であり、対角１０インチ以上（特に対角３０インチ以上）のディスプレイには有利である。
【０２７１】
また、将来的にＥＬ材料の発光輝度が高くなれば、フロント型若しくはリア型のプロジェクターに用いることも可能となる。
【０２７２】
また、上記電子装置はインターネットやＣＡＴＶ（ケーブルテレビ）などの電子通信回線を通じて配信された情報を表示することが多くなり、特に動画情報を表示する機会が増してきている。ＥＬ材料の応答速度は非常に高いため、そのような動画表示を行うに適している。
【０２７３】
また、ＥＬ表示装置は発光している部分が電力を消費するため、発光部分が極力少なくなるように情報を表示することが望ましい。従って、携帯情報端末、特に携帯電話やカーオーディオのような文字情報を主とする表示部にＥＬ表示装置を用いる場合には、非発光部分を背景として文字情報を発光部分で形成するように駆動することが望ましい。
【０２７４】
ここで図２２（Ａ）は携帯電話であり、本体２６０１、音声出力部２６０２、音声入力部２６０３、表示部２６０４、操作スイッチ２６０５、アンテナ２６０６を含む。本発明のＥＬ表示装置は表示部２６０４に用いることができる。なお、表示部２６０４は黒色の背景に白色の文字を表示することで携帯電話の消費電力を抑えることができる。
【０２７５】
また、図２２（Ｂ）は車載用オーディオ（カーオーディオ）であり、本体２７０１、表示部２７０２、操作スイッチ２７０３、２７０４を含む。本発明のＥＬ表示装置は表示部２７０２に用いることができる。また、本実施例では車載用オーディオを示すが、据え置き型オーディオに用いても良い。なお、表示部２７０２は黒色の背景に白色の文字を表示することで消費電力を抑えられる。
【０２７６】
以上の様に、本発明の適用範囲は極めて広く、あらゆる分野の電子装置に適用することが可能である。また、本実施例の電子装置は実施例１〜１６のどのような組み合わせからなる構成を用いても実現することができる。
【０２７７】
【発明の効果】
本発明を用いることで、ＥＬ素子が水分や熱によって劣化することを抑制することができる。また、ＥＬ層からアルカリ金属が拡散してＴＦＴ特性に悪影響を与えることを防ぐことができる。その結果、ＥＬ表示装置の動作性能や信頼性を大幅に向上させることができる。
【０２７８】
また、そのようなＥＬ表示装置を表示ディスプレイとして有することで、画像品質が良く、耐久性のある（信頼性の高い）応用製品（電子装置）を生産することが可能となる。
【図面の簡単な説明】
【図１】 ＥＬ表示装置の画素部の断面構造を示す図。
【図２】 ＥＬ表示装置の画素部の上面構造及び構成を示す図。
【図３】 アクティブマトリクス型ＥＬ表示装置の作製工程を示す図。
【図４】 アクティブマトリクス型ＥＬ表示装置の作製工程を示す図。
【図５】 アクティブマトリクス型ＥＬ表示装置の作製工程を示す図。
【図６】 ＥＬモジュールの外観を示す図。
【図７】 ＥＬ表示装置の回路ブロック構成を示す図。
【図８】 ＥＬ表示装置の画素部を拡大した図。
【図９】 ＥＬ表示装置のサンプリング回路の素子構造を示す図。
【図１０】 ＥＬ表示装置の画素部の構成を示す図。
【図１１】 ＥＬ表示装置の画素部の断面構造を示す図。
【図１２】 ＥＬ表示装置の画素部の上面構造及び構成を示す図。
【図１３】 ＥＬ表示装置の画素部の断面構造を示す図。
【図１４】 ＥＬ表示装置の画素部の断面構造を示す図。
【図１５】 ＥＬ表示装置の画素部の上面構造及び構成を示す図。
【図１６】 電子装置の具体例を示す図。
【図１７】 ＥＬモジュールの外観を示す図。
【図１８】 コンタクト構造の作製工程を示す図。
【図１９】 インクジェット方式を説明するための図。
【図２０】 インクジェット方式によるＥＬ層形成を示す図。
【図２１】 ＥＬ層の積層構造を示す図。
【図２２】 電子装置の具体例を示す図。
【図２３】 ＥＬ表示装置の画素部の回路構成を示す図。
【図２４】 ＥＬ表示装置の画素部の回路構成を示す図。
【図２５】 ＥＬ表示装置の画素部の断面構造を示す図。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electro-optical device typified by an EL (electroluminescence) display device formed by forming a semiconductor element (an element using a semiconductor thin film) on a substrate, and the electro-optical device is also referred to as a display display (display unit). ) As an electronic device (electronic device). In particular, it relates to a manufacturing method thereof.
[0002]
[Prior art]
In recent years, a technology for forming a TFT on a substrate has greatly advanced, and application development to an active matrix display device has been advanced. In particular, a TFT using a polysilicon film has a higher field effect mobility (also referred to as mobility) than a TFT using a conventional amorphous silicon film, and thus can operate at high speed. For this reason, it is possible to control a pixel, which has been conventionally performed by a drive circuit outside the substrate, with a drive circuit formed on the same substrate as the pixel.
[0003]
Such an active matrix display device has various advantages such as a reduction in manufacturing cost, a reduction in size of the display device, an increase in yield, and a reduction in throughput by forming various circuits and elements on the same substrate. It is attracting attention as.
[0004]
In the active matrix EL display device, each pixel is provided with a switching element made of a TFT, and a driving element that controls current is operated by the switching element to cause the EL layer (light emitting layer) to emit light. For example, there is an EL display device described in US Pat. No. 5,684,365 (see Japanese Laid-Open Publication No. 8-234683) and Japanese Laid-Open Publication No. 10-189252.
[0005]
In order to display these EL display devices in color, an attempt has been made to arrange an EL layer that emits three primary colors of red (R), green (G), and blue (B) for each pixel. However, the material generally used for the EL layer is almost an organic material, and its patterning is very difficult. This is because the EL material itself is very weak against moisture and is difficult to handle as it easily dissolves in the developer.
[0006]
As a technique for solving such a problem, a technique for forming an EL layer by an inkjet method has been proposed. For example, Japanese Patent Application Laid-Open No. 10-012377 discloses an active matrix EL display body in which an EL layer is formed by an ink jet method. A similar technique is also disclosed in “Multicolor Pixel Patterning of Light-Emitting Polymers by Ink-jet Printing; T. Shimada et.al., p376-379, SID 99 DIGEST”.
[0007]
However, since the inkjet method is performed at normal pressure, it is disadvantageous in that the EL layer easily takes in contaminants from the outside air. That is, since it is formed in a state in which mobile ions such as alkali metal are easily contained, there is a problem that diffusion of alkali metal from there may cause a fatal blow to the TFT. In this specification, the term “alkali metal” includes alkali metals and alkaline earth metals.
[0008]
[Problems to be solved by the invention]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing an electro-optical device with high operation performance and high reliability, in particular, a method for manufacturing an EL display device. An object of the present invention is to improve the quality of an electronic device (electronic device) having the electro-optical device as a display for display (display unit) by improving the image quality of the electro-optical device.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, in the present invention, diffusion of alkali metal from an EL element formed by an ink jet method is prevented by an insulating film (passivation film) provided between the EL element and the TFT. Specifically, an insulating film that can prevent permeation of alkali metal is provided on the planarization film that covers the TFT. That is, an insulating film having a sufficiently low diffusion rate of alkali metal at the operating temperature (typically 0 to 100 ° C.) of the EL display device may be used.
[0010]
More preferably, an insulating film that does not transmit moisture and alkali metal and has high thermal conductivity (high heat dissipation effect) is selected, and this insulating film is provided in contact with the EL element, or more preferably The EL element is surrounded by an insulating film. That is, an insulating film that has a blocking effect on moisture and alkali metal and has a heat dissipation effect is provided at a position as close as possible to the EL element, and the deterioration of the EL element is suppressed by the insulating film.
[0011]
In the case where such an insulating film cannot be used as a single layer, an insulating film having a blocking effect on moisture and alkali metal and an insulating film having a heat dissipation effect can be stacked and used. Furthermore, an insulating film having a blocking effect on moisture, an insulating film having a blocking effect on alkali metal, and an insulating film having a heat dissipation effect can be stacked and used.
[0012]
In any case, when an EL layer is formed using an ink jet method, it is necessary to take measures to completely protect the TFT that drives the EL element from alkali metal, and further deterioration of the EL layer itself (EL element) In order to suppress the deterioration of water), it is necessary to take measures against both moisture and heat at the same time.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view of a pixel of an EL display device according to the present invention, FIG. 2A is a top view thereof, and FIG. 2B is a circuit configuration thereof. Actually, a plurality of such pixels are arranged in a matrix to form a pixel portion (image display portion).
[0014]
Note that the cross-sectional view of FIG. 1 shows a cut surface cut along AA ′ in the top view shown in FIG. Here, since the same reference numerals are used in FIG. 1 and FIG. Moreover, although two pixels are illustrated in the top view of FIG. 2, both have the same structure.
[0015]
In FIG. 1, 11 is a substrate, and 12 is an insulating film (hereinafter referred to as a base film) serving as a base. As the substrate 11, a glass substrate, a glass ceramic substrate, a quartz substrate, a silicon substrate, a ceramic substrate, a metal substrate, or a plastic substrate (including a plastic film) can be used.
[0016]
The base film 12 is particularly effective when a substrate containing mobile ions or a conductive substrate is used, but it need not be provided on the quartz substrate. As the base film 12, an insulating film containing silicon may be used. Note that in this specification, the “insulating film containing silicon” specifically includes silicon, oxygen, or nitrogen such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film (indicated by SiOxNy) at a predetermined ratio. An insulating film.
[0017]
In addition, it is effective to dissipate the heat generated by the TFT by providing the base film 12 with a heat dissipation effect in order to prevent the deterioration of the TFT or the EL element. Any known material can be used to provide a heat dissipation effect.
[0018]
Here, two TFTs are formed in the pixel. Reference numeral 201 denotes a TFT that functions as a switching element (hereinafter referred to as a switching TFT), and 202 denotes a TFT that functions as a current control element that controls the amount of current flowing to the EL element (hereinafter referred to as a current control TFT). Is also formed of an n-channel TFT.
[0019]
Since the field effect mobility of the n-channel TFT is larger than that of the p-channel TFT, the operation speed is high and a large current is likely to flow. Even when the same amount of current flows, the n-channel TFT can be made smaller in TFT size. Therefore, it is preferable to use an n-channel TFT as a current control TFT because the effective area of the display portion is widened.
[0020]
The p-channel TFT has the advantage that hot carrier injection is hardly a problem and has a low off-current value, and examples of using it as a switching TFT and an example of using it as a current control TFT have already been reported. However, the present invention solves the problem of hot carrier injection and the problem of off-current value even in the n-channel TFT by adopting a structure where the positions of the LDD regions are different, and all the TFTs in all the pixels are n-channel type. Another characteristic is that it is a TFT.
[0021]
However, in the present invention, the switching TFT and the current control TFT need not be limited to n-channel TFTs, and p-channel TFTs can be used for both or one of them.
[0022]
The switching TFT 201 includes a source region 13, a drain region 14, LDD regions 15a to 15d, an active layer including a high concentration impurity region 16 and channel forming regions 17a and 17b, a gate insulating film 18, gate electrodes 19a and 19b, and a first interlayer. An insulating film 20, a source wiring 21, and a drain wiring 22 are formed.
[0023]
In addition, as shown in FIG. 2, the gate electrodes 19a and 19b have a double gate structure in which the gate electrodes 19a and 19b are electrically connected by a gate wiring 211 formed of another material (a material having a lower resistance than the gate electrodes 19a and 19b). ing. Needless to say, not only a double gate structure but also a so-called multi-gate structure (a structure including an active layer having two or more channel formation regions connected in series) such as a triple gate structure may be used. The multi-gate structure is extremely effective in reducing the off-current value. In the present invention, the switching TFT 201 of the pixel has a multi-gate structure, thereby realizing a switching element with a low off-current value.
[0024]
The active layer is formed of a semiconductor film including a crystal structure. That is, a single crystal semiconductor film, a polycrystalline semiconductor film, or a microcrystalline semiconductor film may be used. The gate insulating film 18 may be formed of an insulating film containing silicon. Any conductive film can be used for the gate electrode, the source wiring, or the drain wiring.
[0025]
Further, in the switching TFT 201, the LDD regions 15a to 15d are provided so as not to overlap the gate electrodes 19a and 19b with the gate insulating film 18 interposed therebetween. Such a structure is very effective in reducing the off-current value.
[0026]
Note that it is more preferable to provide an offset region (a region made of a semiconductor layer having the same composition as the channel formation region to which no gate voltage is applied) between the channel formation region and the LDD region in order to reduce the off-state current value. In the case of a multi-gate structure having two or more gate electrodes, a high-concentration impurity region provided between channel formation regions is effective in reducing the off-current value.
[0027]
As described above, a switching element having a sufficiently low off-current value can be realized by using a multi-gate TFT as the pixel switching TFT 201. Therefore, the gate voltage of the current control TFT can be maintained for a sufficient time (between the selection and the next selection) without providing a capacitor as shown in FIG. 2 of JP-A-10-189252.
[0028]
That is, it is possible to eliminate the capacitor that has been a factor for reducing the effective light emitting area, and it is possible to widen the effective light emitting area. This means that the image quality of the EL display device can be brightened.
[0029]
Next, the current control TFT 202 includes an active layer including a source region 31, a drain region 32, an LDD region 33, and a channel formation region 34, a gate insulating film 18, a gate electrode 35, a first interlayer insulating film 20, a source wiring 36, and A drain wiring 37 is formed. The gate electrode 35 has a single gate structure, but may have a multi-gate structure.
[0030]
As shown in FIG. 2, the drain of the switching TFT is electrically connected to the gate of the current control TFT. Specifically, the gate electrode 35 of the current control TFT 202 is electrically connected to the drain region 14 of the switching TFT 201 via the drain wiring (also referred to as connection wiring) 22. The source wiring 36 is connected to the current supply line 212.
[0031]
The current control TFT 202 is characterized in that the channel width is larger than the channel width of the switching TFT 201. That is, as shown in FIG. 8, when the channel length of the switching TFT is L1, the channel width is W1, the channel length of the current control TFT is L2, and the channel width is W2, W2 / L2 ≧ 5 × W1 / The relational expression L1 (preferably W2 / L2 ≧ 10 × W1 / L1) is established. For this reason, it is possible to easily flow more current than the switching TFT.
[0032]
Note that the channel length L1 of the switching TFT having a multi-gate structure is the sum of the channel lengths of two or more formed channel formation regions. In the case of FIG. 8, since it has a double gate structure, the channel length L1 of the switching TFT is obtained by adding the channel lengths L1a and L1b of the two channel formation regions.
[0033]
In the present invention, the channel lengths L1 and L2 and the channel widths W1 and W2 are not limited to specific numerical ranges, but W1 is 0.1 to 5 μm (typically 1 to 3 μm), and W2 is 0. The thickness is preferably 5 to 30 μm (typically 2 to 10 μm). At this time, L1 is preferably 0.2 to 18 μm (typically 2 to 15 μm), and L2 is preferably 0.1 to 50 μm (typically 1 to 20 μm).
[0034]
In the current control TFT, it is desirable to set the channel length L to be longer in order to prevent an excessive current flow. Preferably, W2 / L2 ≧ 3 (preferably W2 / L2 ≧ 5). Desirable Haichi It is set to 0.5 to 2 μA (preferably 1 to 1.5 μA) per pixel.
[0035]
By setting these numerical ranges, all standards are covered, from EL display devices having the number of VGA class pixels (640 × 480) to EL display devices having the number of high-definition class pixels (1920 × 1080 or 1280 × 1024). be able to.
[0036]
The length (width) of the LDD region formed in the switching TFT 201 may be 0.5 to 3.5 μm, typically 2.0 to 2.5 μm.
[0037]
In the EL display device shown in FIG. 1, in the current control TFT 202, an LDD region 33 is provided between the drain region 32 and the channel formation region 34, and the LDD region 33 sandwiches the gate insulating film 18. It is also characterized in that it has a region that overlaps with the gate electrode 35 and a region that does not overlap.
[0038]
The current control TFT 202 supplies a current for causing the EL element 203 to emit light, and at the same time controls the supply amount to enable gradation display. For this reason, it is necessary to take measures against deterioration by hot carrier injection so as not to deteriorate even when a current is passed. In addition, when displaying black, the current control TFT 202 is turned off. However, if the off-current value is high, a clear black display cannot be obtained, resulting in a decrease in contrast. Therefore, it is necessary to suppress the off-current value.
[0039]
Regarding deterioration due to hot carrier injection, it is known that a structure in which an LDD region overlaps a gate electrode is very effective. However, if the entire LDD region is overlaid on the gate electrode, the off-current value increases. Therefore, the applicant has a novel structure in which LDD regions that do not overlap with the gate electrode are provided in series, thereby preventing hot carriers and off-current. It solves value measures at the same time.
[0040]
At this time, the length of the LDD region overlapping with the gate electrode may be 0.1 to 3 μm (preferably 0.3 to 1.5 μm). If it is too long, the parasitic capacitance is increased, and if it is too short, the effect of preventing hot carriers is weakened. The length of the LDD region that does not overlap with the gate electrode may be 1.0 to 3.5 μm (preferably 1.5 to 2.0 μm). If it is too long, it will not be possible to pass a sufficient current.
[0041]
Further, in the above structure, a parasitic capacitance is formed in a region where the gate electrode and the LDD region overlap with each other. Therefore, it is preferable not to provide between the source region 31 and the channel formation region 34. Since the current control TFT always has the same direction of carrier (electrons) flow, it is sufficient to provide an LDD region only on the drain region side.
[0042]
Further, from the viewpoint of increasing the amount of current that can be passed, the thickness of the active layer (especially the channel formation region) of the current control TFT 202 may be increased (preferably 50 to 100 nm, more preferably 60 to 80 nm). It is valid. Conversely, in the case of the switching TFT 201, from the viewpoint of reducing the off-current value, the thickness of the active layer (especially the channel formation region) should be reduced (preferably 20 to 50 nm, more preferably 25 to 40 nm). Is also effective.
[0043]
Next, reference numeral 41 denotes a first passivation film, and the film thickness may be 10 nm to 1 μm (preferably 200 to 500 nm). As a material, an insulating film containing silicon (in particular, a silicon nitride oxide film or a silicon nitride film is preferable) can be used. The passivation film 41 has a role of protecting the formed TFT from alkali metal and moisture. The EL layer finally provided above the TFT contains an alkali metal such as sodium. That is, the first passivation film 41 also functions as a protective layer that prevents these alkali metals (movable ions) from entering the TFT side.
[0044]
It is also effective to prevent thermal degradation of the EL layer by providing the first passivation film 41 with a heat dissipation effect. However, since the EL display device having the structure shown in FIG. 1 emits light toward the substrate 11, the first passivation film 41 needs to have translucency. In the case where an organic material is used for the EL layer, it is preferable that an insulating film that easily releases oxygen is not used because it deteriorates due to bonding with oxygen.
[0045]
As a translucent material that prevents alkali metal from passing through and has a heat dissipation effect, at least one element selected from B (boron), C (carbon), and N (nitrogen), Al (aluminum), Si ( And an insulating film containing at least one element selected from silicon and P (phosphorus). For example, aluminum nitride represented by aluminum nitride (AlxNy), silicon carbide represented by silicon carbide (SixCy), silicon nitride represented by silicon nitride (SixNy), and boron nitride (BxNy) Boron phosphide represented by boron nitride and boron phosphide (BxPy) can be used. In addition, an aluminum oxide typified by aluminum oxide (AlxOy) has excellent translucency and a thermal conductivity of 20 Wm. ^-1 K ^-1 It can be said that it is one of the preferable materials. These materials not only have the above effects, but also have an effect of preventing moisture from entering. In the translucent material, x and y are arbitrary integers.
[0046]
In addition, another element can also be combined with the said compound. For example, it is possible to use aluminum nitride oxide represented by AlNxOy by adding nitrogen to aluminum oxide. This material has not only a heat dissipation effect but also an effect of preventing moisture, alkali metal and the like from entering. In the aluminum nitride oxide, x and y are arbitrary integers.
[0047]
Moreover, the material described in Unexamined-Japanese-Patent No. 62-90260 can be used. That is, an insulating film containing Si, Al, N, O, and M (where M is at least one rare earth element, preferably Ce (cerium), Yb (ytterbium), Sm (samarium), Er (erbium), Y ( Yttrium), La (lanthanum), Gd (gadolinium), Dy (dysprosium), and Nd (neodymium). These materials have not only a heat dissipation effect but also an effect of preventing intrusion of moisture, alkali metals, and the like.
[0048]
Alternatively, a carbon film including at least a diamond thin film or an amorphous carbon film (especially those having characteristics close to diamond are called diamond-like carbon films) can be used. These have very high thermal conductivity and are extremely effective as a heat dissipation layer. However, as the film thickness increases, the film becomes brownish and the transmittance decreases. Therefore, it is preferable to use the film as thin as possible (preferably 5 to 100 nm).
[0049]
Note that the purpose of the first passivation film 41 is to protect the TFT from alkali metals and moisture to the last, and therefore the effect thereof must not be impaired. Accordingly, a thin film made of a material having a heat dissipation effect can be used alone, but these thin films and an insulating film (typically a silicon nitride film (SixNy) or a nitridation oxide) that can prevent alkali metal or moisture from permeating. It is effective to stack a silicon film (SiOxNy). Note that in the silicon nitride film or the silicon nitride oxide film, x and y are arbitrary integers.
[0050]
In addition, the EL display device can be roughly divided into four color display methods, a method of forming three types of EL elements corresponding to RGB, a method of combining a white light emitting EL element and a color filter, and blue or blue-green. There are a method in which a light emitting EL element and a phosphor (fluorescent color conversion layer: CCM) are combined, and a method in which EL elements corresponding to RGB are stacked using a transparent electrode as a cathode (counter electrode).
[0051]
The structure of FIG. 1 is an example in the case of using a method of forming three types of EL elements corresponding to RGB. Although only one pixel is shown in FIG. 1, pixels having the same structure are formed corresponding to the respective colors of red, green, and blue, whereby color display can be performed. A known material may be used for the EL layers of these colors.
[0052]
However, the present invention can be carried out regardless of the light emission method, and all the above four methods can be used in the present invention.
[0053]
When the first passivation film 41 is formed, a second interlayer insulating film (which may be referred to as a planarizing film) 44 is formed so as to cover each TFT, and a step formed by the TFT is planarized. As the second interlayer insulating film 44, a resin film is preferable, and polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like may be used. Of course, an inorganic film may be used if sufficient planarization is possible.
[0054]
It is very important to flatten the step due to the TFT by the second interlayer insulating film 44. Since an EL layer to be formed later is very thin, a light emission defect may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the EL layer can be formed as flat as possible.
[0055]
Reference numeral 45 denotes a second passivation film, which plays an important role in blocking alkali metal diffusing from the EL element. The film thickness may be 5 nm to 1 μm (typically 20 to 300 nm). The second passivation film 45 is an insulating film that can prevent permeation of alkali metal. As the material, the material used as the first passivation film 41 can be used.
[0056]
The second passivation film 45 also functions as a heat dissipation layer that functions to release heat generated in the EL element and prevent the heat from accumulating in the EL element. Further, when the second interlayer insulating film 44 is a resin film, since it is vulnerable to heat, heat generated in the EL element is prevented from adversely affecting the second interlayer insulating film 44.
[0057]
As described above, it is effective to planarize a TFT with a resin film in manufacturing an EL display device. However, there has been no structure that takes into account deterioration of a resin film due to heat generated in an EL element. It can be said that the present invention solves this problem by providing the second passivation film 45.
[0058]
In addition, the second passivation film 45 functions as a protective layer for preventing the alkali metal in the EL layer from diffusing to the TFT side as well as preventing the deterioration due to the heat, and further to the EL layer side to the TFT side. It also functions as a protective layer that prevents moisture and oxygen from entering.
[0059]
As described above, the TFT side and the EL element side are separated from each other by an insulating film that has a high heat dissipation effect and can prevent the permeation of moisture and alkali metal. It can be said that this is a configuration that the display device does not have.
[0060]
Reference numeral 46 denotes a pixel electrode (anode of the EL element) made of a transparent conductive film. After opening contact holes (openings) in the second passivation film 45, the second interlayer insulating film 44, and the first passivation film 41, The opening is formed so as to be connected to the drain wiring 37 of the current control TFT 202.
[0061]
After the pixel electrode 46 is formed, banks 101 a and 101 b made of a resin film are formed on the second passivation film 45. In this embodiment mode, a photosensitive polyimide film is formed by a spin coating method, and the banks 101a and 101b are formed by patterning. The banks 101a and 101b are molds for forming an EL layer by an ink jet method, and the locations where EL elements are formed are defined by the arrangement of the banks.
[0062]
When the banks 101a and 101b are formed, an EL layer (an organic material is preferable) 47 is formed next. The EL layer 47 is used in a single layer or a laminated structure, but is often used in a laminated structure. Various laminated structures have been proposed by combining a light emitting layer, an electron transport layer, an electron injection layer, a hole injection layer, a hole transport layer, or the like, but any structure may be used in the present invention. Further, the EL layer may be doped with a fluorescent dye or the like.
[0063]
Any known EL material can be used in the present invention. As a known material, an organic material is widely known, and it is preferable to use an organic material in consideration of a driving voltage. As the organic EL material, for example, materials disclosed in the following US patents or publications can be used.
[0064]
U.S. Patent No. 4,356,429, U.S. Patent No. 4,539,507, U.S. Patent No. 4,720,432, U.S. Patent No. 4,769,292, U.S. Patent No. 4,885,211, U.S. Patent No. 4,950,950, U.S. Patent No. 5,059,861, U.S. Patent No. 5,047,687, U.S. Patent No. 5,073,446, U.S. Patent No. 5,059,862, US Pat. No. 5,061,617, US Pat. No. 5,151,629, US Pat. No. 5,294,869, US Pat. No. 5,294,870, JP-A-10-189252, JP-A JP-A-8-241048, JP-A-8-78159.
[0065]
Specifically, as the organic material for the hole injection layer, those represented by the following general formula can be used.
[0066]
[Chemical 1]

[0067]
Where Q is N or C—R (carbon chain), M is a metal, metal oxide or metal halide, R is hydrogen, alkyl, aralkyl, allyl or alkaryl, T1, T2 are hydrogen, An unsaturated six-membered ring containing a substituent such as alkyl or halogen.
[0068]
An aromatic tertiary amine can be used as the organic material for the hole transport layer, and preferably includes tetraallyldiamine represented by the following general formula.
[0069]
[Chemical 2]

[0070]
Where Are is an arylene group, n is an integer of 1 to 4, Ar, R ₇ , R ₈ , R ₉ Are the selected allyl groups.
[0071]
In addition, a metal oxinoid compound can be used as the organic material for the EL layer, the electron transport layer, or the electron injection layer. What is necessary is just to use what is represented with the following general formulas as a metal oxinoid compound.
[0072]
[Chemical 3]

[0073]
Where R ₂ -R ₇ Can be replaced, and the following metal oxinoid compounds can also be used.
[0074]
[Formula 4]

[0075]
Where R ₂ -R ₇ Is as defined above, L ₁ -L _Five Is a group of carbohydrates containing 1 to 12 carbon elements and L ₁ , L ₂ Or L ₂ , L _Three Together can form a benzo ring. Moreover, the following metal oxinoid compounds may be used.
[0076]
[Chemical formula 5]

[0077]
Where R ₂ -R ₆ Can be replaced. As described above, the organic EL material includes a coordination compound having an organic ligand. However, the above example is an example of the organic EL material that can be used as the EL material of the present invention, and it is not absolutely necessary to limit to this.
[0078]
In the present invention, since an ink jet method is used as a method for forming an EL layer, polymer materials are often used as preferable EL materials. Typical polymer materials include polymer materials such as polyparaphenylene vinylene (PPV), polyfluorene, and polyvinyl carbazole (PVK). For colorization, for example, cyanopolyphenylene vinylene is preferable for the red light emitting material, polyphenylene vinylene is preferable for the green light emitting material, and polyphenylene vinylene and polyalkylphenylene are preferable for the blue light emitting material.
[0079]
There are various types of PPV organic EL materials. For example, the following molecular formulas have been announced.
("H. Shenk, H. Becker, O. Gelsen, E. Kluge, W. Kreuder, and H. Spreitzer," Polymers for Light Emitting Diodes ", Euro Display, Proceedings, 1999, p. 33-37")
[0080]
[Chemical 6]

[0081]
[Chemical 7]

[0082]
Further, polyphenylvinyl having a molecular formula described in JP-A-10-92576 can also be used. The molecular formula is:
[0083]
[Chemical 8]

[0084]
[Chemical 9]

[0085]
The PVK organic EL material has the following molecular formula.
[0086]
[Chemical Formula 10]

[0087]
The polymer-based organic EL material can be applied after being dissolved in a solvent in a polymer state, or can be polymerized after being dissolved in a solvent and applied in a monomer state. When applied in the monomer state, a polymer precursor is first formed and polymerized by heating in vacuum to a polymer.
[0088]
As specific light-emitting layers, cyanopolyphenylene vinylene may be used for a light-emitting layer that emits red light, polyphenylene vinylene may be used for a light-emitting layer that emits green light, and polyphenylene vinylene or polyalkylphenylene may be used for a light-emitting layer that emits blue light. The film thickness may be 30 to 150 nm (preferably 40 to 100 nm).
[0089]
Typical solvents include toluene, xylene, cymene, chloroform, dichloromethane, γ-butyl lactone, butyl cellosolve or NMP (N-methyl-2-pyrrolidone). It is also effective to add an additive for increasing the viscosity of the coating solution.
[0090]
However, the above example is an example of the organic EL material that can be used as the EL material of the present invention, and it is not absolutely necessary to limit to this. With respect to the organic EL material that can be used in the ink jet method, all materials described in JP-A-10-012377 can be cited.
[0091]
The ink jet method is roughly classified into a bubble jet (registered trademark) method (also referred to as a thermal ink jet method) and a piezo method, but the piezo method is desirable for carrying out the present invention. The difference between the two will be described with reference to FIG.
[0092]
FIG. 19A shows an example of a piezo method, in which 1901 is a piezo element (piezoelectric element), 1902 is a metal pipe, and 1903 is a mixed liquid of an ink material and an EL material (hereinafter referred to as an EL forming solution). When voltage is applied, the piezo element is deformed and the metal pipe 1902 is also deformed. As a result, the internal EL forming solution 1903 is ejected as a droplet 1904. In this way, the EL forming solution is applied by controlling the voltage applied to the piezo element. In this case, since the EL forming solution 1903 is pushed out by a physical external pressure, there is no influence on the composition or the like.
[0093]
FIG. 19B shows an example of a bubble jet (registered trademark) system, in which 1905 is a heating element, 1906 is a metal pipe, and 1907 is an EL forming solution. When energized, the heating element 1905 generates heat, and bubbles 1908 are generated in the EL forming solution 1907. As a result, the EL forming solution 1907 is pushed out by the bubbles and fired as droplets 1909. In this way, the EL forming solution is applied by controlling the current to the heating element. In this case, since the EL forming solution 1907 is heated by the heating element, there is a possibility that the EL forming solution 1907 may have an adverse effect depending on the composition of the EL material.
[0094]
Further, when an EL material is actually applied and formed on the device using an ink jet method, an EL layer is formed in a form as shown in FIG. In FIG. 20, reference numeral 91 denotes a pixel portion, 92 and 93 denote drive circuits, and a plurality of pixel electrodes 94 are formed in the pixel portion 91. Although not shown, each pixel electrode is connected to a current control TFT. In practice, banks (see FIG. 1) for separating the pixel electrodes 94 are provided, but they are not shown here.
[0095]
Then, a red light emitting EL layer 95, a green light emitting EL layer 96, and a blue light emitting EL layer 97 are formed by an inkjet method. At this time, first, the EL layer 95 that emits red light may be formed first, and then the EL layer 96 that emits green light and the EL layer 97 that emits blue light may be sequentially formed. In addition, a baking (firing) treatment is necessary to remove the solvent contained in the EL forming solution. This baking process may be performed after all the EL layers are formed, or may be performed individually when the formation of the EL layers of the respective colors is completed.
[0096]
Further, when the EL layer is formed, as shown in FIG. 20, the pixel in which the red light emitting EL layer 95 is formed (pixel corresponding to red) and the pixel in which the green light emitting EL layer 96 is formed (corresponding to green). Pixel) and the pixel on which the blue light emitting EL layer 97 is formed (pixel corresponding to blue) are always in contact with each other.
[0097]
Such an arrangement is called a so-called delta arrangement, and is effective for good color display. Since the advantage of the inkjet method is that the EL layers of the respective colors can be individually arranged, it can be said that it is the most preferable embodiment when used for an EL display device having a pixel portion in a delta arrangement.
[0098]
Further, when forming the EL layer 47, it is desirable that the treatment atmosphere is a dry atmosphere with as little moisture as possible, and is performed in an inert gas. Since the EL layer easily deteriorates due to the presence of moisture and oxygen, it is necessary to eliminate such factors as much as possible when forming the EL layer. For example, a dry nitrogen atmosphere or a dry argon atmosphere is preferable.
[0099]
After the EL layer 47 is formed by the inkjet method as described above, a cathode 48 and a protective electrode 49 are formed next. In this specification, a light-emitting element formed using a pixel electrode (anode), an EL layer, and a cathode is referred to as an EL element.
[0100]
As the cathode 48, a material containing magnesium (Mg), lithium (Li), cesium (Cs), barium (Ba), potassium (K), beryllium (Be), or calcium (Ca) having a small work function is used. An electrode made of MgAg (a material in which Mg and Al are mixed at Mg: Ag = 10: 1) is preferably used. Other examples include MgAgAl electrodes, LiAl electrodes, and LiFAl electrodes. The protective electrode 49 is an electrode provided for protecting the cathode 48 from external moisture and the like, and a material containing aluminum (Al) or silver (Ag) is used. The protective electrode 49 also has a heat dissipation effect.
[0101]
Note that the EL layer 47 and the cathode 48 are desirably formed continuously in a dry inert atmosphere without being released to the atmosphere. This is because, when an organic material is used as the EL layer, it is very sensitive to moisture, so that moisture absorption when released to the atmosphere is avoided. Furthermore, it is better to continuously form not only the EL layer 47 and the cathode 48 but also the protective electrode 49 thereon.
[0102]
Reference numeral 50 denotes a third passivation film, and the film thickness may be 10 nm to 1 μm (preferably 200 to 500 nm). The purpose of providing the third passivation film 50 is mainly for the purpose of protecting the EL layer 47 from moisture. However, as with the second passivation film 45, a heat dissipation effect may be provided. Accordingly, the same material as the first passivation film 41 can be used as the forming material. However, in the case where an organic material is used for the EL layer 47, there is a possibility that the EL layer 47 may be deteriorated due to bonding with oxygen. Therefore, it is preferable not to use an insulating film that easily releases oxygen.
[0103]
Further, since the EL layer is vulnerable to heat as described above, it is desirable to form the film at as low a temperature as possible (preferably in a temperature range from room temperature to 120 ° C.). Therefore, it can be said that a plasma CVD method, a sputtering method, a vacuum deposition method, an ion plating method, or a solution coating method (spin coating method) is a preferable film forming method.
[0104]
As described above, it is possible to sufficiently suppress the deterioration of the EL element only by providing the second passivation film 45, but it is more preferable that the EL element is referred to as the second passivation film 45 and the third passivation film 50. Surrounded by a two-layer insulating film sandwiched between them, moisture and oxygen are prevented from entering the EL layer, alkali metal diffusion from the EL layer is prevented, and heat accumulation in the EL layer is prevented. As a result, the EL layer can be further prevented from deteriorating and a highly reliable EL display device can be obtained.
[0105]
Further, the EL display device of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 1, and TFTs having different structures are arranged in the pixels according to functions. As a result, a switching TFT having a sufficiently low off-current value and a current control TFT resistant to hot carrier injection can be formed in the same pixel, have high reliability, and can display a good image (operation) An EL display device with high performance is obtained.
[0106]
Although the multi-gate TFT is used as the switching TFT in the pixel structure of FIG. 1, the arrangement of the LDD region and the like need not be limited to those shown in FIG.
[0107]
The present invention having the above-described configuration will be described in more detail with the following examples.
[0108]
[Example 1]
An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing a TFT of a pixel portion and a driver circuit portion provided around the pixel portion will be described. However, in order to simplify the description, a CMOS circuit, which is a basic circuit, is illustrated with respect to the drive circuit.
[0109]
First, as shown in FIG. 3A, a base film 301 is formed to a thickness of 300 nm over a glass substrate 300. In this embodiment, a silicon nitride oxide film is stacked as the base film 301. At this time, the nitrogen concentration in contact with the glass substrate 300 is preferably set to 10 to 25 wt%.
[0110]
In addition, it is effective to provide an insulating film made of the same material as the first passivation film 41 shown in FIG. Since the current control TFT flows a large current, it easily generates heat, and it is effective to provide an insulating film having a heat dissipation effect as close as possible.
[0111]
Next, an amorphous silicon film (not shown) having a thickness of 50 nm is formed on the base film 301 by a known film formation method. Note that the semiconductor film is not limited to an amorphous silicon film, and any semiconductor film including an amorphous structure (including a microcrystalline semiconductor film) may be used. Further, a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film may be used. The film thickness may be 20 to 100 nm.
[0112]
Then, the amorphous silicon film is crystallized by a known technique to form a crystalline silicon film (also referred to as a polycrystalline silicon film or a polysilicon film) 302. Known crystallization methods include a thermal crystallization method using an electric furnace, a laser annealing crystallization method using laser light, and a lamp annealing crystallization method using infrared light. In this embodiment, crystallization is performed using excimer laser light using XeCl gas.
[0113]
In this embodiment, a pulse oscillation type excimer laser beam processed into a linear shape is used. However, a rectangular shape, a continuous oscillation type argon laser beam, or a continuous oscillation type excimer laser beam may be used. .
[0114]
In this embodiment, a crystalline silicon film is used as an active layer of a TFT, but an amorphous silicon film can also be used. However, since the current control TFT needs to pass a large current, it is advantageous to use a crystalline silicon film that easily allows a current to flow.
[0115]
It is effective to form the active layer of the switching TFT that needs to reduce the off current from an amorphous silicon film, and to form the active layer of the current control TFT from a crystalline silicon film. Since the amorphous silicon film has low carrier mobility, it is difficult for an electric current to flow and an off current is difficult to flow. That is, the advantages of both an amorphous silicon film that hardly allows current to flow and a crystalline silicon film that easily allows current to flow can be utilized.
[0116]
Next, as shown in FIG. 3B, a protective film 303 made of a silicon oxide film is formed on the crystalline silicon film 302 to a thickness of 130 nm. This thickness may be selected in the range of 100 to 200 nm (preferably 130 to 170 nm). Any other film may be used as long as it is an insulating film containing silicon. This protective film 303 is provided in order to prevent the crystalline silicon film from being directly exposed to plasma when an impurity is added and to enable fine concentration control.
[0117]
Then, resist masks 304 a and 304 b are formed thereon, and an impurity element imparting n-type (hereinafter referred to as an n-type impurity element) is added through the protective film 303. Note that as the n-type impurity element, an element typically belonging to Group 15, typically phosphorus or arsenic can be used. In this embodiment, phosphine (PH _Three ) Using a plasma doping method in which plasma is excited without mass separation, and phosphorus is 1 × 10 ¹⁸ atoms / cm ^Three Add at a concentration of Of course, an ion implantation method for performing mass separation may be used.
[0118]
In the n-type impurity regions 305 and 306 formed by this step, an n-type impurity element is 2 × 10 6. ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three (Typically 5 × 10 ¹⁷ ~ 5x10 ¹⁸ atoms / cm ^Three ) Adjust the dose so that it is included at the concentration of
[0119]
Next, as shown in FIG. 3C, the protective film 303 is removed, and the added element belonging to Group 15 is activated. As the activation means, a known technique may be used. In this embodiment, activation is performed by irradiation with excimer laser light. Of course, the pulse oscillation type or the continuous oscillation type may be used, and it is not necessary to limit to the excimer laser beam. However, since the purpose is to activate the added impurity element, it is preferable to irradiate with energy that does not melt the crystalline silicon film. Note that laser light may be irradiated with the protective film 303 attached.
[0120]
Note that activation by heat treatment may be used in combination with the activation of the impurity element by the laser beam. When activation by heat treatment is performed, heat treatment at about 450 to 550 ° C. may be performed in consideration of the heat resistance of the substrate.
[0121]
By this step, the end portion of the n-type impurity regions 305 and 306, that is, the boundary portion (junction portion) with the region to which the n-type impurity element existing around the n-type impurity regions 305 and 306 is not added becomes clear. . This means that when the TFT is later completed, the LDD region and the channel formation region can form a very good junction.
[0122]
Next, as shown in FIG. 3D, unnecessary portions of the crystalline silicon film are removed, and island-shaped semiconductor films (hereinafter referred to as active layers) 307 to 310 are formed.
[0123]
Next, as illustrated in FIG. 3E, a gate insulating film 311 is formed to cover the active layers 307 to 310. As the gate insulating film 311, an insulating film containing silicon with a thickness of 10 to 200 nm, preferably 50 to 150 nm may be used. This may be a single layer structure or a laminated structure. In this embodiment, a silicon nitride oxide film having a thickness of 110 nm is used.
[0124]
Next, a conductive film having a thickness of 200 to 400 nm is formed and patterned to form gate electrodes 312 to 316. Note that in this embodiment, the gate electrode and a wiring (hereinafter referred to as a gate wiring) electrically connected to the gate electrode are formed using different materials. Specifically, a material having a resistance lower than that of the gate electrode is used for the gate wiring. This is because a material that can be finely processed is used for the gate electrode, and a material that has a low wiring resistance is used for the gate wiring even though it cannot be finely processed. Of course, the gate electrode and the gate wiring may be formed of the same material.
[0125]
The gate electrode may be formed of a single-layer conductive film, but it is preferable to form a stacked film of two layers or three layers as necessary. Any known conductive film can be used as the material of the gate electrode. However, a material that can be finely processed as described above, specifically, that can be patterned to a line width of 2 μm or less is preferable.
[0126]
Typically, a film made of an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), or chromium (Cr), or a nitride film of the element (typically A tantalum nitride film, a tungsten nitride film, a titanium nitride film), an alloy film (typically Mo—W alloy, Mo—Ta alloy), or a silicide film of the above elements (typically tungsten silicide). A film, a titanium silicide film) or a silicon film having conductivity can be used. Of course, it may be used as a single layer or may be laminated.
[0127]
In this embodiment, a laminated film including a tantalum nitride (TaN) film having a thickness of 50 nm and a Ta film having a thickness of 350 nm is used. This may be formed by sputtering. Further, when an inert gas such as Xe or Ne is added as a sputtering gas, peeling of the film due to stress can be prevented.
[0128]
At this time, the gate electrodes 313 and 316 are formed so as to overlap part of the n-type impurity regions 305 and 306 with the gate insulating film 311 interposed therebetween. This overlapped portion later becomes an LDD region overlapping with the gate electrode.
[0129]
Next, as shown in FIG. 4A, an n-type impurity element (phosphorus in this embodiment) is added in a self-aligning manner using the gate electrodes 312 to 316 as masks. The impurity regions 317 to 323 thus formed are adjusted so that phosphorus is added at a concentration of 1/2 to 1/10 (typically 1/3 to 1/4) of the n-type impurity regions 305 and 306. To do. Specifically, 1 × 10 ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three (Typically 3x10 ¹⁷ ~ 3x10 ¹⁸ atoms / cm ^Three ) Is preferred.
[0130]
Next, as shown in FIG. 4B, resist masks 324a to 324d are formed so as to cover the gate electrodes and the like, and an n-type impurity element (phosphorus in this embodiment) is added to contain phosphorus at a high concentration. Impurity regions 325 to 331 are formed. Again phosphine (PH _Three The concentration of phosphorus in this region is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three (Typically 2 × 10 ²⁰ ~ 5x10 ²⁰ atoms / cm ^Three ).
[0131]
In this step, the source region or drain region of the n-channel TFT is formed. However, in the switching TFT, a part of the n-type impurity regions 320 to 322 formed in the step of FIG. This remaining region corresponds to the LDD regions 15a to 15d of the switching TFT in FIG.
[0132]
Next, as shown in FIG. 4C, the resist masks 324a to 324d are removed, and a new resist mask 332 is formed. Then, a p-type impurity element (boron in this embodiment) is added to form impurity regions 333 and 334 containing boron at a high concentration. Here, diborane (B ₂ H ₆ 3 × 10 by ion doping method using ²⁰ ~ 3x10 ^{twenty one} atoms / cm ^Three (Typically 5 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three ) Add boron to achieve a concentration.
[0133]
Note that the impurity regions 333 and 334 already have 1 × 10 6. ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three However, the boron added here is added at a concentration at least three times that of phosphorus. Therefore, the n-type impurity region formed in advance is completely inverted to the P-type and functions as a P-type impurity region.
[0134]
Next, after removing the resist mask 332, the n-type or p-type impurity element added at each concentration is activated. As the activation means, furnace annealing, laser annealing, or lamp annealing can be used. In this embodiment, heat treatment is performed in an electric furnace in a nitrogen atmosphere at 550 ° C. for 4 hours.
[0135]
At this time, it is important to eliminate oxygen in the atmosphere as much as possible. This is because the presence of even a small amount of oxygen oxidizes the exposed surface of the gate electrode, which increases resistance and makes it difficult to make ohmic contact later. Therefore, the oxygen concentration in the treatment atmosphere in the activation step is 1 ppm or less, preferably 0.1 ppm or less.
[0136]
Next, when the activation process is completed, a gate wiring 335 having a thickness of 300 nm is formed. As a material of the gate wiring 335, a metal film containing aluminum (Al) or copper (Cu) as a main component (occupying 50 to 100% as a composition) may be used. As the arrangement, the gate electrodes 314 and 315 (corresponding to the gate electrodes 19a and 19b in FIG. 2) of the switching TFT are formed so as to be electrically connected as in the gate wiring 211 in FIG. (Fig. 4 (D))
[0137]
With such a structure, the wiring resistance of the gate wiring can be extremely reduced, so that an image display region (pixel portion) having a large area can be formed. That is, the pixel structure of this embodiment is extremely effective in realizing an EL display device having a screen size of 10 inches or more (or 30 inches or more) diagonally.
[0138]
Next, as shown in FIG. 5A, a first interlayer insulating film 336 is formed. As the first interlayer insulating film 336, an insulating film containing silicon may be used as a single layer, or a laminated film combined therewith may be used. The film thickness may be 400 nm to 1.5 μm. In this embodiment, a structure is formed in which a silicon oxide film having a thickness of 800 nm is stacked on a silicon nitride oxide film having a thickness of 200 nm.
[0139]
Further, a hydrogenation treatment is performed by performing a heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. This step is a step in which the dangling bonds of the semiconductor film are terminated with hydrogen by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0140]
Note that the hydrogenation treatment may be performed while the first interlayer insulating film 336 is formed. That is, after the 200 nm-thick silicon nitride oxide film is formed, the hydrogenation treatment may be performed as described above, and then the remaining 800 nm-thick silicon oxide film may be formed.
[0141]
Next, contact holes are formed in the first interlayer insulating film 336, and source wirings 337 to 340 and drain wirings 341 to 343 are formed. In this embodiment, the electrode is a laminated film having a three-layer structure in which a titanium film is 100 nm, an aluminum film containing titanium is 300 nm, and a titanium film 150 nm is continuously formed by sputtering. Of course, other conductive films may be used, and an alloy film containing silver, palladium, and copper may be used.
[0142]
Next, a first passivation film 344 is formed with a thickness of 50 to 500 nm (typically 200 to 300 nm). In this embodiment, a silicon nitride oxide film having a thickness of 300 nm is used as the first passivation film 344. This may be replaced by a silicon nitride film. Of course, it is possible to use the same material as the first passivation film 41 of FIG.
[0143]
Prior to the formation of the silicon nitride oxide film, H ₂ , NH _Three It is effective to perform plasma treatment using a gas containing isohydrogen. Hydrogen excited by this pretreatment is supplied to the first interlayer insulating film 336 and heat treatment is performed, whereby the film quality of the first passivation film 344 is improved. At the same time, since hydrogen added to the first interlayer insulating film 336 diffuses to the lower layer side, the active layer can be effectively hydrogenated.
[0144]
Next, a second interlayer insulating film 347 made of an organic resin is formed. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, since the second interlayer insulating film 347 has a strong meaning of flattening, acrylic having excellent flatness is preferable. In this embodiment, the acrylic film is formed with a film thickness that can sufficiently flatten the step formed by the TFT. The thickness is preferably 1 to 5 μm (more preferably 2 to 4 μm).
[0145]
Next, a second passivation film 348 having a thickness of 100 nm is formed on the second interlayer insulating film 347. In this embodiment, since an insulating film containing Si, Al, N, O, and La is used, diffusion of alkali metal from the EL layer provided thereon can be prevented. At the same time, moisture can be prevented from entering the EL layer and heat generated in the EL layer can be dispersed to suppress deterioration of the EL layer and planarization film (second interlayer insulating film) due to heat. .
[0146]
Then, a contact hole reaching the drain wiring 343 is formed in the second passivation film 348, the second interlayer insulating film 347, and the first passivation film 344, and a pixel electrode 349 is formed. In this embodiment, a compound electrode (ITO) film of indium oxide and tin oxide is formed to a thickness of 110 nm and patterned to form a pixel electrode. This pixel electrode 349 becomes the anode of the EL element. Note that as another material, a compound film of indium oxide and zinc oxide or a zinc oxide film containing gallium oxide can be used.
[0147]
In this embodiment, the pixel electrode 349 is electrically connected to the drain region 331 of the current control TFT via the drain wiring 343. This structure has the following advantages.
[0148]
Since the pixel electrode 349 is in direct contact with an organic material such as an EL layer (light emitting layer) or a charge transport layer, mobile ions contained in the EL layer or the like may diffuse in the pixel electrode. That is, in the structure of this embodiment, the pixel electrode 349 is not directly connected to the drain region 331 which is a part of the active layer, and the penetration of the mobile ions into the active layer can be prevented by relaying the drain wiring 343. .
[0149]
Next, as shown in FIG. 5C, an EL layer 350 is formed by an inkjet method, and further, a cathode (MgAg electrode) 351 and a protective electrode 352 are formed without being released to the atmosphere. At this time, it is preferable that the pixel electrode 349 is subjected to a heat treatment before the EL layer 350 and the cathode 351 are formed to completely remove moisture. In this embodiment, an MgAg electrode is used as the cathode of the EL element, but other known materials may be used.
[0150]
Note that the material described in the section of the present invention can be used for the EL layer 350. In this embodiment, as shown in FIG. 21, four layers comprising a hole injecting layer, a hole transporting layer, a light emitting layer, and an electron transporting layer. Although the structure is an EL layer, an electron transport layer may not be provided, or an electron injection layer may be provided. Further, the hole injection layer may be omitted. As described above, various examples of combinations have already been reported, and any of the configurations may be used.
[0151]
As the hole injection layer or the hole transport layer, an amine-based TPD (triphenylamine derivative) may be used. Besides, hydrazone (typically DEH), stilbene (typically STB), star A bust system (typically m-MTDATA) or the like can be used. In particular, a star bust material having a high glass transition temperature and being difficult to crystallize is preferable. Further, polyaniline (PAni), polythiophene (PEDOT) or copper phthalocyanine (CuPc) may be used.
[0152]
In addition, as the light emitting layer used in this example, cyanopolyphenylene vinylene is used for the light emitting layer emitting red, polyphenylene vinylene is used for the light emitting layer emitting green, and polyphenylene vinylene or polyalkylphenylene is used for the light emitting layer emitting blue light. Use it. The film thickness may be 30 to 150 nm (preferably 40 to 100 nm). In this embodiment, toluene is used as a solvent.
[0153]
In addition, the protective electrode 352 can protect the EL layer 350 from moisture and oxygen; however, a third passivation film 353 is more preferably provided. In this embodiment, a silicon nitride film having a thickness of 300 nm is provided as the third passivation film 353. This third passivation film may also be continuously formed after the protective electrode 352 without being released to the atmosphere. Of course, the same material as the third passivation film 50 of FIG. 1 can be used for the third passivation film 353.
[0154]
The protective electrode 352 is provided in order to prevent the MgAg electrode 351 from being deteriorated, and a metal film mainly composed of aluminum is typical. Of course, other materials may be used. Further, since the EL layer 350 and the MgAg electrode 351 are very sensitive to moisture, it is desirable that the protective electrode 352 be continuously formed without being released to the atmosphere to protect the EL layer from the outside air.
[0155]
Note that the thickness of the EL layer 350 may be 10 to 400 nm (typically 60 to 160 nm), and the thickness of the MgAg electrode 351 may be 180 to 300 nm (typically 200 to 250 nm). In the case where the EL layer 350 has a stacked structure, the thickness of each layer may be in the range of 10 to 100 nm.
[0156]
Thus, an active matrix EL display device having a structure as shown in FIG. 5C is completed. By the way, the active matrix EL display device of this embodiment can provide extremely high reliability and improve the operating characteristics by arranging TFTs having an optimal structure not only in the pixel portion but also in the drive circuit portion.
[0157]
First, a TFT having a structure that reduces hot carrier injection so as not to reduce the operating speed as much as possible is used as an n-channel TFT 205 of a CMOS circuit that forms a driving circuit. Note that the drive circuit here includes a shift register, a buffer, a level shifter, a sampling circuit (transfer gate), and the like. In the case of performing digital driving, a signal conversion circuit such as a D / A converter may be included.
[0158]
In this embodiment, as shown in FIG. 5C, the active layer of the n-channel type 205 includes a source region 355, a drain region 356, an LDD region 357, and a channel formation region 358, and the LDD region 357 has gate insulation. It overlaps with the gate electrode 313 with the film 311 interposed therebetween.
[0159]
The reason why the LDD region is formed only on the drain region side is to prevent the operation speed from being lowered. In addition, the n-channel TFT 205 does not need to care about the off-current value, and it is better to focus on the operation speed than that. Therefore, it is desirable that the LDD region 357 is completely overlapped with the gate electrode and the resistance component is reduced as much as possible. That is, it is better to eliminate the so-called offset.
[0160]
In addition, since the p-channel TFT 206 of the CMOS circuit is hardly concerned about deterioration due to hot carrier injection, it is not particularly necessary to provide an LDD region. Needless to say, it is possible to provide an LDD region as in the case of the n-channel TFT 205 and take measures against hot carriers.
[0161]
Note that the sampling circuit in the driver circuit is a little special compared to other circuits, and a large current flows in both directions in the channel formation region. That is, the roles of the source region and the drain region are interchanged. Furthermore, it is necessary to keep the off-current value as low as possible, and in that sense, it is desirable to dispose a TFT having an intermediate function between the switching TFT and the current control TFT.
[0162]
Therefore, it is desirable to arrange a TFT having a structure as shown in FIG. 9 as the n-channel TFT forming the sampling circuit. As shown in FIG. 9, part of the LDD regions 901a and 901b overlap with the gate electrode 903 with the gate insulating film 902 interposed therebetween. This effect is as described in the description of the current control TFT 202. In the case of the sampling circuit, the difference is that the LDD regions 901a and 901b are provided so as to sandwich the channel formation region 904.
[0163]
In addition, a pixel portion is formed by forming a pixel having a structure as shown in FIG. Since the structure of the switching TFT and the current control TFT formed in the pixel has already been described with reference to FIG. 1, the description thereof is omitted here.
[0164]
Actually, when completed up to FIG. 5C, packaging with a housing material such as a highly airtight protective film (laminate film, UV curable resin film, etc.) or a ceramic sealing can so as not to be exposed to the outside air ( (Encapsulation) is preferable. At that time, the reliability (life) of the EL layer is improved by making the inside of the housing material an inert atmosphere or arranging a hygroscopic agent (for example, barium oxide) or an antioxidant inside.
[0165]
In addition, when the airtightness is improved by processing such as packaging, a connector (flexible printed circuit: FPC) for connecting the terminal routed from the element or circuit formed on the substrate and the external signal terminal is attached. Completed as a product. In this specification, an EL display device that can be shipped is referred to as an EL module.
[0166]
Here, the configuration of the active matrix EL display device of this embodiment will be described with reference to the perspective view of FIG. The active matrix EL display device of this embodiment includes a pixel portion 602, a gate side driver circuit 603, and a source side driver circuit 604 formed on a glass substrate 601. The switching TFT 605 in the pixel portion is an n-channel TFT and is arranged at an intersection of a gate wiring 606 connected to the gate side driving circuit 603 and a source wiring 607 connected to the source side driving circuit 604. The drain of the switching TFT 605 is connected to the gate of the current control TFT 608.
[0167]
Further, the source of the current control TFT 608 is connected to the current supply line 609, and the EL element 610 is electrically connected to the drain of the current control TFT 608. At this time, if the current control TFT 608 is an n-channel TFT, the drain of the EL element 610 is preferably connected to the drain thereof. If the current control TFT 608 is a p-channel TFT, the anode of the EL element 610 is preferably connected to the drain thereof.
[0168]
The FPC 611 serving as an external input terminal is provided with input wirings (connection wirings) 612 and 613 for transmitting signals to the driving circuit, and an input wiring 614 connected to the current supply line 609.
[0169]
FIG. 7 shows an example of a circuit configuration of the EL display device shown in FIG. The EL display device of this embodiment includes a source side driver circuit 701, a gate side driver circuit (A) 707, a gate side driver circuit (B) 711, and a pixel portion 706. Note that in this specification, the drive circuit is a generic name including a source side processing circuit and a gate side drive circuit.
[0170]
The source side driver circuit 701 includes a shift register 702, a level shifter 703, a buffer 704, and a sampling circuit (transfer gate) 705. The gate side driver circuit (A) 707 includes a shift register 708, a level shifter 709, and a buffer 710. The gate side driver circuit (B) 711 has a similar structure.
[0171]
Here, the driving voltages of the shift registers 702 and 708 are 5 to 16 V (typically 10 V), and the n-channel TFT used in the CMOS circuit forming the circuit has a structure indicated by 205 in FIG. Is suitable.
[0172]
The level shifters 703 and 709 and the buffers 704 and 710 have a driving voltage as high as 14 to 16 V, but a CMOS circuit including the n-channel TFT 205 in FIG. 5C is suitable as in the shift register. In addition, it is effective in improving the reliability of each circuit that the gate wiring has a multi-gate structure such as a double gate structure or a triple gate structure.
[0173]
The sampling circuit 705 has a driving voltage of 14 to 16 V. However, since the source region and the drain region are inverted and the off current value needs to be reduced, a CMOS circuit including the n-channel TFT 208 in FIG. 9 is suitable. ing.
[0174]
Further, the pixel portion 706 has a driving voltage of 14 to 16 V, and the pixel having the structure shown in FIG.
[0175]
In addition, the said structure can be easily implement | achieved by manufacturing TFT according to the manufacturing process shown to FIGS. In addition, in this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of this embodiment, other driving such as a signal division circuit, a D / A converter circuit, an operational amplifier circuit, and a γ correction circuit It is considered that logic circuits other than circuits can be formed on the same substrate, and further, a memory portion, a microprocessor, and the like can be formed.
[0176]
Further, the EL module of this embodiment including the housing material will be described with reference to FIGS. Note that the reference numerals used in FIGS. 6 and 7 are cited as necessary.
[0177]
A pixel portion 1701, a source side driver circuit 1702, and a gate side driver circuit 1703 are formed over a substrate (including a base film under the TFT) 1700. Various wirings from the respective driving circuits reach the FPC 611 through the input wirings 612 to 614 and are connected to an external device.
[0178]
At this time, a housing material 1704 is provided so as to surround at least the pixel portion, preferably the driver circuit and the pixel portion. Note that the housing material 1704 has a recess or a sheet shape whose inner dimension is larger than the outer dimension of the EL element, and is fixed to the substrate 1700 by an adhesive 1705 so as to form a sealed space in cooperation with the substrate 1700. Is done. At this time, the EL element is completely enclosed in the sealed space and is completely shielded from the outside air. Note that a plurality of housing materials 1704 may be provided.
[0179]
The material of the housing material 1704 is preferably an insulating material such as glass or polymer. For example, amorphous glass (borosilicate glass, quartz, etc.), crystallized glass, ceramic glass, organic resin (acrylic resin, styrene resin, polycarbonate resin, epoxy resin, etc.), silicone resin Can be mentioned. Ceramics may also be used. Further, if the adhesive 1705 is an insulating substance, a metal material such as a stainless alloy can be used.
[0180]
The material of the adhesive 1705 can be an adhesive such as an epoxy resin or an acrylate resin. Furthermore, a thermosetting resin or a photocurable resin can also be used as an adhesive. However, it is necessary that the material does not transmit oxygen and moisture as much as possible.
[0181]
Further, it is desirable that the gap 1706 between the housing material and the substrate 1700 be filled with an inert gas (such as argon, helium, or nitrogen). In addition to gases, inert liquids (typically perfluoroalkanes) Liquid It is also possible to use fluorinated carbon. As for the inert liquid, a material as used in JP-A-8-78159 may be used. Moreover, you may fill with resin.
[0182]
It is also effective to provide a desiccant in the gap 1706. As the desiccant, materials described in JP-A-9-148066 can be used. Typically, barium oxide may be used. It is also effective to provide an antioxidant in addition to the desiccant.
[0183]
As shown in FIG. 17B, a plurality of pixels each having an isolated EL element are provided in the pixel portion, and all of them have a protective electrode 1707 as a common electrode. In this embodiment, the EL layer, the cathode (MgAg electrode), and the protective electrode are preferably formed continuously without being released to the atmosphere, but the EL layer and the cathode are formed using the same mask material, and the protective electrode If only another mask material is used, the structure shown in FIG. 17B can be realized.
[0184]
At this time, the EL layer and the cathode need only be provided in the pixel portion, and need not be provided over the driver circuit. Of course, there is no problem even if it is provided on the driver circuit, but it is preferable not to provide it in consideration of the fact that the EL layer contains an alkali metal.
[0185]
Note that the protective electrode 1707 is connected to the input wiring 1709 in a region indicated by 1708. The input wiring 1709 is a wiring for applying a predetermined voltage to the protective electrode 1707 and is connected to the FPC 611 through a conductive paste material (anisotropic conductive film) 1710.
[0186]
Here, a manufacturing process for realizing a contact structure in the region 1708 will be described with reference to FIGS.
[0187]
First, the state shown in FIG. 5A is obtained according to the steps of this embodiment. At this time, the first interlayer insulating film 336 and the gate insulating film 311 are removed from the end portion of the substrate (a region indicated by 1708 in FIG. 17B), and an input wiring 1709 is formed thereon. Of course, it is formed simultaneously with the source wiring and drain wiring of FIG. (FIG. 18 (A))
[0188]
Next, in FIG. 5B, when etching the second passivation film 348, the second interlayer insulating film 347, and the first passivation film 344, a region indicated by 1801 is removed and an opening 1802 is formed. . (Fig. 18B)
[0189]
In this state, an EL element formation process (pixel electrode, EL layer and cathode formation process) is performed in the pixel portion. At this time, in the region shown in FIG. 18, a mask material is used to prevent the EL element from being formed. Then, after forming the cathode 351, the protective electrode 352 is formed using another mask material. As a result, the protective electrode 352 and the input wiring 1709 are electrically connected. Further, a third passivation film 353 is provided to obtain the state of FIG.
[0190]
Through the above steps, a contact structure in a region indicated by 1708 in FIG. The input wiring 1709 is filled with a gap between the housing material 1704 and the substrate 1700 (however, it is filled with an adhesive 1705. That is, the adhesive 1705 needs to have a thickness that can sufficiently flatten the steps of the input wiring. .) Is connected to the FPC 611. Although the input wiring 1709 has been described here, the other output wirings 612 to 614 are similarly connected to the FPC 611 under the housing material 1704.
[0191]
[Example 2]
In this embodiment, an example in which the pixel configuration is different from the configuration shown in FIG. 2B is shown in FIG.
[0192]
In this embodiment, the two pixels shown in FIG. 2B are arranged so as to be symmetric with respect to the current supply line. That is, as shown in FIG. 10, by sharing the current supply line 213 between two adjacent pixels, the number of necessary wirings can be reduced. Note that the TFT structure and the like disposed in the pixel can be left as they are.
[0193]
With such a configuration, a higher-definition pixel portion can be manufactured, and the image quality is improved.
[0194]
Note that the structure of this embodiment can be easily realized in accordance with the manufacturing process of Embodiment 1, and the description of Embodiment 1 and FIG.
[0195]
Example 3
In this embodiment, the case where a pixel portion having a structure different from that in FIG. 1 is formed will be described with reference to FIGS. The first embodiment may be followed up to the step of forming the second interlayer insulating film 44. The switching TFT 201 and the current control TFT 202 covered with the second interlayer insulating film 44 have the same structure as that shown in FIG.
[0196]
In the case of this embodiment, when contact holes are formed in the second passivation film 45, the second interlayer insulating film 44, and the first passivation film 41, the pixel electrode 51 and the banks 103a and 103b are formed, and then the cathode 52 and the EL. Layer 53 is formed. In this embodiment, after the cathode 52 is formed by a vacuum deposition method, the EL layer 53 is formed by an ink jet method while maintaining a dry inert atmosphere without being released to the atmosphere. At this time, the red light emitting EL layer, the green light emitting EL layer, and the blue light emitting EL layer are selectively formed in separate pixels by the banks 103a and 103b. Although only one pixel is shown in FIG. 11, pixels having the same structure are formed corresponding to the respective colors of red, green, and blue, whereby color display can be performed. A known material may be used for the EL layers of these colors.
[0197]
In this embodiment, an aluminum alloy film (aluminum film containing 1 wt% titanium) having a thickness of 150 nm is provided as the pixel electrode 51. The material for the pixel electrode may be any material as long as it is a metal material, but is preferably a material having high reflectivity. Further, a 230 nm-thick MgAg electrode is used as the cathode 52, and the EL layer 53 has a thickness of 90 nm (from the bottom, the electron transport layer 20 nm, the light emitting layer 40 nm, and the hole transport layer 30 nm).
[0198]
Next, an anode 54 made of a transparent conductive film (ITO film in this embodiment) is formed to a thickness of 110 nm. Thus, the EL element 209 is formed, and the pixel having the structure shown in FIG. 11 is completed by forming the third passivation film 55 with the material shown in the first embodiment.
[0199]
In the case of the structure of this embodiment, red, green, or blue light generated in each pixel is emitted to the opposite side of the substrate on which the TFT is formed. Therefore, almost the entire region in the pixel, that is, the region where the TFT is formed can be used as an effective light emitting region. As a result, the effective light emission area of the pixel is greatly improved, and the brightness and contrast ratio (brightness / darkness ratio) of the image are improved.
[0200]
The configuration of this embodiment can be freely combined with any of the configurations of Embodiments 1 and 2.
[0201]
Example 4
In this embodiment, a case where a pixel having a structure different from that in FIG. 2 of Embodiment 1 is formed will be described with reference to FIGS.
[0202]
In FIG. 12A, reference numeral 1201 denotes a switching TFT, which includes an active layer 56, a gate electrode 57a, a gate wiring 57b, a source wiring 58, and a drain wiring 59 as a configuration. Reference numeral 1202 denotes a current control TFT, which includes an active layer 60, a gate electrode 61, a source wiring 62, and a drain wiring 63 as a configuration. The source wiring 62 of the current control TFT 1202 is connected to the current supply line 64, and the drain wiring 63 is connected to the EL element 65. FIG. 12B shows the circuit configuration of this pixel.
[0203]
The difference between FIG. 12A and FIG. 2A is the structure of the switching TFT. In this embodiment, a thin gate electrode 57a having a line width of 0.1 to 5 μm is formed, and an active layer 56 is formed so as to cross that portion. Then, a gate wiring 57b is formed so as to electrically connect the gate electrode 57a of each pixel. This realizes a triple gate structure without occupying much area.
[0204]
The other portions are the same as in FIG. 2A, but with the structure as in this embodiment, the area occupied by the switching TFT is reduced, so the effective light emission area is increased, that is, the brightness of the image is improved. . In addition, since the gate structure with increased redundancy for reducing the off-current value can be realized, the image quality can be further improved.
[0205]
Note that the configuration of this embodiment may be configured such that the current supply line 64 is shared between adjacent pixels as in the second embodiment, or may be configured as in the third embodiment. In addition, the manufacturing process may be according to Example 1.
[0206]
Example 5
In the first to fourth embodiments, the case of a top gate TFT has been described. However, the present invention may be implemented using a bottom gate TFT. In this embodiment, FIG. 13 shows the case where the present invention is implemented using an inverted staggered TFT. Since the structure other than the TFT structure is the same as that in FIG. 1, the same reference numerals as those in FIG. 1 are used as necessary.
[0207]
In FIG. 13, the same material as in the first embodiment can be used for the substrate 11 and the base film 12. A switching TFT 1301 and a current control TFT 1302 are formed on the base film 12.
[0208]
The configuration of the switching TFT 1301 includes gate electrodes 70a and 70b, a gate wiring 71, a gate insulating film 72, a source region 73, a drain region 74, LDD regions 75a to 75d, a high concentration impurity region 76, channel forming regions 77a and 77b, a channel. Protective films 78a and 78b, a first interlayer insulating film 79, a source wiring 80 and a drain wiring 81 are included.
[0209]
The current control TFT 1302 includes a gate electrode 82, a gate insulating film 72, a source region 83, a drain region 84, an LDD region 85, a channel forming region 86, a channel protective film 87, a first interlayer insulating film 79, and a source wiring. 88 and drain wiring 89. At this time, the gate electrode 82 is electrically connected to the drain wiring 84 of the switching TFT 1301.
[0210]
Note that the switching TFT 1301 and the current control TFT 1302 may be formed by a known method for manufacturing an inverted staggered TFT. In addition, as the material of each portion (wiring, insulating film, active layer, etc.) for forming the TFT, the same material as each corresponding portion in the top gate type TFT of Embodiment 1 can be used. However, the channel protective films 78a, 78b, and 87 that are not included in the top gate TFT may be formed of an insulating film containing silicon. In addition, the impurity regions such as the source region, the drain region, and the LDD region may be formed by individually changing the impurity concentration using a photolithography technique.
[0211]
When the TFT is completed, the first passivation film 41, the second interlayer insulating film (planarization film) 44, the second passivation film 45, the pixel electrode (anode) 46, the banks 101a and 101b, the EL layer 47, and the MgAg electrode (cathode) 48, an aluminum electrode (protective electrode) 49, and a third passivation film 50 are sequentially formed to complete a pixel having the EL element 1303. Example 1 may be referred to for these manufacturing steps and materials.
[0212]
In addition, the structure of a present Example can be freely combined with any structure of Examples 2-4.
[0213]
Example 6
In the structure shown in FIG. 5C or FIG. 1 of the first embodiment, it is effective to use a material having a high heat dissipation effect as the second passivation film 45 as the base film provided between the active layer and the substrate. . In particular, the current control TFT easily generates heat because a large amount of current flows, and deterioration due to self-heating can be a problem. In such a case, the thermal degradation of the TFT can be prevented because the base film has a heat dissipation effect as in this embodiment.
[0214]
Of course, since the effect of preventing from mobile ions diffusing from the substrate is also important, similarly to the first passivation film 41, a stacked structure of a compound containing Si, Al, N, O, and M and an insulating film containing silicon is used. It is also preferable.
[0215]
In addition, the structure of a present Example can be freely combined with any structure of Examples 1-5.
[0216]
Example 7
In the case of the pixel structure shown in Embodiment 3, since light emitted from the EL layer is emitted to the opposite side of the substrate, it is necessary to consider the transmittance of an insulating film or the like existing between the substrate and the pixel electrode. There is no. That is, even a material having a somewhat low transmittance can be used.
[0217]
Therefore, it is advantageous to use a carbon film called a diamond thin film, a diamond-like carbon film, or an amorphous carbon film as the base film 12, the first passivation film 41, or the second passivation film 45. That is, since it is not necessary to worry about a decrease in transmittance, the film thickness can be set as thick as 100 to 500 nm, and the heat dissipation effect can be further enhanced.
[0218]
Note that when the carbon film is used for the third passivation film 50, the decrease in transmittance should be avoided, so the film thickness is preferably about 5 to 100 nm.
[0219]
In this embodiment, even when a carbon film is used for any of the base film 12, the first passivation film 41, the second passivation film 45, and the third passivation film 50, it can be used by being laminated with another insulating film. It is valid.
[0220]
Note that this embodiment is effective when the pixel structure shown in Embodiment 3 is used, and other configurations can be freely combined with any of the configurations of Embodiments 1 to 6.
[0221]
Example 8
In the present invention, the switching TFT has a multi-gate structure in the pixel of the EL display device, thereby reducing the off-current value of the switching TFT and eliminating the need for a storage capacitor. This is a device for effectively utilizing the area occupied by the storage capacitor as a light emitting region.
[0222]
However, even if the storage capacity cannot be completely eliminated, the effect of widening the effective light emitting area can be obtained only by reducing the exclusive area. That is, it is sufficient to reduce the off-current value and reduce the area occupied by the storage capacitor by making the switching TFT have a multi-gate structure.
[0223]
Therefore, a pixel structure as shown in FIG. 14 is also possible. In FIG. 14, the same reference numerals as those in FIG.
[0224]
The difference between FIG. 14 and FIG. 1 is that there is a storage capacitor 1401 connected to the switching TFT. The storage capacitor 1401 is formed of a semiconductor region (lower electrode) 1402 extended from the drain region 14 of the switching TFT 201, a gate insulating film 18, and a capacitor electrode (upper electrode) 1403. The capacitor electrode 1403 is formed simultaneously with the gate electrodes 19a, 19b, and 35 of the TFT.
[0225]
This top view is shown in FIG. A cross-sectional view taken along line AA ′ in FIG. 15A corresponds to FIG. As shown in FIG. 15A, the capacitor electrode 1403 is electrically connected to the source region 31 of the current control TFT through an electrically connected connection wiring 1404. Note that the connection wiring 1404 is formed simultaneously with the source wirings 21 and 36 and the drain wirings 22 and 37. FIG. 15B illustrates a circuit configuration of the top view illustrated in FIG.
[0226]
In addition, the structure of a present Example can be freely combined with any structure of Examples 1-7. That is, only a storage capacitor is provided in the pixel, and the TFT structure and the material of the EL layer are not limited.
[0227]
Example 9
In the first embodiment, laser crystallization is used as a means for forming the crystalline silicon film 302. In this embodiment, a case where a different crystallization means is used will be described.
[0228]
In this embodiment, after an amorphous silicon film is formed, crystallization is performed using the technique described in Japanese Patent Laid-Open No. 7-130652. The technique described in this publication is a technique for obtaining a crystalline silicon film having high crystallinity by using an element such as nickel as a catalyst for promoting (promoting) crystallization.
[0229]
Further, after the crystallization step is completed, a step of removing the catalyst used for crystallization may be performed. In that case, the catalyst may be gettered by the technique described in JP-A-10-270363 or JP-A-8-330602.
[0230]
Further, a TFT may be formed using the technique described in the application specification of Japanese Patent Application No. 11-076967 by the present applicant.
[0231]
As described above, the manufacturing process shown in Embodiment 1 is an example, and other manufacturing processes can be used as long as the structure of FIG. 1 or FIG. 5C of Embodiment 1 can be realized. No problem.
[0232]
In addition, the structure of a present Example can be freely combined with any structure of Examples 1-8.
[0233]
Example 10
In driving the EL display device of the present invention, analog driving using an analog signal as an image signal can be performed, or digital driving using a digital signal can be performed.
[0234]
When analog driving is performed, an analog signal is sent to the source wiring of the switching TFT, and the analog signal including the gradation information becomes the gate voltage of the current control TFT. Then, the current control TFT controls the current flowing in the EL element, and the light emission intensity of the EL element is controlled to perform gradation display. In this case, it is desirable to operate the current control TFT in a saturation region. That is, it is desirable to operate within the condition of | Vds |> | Vgs−Vth |. Here, Vds is a voltage between the source region and the drain region, Vgs is a voltage between the source region and the gate electrode, and Vth is a threshold voltage of the TFT.
[0235]
On the other hand, when digital driving is performed, unlike analog gray scale display, gray scale display called time-division driving (time gray scale driving) or area gray scale driving is performed. That is, the color gradation is visually changed by adjusting the length of the light emission time and the light emission area ratio. In this case, it is desirable to operate the current control TFT in a linear region. That is, it is desirable to operate within the condition of | Vds | <| Vgs−Vth |.
[0236]
Since an EL element has a very high response speed compared to a liquid crystal element, it can be driven at a high speed. Therefore, it can be said that the element is suitable for time-division driving in which gradation display is performed by dividing one frame into a plurality of subframes. Further, since one frame period is short, the time for holding the gate voltage of the current control TFT can be shortened, which is advantageous in reducing or omitting the holding capacitor.
[0237]
As described above, since the present invention is a technique related to an element structure, any driving method may be used.
[0238]
Example 11
In this embodiment, an example of a pixel structure of an EL display device according to the present invention is shown in FIGS. In this embodiment, 4701 is the source wiring of the switching TFT 4702, 4703 is the gate wiring of the switching TFT 4702, 4704 is the current control TFT, 4705 is the current supply line, 4706 is the power control TFT, and 4707 is the power control. Gate wirings 4708 are EL elements. Refer to Japanese Patent Application No. 11-341272 for the operation of the power supply control TFT 4706.
[0239]
In this embodiment, the power control TFT 4706 is provided between the current control TFT 4704 and the EL element 4708. However, the current control TFT 4704 is provided between the power control TFT 4706 and the EL element 4708. Also good. The power supply control TFT 4706 preferably has the same structure as the current control TFT 4704 or is formed in series with the same active layer.
[0240]
FIG. 23A shows an example in which the current supply line 4705 is shared between two pixels. That is, there is a feature in that the two pixels are formed so as to be symmetrical with respect to the current supply line 4705. In this case, since the number of current supply lines can be reduced, the pixel portion can be further refined.
[0241]
FIG. 23B shows an example in which a current supply line 4710 is provided in parallel with the gate wiring 4703 and a power supply control gate wiring 4711 is provided in parallel with the source wiring 4701. In FIG. 23B, the current supply line 4710 and the gate wiring 4703 are provided so as not to overlap with each other. However, if the wirings are formed in different layers, they overlap with each other with an insulating film interposed therebetween. It can also be provided. In this case, the current supply line 4710 and the gate wiring 4703 can share an exclusive area, so that the pixel portion can be further refined.
[0242]
Example 12
In this embodiment, examples of a pixel structure of an EL display device according to the present invention are shown in FIGS. In this embodiment, 4801 is the source wiring of the switching TFT 4802, 4803 is the gate wiring of the switching TFT 4802, 4804 is the current control TFT, 4805 is the current supply line, 4806 is the erasing TFT, and 4807 is the erasing gate wiring. Reference numeral 4808 denotes an EL element. Refer to Japanese Patent Application No. 11-338786 for the operation of the erasing TFT 4806.
[0243]
The drain of the erasing TFT 4806 is connected to the gate of the current control TFT 4804 so that the gate voltage of the current control TFT 4804 can be forcibly changed. Note that the erasing TFT 4806 may be either an n-channel TFT or a p-channel TFT, but preferably has the same structure as the switching TFT 4802 so that off-state current can be reduced.
[0244]
FIG. 24A shows an example in which the current supply line 4805 is shared between two pixels. In other words, the two pixels are formed so as to be symmetrical about the current supply line 4805. In this case, since the number of current supply lines can be reduced, the pixel portion can be further refined.
[0245]
FIG. 24B shows an example in which a current supply line 4810 is provided in parallel with the gate wiring 4803 and an erasing gate wiring 4811 is provided in parallel with the source wiring 4801. Note that in FIG. 24B, the current supply line 4810 and the gate wiring 4803 are provided so as not to overlap with each other. However, if the wirings are formed in different layers, they overlap with each other with an insulating film interposed therebetween. It can also be provided. In this case, the current supply line 4810 and the gate wiring 4803 can share an exclusive area, so that the pixel portion can be further refined.
[0246]
Example 13
The EL display device of the present invention may have a structure in which any number of TFTs are provided in a pixel. In Examples 11 and 12, an example in which three TFTs are provided is shown, but four to six TFTs may be provided. The present invention can be practiced without being limited to the pixel structure of an EL display device.
[0247]
Example 14
In this embodiment, an example in which a p-channel TFT is used as the current control TFT 202 in FIG. 1 will be described. Since other parts are the same as those in FIG. 1, detailed description thereof is omitted.
[0248]
FIG. 25 shows a cross-sectional structure of the pixel of this example. For the manufacturing method of the p-channel TFT used in this embodiment, Embodiment 1 may be referred to. The active layer of the p-channel TFT includes a source region 2801, a drain region 2802, and a channel formation region 2803. The source region 2801 is connected to the source wiring 36, and the drain region 2802 is connected to the drain wiring 37.
[0249]
Thus, when the anode of the EL element is connected to the current control TFT, it is preferable to use a p-channel TFT as the current control TFT.
[0250]
In addition, the structure of a present Example can be implemented in combination with any structure of Examples 1-13 freely.
[0251]
Example 15
In the present invention, by using an EL material that can use phosphorescence from triplet excitons for light emission, the external light emission quantum efficiency can be dramatically improved. This makes it possible to reduce the power consumption, extend the life, and reduce the weight of the EL element.
Here, a report of using triplet excitons to improve the external emission quantum efficiency is shown. (T. Tsutsui, C. Adachi, S. Saito, Photochemical Processes in Organized Molecular Systems, ed. K. Honda, (Elsevier Sci. Pub., Tokyo, 1991) p. 437.) EL materials reported in the above paper The molecular formula of (coumarin dye) is shown below.
[0252]
Embedded image

[0253]
(MABaldo, DFO'Brien, Y.You, A.Shoustikov, S.Sibley, METhompson, SRForrest, Nature 395 (1998) p.151.)
The molecular formula of the EL material (Pt complex) reported in the above paper is shown below.
[0254]
Embedded image

[0255]
(MABaldo, S. Lamansky, PEBurrrows, METhompson, SRForrest, Appl.Phys.Lett., 75 (1999) p.4.)
(T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamura, T.Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguchi, Jpn.Appl.Phys., 38 (12B (1999) L1502.) The molecular formula of the EL material (Ir complex) reported in the above paper is shown below.
[0256]
Embedded image

[0257]
As described above, if phosphorescence emission from triplet excitons can be used, in principle, it is possible to realize an external emission quantum efficiency that is 3 to 4 times higher than that in the case of using fluorescence emission from singlet excitons. In addition, the structure of a present Example can be implemented in combination freely with any structure of Examples 1-13.
[0258]
Example 16
In Example 1, it was preferable to use an organic EL material as the EL layer, but the present invention can also be implemented using an inorganic EL material. However, since the current inorganic EL material has a very high driving voltage, a TFT having a withstand voltage characteristic that can withstand such a driving voltage must be used when performing analog driving.
[0259]
Alternatively, if an inorganic EL material with a lower driving voltage is developed in the future, it can be applied to the present invention.
[0260]
Moreover, the structure of a present Example can be freely combined with any structure of Examples 1-14.
[0261]
Example 17
An active matrix EL display device (EL module) formed by implementing the present invention is a self-luminous type, and thus has better visibility in a bright place than a liquid crystal display device. Therefore, the application is wide as a direct-view type EL display (referring to a display display incorporating an EL module).
[0262]
One of the advantages of the EL display over the liquid crystal display is the wide viewing angle. Therefore, in order to watch TV broadcasts or the like on a large screen, the EL display of the present invention may be used as a display display (display monitor) having a diagonal of 30 inches or more (typically 40 inches or more).
[0263]
Further, it can be used not only as an EL display (a personal computer monitor, a TV broadcast reception monitor, an advertisement display monitor, etc.) but also as a display display of various electronic devices.
[0264]
Such electronic devices include video cameras, digital cameras, goggle-type displays (head-mounted displays), car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), and images equipped with recording media. A playback device (specifically, a device having a display that can play back a recording medium such as a compact disc (CD), a laser disc (LD), or a digital video disc (DVD) and display an image thereof). Examples of these electronic devices are shown in FIG.
[0265]
FIG. 16A illustrates a personal computer, which includes a main body 2001, a housing 2002, a display portion 2003, and a keyboard 2004. The present invention can be used for the display portion 2003.
[0266]
FIG. 16B illustrates a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be used for the display portion 2102.
[0267]
FIG. 16C illustrates a goggle type display including a main body 2201, a display portion 2202, and an arm portion 2203. The present invention can be used for the display portion 2202.
[0268]
FIG. 16D illustrates a portable (mobile) computer, which includes a main body 2301, a camera portion 2302, an image receiving portion 2303, operation switches 2304, and a display portion 2305. The present invention can be used for the display portion 2305.
[0269]
FIG. 16E shows an image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a recording medium (CD, LD, DVD, etc.) 2402, an operation switch 2403, and a display unit (a). 2404 and a display portion (b) 2405. The display unit (a) mainly displays image information, and the display unit (b) mainly displays character information. The present invention can be used for these display units (a) and (b). Note that the present invention can be used for a CD playback device, a game machine, or the like as an image playback device provided with a recording medium.
[0270]
FIG. 16F illustrates an EL display which includes a housing 2501, a support base 2502, and a display portion 2503. The present invention can be used for the display portion 2503. The EL display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly, a diagonal of 30 inches or more).
[0271]
Further, if the emission luminance of the EL material is increased in the future, it can be used for a front type or rear type projector.
[0272]
In addition, the electronic devices often display information distributed through an electronic communication line such as the Internet or CATV (cable television), and in particular, opportunities for displaying moving image information are increasing. Since the response speed of the EL material is very high, it is suitable for displaying such a moving image.
[0273]
In addition, since the EL display device consumes power in the light emitting portion, it is desirable to display information so that the light emitting portion is minimized. Therefore, when an EL display device is used for a display unit mainly including character information such as a portable information terminal, particularly a mobile phone or a car audio, it is driven so that the character information is formed by the light emitting part with the non-light emitting part as the background It is desirable to do.
[0274]
Here, FIG. 22A shows a mobile phone, which includes a main body 2601, an audio output portion 2602, an audio input portion 2603, a display portion 2604, operation switches 2605, and an antenna 2606. The EL display device of the present invention can be used for the display portion 2604. Note that the display portion 2604 can suppress power consumption of the mobile phone by displaying white characters on a black background.
[0275]
FIG. 22B shows in-vehicle audio (car audio), which includes a main body 2701, a display portion 2702, and operation switches 2703 and 2704. The EL display device of the present invention can be used for the display portion 2702. In this embodiment, in-vehicle audio is shown, but it may be used for stationary audio. Note that the display portion 2702 can reduce power consumption by displaying white characters on a black background.
[0276]
As described above, the applicable range of the present invention is extremely wide and can be applied to electronic devices in various fields. Further, the electronic device of the present embodiment can be realized by using a configuration including any combination of Embodiments 1 to 16.
[0277]
【The invention's effect】
By using the present invention, the EL element can be prevented from being deteriorated by moisture or heat. Further, it is possible to prevent the alkali metal from diffusing from the EL layer and adversely affecting the TFT characteristics. As a result, the operation performance and reliability of the EL display device can be greatly improved.
[0278]
In addition, by having such an EL display device as a display display, it is possible to produce an application product (electronic device) having good image quality and durability (high reliability).
[Brief description of the drawings]
FIG. 1 illustrates a cross-sectional structure of a pixel portion of an EL display device.
FIGS. 2A and 2B illustrate a top structure and a structure of a pixel portion of an EL display device. FIGS.
FIGS. 3A and 3B illustrate a manufacturing process of an active matrix EL display device. FIGS.
FIGS. 4A and 4B illustrate a manufacturing process of an active matrix EL display device. FIGS.
FIGS. 5A and 5B illustrate a manufacturing process of an active matrix EL display device. FIGS.
FIG. 6 is a diagram showing the appearance of an EL module.
FIG. 7 illustrates a circuit block configuration of an EL display device.
FIG. 8 is an enlarged view of a pixel portion of an EL display device.
FIG. 9 is a diagram showing an element structure of a sampling circuit of an EL display device.
FIG. 10 illustrates a structure of a pixel portion of an EL display device.
FIG. 11 illustrates a cross-sectional structure of a pixel portion of an EL display device.
FIGS. 12A and 12B illustrate a top structure and a structure of a pixel portion of an EL display device. FIGS.
13 illustrates a cross-sectional structure of a pixel portion of an EL display device. FIG.
FIG 14 illustrates a cross-sectional structure of a pixel portion of an EL display device.
FIGS. 15A and 15B illustrate a top structure and a structure of a pixel portion of an EL display device. FIGS.
FIG. 16 illustrates a specific example of an electronic device.
FIG. 17 is a diagram showing the appearance of an EL module.
FIG. 18 is a view showing a manufacturing process of a contact structure.
FIG. 19 is a diagram for explaining an ink jet method.
FIG. 20 is a diagram showing formation of an EL layer by an inkjet method.
FIG. 21 is a diagram showing a stacked structure of an EL layer.
FIG. 22 illustrates a specific example of an electronic device.
FIG 23 illustrates a circuit configuration of a pixel portion of an EL display device.
FIG 24 illustrates a circuit structure of a pixel portion of an EL display device.
FIG 25 illustrates a cross-sectional structure of a pixel portion of an EL display device.

Claims (23)

A thin film transistor including an active layer, a gate insulating film, a gate electrode, a source wiring, and a drain wiring is formed over a substrate,
Forming a first insulating film containing silicon nitride on the thin film transistor;
Forming a second insulating film containing an organic resin on the first insulating film;
Forming a third insulating film made of the same material as the first insulating film on the second insulating film;
Forming a first electrode electrically connected to the source wiring or the drain wiring on the third insulating film;
Forming an EL layer on the first electrode by an inkjet method;
A method for manufacturing an electro-optical device, wherein a second electrode is formed over the EL layer. A thin film transistor including an active layer, a gate insulating film, a gate electrode, a source wiring, and a drain wiring is formed over a substrate,
Forming a first insulating film including at least one of aluminum oxide, aluminum nitride, and aluminum nitride oxide on the thin film transistor;
Forming a second insulating film containing an organic resin on the first insulating film;
Forming a third insulating film made of the same material as the first insulating film on the second insulating film;
Forming a first electrode electrically connected to the source wiring or the drain wiring on the third insulating film;
Forming an EL layer on the first electrode by an inkjet method;
A method for manufacturing an electro-optical device, wherein a second electrode is formed over the EL layer. A thin film transistor including an active layer, a gate insulating film, a gate electrode, a source wiring, and a drain wiring is formed over a substrate,
On the thin film transistor, a first insulating film including at least one element selected from boron, carbon, and nitrogen and at least one element selected from aluminum, silicon, and phosphorus is formed.
Forming a second insulating film containing an organic resin on the first insulating film;
Forming a third insulating film made of the same material as the first insulating film on the second insulating film;
Forming a first electrode electrically connected to the source wiring or the drain wiring on the third insulating film;
Forming an EL layer on the first electrode by an inkjet method;
A method for manufacturing an electro-optical device, wherein a second electrode is formed over the EL layer. A thin film transistor including an active layer, a gate insulating film, a gate electrode, a source wiring, and a drain wiring is formed over a substrate,
Forming a first insulating film containing silicon nitride on the thin film transistor;
Forming a second insulating film containing an organic resin on the first insulating film;
Forming a third insulating film made of the same material as the first insulating film on the second insulating film;
Forming a contact hole in the first to third insulating films;
Forming a first electrode electrically connected to the source wiring or the drain wiring through the contact hole on the third insulating film;
Forming a bank on the third insulating film;
Forming an EL layer on the first electrode by an inkjet method;
Forming a second electrode on the EL layer;
A method for manufacturing an electro-optical device, wherein a fourth insulating film is formed over the second electrode. Oite to claim 3, wherein the boron, carbon, and at least one element selected from nitrogen, aluminum, silicon, an insulating film containing at least one element selected from phosphorus, silicon carbide or boron phosphide A method for manufacturing an electro-optical device, which includes an insulating film . In claim 1 or 4, wherein the first and third insulating films, a method for manufacturing an electro-optical device which is a silicon nitride oxide film. 5. The method for manufacturing an electro-optical device according to claim 4 , wherein the fourth insulating film includes the same material as the first insulating film. Oite to claim 4 or 7, a method for manufacturing an electro-optical device upper diameter of the contact hole, wherein greater than the lower diameter. In any one of claims 4, 7 and 8, a manufacturing method of an electro-optical device, wherein the bank is a resin film. In any one of claims 1, 2, 3 and 5, a manufacturing method of an electro-optical device, characterized in that said on the second electrode, a protective electrode. In any one of claims 4, 7 to 9, a manufacturing method of an electro-optical device characterized by between said fourth insulating film and the second electrode, a protective electrode. In any one of claims 1, 2, 3 and 5, a manufacturing method of an electro-optical device characterized by providing a housing material on the second electrode. According to claim 4, 7 to 9, 11 to any one of the method for manufacturing an electro-optical device characterized by providing a housing material over the fourth insulating film. According to claim 12 or 13, wherein the housing material, method for manufacturing the electro-optical device comprising a glass, organic resin, silicone resin, to become a ceramic or stainless steel alloy. In any one of claims 12 to 14, the gap between the substrate and the housing material an inert gas, a method for manufacturing an electro-optical device characterized by filling the inert liquid or resin. 16. The method for manufacturing an electro-optical device according to claim 12 , wherein a desiccant is provided in a gap between the substrate and the housing material. 17. The method for manufacturing an electro-optical device according to claim 16 , wherein the desiccant is barium oxide. In any one of claims 12 to 17, a manufacturing method of an electro-optical device characterized by the gap between the substrate and the housing material, is provided an antioxidant. In any one of claims 1 to 18, the formation of the EL layer, a manufacturing method of an electro-optical device is also in a dry nitrogen atmosphere and performing in a dry argon atmosphere. In any one of claims 1 to 19, a manufacturing method of an electro-optical device wherein the EL layer is characterized in that it consists of an organic or inorganic material. In any one of claims 1 to 2 0, the inkjet method is a method for manufacturing an electro-optical device, which comprises using a piezo method or bubble jet system. In any one of claims 1 to 21, wherein the first electrode include indium oxide, zinc oxide, tin oxide, gallium oxide, a manufacturing method of an electro-optical device which comprises at least one of aluminum. In any one of claims 1 to 22, wherein the second electrode, Mg, Li, Cs, Ba , K, Be, a manufacturing method of an electro-optical device characterized in that it comprises at least one of Ca.

Images