JP4092598B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor device including a heterojunction bipolar transistor (HBT) using a compound semiconductor.SetThe present invention relates to an improvement of a manufacturing method.
[0002]
Currently, a compound semiconductor HBT, particularly an HBT having a base layer made of InGaAs, for example, an HBT having an InP emitter layer / InGaAs base layer, or an HBT having an InAlAs emitter layer / InGaAs base layer, is operated at high speed. It is attracting attention in terms of sex.
[0003]
However, due to the element isolation structure, parasitic capacitance, especially base-collector capacitance C_bCTherefore, it is necessary to overcome this problem. In the present invention, one means is disclosed.
[0004]
[Prior art]
Usually, in an HBT having a base layer made of InGaAs, InGaAs or InP is used as a sub-collector layer for a collector contact. For example, an AlGaAs emitter layer / GaAs base layer or an InGaP emitter layer / GaAs base layer is used. The sub-collector layer cannot be deactivated by ion implantation as in the case of HBTs having
[0005]
Therefore, the one using an element isolation structure depending on mesa etching has become the mainstream, and as a result, parasitic capacitance, especially base-collector capacitance C_bcCannot be made small, and high-speed operation performance has been sacrificed.
[0006]
In order to solve such a problem, a structure in which a part of the external base region under the base electrode and the collector layer under the base electrode are undercut, that is, the base layer and the collector layer are side-etched using the base electrode as a mask. HBTs having the structure described above are known (InAlAs / InGaAs-InP HBT: 1997 GaAs IC Symposium (p. 141) TRW KW Kobayashi et al.), “AlGaAs / GaAs HBT: 1996 GaAs IC Symposium. (P.167) TI W. Liu et al., “JP 9-36131 A”, “JP 7-245317 A”, etc.).
[0007]
Base collector capacity C_bc(1) In the base electrode lead-out portion, the resistance is increased by removing the base layer, forming the insulating film, ion implantation into the collector layer and the sub-collector layer, and (2) external base. It is known to increase the resistance of the external collector region by ion implantation under the region (refer to “Japanese Patent Laid-Open No. 5-198586” if necessary).
[0008]
FIG. 14 is a main part explanatory view showing an HBT for explaining a structure in which a part of the external base region under the base electrode and the collector layer under the base electrode are undercut, and FIG. B) shows a cross section of the main part along the line XX, and (C) shows a cross section of the main part along the line Y-Y.
[0009]
In the figure, 1 is a sub-collector layer, 2 is a collector layer, 3 is a base layer, 3A is an intrinsic base region, 3B is an external base region, 4 is an emitter layer, 5 is an emitter cap layer, and 6 is an emitter electrode. , 7 is a base electrode, 7A is a base electrode lead portion, 8 is a collector electrode, 9 is an interlayer insulating film, 9A is an electrode contact hole, 10 is an emitter lead wire, 11 is a base lead wire, and 12 is a collector lead wire. Show.
[0010]
As is apparent from FIG. 14C, as shown by the broken line, a part of the external base region 3B and a part of the collector layer 2 therebelow are side etched using the base electrode 7 as a mask. By removing it, the parasitic capacitance is reduced.
[0011]
However, this HBT hardly considers the reduction of the parasitic capacitance in the base electrode lead portion 7A.
[0012]
That is, as described above, when part of the external base region 3B and part of the collector layer 2 therebelow are removed, side etching is performed in the same manner in the base electrode lead portion 7A. A part of the semiconductor layer is removed, but each semiconductor layer present in the base electrode lead-out portion 7A serves to support the contact portion between the base electrode 7 and the base lead-out wiring 11, but in addition to this, there are no other types. It only serves as a source of parasitic capacitance without playing a role. In addition, the base electrode lead-out portion 7A usually has an enlarged structure in the vicinity of the electrode contact hole 9A. Therefore, even if the side etching is performed, the depth thereof is It is the same, and most of the remaining state is left, and there is little contribution to the reduction of parasitic capacitance.
[0013]
Further, in order to sufficiently reduce the parasitic capacitance in the base electrode lead-out portion 7A, when the respective semiconductor layers in the portion are almost removed, the external base region 3B and the like are side-etched in the same manner, so that the HBT is normal. It will be in a state that does not work. In order to avoid this, it may be possible to make the width of the external base region 3B equal to the width of the base electrode lead-out portion 7A. However, the area must be increased as a whole, which leads to high integration. It will be disadvantageous.
[0014]
The above-described problem exists in common with conventional HBTs that adopt a means similar to the means for removing a part of the external base region 3B and the part of the collector layer 2 below it, and the base In the electrode lead-out portion, the means shown in Japanese Patent Laid-Open No. Hei 5-198586 is employed in which the base layer is removed, the insulating film is formed, and the resistance is increased by ion implantation into the collector layer and the sub-collector layer. Aside from the research stage, the manufacturing process becomes so complicated that it is not familiar with the practical use base.
[0015]
[Problems to be solved by the invention]
In a simple process, the semiconductor parts such as the base layer and the collector layer in the base electrode lead-out portion are removed, and the base-collector capacitance C_bcThe characteristics of the HBT, particularly the high-speed operability, are further improved.
[0016]
[Means for Solving the Problems]
In the present invention, the base electrode lead-out portion has a structure in which the base electrode and the base layer do not contact each other, in other words, a structure in which the base layer and the collector layer do not exist under the base electrode._bcIn order to realize a structure in which the base electrode and the base layer do not contact each other, there are several means.
[0017]
FIG. 1 is a cut-away side view of the principal part showing the basic HBT structure for explaining the present invention.
[0018]
In the figure, 21 is a sub-collector layer, 22 is a collector layer, 23 is a base layer, 24 is an emitter layer, 25 is an emitter cap layer, 26 is an emitter electrode, 27 is a base electrode, and 27A is a base electrode lead-out portion. , 28 are collector electrodes, 29 is an interlayer insulating film made of polyimide, 30 is an emitter lead wire, 31 is a base lead wire, and 32 is a collector lead wire.
[0019]
As is apparent from the figure, the base electrode lead-out portion 27A has a shape that is bent and raised from the surface of the base layer 23, and has a structure in which the base layer 23 and the collector layer 22 do not exist below it. .
[0020]
In order to obtain such a structure, when the base electrode 27 is formed, a structure having a shape that separates the base electrode lead portion 27A from the surface of the base layer 23 under the portion to be the base electrode lead portion 27A, that is, If a pedestal is formed in advance and the pedestal is also removed when the base mesa is etched after the base electrode 27 is formed, the shape shown in the figure can be obtained.
[0021]
At this time, since the surface of the portion of the base layer 23 under the base electrode lead portion 27A is exposed, many regions can be easily and easily removed unlike the case of side etching or the like. .
[0022]
The pedestal can be formed of an insulating film or an emitter layer made of InP or InAlAs before the base electrode 27 is formed.
[0023]
FIG. 2 is a cutaway side view showing the principal part of another HBT structure in principle for explaining the present invention. The same symbols as those used in FIG. 1 represent the same parts or have the same meanings. Shall.
[0024]
In the figure, 33 indicates an interlayer insulating film, and 33A indicates a cavity generated under the base electrode lead portion 27A.
[0025]
In order to realize such a configuration, if the collector electrode 28 is formed to have substantially the same thickness as the collector layer 22 and then the interlayer insulating film 33 is formed, the cavity 33A is generated. Relative permittivity (ε_r) Is 1, the parasitic capacitance can be reduced and the support of the base electrode lead portion 27A can be strengthened. If the interlayer insulating film 33 has no cavity 33A and is in a dense state, the support strength of the base electrode lead portion 27A can be increased, but the parasitic capacitance increases.
[0026]
  From the above, the semiconductor device according to the present invention.SetIn the manufacturing method,
(1)
  Forming a one-conductivity-type collector layer (eg, collector layer 22), an opposite-conductivity-type base layer (eg, base layer 23), and a one-conductivity-type emitter layer (eg, emitter layer 24) on a semiconductor substrate (eg, substrate 20); Next, a step of mesa-forming the one-conductivity-type emitter layer, and then a base electrode lead-out portion (for example, the base electrode lead-out portion 27A) on the side of the mesa-formed one-conductivity-type emitter layer Forming a pedestal (for example, pedestal 42A) for lifting and bending in a direction away from the surface of the layer, and then forming a base electrode (for example, base electrode 27) including the base electrode lead-out portion And then removing the opposite conductivity type base layer below the pedestal and the base electrode lead-out portion. Either, or,
(2)
  In the above (1), the method further comprises the step of removing the collector layer (for example, the collector layer 22) below the base electrode lead-out portion following the removal of the opposite conductivity type base layer, or
(3)
  Forming a one-conductivity-type collector layer (eg, collector layer 22), an opposite-conductivity-type base layer (eg, base layer 23), and a one-conductivity-type emitter layer (eg, emitter layer 24) on a semiconductor substrate (eg, substrate 20); Next, the one conductivity type emitter layer is etched to form a mesa, and a base electrode lead portion (for example, the base electrode lead portion 27A) is lifted in a direction away from the surface of the opposite conductivity type base layer to the side of the mesa. Forming a pedestal (for example, pedestal 42A) for forming a bent shape using the same one-conductivity type emitter layer, and then forming a base electrode (for example, base electrode 27) including the base electrode lead-out portion. And a step of removing at least the opposite conductivity type base layer below the pedestal and the base electrode lead portion. It is either characterized by comprising, or,
(4)
  In the above (3), the side surface of the pedestal is etched to give a gentle inclination of the forward mesa.
[0034]
By adopting the above-mentioned means, the semiconductor portion such as the base layer and the collector layer in the base lead-out portion is removed by a simple process, and the base-collector capacitance C_bcCan be greatly reduced, and the characteristics of the HBT, in particular, high-speed operability can be further improved.
[0035]
Incidentally, in the HBT of the present invention, when it is assumed that the base layer and the collector layer remain below the base electrode lead portion to be removed, the relative dielectric constant is about 13.9 for InGaAs and about 12.4 for InP. However, as seen in the embodiment of the present invention, when the interlayer insulating film made of polyimide is embedded after removing the portion, the relative dielectric constant is about 4, and from the surface of the sub-collector layer Therefore, the parasitic capacitance is further reduced.
[0036]
In the case where a cavity is generated in the interlayer insulating film, the base-collector capacitance C_bcSince the support strength of the base electrode lead-out portion can be improved without increasing, a mechanically stable structure can be realized.
[0037]
In this case, the lower part of the base electrode lead-out part is partially covered with an insulating film, but most is hollow and the relative permittivity of air is 1.₂= 3.9, SiON = about 6, SiN = 7.5, and so on.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 3 to FIG. 5 are main part cut side views showing the HBT at the main points of the process for explaining one embodiment of the present invention.
[0039]
This embodiment is an example in which a base made of an insulator is used to separate the base electrode lead portion 27A from the surface of the base layer 23, and will be described below with reference to the drawings.
[0040]
Refer to FIG.
3- (1)
A sub-collector layer 21, a collector layer 22, a base layer 23, an emitter layer 24, and an emitter / cap layer 25 are grown on the substrate 20 by applying a MOCVD (Metalorganic Chemical Vapor Deposition) method.
[0041]
Here, main data regarding each semiconductor portion is exemplified as follows.
(1) About the substrate 20
Material: Semi-insulating InP
(2) Sub-collector layer 21
Material: n⁺-InGaAs
Impurity concentration: 4 × 10¹⁹〔cm^-3]
Thickness: 4000 [Å]
(3) About the collector layer 22
Material: n^--InGaAs
Impurity concentration: 1 × 10¹⁷〔cm^-3〕Less than
Thickness: 5000 [Å]
(4) About the base layer 23
Material: p⁺-InGaAs
Impurity concentration: 4 × 10¹⁹〔cm^-3]
Thickness: 500 [Å]
(5) About the emitter layer 24
Material: n-InP
Impurity concentration: 4 × 10¹⁷〔cm^-3]
Thickness: 2000 [Å]
(6) Emitter cap layer 25
Material: n⁺-InGaAs
Impurity concentration: 4 × 10¹⁹〔cm^-3]
Thickness: 1000 [Å]
[0042]
3- (2)
By applying a resist process in the lithography technique, a resist film 41 is formed on the emitter cap layer 25 so as to cover a portion where the emitter is to be formed.
[0043]
3- (3)
Etchant for example H_ThreePO_Four: H₂O₂: H₂O = 1: 1: 50 (for InGaAs) and HCl: H_ThreePO_FourBy applying a wet etching method of 1: 5 (for InP), mesa etching of the emitter cap layer 25 and the emitter layer 24 is performed using the resist film 41 as a mask. In the figure, the emitter / cap layer 25 is etched.
[0044]
Of course, a dry etching method can be applied to the etching in this case.
[0045]
Refer to FIG.
3- (4)
By removing the resist film 41 and then applying a CVD (Chemical Vapor Deposition) method, a thickness of, for example, 1000 [Å] to 3000 [Å] SiO₂An insulating film 42 made of is formed. In addition, SiO₂May be replaced by SiON or the like.
[0046]
3- (5)
By applying a resist process in lithography technology, a resist film 43 is formed on a base formation scheduled portion for obtaining a configuration in which the base electrode lead portion is separated from the base layer.
[0047]
Refer to FIG.
4- (1)
By applying a wet etching method using hydrofluoric acid or buffered hydrofluoric acid as an etchant, the insulating film 42 is etched using the resist film 43 as a mask to form the base 42A.
[0048]
4- (2)
The emitter electrode 26 made of Ti / Pt / Au is formed by applying a resist process, a vacuum deposition method, and a lift-off method in lithography technology, and then Ti / Pt / Au is used by the same means. A base electrode 27 is formed. Needless to say, the base electrode 27 includes the base electrode lead-out portion 27A in an integrated manner, and the base of the base electrode lead-out portion 27A, that is, the base 42A, is the base electrode lead-out portion 27A. A part is expressed beyond the range.
[0049]
In this step, the order of forming the emitter electrode 26 and the base electrode 27 may be reversed. In addition to the materials described above, WSi may be used as the emitter electrode 26, or WSi or AuZn / Au may be used as the base electrode 27. Can be used.
[0050]
Refer to FIG.
4- (3)
By applying a resist process in the lithography technique, a resist film 44 covering the emitter region is formed.
[0051]
4- (4)
By applying a wet etching method using an etchant as a buffered hydrofluoric acid, all of the pedestal 42A and a part of the base layer 23 and the collector layer 22, that is, a part indicated by a mesh in the figure are removed.
[0052]
Refer to FIG.
5- (1)
FIG. 5A shows a state in which all of the pedestal 42A and a part of the base layer 23 and the collector layer 22 are removed. As is clear from this, the base of the base electrode lead portion 27A is the base layer 23. Is etched from the exposed surface, so it can be greatly undercut.
[0053]
5- (2)
The collector electrode 28 made of AuGe / Ni / Au is formed by applying a resist process, a vacuum deposition method, and a lift-off method in lithography technology.
[0054]
5- (3)
Thereafter, an ordinary technique may be applied to form an interlayer insulating film, electrode contacts / holes, lead wirings, and the like to complete the HBT having the structure shown in FIG.
[0055]
FIG. 5B shows a state in which all of the pedestal 42A and a part of the base layer 23 are removed in the step 5- (1), and a lithography technique is applied to remove a part of the collector layer 22. In this example, the collector electrode formation scheduled portion of the sub-collector layer 21 is exposed to form the collector electrode 28. In this case, a part of the base layer 23 is removed, but the collector layer 22 is large. Since it remains, the degree of reduction of the parasitic capacitance is small, but the strength is high, so the impact resistance is high.
[0056]
FIGS. 6 to 9 are side sectional views showing the main part of the HBT in the main process steps for explaining another embodiment of the present invention. The symbols used in FIGS. 1 to 5 represent the same parts or have the same meaning.
[0057]
In this embodiment, in order to separate the base electrode lead portion 27A from the surface of the base layer 23, a part of the emitter layer is used as a pedestal, and the base electrode and the collector electrode are arranged in a self-aligned manner with respect to the emitter electrode. This is an example of formation, and will be described below with reference to the drawings.
[0058]
Refer to FIG.
6- (1)
The process of forming a required semiconductor layer such as the sub-collector layer 21 on the substrate 20 is exactly the same as the embodiment described above.
[0059]
The emitter electrode 26 made of Ti / Pt / Au or WSi having a thickness of, for example, 2000 [Å] to 4000 [Å] by applying a resist process, a vacuum deposition method, and a lift-off method in lithography technology. Form. The emitter electrode 26 may be formed by wet or dry etching means.
[0060]
6- (2)
By applying the wet etching method, the emitter cap layer 25 is etched using the emitter electrode 26 as a mask.
[0061]
Refer to FIG.
6- (3)
By applying a resist process in lithography technology, a resist film 45 is formed on a portion where a base electrode lead portion is to be formed on the emitter layer 24.
[0062]
6- (4)
By applying the wet etching method, the emitter layer 24 is etched by using the resist film 45 and the emitter electrode 26 as a mask, so that the emitter layer 24 immediately below the emitter electrode 26 is mesa and the base electrode lead portion 27A. 24A is formed to be bent from the surface of the base layer 23 and lifted. In this etching, in order to facilitate separation when the base electrode 27 is formed by the self-alignment method, it is desirable to add some side etching, and the wet etching method is a dry etching method. It may be replaced.
[0063]
Refer to FIG.
7- (1)
After removing the resist film 45, an Au-based or refractory metal-based base electrode material film is formed by applying a vacuum deposition method.
[0064]
Refer to FIG.
7- (2)
By applying a resist process in the lithography technique, a base electrode pattern resist film 46 including the base electrode 27 and the base electrode lead portion 27A is formed.
[0065]
7- (3)
By applying an ion milling method (in the case of Au-based material), the base electrode material film is etched to form the base electrode 27. When the base electrode material film is a refractory metal material, an RIE (reactive ion etching) method is preferably applied as an etching means.
[0066]
The base electrode 27 includes the base electrode lead portion 27A as in the other embodiments. In this case as well, the pedestal 24A partially extends beyond the range of the base electrode lead portion 27A. Has been issued.
[0067]
7- (4)
With the resist film 46 remaining, the entire pedestal 24A and a part of the base layer 23 and the collector layer 22, that is, the part indicated by meshes in the figure are removed.
[0068]
Refer to FIG.
8- (1)
FIG. 8A shows a state in which all of the pedestal 24A and a part of the base layer 23 and the collector layer 22 are removed, and the base of the base electrode lead portion 27A is from the surface where the base layer 23 is exposed. Since it is etched, a large undercut is realized.
[0069]
A collector electrode material film is formed on the entire surface by applying a vacuum vapor deposition method with the resist film 46 remaining. The vacuum deposition method may be replaced with a sputtering method.
[0070]
Refer to FIG.
8- (2)
By applying a lift-off method for dissolving and removing the resist film 46, the collector electrode material film on the resist film 46 is removed.
[0071]
8- (3)
A resist film 47 having a collector electrode pattern is formed by applying a resist process in lithography technology.
[0072]
See FIG.
9- (1)
By applying an ion milling method or an RIE method, unnecessary portions of the collector electrode material film are removed using the resist film 47 as a mask, and the collector electrode 28 is formed.
[0073]
9- (2)
Subsequently, ion milling is continued to make the sub-collector layer 21 mesa.
[0074]
9- (3)
Thereafter, the resist film 47 is removed, and then an ordinary technique is applied to form an interlayer insulating film, electrode contact holes, and lead wiring, and an HBT having a structure as shown in FIG. To complete.
[0075]
In the completed HBT, since the base electrode 27 and the like are formed in a self-alignment manner, the occupied area seen in a plane can be reduced to a limit, and parasitic capacitance and parasitic resistance can be reduced. Effective for reduction.
[0076]
FIG. 10 and FIG. 11 are main part cut side views showing the HBT at the main points of the process for explaining another embodiment of the present invention. The symbols used in FIG. 1 to FIG. 9 represent the same parts or have the same meaning.
[0077]
This embodiment is an example in which the base electrode lead portion 27A is bent and lifted from the surface of the base layer 23 to prevent disconnection, and will be described below with reference to the drawings.
[0078]
Refer to FIG.
10- (1)
After a required semiconductor layer such as the sub-collector layer 21 is formed on the substrate 20, a resist film is formed on the portion where the emitter electrode 26 is formed, the emitter / cap layer 25 is etched, and the base electrode leading portion on the emitter layer 24 is to be formed. The process up to formation of 45 is exactly the same as the previous embodiment.
[0079]
10- (2)
Etchant is HCl: H_ThreePO_FourBy applying the wet etching method of 1: 5, etching of the emitter layer 24 is performed using the resist film 45 and the emitter electrode 26 as a mask, and the mesaization of the emitter layer 24 immediately below the emitter electrode 26 is performed. A base 24A is formed for bending the base electrode lead portion 27A from the surface of the base layer 23 and lifting it.
[0080]
According to this etching, the mesa can be formed so that the longitudinal direction of the base electrode 27, that is, the surface of the pedestal 24A intersecting the direction in which the base electrode lead portion 27A extends forms a forward taper.
[0081]
Refer to FIG.
10- (3)
The resist film 45 is removed and the base electrode material film is formed.
[0082]
See FIG.
11- (1)
Formation of the base electrode 27, removal of all of the pedestal 24A and part of the base layer 23 and the collector layer 22, and formation of the collector electrode 28 are performed.
[0083]
11- (2)
Thereafter, an ordinary technique is applied to form an interlayer insulating film, electrode contacts and holes, and lead wirings to complete the HBT.
[0084]
The completed HBT is effective in preventing disconnection because the base electrode leading portion 27A is bent and lifted from the surface of the base layer 23.
[0085]
FIG. 12 is a cutaway side view of the main part showing the HBT at the main points of the process for explaining another embodiment of the present invention. The symbols used in FIGS. 1 to 11 represent the same parts or have the same meaning.
[0086]
In this embodiment, the undercut under the base electrode lead portion 27A is further increased to reduce the parasitic capacitance. Hereinafter, description will be given with reference to the drawings.
[0087]
In each of the above embodiments, the HBT using InGaAs as the material of the collector layer 22 has been described. However, in the case of a double heterostructure HBT in which the material of the collector layer 22 is InP, the base layer 23 is mesa. After that, since only the collector layer 22 can be selectively etched, a deep undercut is performed irrespective of other portions, and as shown in FIG. 12, for example, only an intrinsic region directly under the emitter is left, Since it can be removed even under the base electrode 27, the parasitic capacitance is remarkably reduced.
[0088]
FIG. 13 is a cutaway side view of an essential part showing an HBT at a process point for explaining another embodiment of the present invention. The symbols used in FIGS. 1 to 12 represent the same parts or have the same meaning.
[0089]
In this embodiment, after the emitter electrode 26, the base electrode 27, and the collector electrode 28 are formed, the whole is covered with an interlayer insulating film, so that the rigidity of the base electrode lead portion 27A separated from the surface of the base layer 23 is compared. This is an example in which an increase in the parasitic capacitance is suppressed by generating a cavity in the lower undercut portion while maintaining a high level, and will be described below with reference to the drawings.
[0090]
Refer to FIG.
13- (1)
The HBT seen here is similar to the HBT in the state seen in FIG. 11, but the thickness of the collector electrode 28 is the maximum in the range where it does not contact the base layer 23, and therefore the thickness is approximately equal to the thickness of the collector layer 22. Are different in that they are formed.
[0091]
Refer to FIG.
13- (2)
By applying the CVD method, SiO having a thickness of, for example, 500 [nm] to 1000 [nm]₂An interlayer insulating film 33 made of is formed. The material of the interlayer insulating film 33 is SiO.₂In addition, SiON, SiN, or the like can be used.
[0092]
When the interlayer insulating film 33 is formed by increasing the thickness of the collector layer 22 as described above, a cavity 33A is spontaneously generated in the interlayer insulating film 33 below the base electrode lead portion 27A.
[0093]
Therefore, the support of the base electrode lead portion 27A can be strengthened without increasing the parasitic capacitance. Of course, if the dense interlayer insulating film 33 is formed without generating the cavity 33A, the strength of the support can be increased, but the parasitic capacitance is increased.
[0094]
The present invention is not limited to the above-described embodiment, and many other modifications can be realized. For example, in the above-described embodiment, an InP (emitter) / InGaAs (base) system, and Although the InAlAs (emitter) / InGaAs (base) HBT has been described, HBTs using other materials such as AlGaAs (emitter) / GaAs (base), InGaP (emitter) / GaAs (base) Can be implemented in HBT.
[0095]
【The invention's effect】
  Semiconductor device according to the inventionSetIn the manufacturing method, a one conductivity type collector layer, an opposite conductivity type base layer, and a one conductivity type emitter layer are formed on a semiconductor substrate.And then forming a mesa of the one-conductivity type emitter layer, and then forming a base electrode lead-out portion on the side of the mesa-conducted one-conductivity type emitter layer. A step of forming a pedestal for forming a bent shape by lifting in a direction away from the surface, a step of forming a base electrode including the base electrode lead portion, and a lower portion of the pedestal and the base electrode lead portion The step of removing the opposite conductivity type base layer is basically included.
[0096]
  By adopting the above-mentioned configuration, the semiconductor portion such as the base layer and the collector layer in the base leading portion is removed by a simple process, and the base-collector capacitance C_bcGreatly reducing the characteristics of HBT, especially high-speed operationImprovementcan do.
[Brief description of the drawings]
FIG. 1 is a cut-away side view of a principal part showing a fundamental HBT structure for explaining the present invention.
FIG. 2 is a cut-away side view of a principal part showing another fundamental HBT structure for explaining the present invention.
FIG. 3 is a cutaway side view of a main part showing an HBT at a process key point for explaining an embodiment of the present invention.
FIG. 4 is a cutaway side view of an essential part showing an HBT at a process point for explaining an embodiment in the present invention.
FIG. 5 is a cut-away side view of a main part showing an HBT at a process key point for explaining an embodiment in the present invention.
FIG. 6 is a cut-away side view of a main part showing an HBT at a process point for explaining another embodiment of the present invention.
FIG. 7 is a cut-away side view of a main part showing an HBT at a process point for explaining another embodiment of the present invention.
FIG. 8 is a cutaway side view of a main part showing an HBT at a process point for explaining another embodiment of the present invention.
FIG. 9 is a cutaway side view of a main part showing an HBT at a process point for explaining another embodiment of the present invention.
FIG. 10 is a cutaway side view of a main part showing an HBT at a process point for explaining another embodiment of the present invention.
FIG. 11 is a cutaway side view of an essential part showing an HBT at a process point for explaining another embodiment of the present invention.
FIG. 12 is a cutaway side view of an essential part showing an HBT at a process point for explaining another embodiment of the present invention.
FIG. 13 is a cutaway side view of an essential part showing an HBT at a process point for explaining another embodiment of the present invention.
FIG. 14 is a main part explanatory view showing an HBT for explaining a structure in which a part of an external base region under a base electrode and a collector layer thereunder are undercut.
[Explanation of symbols]
21 Sub-collector layer
22 Collector layer
23 Base layer
24 Emitter layer
25 Emitter cap layer
26 Emitter electrode
27 Base electrode
27A Base electrode lead-out part
28 Collector electrode
29 Interlayer insulation film made of polyimide
30 Emitter lead wiring
31 Base drawer wiring
32 Collector lead wiring
33 Interlayer insulation film
33A Cavity generated under base electrode lead 27A

Claims (4)

Forming a one-conductivity type collector layer, an opposite-conductivity type base layer, and a one-conductivity type emitter layer on a semiconductor substrate;
Next, a step of mesa-forming the one conductivity type emitter layer;
Next, forming a base for forming a bent shape by lifting the base electrode lead-out portion in a direction away from the surface of the opposite conductivity type base layer to the side of the mesa-formed one conductivity type emitter layer;
A step of forming a base electrode including the base electrode lead portion;
And a step of removing the opposite conductivity type base layer below the base and the base electrode lead-out portion. The method of manufacturing a semiconductor device according to claim 1, characterized in that contains the step of removing the collector layer of the base electrode lead-out men side following the removal of the opposite conductivity type base layer. Forming a one-conductivity type collector layer, an opposite-conductivity type base layer, and a one-conductivity type emitter layer on a semiconductor substrate;
Next, the one-conductivity-type emitter layer is etched to form a mesa, and a base for forming a bent shape by lifting a base electrode lead-out portion in a direction away from the surface of the opposite-conductivity-type base layer to the side of the mesa Forming using the same one conductivity type emitter layer,
A step of forming a base electrode including the base electrode lead portion;
And a step of removing at least the opposite conductivity type base layer below the base and the base electrode lead-out portion. 4. The method of manufacturing a semiconductor device according to claim 3 , wherein etching is performed so that a gentle slope of a forward mesa is applied to a side surface of the pedestal.

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