JP4507295B2 - Bipolar transistor manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bipolar transistor and a manufacturing method thereof.
[0002]
[Prior art]
A conventional method of manufacturing a heterojunction bipolar transistor will be described below with reference to FIGS. 4 (a) to 4 (c) and FIGS. 5 (d) to 5 (e).
[0003]
First, a collector contact layer 2 having a thickness of 0.5 μm made of n-type GaAs doped with Si 5 × 10 ¹⁸ cm ⁻³ on a GaAs substrate 1 and made of n-type GaAs doped with Si 2 × 10 ¹⁶ cm ^−3. A collector layer 3 having a thickness of 0.5 μm, a base layer 4 made of p-type GaAs doped with C 3 × 10 ¹⁹ cm ^−3, and an n-type AlGaAs doped with Si 5 × 10 ¹⁷ cm ⁻³ A 0.1 μm thick emitter layer 5 and a 0.2 μm thick emitter contact layer 6 made of InGaAs or the like are sequentially stacked by MOCVD (FIG. 4A).
[0004]
Next, by using the resist 7 patterned by photolithography as a mask, the emitter contact layer 6 and the emitter layer 5 are etched with a phosphoric acid-based etchant, whereby a forward mesa type emitter contact layer 6a having a width of about 5 μm, an emitter layer 5a is formed (FIG. 4B), and then the resist 7 is peeled off.
[0005]
Further, by using the resist 8 patterned by photolithography as a mask, the base layer 4 and the collector layer 3 are etched with a phosphoric acid-based etchant to form a forward mesa type base layer 4a and a collector layer 3a having a width of about 11 μm. (FIG. 4C), and then the resist 8 is peeled off.
[0006]
Next, using the resist 9 patterned by photolithography as a mask, the collector contact layer 2 is etched with a phosphoric acid-based etchant to form a forward mesa collector contact layer 2a having a width of about 40 μm (FIG. 5D Then, the resist 9 is peeled off.
[0007]
Finally, collector electrodes 10a and 10b having a width of about 10 μm, base electrodes 11a and 11b having a width of about 2 μm, and an emitter electrode 12 having a width of about 4 μm are formed by a lift-off method (FIG. 5E).
[0008]
Through the above steps, a heterojunction bipolar transistor 13 having collector electrodes 10a and 10b, base electrodes 11a and 11b, and an emitter electrode 12 is obtained. At this time, the distance between the inner end of the base electrode and the mesa lower surface end of the emitter layer is about 0.5 μm, and the distance between the outer end of the base electrode and the mesa upper surface end of the base layer is about 0.5 μm.
[0009]
[Problems to be solved by the invention]
However, in the above bipolar transistor, if the base electrode is formed so that the mesa side surface (of the base layer) protrudes from the upper surface of the base layer, there is a strong possibility of short-circuiting with the collector layer or the collector contact layer. Only the upper surface of the layer is formed. As a result, the base electrode area (planar projection area) is limited, the base resistance cannot be reduced, and it is difficult to improve the high frequency characteristics.
[0010]
As one method for avoiding this problem, a method of reducing the base resistance by increasing the mesa area (planar projection area) of the base layer and expanding the region where the base electrode can be formed can be considered. However, according to this method, the contact area between the base layer and the collector layer also increases, and the base-collector capacitance increases. As a result, the high-frequency characteristics cannot be improved. In addition, a new problem has arisen that the element size increases and the cost increases.
[0011]
As another method for avoiding the above-described problem, a method of reducing the base resistance by increasing the thickness of the base electrode without changing the base electrode area is conceivable. According to this method, the base resistance can be reduced without increasing the base-collector capacitance. However, when the electrode film thickness is increased, fine patterning of the base electrode becomes difficult, and the demerit that the time required for electrode formation increases.
[0012]
In the above-described prior art, since the base layer and the collector layer are inevitably located at the same position (on the same plane), the area of the base layer (planar) The base-collector capacity is uniquely determined by the projected area. The area of the base layer cannot be made smaller than a certain level because there is a limit to the miniaturization of the emitter electrode and the base electrode, and as a result, the base-collector capacitance cannot be made smaller than a certain level. However, it has a problem that it limits the improvement of the high frequency characteristics.
[0013]
Accordingly, an object of the present invention is to solve the above-mentioned technical problem, and without causing an increase in device size and cost, the base resistance and the base-collector capacitance are small, and high frequency characteristics are achieved. An object of the present invention is to provide an excellent bipolar transistor and a manufacturing method thereof.
[0014]
[Means for Solving the Problems]
In order to solve the above technical problem, a bipolar transistor manufacturing method according to claim 1 of the present invention is formed on a mesa type epitaxial growth layer formed on a semiconductor substrate, a base layer, and a base layer. Forming a base electrode in contact with at least part of the upper surface of the base layer and at least part of the mesa side surface of the base layer; At least a part of the base electrode as a mask so that the mesa side surface of the epitaxial growth layer is located inside the mesa side surface of the base layer when the epitaxial growth layer formed under the base layer is viewed from the planar direction of the semiconductor substrate. It is characterized in Rukoto comprising the step of partially removing the epitaxial growth layer.
[0016]
The method of manufacturing a bipolar transistor according to claim 2 of the present invention, the epitaxial growth layer, wherein the collector layer or emitter layer der Rukoto.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
[First embodiment, FIGS. 1 to 2]
A bipolar transistor according to a first embodiment of the present invention will be described below with reference to the drawings. FIGS. 1A to 1D and FIGS. 2E to 2G are cross-sectional views illustrating a method for manufacturing the bipolar transistor 20.
[0020]
First, a collector contact layer 22 made of n-type GaAs doped with Si of 5 × 10 ¹⁸ cm ⁻³ and having a thickness of 0.5 μm is formed on a GaAs substrate 21, and n-type GaAs doped with Si of 2 × 10 ¹⁶ cm ^−3. A collector layer 23 having a thickness of 0.5 μm, a base layer 24 having a thickness of 0.1 μm made of p-type GaAs doped with C 3 × 10 ¹⁹ cm ^−3, and an n-type doped with Si 5 × 10 ¹⁷ cm ^−3. A 0.1 μm thick emitter layer 25 made of AlGaAs and a 0.2 μm thick emitter contact layer 26 made of n-type InGaAs doped with Si 2 × 10 ¹⁹ cm ⁻³ are sequentially stacked by MOCVD. It forms (FIG. 1 (a)).
[0021]
Next, an emitter electrode 27 having a width of about 5 μm is formed by a lift-off method, and the emitter contact layer 26 and the emitter layer 25 are etched by a phosphoric acid-based etchant using the emitter electrode 27 as a mask, for example, a forward mesa type having a width of about 5 μm. An emitter contact layer 26a and an emitter layer 25a are formed (FIG. 1B).
[0022]
Further, the base layer 24 is etched with a phosphoric acid etchant using the resist 28 patterned by photolithography as a mask to form a forward mesa type base layer 24a having a width of about 11 μm, for example (FIG. 1C), and then the resist 28 is peeled off.
[0023]
Further, base electrodes 29a and 29b having a width (planar projection width) of about 3.5 μm are formed by a lift-off method. At this time, the base electrodes 29a and 29b are formed so as to straddle the step on the mesa side surface of the base layer 24a and so that each base electrode contacts the mesa side surface without a gap. The gap between the inner ends of the base electrodes 29a, 29b and the mesa lower surface end of the emitter layer 25a is, for example, about 0.5 μm, and the contact width between the base electrodes 29a, 29b and the upper surface of the base layer 24a is about 2.5 μm. The contact width between 29a and 29b and the collector layer 23 is about 1.0 μm (FIG. 1D).
[0024]
Next, a resist 31 is patterned and formed by photolithography so as to cover the emitter electrode 27, the emitter contact layer 26a, and the emitter layer 25a. Is used to etch the collector layer 23. At this time, in some cases, a part of the base layer 24a is under-etched while the side etching of the collector layer 23 is advanced to form the collector layer 23a with a narrower width (for example, about 10 μm) than the base layer 24a (FIG. 2). (E)). After the etching is completed, the resist 31 is removed. As described above, since the collector layer 23a is side-etched, the mesa side surface of the collector layer 23a is positioned about 0.5 μm inside the mesa side surface of the base layer 24a. Thereby, the base electrodes 29a and 29b and the collector layer 23a can be reliably electrically insulated.
[0025]
Next, by using the resist 32 patterned by photolithography as a mask, the collector contact layer 22 is etched using a phosphoric acid-based etchant to form, for example, a forward mesa collector contact layer 22a having a width of about 40 μm ( 2 (f)), and then the resist 32 is removed.
[0026]
Finally, collector electrodes 33a and 33b having a width of about 10 μm are formed by a lift-off method (FIG. 2G). Through the above steps, the heterojunction bipolar transistor 20 having the collector electrodes 33a and 33b, the base electrodes 29a and 29b, and the emitter electrode 27 is obtained.
[0027]
In the bipolar transistor 20 of this embodiment, the base electrodes 29a and 29b are formed not only on the upper surface of the base layer 24a but also on the entire mesa side surface of the base layer, and extend across the mesa side surface to the outer edge thereof. Therefore, the contact area between the base layer and the base electrode can be increased, and the cross-sectional area can be increased as compared with the base electrode of the bipolar transistor having the conventional structure without increasing the film thickness. This makes it possible to reduce the base resistance without increasing the element size or increasing the thickness of the base electrode, and provides a bipolar transistor with good high-frequency characteristics, specifically with a high maximum oscillation frequency and high cutoff frequency can do.
[0028]
In the bipolar transistor 20, since the mesa side surface of the collector layer 23a is located inside the mesa side surface of the base layer 24a, the contact area between the base layer and the collector layer is smaller than that of the bipolar transistor having the conventional structure. As a result, the base-collector capacitance can be reduced, and a bipolar transistor having good high-frequency characteristics can be provided.
[0029]
In the above-described embodiment, after the layers are formed by MOCVD, the emitter electrode 27, the emitter contact layer 26 and the emitter layer 25, the base layer 24, the base electrodes 29a and 29b, and the base electrode 29a are formed. 29b (and resist 31) as a mask, the bipolar transistor 20 is formed in the order of etching of the collector layer 23, etching of the collector contact layer 22, and formation of the collector electrodes 33a and 33b. There is no need to form.
[0030]
The important points in the manufacturing process described above are the three processes of etching the base layer 24, forming the base electrodes 29a and 29b, and etching the collector layer 23 using the base electrodes 29a and 29b (and the resist 31) as a mask. It is to be performed in order (however, each of these steps is not necessarily performed continuously, and other steps may be interposed in the middle).
[0031]
Therefore, for example, etching of the emitter contact layer 26 and the emitter layer 25, etching of the base layer 24, formation of the base electrodes 29a and 29b, etching of the collector layer 23 using the base electrodes 29a and 29b (and resist 31) as a mask, collector The order of the steps may be changed such as etching of the contact layer 22 and formation of the emitter electrode 27 and the collector electrodes 33a and 33b. Further, both the process order and the formation method may be changed, such as forming the emitter electrode by the lift-off method after etching the emitter contact layer 26 and the emitter layer 25 using the resist as a mask.
[0032]
In the present embodiment, each semiconductor layer is formed in a forward mesa shape having a forward taper shape that is wider toward the bottom, but may be formed in a vertical mesa having no taper, for example. Absent.
[Second Embodiment, FIG. 3]
The bipolar transistor of the first embodiment has been described by taking an example of a so-called emitter-up type bipolar transistor in which the emitter layer is located in the uppermost layer. However, the present invention also applies to a collector-up type bipolar transistor in which the collector layer is located in the uppermost layer. The structure and the manufacturing method can be suitably applied.
[0033]
In this case, the stacking order of the semiconductor layers on the substrate is as follows. That is, as shown in FIG. 3, a 0.5 μm thick emitter contact layer 42 made of n-type GaAs doped with Si 5 × 10 ¹⁸ cm ⁻³ and Si 5 × 10 ¹⁷ cm ⁻ on a GaAs substrate 41. ^A 0.1 μm thick emitter layer 43 made of ³ doped n-type AlGaAs, a 0.1 μm thick base layer 44 made of C 3 × 10 ¹⁹ cm ⁻³ doped p-type GaAs, and 2 × 10 ¹⁶ Si. A collector layer 45 of 0.5 μm thickness made of cm ⁻³ doped n-type GaAs, a collector contact layer 46 of 0.2 μm thickness made of n-type InGaAs doped with 2 × 10 ¹⁹ cm ^{−3 of} Si, Each layer is sequentially formed by MOCVD (FIG. 3).
[0034]
The subsequent etching steps and electrode forming steps may be performed in the same flow as the steps in the first embodiment. That is, collector electrode formation, collector contact layer / collector layer etching, base layer etching, base electrode formation, emitter electrode etching using the base electrode and resist as a mask, emitter contact layer etching, emitter electrode formation, A collector-up type bipolar transistor may be manufactured in the following order.
[0035]
【The invention's effect】
As is clear from the above description, in the bipolar transistor of the present invention, the base electrode is formed not only on the upper surface of the base layer but also on the mesa side surface of the base layer and extending to the outer edge thereof. Therefore, the cross-sectional area can be increased without increasing the film thickness. In addition, the contact area between the base layer and the base electrode can be increased. This makes it possible to reduce the base resistance without increasing the element size or increasing the thickness of the base electrode, and provides a bipolar transistor with good high-frequency characteristics, specifically with a high maximum oscillation frequency and high cutoff frequency can do. Further, since it is not necessary to increase the thickness of the base electrode, the time for forming the base electrode does not increase.
[0036]
Further, in the emitter-up bipolar transistor as in the first embodiment, the contact area between the base layer and the collector layer is small because the mesa side surface of the collector layer is located inside the mesa side surface of the base layer. . As a result, the base-collector capacitance can be reduced, and a bipolar transistor with good high-frequency characteristics can be provided.
[0037]
Further, in the collector-up bipolar transistor as in the second embodiment, the mesa side surface of the emitter layer is located inside the mesa side surface of the base layer, so that the emitter area can be reduced and the collector area can be brought close to the collector area. Can do. As a result, the external emitter region can be reduced, the emitter injection efficiency can be increased, and a bipolar transistor having a high current amplification factor can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a method for manufacturing a bipolar transistor according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a method for manufacturing the bipolar transistor of the first embodiment.
FIG. 3 is a sectional view showing a laminated structure of a film of a bipolar transistor according to a second embodiment.
FIG. 4 is a cross-sectional view illustrating a conventional bipolar transistor manufacturing method.
FIG. 5 is a cross-sectional view showing a conventional bipolar transistor manufacturing method.
[Explanation of symbols]
20 ・ ・ ・ Bipolar transistor 21 ・ ・ ・ GaAs substrate 22 ・ ・ ・ Collector contact layer 23 ・ ・ ・ Collector layer 24 ・ ・ ・ Base layer 25 ・ ・ ・ Emitter layer 26 ・ ・ ・ Emitter contact layers 27, 28, 31, 32... Resist 29a, 29b... Base electrode 33a, 33b... Collector electrode

Claims (2)

A method of manufacturing a bipolar transistor having a mesa-type epitaxial growth layer formed on a semiconductor substrate, a base layer, and a base electrode formed on the base layer in this order,
Forming a base electrode in contact with at least part of the upper surface of the base layer and at least part of the mesa side surface of the base layer; and forming the base electrode under the base layer using at least part of the base electrode as a mask And a step of partially removing the epitaxial growth layer so that the mesa side surface of the epitaxial growth layer is located inside the mesa side surface of the base layer when the semiconductor substrate is viewed from the planar direction. A method of manufacturing a bipolar transistor. 2. The method for manufacturing a bipolar transistor according to claim 1 , wherein the epitaxial growth layer is a collector layer or an emitter layer.

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