JP4075934B2 - Carrier recovery device - Google Patents

Description

  The present invention relates to a carrier recovery apparatus used when demodulating a digital modulation signal such as a multilevel quadrature amplitude modulation (QAM) signal or a multiphase phase modulation (PSK) signal.

  In recent years, digitalization of video has progressed, and digital broadcasting has been started in each country on satellite, CATV, and terrestrial broadcasting media. As the transmission method, a method suitable for the characteristics of each transmission path is selected. For example, satellite broadcasting uses multiphase phase modulation such as 4PSK and 8PSK, and CATV uses multilevel quadrature amplitude modulation such as 64QAM and 256QAM.

  Such digital modulation signal demodulation systems have been introduced in a number of documents. As an example, “Taga, Ishikawa, Komatsu:“ A Study of QPSK Demodulation System ”” (Technical Report of the Television Society, vol. .15, No. 46, CE'91-42 (1991.08)), a conventional carrier recovery device will be described.

  FIG. 30 is a block diagram showing a configuration of a conventional carrier reproducing apparatus. Referring to FIG. 30, a conventional carrier recovery apparatus includes a modulation signal input terminal 5010, a complex multiplier 5011, an arc tangent calculator 5030 that calculates an arc tangent, a loop filter 5013, a numerically controlled oscillator 5014, and a demodulator. A signal output terminal 5015.

  In FIG. 30, a signal line indicated by a thick line and “/ 2” indicates a signal line of a complex-represented signal.

  The operation of the conventional carrier recovery circuit will be briefly described below.

  In FIG. 30, the received digital modulation signal is once subjected to quadrature detection in the previous stage and input to the modulation signal input terminal 5010. However, when quadrature detection is performed in the preceding stage, the carrier wave for quadrature detection is not always the correct frequency and the correct phase. Accordingly, the signal input to the modulation signal input terminal 5010 still has a frequency and phase shift. The signal input to the modulation signal input terminal 5010 is input to one input terminal of the complex multiplier 5011. The numerical control oscillation unit 5014 outputs a complex oscillation signal composed of two oscillation signals orthogonal to each other, and this is input to the other input terminal of the complex multiplication unit 5011.

  The complex multiplier 5011 removes the frequency and phase shift of the signal input to the input terminal 5010 by performing complex multiplication of the output of the numerically controlled oscillator 5014 and the signal input to the modulation signal input terminal 5010. The demodulated signal is output via the demodulated signal output terminal 5015.

On the other hand, the demodulated signals Si and Sq that are the outputs of the complex multiplier 5011 are input to the arctangent calculator (Tan ⁻¹ ) 5030. An arc tangent calculation unit (Tan ⁻¹ ) 5030 calculates an arc tangent based on the values of Si and Sq, and a digital modulation signal carrier signal supplied to the modulation signal input terminal 5010 and a numerically controlled oscillation unit 5014. The phase error from the output signal is detected. The output of the arc tangent calculation unit 5030 is input to the loop filter 5013, and high frequency components of the phase error are removed. Thus, the output of the loop filter 5013 is input to the numerically controlled oscillator 5014 as a control signal for the numerically controlled oscillator 5014. The output signal of the numerically controlled oscillator 5014 controlled by the output signal of the loop filter 5013 is supplied to the complex multiplier 5011.

In the above description, as shown in (Equation 1) and (Equation 2), the output of the numerically controlled oscillator 5014 has a conjugate relationship with the carrier signal of the signal input to the modulation signal input terminal 5010 (that is, the frequency shift). And a signal having no phase shift). Therefore, when there is a relationship of (Equation ¹ ) and (Equation 2), the arctangent calculation unit (Tan ⁻¹ ) 5030 detects zero phase error. If there is a phase difference between (Equation 1) and (Equation 2), the arctangent calculation unit (Tan ⁻¹ ) 5030 outputs a signal corresponding to the phase error.

  Since the negative feedback control loop is configured by the phase control loop configured as described above, the numerically controlled oscillation unit 5014 reproduces a carrier wave that is phase-synchronized with the received digital modulation signal. Further, the reproduced carrier wave is conjugate with the carrier wave signal of the signal input to the modulation signal input terminal 5010 (that is, there is no frequency shift and phase shift), and there is no frequency error and phase error. Can be obtained.

  As described above, the phase error detection in the conventional carrier recovery circuit is obtained by the arctangent calculation unit 5030 performing arctangent calculation on the output of the complex multiplication unit 5011. The operation will be described in more detail with reference to FIG.

FIG. 31 is an output signal space diagram for explaining the conventional phase error detection operation. Here, it is assumed that the received digital modulation signal is 4PSK, and only the first quadrant will be described to simplify the description. Assume that a phase error Δθ exists between the digital modulation signal input to the modulation signal input terminal 5010 and the output signal of the numerically controlled oscillation unit 5014. The demodulated signal that is the output of the complex multiplier 5011 is indicated by a circle 5041. If the correct carrier wave is reproduced, the above-described phase error Δθ does not exist. Therefore, the demodulated signal that is the output of the complex multiplier 5011 is indicated by a mark 5042 that is the original phase of the 4PSK symbol. The phase indicated by the mark 5042 is (π / 4 + n · π / 2) [radians] (n = 0, 1, 2, 3). However, since it is assumed that a phase error Δθ exists, the signal output from the complex multiplier 5011 exists at the position of phase φ (φ = π / 4 + Δθ).

  This phase error Δθ is obtained by performing an arctangent operation on the basis of Si and Sq, which are outputs of the complex multiplier 5011, to obtain a phase φ, and this received symbol phase φ and the original 4PSK symbol phase (π / 4) ) To obtain the difference.

By the way, the arctangent calculation for obtaining the phase φ of the received symbol is generally performed by storing the value of Tan ⁻¹ (Sq / Si) calculated in advance for Si and Sq in a storage device such as a ROM. And Sq as addresses. Alternatively, a codec algorithm is also used in which a rotation of a two-dimensional vector is calculated based on Si and Sq, and an angle for the amount of rotation is obtained.
Taga, Ishikawa, Komatsu, "A Study on QPSK Demodulation System", Television Society Technical Report, vol. 15, no. 46, CE'91-42 (1991.08)

  However, in the method of calculating the arctangent using the ROM, an enormous ROM capacity is required, which increases the circuit scale. In addition, the codec method requires many steps to obtain a highly accurate phase, and there is a problem that a frequency pull-in range (capture range) is narrowed with an increase in delay in a loop of a carrier recovery circuit.

Carrier wave recovery device
Numerically controlled oscillation means for outputting a complex oscillation signal;
Complex multiplication means for complex multiplication of the input modulation signal and the output of the numerically controlled oscillation means;
Phase error detection means for detecting a phase error between the modulation signal and the complex oscillation signal based on the output of the complex multiplication means;
A carrier filter for regenerating a carrier wave of a modulation signal by means of a numerically controlled oscillating means, comprising a loop filter for controlling a numerically controlled oscillating means by filtering phase errors,
The phase error detection means includes at least symbol estimation means for estimating a symbol based on the output of the complex multiplication means.

  The carrier wave reproducing apparatus of the present invention reproduces a carrier wave for demodulating a digital modulation signal such as a multilevel quadrature amplitude modulation signal or a multiphase phase modulation signal. The carrier recovery apparatus of the present invention can detect the phase error of the modulation signal with a simple calculation, can reduce the circuit scale, and can improve the frequency pull-in characteristic and the phase jitter characteristic.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS.

  In the following description, Embodiment 1 is a carrier wave reproducing device that is the basis of the present invention.

  The second embodiment is a carrier recovery device in which the frequency pull-in characteristics and the phase jitter characteristics when receiving a multilevel quadrature amplitude modulation signal (QAM) are further improved as compared with the first embodiment.

  The third embodiment is a carrier recovery device in which the frequency pull-in characteristics and the phase jitter characteristics are further improved in the reception situation having noise and reflection interference as compared with the first and second embodiments.

The fourth embodiment is different from the first, second, and third embodiments in 16QAM, 64QAM, 256QAM, 1024QAM, and the like (that is, (2 ^ 2n)
This is a carrier recovery apparatus that further improves the frequency pull-in characteristics and phase jitter characteristics in a reception situation having noise and reflection interference when receiving QAM and n = 2, 3, 4, 5,.

  The fifth embodiment is a carrier wave reproducing device in which the frequency pull-in range (capture range) is further improved with respect to the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a carrier recovery apparatus according to Embodiment 1 of the present invention.

  In FIG. 1, a modulation signal input terminal 10, a complex multiplication unit 11, a phase error detection unit 12a, a loop filter 13, a numerical control oscillation unit 14, and a demodulation signal output terminal 15 are provided.

  In FIG. 1, a signal line indicated by a bold line and indicated by “/ 2” indicates a signal line of a complex-represented signal (hereinafter, a signal line indicated by a bold line and indicated by “/ 2” in each drawing). Is the same).

  The outline of the carrier wave reproducing apparatus according to Embodiment 1 will be described below.

  FIG. 1 shows an example in which a signal subjected to multilevel quadrature amplitude modulation or multiphase phase modulation is received. The received digital modulation signal is once subjected to quadrature detection in the previous stage and input to the modulation signal input terminal 10. However, when quadrature detection is performed in the preceding stage, the carrier wave for quadrature detection is not always the correct frequency and the correct phase. Therefore, the signal input to the modulation signal input terminal 10 remains in frequency and phase shift. That is, this signal is a signal that can be expressed by (Equation 1) where I (also called in-phase) signal component is Si and Q (also called quadrature) signal component is Sq.

A signal expressed by (Expression 1) is input to the modulation signal input terminal 10 and input to one input terminal of the complex multiplier 11. The numerically controlled oscillator 14 outputs a signal expressed by (Expression 2) assuming that the signal is a conjugate signal with the carrier component of the signal expressed by (Expression 1) exp (j (Δwt + Δθ).

  That is, the numerically controlled oscillation unit 14 outputs a complex oscillation signal composed of two oscillation signals orthogonal to each other, and this is input to the other input terminal of the complex multiplication unit 11.

  The complex multiplier 11 performs the calculation shown in (Equation 3) by performing complex multiplication of the output of the numerically controlled oscillator 14 and the signal input to the modulation signal input terminal 10.

  The complex multiplier 11 removes the frequency and phase shift of the signal input to the input terminal 10 and outputs the demodulated signal (Si + jSq) via the demodulated signal output terminal 15.

On the other hand, the demodulated signal output from the complex multiplier 11 is also input to the phase error detector 12a. The phase error detector 12a detects the phase error of the received digital modulation signal based on Si and Sq. The output of the phase error detector 12a is input to the loop filter 13, and the high frequency component of the phase error is removed. Then, it is input as a control signal to the numerically controlled oscillator 14. The output signal of the numerically controlled oscillator 14 controlled by the output signal of the loop filter 13 is supplied to the complex multiplier 11.

  In the above description, as shown in (Equation 1) and (Equation 2), the output of the numerical control oscillation unit 14 is conjugate with the carrier signal of the signal input to the modulation signal input terminal 10 (that is, the frequency). The case where there is no shift and no phase shift is illustrated. Therefore, when there is a relationship of (Equation 1) and (Equation 2), the phase error detector 12a detects a phase error of zero. If there is a phase difference between (Equation 1) and (Equation 2), the phase error detector 12a detects the phase error.

  Since the negative feedback control loop is configured by the phase control loop configured as described above, a carrier wave that is phase-synchronized with the received digital modulation signal is regenerated by the numerically controlled oscillator 14. Since the reproduced carrier wave is conjugate with the carrier wave signal of the signal input to the modulation signal input terminal 10 and there is no frequency error and phase error, a correct demodulated signal can be obtained.

  FIG. 5 is a block diagram showing a detailed configuration of the loop filter 13 in FIG. The loop filter 13 includes a phase error signal input terminal 200, a direct amplifier 201, an integrating amplifier 202, a first adder 203, a one-symbol delay device 204, a second adder 205, a control signal, And an output terminal 206.

The output of the phase error detector 12a is supplied to the phase error signal input terminal 200. The loop filter 13 includes a phase error signal input terminal 200, a direct system 207, an integration system 208, a second addition unit 205, and a loop filter output terminal 206. Thus, the direct system 207 is composed of the direct system amplification unit 201. on the other hand,
The integration system 208 includes an integration system amplification unit 202, a first addition unit 203, and a 1 symbol delay unit 204.

  The direct system 207 is composed only of the direct system amplification unit 201 having an amplification degree of α, and performs processing only to amplify the phase error signal input via the phase error signal input terminal 200 with the amplification degree α. To do. By the way, the numerically controlled oscillator 14 is an oscillator of a type that advances (or delays) its output phase in proportion to an input control signal. Therefore, the direct system 207 functions to advance (or delay) the output phase of the numerically controlled oscillator 14 linearly with respect to the phase error signal. That is, this direct system is a system that acts to correct a phase error in carrier wave reproduction.

  On the other hand, in the integration system 208, first, the integration system amplification unit 202 amplifies the phase error signal input via the phase error signal input terminal 200 with the amplification degree β. The first addition unit 203 adds the output of the integration system amplification unit 202 and the output of the 1-symbol delay unit 204. Then, the output of the first addition unit 203 is input to the 1 symbol delay unit 204. Therefore, the loop of the first adder 203 and the 1-symbol delay unit 204 has a so-called integration function. In this way, the integration system 208 performs a so-called integration process after amplifying the phase error signal input via the phase error signal input terminal 200 with the amplification factor β. By the way, the numerically controlled oscillator 14 is an oscillator of a type that advances (or delays) its output phase in proportion to an input control signal. Therefore, the integration system 208 has a function of controlling the output frequency of the numerically controlled oscillator 14 based on the phase error signal. That is, the integration system 208 is a system that acts to correct a frequency error in carrier wave reproduction.

  The output signal of the numerically controlled oscillator 14 controlled by the output signal of the loop filter 13 is supplied to the complex multiplier 11.

Since the negative feedback control loop is constituted by the thus configured phase control loop, the carrier wave that is phase-synchronized with the received digital modulation signal is converted into the numerically controlled oscillator 14.
It is played with. Since the reproduced carrier wave is conjugate with the carrier wave signal of the signal input to the modulation signal input terminal 10 and there is no frequency error and phase error, a correct demodulated signal can be obtained.

  Next, the operation of the phase error detection unit 12a of the carrier wave reproduction device according to Embodiment 1 of the present invention will be described using FIG.

  FIG. 2 is a block diagram showing a detailed configuration of the phase error detector 12a in the carrier wave reproducing apparatus of FIG. In FIG. 2, the phase error detection unit 12 a includes a demodulated signal input terminal 100, a symbol estimation unit 101, a complex conjugate unit 102, a second complex multiplication unit 103, an imaginary number selection unit 104, and a phase error output terminal 105. With.

  If the output of the numerically controlled oscillator 14 in FIG. 1 is conjugate with the carrier wave of the signal applied to the modulation signal input terminal 10 (that is, there is no frequency shift and phase shift), the output of the complex multiplier 11 is correct. Output demodulated signal. If the phase of the output signal of the numerically controlled oscillator 14 is not conjugate with the phase of the carrier wave of the signal applied to the modulation signal input terminal 10 (that is, if there is a frequency shift and a phase shift), the complex multiplier 11 is correct. The demodulated signal cannot be output.

  The output of the complex multiplier 11 is supplied to the symbol estimator 101 and the second complex multiplier 103 via the demodulated signal input terminal 100. The symbol estimation unit 101 estimates the transmitted symbol based on the demodulated signal input from the demodulated signal input terminal 100, and outputs the estimation result.

  The symbol estimation unit 101 will be described in detail with reference to FIGS. 15A and 15B. 15A and 15B are diagrams illustrating the operation of the symbol estimation unit 101. FIG. 15A illustrates the case of 4PSK, and FIG. 15B illustrates the case of 16QAM.

In FIG. 15A, the axis 150 is an I signal axis, and the axis 151 is a Q signal axis. Assume that the output signal phase of the numerically controlled oscillator 14 in FIG. 1 is not conjugate with the phase of the carrier wave of the signal input via the modulation signal input terminal 10 (that is, there is a frequency shift and a phase shift). The signal output from the complex multiplier 11 is the symbol indicated by the circle 152 even if the symbol indicated by the circle 153 is transmitted.

  On the other hand, in FIG. 15B, the axis 154 is the I signal axis, and the axis 155 is the Q signal axis. Assuming that the output signal phase of the numerically controlled oscillator 14 in FIG. 1 is not conjugate with the phase of the carrier wave of the signal input to the modulation signal input terminal 10 (that is, there is a frequency shift and a phase shift) Even if the symbol indicated by the mark 157 is transmitted, the signal output from the complex multiplier 11 is the symbol indicated by the mark 156.

  An arrow 158 indicates the minimum inter-code distance d in the I signal axis direction (axis 154 direction), and an arrow 159 indicates the minimum inter-code distance d in the Q signal axis direction (axis 155 direction).

  If the input signal is a symbol with a circle 152 in FIG. 15A, the symbol estimation unit 101 estimates that the symbol with the closest mark 153 is transmitted, and Output symbols. When the input signal is a symbol indicated by a circle 156 in FIG. 15B, the symbol estimation unit 101 estimates that the symbol with the closest mark 157 is transmitted, and Output symbols.

  In this way, the value of the I signal axis of the estimated and output value is Di, and the value of the Q signal axis is Dq. Therefore, this output is expressed as (Di + jDq) in complex expression.

The output of the symbol estimation unit 101 is input to the complex conjugate unit 102 of FIG. 2, and the complex conjugate unit 102 takes the complex conjugate of the output of the symbol estimation unit 101 expressed by (Di + jDq). That is, complex conjugate section 102 inverts the sign of Dq that is the Q-axis component of the output of symbol estimation section 101 to generate (Di−jDq). The output of the complex conjugate unit 102 is input to the second complex multiplication unit 103. Second complex multiplier 10
3 performs complex multiplication on the output (Di−jDq) of the complex conjugate unit 102 and the demodulated signal (Si + jSq) input from the demodulated signal input terminal 100. Therefore, the second complex multiplier 103 outputs the calculation result expressed by (Equation 4).

  The output of the second complex multiplier 103 is input to the imaginary part selector 104, and the imaginary part selector 104 selects only the imaginary part (Sq · Di-Si · Dq) of (Equation 4) to obtain a phase error. Output as a signal.

  Next, the principle of derivation of the phase error by the above-described phase error detector 12a will be further described with reference to FIG. FIG. 16 shows the operation of the phase error detector 12a in a signal space diagram. Here, it is assumed that the received digital modulation signal is 4PSK, and only the first quadrant will be used for the sake of simplicity.

  In FIG. 16, the axis 150 is an I signal axis, and the axis 151 is a Q signal axis. These correspond to the axes 150 and 151 in FIG. 15A, respectively. The ● mark 153 and the ○ mark 152 correspond to the ● mark 153 and the ○ mark 152 in FIG. 15A, respectively. A circle 152 is an output signal of the complex multiplier 11 in FIG. It is assumed that the carrier wave of the orthogonal modulation signal input from the modulation signal input terminal 10 and the output signal of the numerically controlled oscillation unit 14 have a phase error Δθ. Accordingly, the circle mark 152 has a phase error Δθ with respect to the mark 153 that is the original symbol. That is, the output of the complex multiplier 11 in FIG. 1 can be expressed as (Equation 5).

  As described above, the symbol estimation unit 101 in FIG. 2 is the first symbol that is the closest to the demodulated signal (◯ mark 152 in FIG. 15A) that is the output of the complex multiplication unit 11 among the four original 4PSK symbols. A quadrant symbol (-mark 153 in FIG. 15A) is estimated as a transmitted symbol and output. The output of the symbol estimation unit 101 can be expressed as (Equation 6).

  The output of the symbol estimation unit 101 is a complex conjugate unit 102, which takes complex conjugate as shown in (Equation 7) and is input to the second complex multiplication unit 103.

  The second complex multiplier 103 complex-multiplies the demodulated signal output from the complex multiplier 11 and the output from the complex conjugate unit 102 as shown in (Equation 8).

As can be seen from (Equation 8), the output of the second complex multiplier 103 is a signal whose phase term has only a phase error Δθ. The output of the second complex multiplier 103 is indicated by a square 161 in FIG. (A = 1 in FIG. 16) That is, the output of the complex multiplier 11 input to the phase error detector 12a is the original modulation symbol by the calculation up to the second complex multiplier 103. ● The vector centered on the mark 153 is moved to the vector centered on the positive portion of the I signal axis 150.

  Then, the imaginary part selecting unit 104 selects only the imaginary part of the output of the second complex multiplier 103, that is, (Sq · Di−Si · Dq) as a value corresponding to the phase error Δθ. In this way, phase error detection is realized.

  Next, FIG. 3 shows another configuration of the phase error detector 12a in FIG. In FIG. 3, the demodulated signal input terminal 100, the symbol estimation unit 101, the complex conjugate unit 102, the second complex multiplication unit 103, the imaginary part selection 104, and the phase error detection output terminal 105 are the same as those in FIG. Therefore, detailed description thereof will be omitted.

  The complex conjugate unit 102 takes a complex conjugate of the demodulated signal input via the demodulated signal input terminal 100. Second complex multiplication section 103 complex-multiplies the output of symbol estimation section 101 and the output of complex conjugate section 102. The imaginary part selection 104 selects and outputs only the imaginary part of the output of the second complex multiplier 103. The sign inversion unit 106 inverts the output of the imaginary part selection 104 and outputs the result as a phase error signal via the phase error output terminal 105. The phase error detection output generated in this way is (Sq · Di-Si · Dq), as in FIG.

  2 and 3 are both imaginary parts of the result of complex multiplication of the demodulated signal input from the demodulated signal input terminal 100 and the symbol estimation result thereof (Sq). (Di-Si · Dq) is output.

FIG. 4 shows another configuration for executing processing equivalent to this processing. In FIG.
The demodulated signal input terminal 100, the symbol estimation unit 101, and the phase error detection output terminal 105 are the same as those in FIGS. Therefore, detailed description thereof will be omitted.

  The symbol estimation unit 101 performs symbol estimation on the demodulated signal input via the demodulated signal input terminal 100. The multiplier 122 multiplies the I signal component (Di) output from the symbol estimator 101 by the Q signal component (Sq) of the demodulated signal input via the demodulated signal input terminal 100, and (Di · Sq ) Is output. The multiplier 121 multiplies the Q signal component (Dq) output from the symbol estimator 101 by the I signal component (Si) of the demodulated signal input via the demodulated signal input terminal 100 to obtain (Dq · Si ) Is output. The subtractor 123 subtracts the output of the multiplier 121 and the output of the multiplier 122 and outputs the result as a phase error via the phase error detection output terminal 105. Therefore, the phase error output from the phase error detection output terminal 105 is (Sq · Di-Si · Dq), and the phase error can be detected as in FIGS.

  As described above, according to the carrier wave recovery device according to the first embodiment of the present invention, the phase error of the quadrature modulation signal can be detected with a simple calculation. It becomes possible to prevent the frequency pull-in range (capture range) from becoming narrow as the delay increases.

  In the above description, 4PSK has been described as an example, but it goes without saying that the same effect can be obtained with other multiphase phase modulation (nPSK) and multilevel quadrature modulation (nQAM).

(Embodiment 2)
The carrier wave reproducing apparatus according to Embodiment 2 of the present invention further improves the frequency acquisition characteristic and the phase jitter characteristic when receiving a multilevel quadrature amplitude modulation signal (nQAM) in the carrier wave reproducing apparatus according to Embodiment 1 above. Is.

  Hereinafter, the carrier wave reproducing apparatus according to the second embodiment of the present invention will be described.

  FIG. 6 is a block diagram showing a configuration of a carrier wave reproducing device according to Embodiment 2 of the present invention. In FIG. 6, a modulation signal input terminal 10, a complex multiplication unit 11, a phase error detection unit 12 b, a loop filter 13, a numerical control oscillation unit 14, and a demodulation signal output terminal 15 are provided.

  As shown in FIG. 6, the carrier wave reproducing device according to the second embodiment has a configuration in which the phase error detecting unit 12a in the carrier wave reproducing device according to the first embodiment is replaced with a phase error detecting unit 12b.

  The other configurations of the carrier recovery apparatus according to the second embodiment are the same as those of the carrier recovery apparatus according to the first embodiment, and the same reference numerals are given to the components and the description thereof will be made. Omitted.

  Hereinafter, the operation of the phase error detection unit 12b different from the carrier wave reproduction device according to the first embodiment will be described with reference to FIG.

  In FIG. 7, the phase error detector 12b includes a demodulated signal input terminal 100, a symbol estimator 101, a complex conjugate unit 102, a second complex multiplier 103, an imaginary part selector 104, and a phase error output terminal. 105 and an amplitude normalization unit 107.

  This phase error detection unit 12b is configured by further adding an amplitude normalization unit 107 to the phase error detection unit 12a in the carrier wave reproducing device according to the first embodiment. The other configuration is the same as that of the phase error detection unit 12a, and the same reference numerals are given to the components and the description thereof is omitted.

Now, as described in the carrier wave reproducing apparatus according to the first embodiment, the second complex multiplication section 103 receives the demodulated signal (Si + jSq) input via the demodulated signal input terminal 100 and the output of the complex conjugate section 102 ( Di-jDq) is complex multiplied. The output signal is expressed by (Equation 8). As shown in (Equation 8), the output of the second complex multiplier 103 is a function of the phase error (Δθ) and the square of the amplitude value (A2). for that reason,
When a QAM having a different amplitude depending on a symbol is received, the gain of the detected phase error differs depending on the transmitted symbol. This will be described with reference to FIG.

In FIG. 17, the axis 154 is an I signal axis, and the axis 155 is a Q signal axis. ○ marks 171 to 174 are input symbols, and ● marks 175 to 178 are original symbols being transmitted. When QAMs having different amplitudes according to symbols are received, the detected phase error is also a function of the square of the amplitude value (A2), so the detected phase error gain is added to the transmitted modulation symbol. Depending on. For this reason, it may be difficult to pull in the frequency. Also, frequency can be pulled in, and even if phase synchronization is established, a large phase jitter may occur in the demodulated output. Therefore, the carrier wave reproduction device according to Embodiment 2 further includes an amplitude normalization unit 107. The amplitude normalization unit 107 corrects the gain fluctuation of the phase error signal that is caused by the difference in the detected phase error. Hereinafter, the operation of the amplitude correction unit 107 will be described.

  In FIG. 7, the amplitude correction unit 107 includes a coefficient generation unit 109 and a multiplication unit 108. Coefficient generator 109 receives the output of symbol estimator 101 and generates a coefficient corresponding to the amplitude of each modulation symbol.

  18A, 18B, and 18C show an example of the coefficient generation method. Here, in order to simplify the explanation, it is assumed that the received digital modulation signal is 16QAM, and only the first quadrant is used for explanation (not limited to 16QAM).

18A, an I signal axis 154, a Q signal axis 155, and symbols 175 to 178 are the same as the I signal axis 154, Q signal axis 155, and symbols 175 to 178 in FIG. The estimation result of the symbol estimation unit 101 is one of the symbols 175 to 178. There are three types of amplitude values for each symbol 175-178.

  Hereinafter, the coordinates of each symbol are expressed by (I signal component, Q signal component). The outermost symbol 178 is (Di, Dq) = (3, 3), and the amplitude A3 in that case is normalized to “1”.

  Symbol 176 has (Di, Dq) = (1, 3), symbol 177 has (Di, Dq) = (3, 1), and its normalized amplitude A2 is √ (5/9).

  The symbol 175 is (Di, Dq) = (1, 1), and its normalized amplitude A1 is 1/3.

Further, as can be seen from the above (Equation 8), the output of the second complex multiplier 103 is proportional to the square of the symbol amplitude value (A2). Therefore, the coefficient generator 109 generates a coefficient corresponding to the reciprocal (1 / A2) of the square A2 of the amplitude value in each symbol, as shown below. That is,
When (Di, Dq) = (3, 3), 1 / A2 = 1 / (A3) 2 = 1 is generated as a coefficient.

In the case of (Di, Dq) = (1, 3) and (3, 1), 1 / A2 =
1 / (A2) 2 = 9/5 is generated.

  When (Di, Dq) = (1, 1), 1 / A2 = 1 / (A3) 2 = 9 is generated as a coefficient.

As described above, the coefficient for amplitude normalization of the phase error is uniquely determined by the symbol estimation unit 101 if the symbol is estimated. Therefore, as shown in FIG. 18B, the coefficient generation unit 109 uses the symbol estimation result (Di, Dq) of the symbol estimation unit 101 as an address, and the reciprocal (1 / A2) of the square (A2) of the amplitude value of each symbol.
It can be realized by a storage device such as a ROM that stores the value of.

  The output of the coefficient generator 109 in FIG. 7 is input to the multiplier 108. The output of the imaginary part selection unit 104 is multiplied by the output of the coefficient generation unit 109 in the multiplication unit 108, whereby the difference in the detected phase error due to the amplitude of each modulation symbol is corrected.

  19A, 19B, and 19C are diagrams schematically showing the operation of the phase error detection unit 12b in the carrier wave reproduction according to the second embodiment having the amplitude normalization unit 107 described above. 19A shows a case where (Di, Dq) = (3, 3), FIG. 19B shows a case where (Di, Dq) = (1, 3) and (3, 1), and FIG. 19C shows a case where (Di, Dq) = The phase error detection operation in the case of (1, 1) is shown. In these figures, an I signal axis 154, a Q signal axis 155, and symbols 171 to 178 are the same as the I signal axis 154, Q signal axis 155, and symbols 171 to 178 in FIGS. 17 and 18A, respectively.

When the quadrature modulation signal input via the modulation signal input terminal 10 in FIG. 6 and the output signal of the numerically controlled oscillator 14 have a phase error Δθ, the demodulated signal (Si + jSq) that is the output of the complex multiplier 11 is It is one of the symbols indicated by ◯ marks 174 in FIG. 19A, the symbols indicated by ◯ marks 172 and 173 in FIG. 19B, and the symbols indicated by ◯ marks 171 in FIG. 19C. The symbol estimation results of these symbols 171 to 174 are indicated by the symbols indicated by ● marks 178 in FIG. 19A, the symbols indicated by ● marks 176 and 177 in FIG. 19B, and the ● marks 175 in FIG. 19C. It will be one of the symbols. The conjugate signal (Di−jDq) and the demodulated signal (Si + jSq) are complex-multiplied by the second complex multiplier 103 to obtain {(Si ·
Di + Sq · Dq) + j (Sq · Di−Si · Dq)} is calculated. The value expressed by {(Si · Di + Sq · Dq) + j (Sq · Di−Si · Dq)} is as shown in FIG.
◇ mark 191, ◇ mark 193 in FIG. 19B, and ◇ mark 195 in FIG. 19C. In this way, the output signal of the second complex multiplier 103 has a different amplitude gain depending on the amplitude value of each symbol. Therefore, the amplitude normalization unit 107 normalizes the output of the second complex multiplication unit 103 by the reciprocal (1 / A2) of the square of the amplitude value (A2) in each symbol. That is, the amplitude normalization unit 107 converts the mark 191 in FIG. 19A, mark 193 in FIG. 19B, mark 195 in FIG. 19C, mark 192 in FIG. 19A, mark 194 in FIG. 19B, mark 196 in FIG. 19C. Convert to and output. In this way, the output gain of the amplitude normalization unit 107 is constant regardless of the received symbol. The phase error detection unit 12b in the carrier wave reproduction according to the second embodiment performs the imaginary part (the Q signal axis component 197 in FIG. 19A and the Q signal axis component 198 in FIG. 19B) of the normalized output of the second complex multiplication unit 103. The Q signal axis component 199 in FIG. 19C is output as a phase error.

  As described above, the result of obtaining the reciprocal of the square value of the amplitude value in each symbol is used as a coefficient, and by normalizing the output of the second complex multiplier 103 based on this coefficient, the detected phase error is reduced. Variations depending on the amplitude of each modulation symbol can be eliminated.

  As described above, according to the carrier wave device according to the second embodiment of the present invention, the phase error of the quadrature modulation signal can be detected with a simple calculation. It is possible to prevent the frequency pull-in range (capture range) from becoming narrow due to the increase in. Furthermore, it is possible to improve the frequency pull-in characteristics and the phase jitter characteristics when receiving a multilevel quadrature amplitude modulation signal (QAM).

  18C shows a case where the ROM stores the square value of the amplitude of each symbol as a coefficient, unlike FIG. 18B. The phase error detection unit 12b having the configuration shown in FIG. 7 includes, as the amplitude normalization unit 107, a coefficient generation unit 109 that uses the inverse of the square value of the amplitude of each symbol as a coefficient, and a multiplication unit 108. . However, the same function can be exhibited by replacing the multiplication unit 108 with a division unit and using the coefficient generation unit 109 shown in FIG. 18C.

The generation of the square of the amplitude value (A2) in each symbol is not limited to the above-described configuration, and (Di) 2+ (Dq) is based on (Di, Dq) that is the output of the symbol estimation unit 101. ) The same effect can be obtained even if 2 is replaced with an operation.

  Further, in the phase error detection unit 12b having the configuration shown in FIG. 7, the components other than the amplitude normalization unit 107 have been described based on the phase error detection unit 12a of FIG. 2 in the first embodiment. It goes without saying that the same effect can be obtained even with the phase error detector 12a configured as shown in FIG.

  In the above description, 16QAM has been described as an example, but it goes without saying that similar effects can be obtained with other quadrature amplitude modulations (32QAM, 64QAM, 128QAM, 256QAM, 512QAM, 1024QAM, etc.).

(Embodiment 3)
The carrier wave reproducing device according to Embodiment 3 of the present invention is the same as the carrier wave reproducing device according to Embodiments 1 and 2 described above, and has a frequency pull-in characteristic and a phase jitter characteristic in a reception situation having noise and reflection interference. It can be improved.

  Hereinafter, the carrier wave reproducing apparatus according to the third embodiment of the present invention will be described.

  FIG. 8 is a block diagram showing a configuration of a carrier recovery apparatus according to Embodiment 3 of the present invention. 8, the carrier wave recovery device according to the third embodiment includes a modulation signal input terminal 10, a complex multiplier 11, a phase error detector 12c, a loop filter 13, a numerically controlled oscillator 14, and a demodulated signal output. And a terminal 15.

As shown in FIG. 8, the carrier wave reproducing device according to the third embodiment includes the phase error detecting unit 12c in the carrier wave reproducing device according to the first embodiment described above.
It is the structure replaced with.

  The other configurations of the carrier recovery apparatus according to the third embodiment are the same as those of the carrier recovery apparatus according to the first embodiment, and the same reference numerals are given to the components, and the description thereof will be given. Omitted.

  Hereinafter, the operation of the phase error detector 12c different from the carrier wave reproducing device according to the first embodiment will be described with reference to FIG.

  FIG. 9 is a block diagram showing a detailed configuration of the phase error detector 12c in the carrier wave reproducing device of FIG.

  In FIG. 9, the phase error detection unit 12 c includes a demodulated signal input terminal 100, a symbol estimation unit 101, a complex conjugate unit 102, a second complex multiplication unit 103, an imaginary number selection unit 104, and a phase error output terminal 105. A complex subtraction unit 110, a phase error determination unit 111, a selection unit 112, and a constant generation unit 113.

  The phase error detection unit 12c in the carrier wave reproduction according to the third embodiment is similar to the phase error detection unit 12a in the carrier wave reproduction device according to the first embodiment, except for the complex subtraction unit 110, the phase error determination unit 111, and the selection unit 112. And a constant generator 113 are further added. The other configuration is the same as that of the phase error detection unit 12a, and the same reference numerals are given to the components and the description thereof is omitted.

  9, the output (Di + jDq) of the symbol estimation unit 101 and the demodulated signal (Si + jSq) that is the output of the complex multiplication unit 11 in FIG. 8 input via the demodulated signal input terminal 100 are input to the complex subtraction unit 110. The The complex subtractor 110 calculates the amplitude error (Ei + jEq) of the I signal component and Q signal component of the demodulated signal by performing complex subtraction between the output of the complex multiplier 11 and the symbol estimation result thereof. This calculation is represented by (Equation 9).

  The output (Ei + jEq) of the complex subtraction unit 110 and the output (Di + jDq) of the symbol estimation unit 101 are input to the phase error determination unit 111. The phase error determination unit 111 determines whether the phase error output from the imaginary number part selection unit 104 is reliable as a phase error based on both input signals. The selection unit 112 is controlled by the determination result of the phase error determination unit 111 and selects either the output from the imaginary part selection unit 104 or the output from the constant generation unit 113.

  Next, FIG. 20A and FIG. 20B show the state of the output signal of the complex multiplier 11 when an interference signal such as noise or reflection is superimposed on the orthogonal modulation signal input via the modulation signal input terminal 10 in FIG. Indicates. 20A and 20B, the I signal axes 150 and 154, the Q signal axes 151 and 155, the circles 153 and 175 to 178, and the circles 152 and 171 to 174 are the same as those in FIGS. 16 and 17, respectively. . In addition to moving in the phase error (Δθ) direction, each mark ● 153, 175 to 178, which is the transmitted original symbol, is further diffused in the phase direction and amplitude direction by interference signals such as noise and reflection. Thus, the received symbol is indicated by Δ. When a phase error is detected based on such a spread received symbol, the detected phase error becomes erroneous and it is difficult to pull in the frequency. Further, even if the frequency can be drawn and phase synchronization is established, a large phase jitter may occur. In order to avoid such a problem, it is necessary to use only the phase error detected by the received symbol rotated in the phase error direction for carrier wave recovery. For this purpose, the embodiment shown in FIG. 9 is provided with a phase error determination unit 111 that determines whether or not a phase error has been detected in a received symbol rotated in the phase error direction.

Two examples of specific configurations are conceivable as the phase error determination unit 111 that determines the phase error detected by the received symbol rotated in the phase error direction. Hereinafter, these two embodiments will be described in order.

(Example 1 of the phase error determination unit 111)
FIG. 22 is a block diagram illustrating a configuration of the phase error determination unit 111 according to the first embodiment. 23A and 23B are signal space diagrams for explaining the operation of the phase error determination unit 111 according to the first embodiment. Hereinafter, the operation of the first embodiment of the phase error determination unit 111 will be described with reference to FIGS. 22, 23A, and 23B. Here, for the sake of simplicity, the operation of the phase error determination unit 111 according to the first embodiment will be described using only the first quadrant in the case of 4PSK reception and 16QAM reception. Although FIG. 23A shows the case of 4PSK and FIG. 23B shows the case of 16QAM, the first embodiment is not limited to 4PSK and 16QAM.

  First, the operation principle of the first embodiment of the phase error determination unit 111 will be described with reference to FIGS. 23A and 23B. In FIG. 23A, the I signal axis 150, the Q signal axis 151, the ◯ marks, and the ● marks are the same as those in FIG. In FIG. 23B, the I signal axis 154, the Q signal axis 155, the ◯ mark, and the ● mark are the same as those in FIG. 17, and detailed description thereof is omitted. Of the symbols output from the complex multiplication unit 11 in FIG. 8, symbols rotated only in the phase error direction exist in regions 231 and 232 indicated by hatched portions. Focusing on this, the phase error determination unit 111 outputs the output of the complex multiplication unit 11 based on the amplitude error (Ei + jEq) of the demodulated signal, which is the output of the complex subtraction unit 110, and the output (Di + jDq) of the symbol estimation unit 101. When the demodulated signal is in the hatched portions 231 and 232 of FIG. 23A, it is determined that the output of the imaginary part selecting unit 104 is appropriate as the phase error signal. That is, the phase error determination unit 111 determines that the output of the imaginary number part selection unit 104 is appropriate as a phase error signal if either of the following (condition 1) or (condition 2) is met.

(Condition 1) When the estimated symbol is in the first quadrant (Di ≧ 0 and Dq ≧ 0) or the third quadrant (Di <0 and Dq <0), Ei <0 and Eq ≧ 0, or Ei ≧ 0 and Eq <0
(Condition 2) When the estimated symbol is in the second quadrant (Di <0 and Dq ≧ 0) or the fourth quadrant (Di ≧ 0 and Dq <0), Ei ≧ 0 and Eq ≧ 0, or Ei < 0 and Eq <0
(Ei + jEq) is the difference between the received symbol (Si + jSq) and the estimated symbol (Di + jDq). Accordingly, the regions satisfying the above condition in 4PSK are the hatched regions 231 and 232 in FIG. 23A, and the regions satisfying the above condition in 16QAM are the hatched regions in FIG. 23B.

  FIG. 22 shows a configuration of the phase error determination unit 111 that realizes the above phase error determination operation. 22, the output (Di + jDq) of the symbol estimation unit 101 and the output (Ei + jEq) of the complex subtraction unit 110 in FIG. 9 are input to input terminals 1110 and 1111, respectively. Comparators 1112, 1113, 1114, and 1115 determine whether Di, Dq, Ei, and Eq are each 0 or more. The outputs of the comparators 1112 and 1113 are input to the exclusive OR operation unit 1116, and the outputs of the comparators 1114 and 1115 are input to the exclusive OR operation unit 1117, respectively. The outputs of the exclusive OR operation units 1116 and 1117 are input to the exclusive OR operation unit 1118, respectively, and an exclusive OR operation is performed.

  With the above configuration, only when the above (Condition 1) or (Condition 2) is satisfied, “1” indicating that the phase error is appropriate is output from the phase error determination output terminal 1119. When neither of the above (Condition 1) and (Condition 2) is satisfied, “0” indicating that the phase error is not appropriate is output from the phase error determination output terminal 1119.

(Embodiment 2 of phase error determination unit 111)
In the first embodiment, the phase error determination is performed using the sign of the real part (Ei) and the imaginary part (Eq) in the amplitude error (Ei + jEq) of the input signal that is the output of the complex subtraction unit 110. A method for more accurately determining the phase direction error will be described below.

  FIG. 24 is a block diagram illustrating the configuration of the phase error determination unit 111 according to the second embodiment. 25A, 25B, and 25C are signal space diagrams for explaining the operation of the phase error determination unit 111 according to the second embodiment. Hereinafter, the operation of the phase error determination unit 111 according to the second embodiment will be described with reference to FIGS. 24, 25A, 25B, and 25C. Here, for simplicity of explanation, the operation of the second embodiment of the phase error determination unit 111 will be described using 4PSK reception and 16QAM reception and using only the first quadrant. 24A shows the case of 4PSK, and FIG. 24B shows the case of 16QAM. However, the second embodiment is not limited to 4PSK and 16QAM.

  First, the operation principle of the second embodiment of the phase error determination unit 111 will be described with reference to FIGS. 25A, 25B, and 25C. In FIG. 25A, the I signal axis 150, the Q signal axis 151, the ◯ mark, and the ● mark are the same as those in FIG. 16, and detailed description thereof is omitted. In FIG. 25B, the I signal axis 154, the Q signal axis 155, the ◯ mark, and the ● mark are the same as those in FIG. 17, and detailed description thereof is omitted. Of the symbols output from the complex multiplication unit 11 in FIG. 8, symbols rotated only in the phase error direction exist in regions 251 to 255 indicated by hatched portions. Paying attention to this, the phase error determination unit 111 outputs the output of the complex multiplication unit 11 based on the amplitude error (Ei + jEq) of the input signal that is the output of the complex subtraction unit 110 and the output (Di + jDq) of the symbol estimation unit 101. When the demodulated signal is in the hatched portions 251 to 255 of FIGS. 25A to 25C, it is determined that the output of the imaginary part selecting unit 104 is appropriate as the phase error signal. That is, the phase error determination unit 111 determines that the output of the imaginary number part selection unit 104 is appropriate as the phase error signal if either of the following (condition 3) or (condition 4) is met.

(Condition 3) When the estimated symbol is in the first quadrant (Di ≧ 0 and Dq ≧ 0) or the third quadrant (Di <0 and Dq <0), (−a−Ei) ≦ Eq ≦ (a− Ei)
(However, 0 <a <minimum inter-code distance d)
(Condition 2) The estimated symbol is in the second quadrant (Di <0 and Dq ≧ 0) or the fourth quadrant (Di ≧ 0 and Dq <0), and (−a + Ei) ≦ Eq ≦ (a + Ei)
(However, 0 <a <minimum inter-code distance d)
(Ei + jEq) is the difference between the received symbol (Si + jSq) and the estimated symbol (Di + jDq). Therefore, the region satisfying the above condition in 4PSK is the hatched region 251 in FIG. 25A, and the region satisfying the above condition in 16QAM is the hatched region 252 to 255 in FIG. 25B.

  FIG. 25C is an enlarged view centering on the transmission symbol in FIG. 25B.

  FIG. 24 shows a configuration of the phase error determination unit 111 that realizes the above phase error determination operation. The output (Di + jDq) of the symbol estimation unit 101 and the output (Ei + jEq) of the complex subtraction unit 110 in FIG. 9 are input to input terminals 1110 and 1111 respectively. Di and Dq input to the input terminal 1110 are input to the comparators 111a0 and 111a1, and it is determined whether or not they are 0 or more. The outputs of the comparators 111a0 and 111a1 are respectively input to an exclusive OR operation unit 111a2, and the exclusive OR operation unit 111a2 performs an exclusive OR operation on these, and outputs the complex signal in FIG. The quadrant of the symbol output from the multiplier 11 is determined. That is, the exclusive OR operation unit 111a2 determines whether the output of the symbol estimation unit 101 exists in either the first quadrant or the three quadrants, or the second quadrant or the four quadrants.

  Of the outputs (Ei + jEq) of the complex subtraction unit 110 input from the input terminal 1111, Ei is input to the subtraction units 111 a 4 and 111 a 7 and the addition units 111 a 9 and 111 a 11, respectively. On the other hand, Eq is input to the comparators 111a5, 111a8, 111a10, and 111a12, respectively.

The subtractor 111a4 calculates (a−Ei) from the output value “a” of the constant generator 111a3 and the input Ei. The subtraction unit 111a7 calculates (−a−Ei) from the output value “−a” of the constant generation unit 111a6 and the input Ei. The output of the subtraction unit 111a4 is input to the comparator 111a5. The comparator 111a5 compares the output of the subtractor 111a4 with Eq input to the other input terminal of the comparator 111a5, and outputs “1” when Eq ≦ (a−Ei) is satisfied. If not established, “0” is output. The output of the subtraction unit 111a7 is input to the comparator 111a8. The comparator 111a8 compares the output of the subtractor 111a7 with Eq input to the other input terminal of the comparator 111a8, and outputs “1” when Eq ≧ (−a−Ei) is satisfied. . If not established, “0” is output. The outputs of the comparator 111a5 and the comparator 111a8 are respectively input to the AND operation unit 111a9. The AND operation unit 111a9 performs an AND operation on the outputs of the comparators 111a5 and 111a8 and supplies the result to the selection unit 111a14.

  On the other hand, the adder 111a9 adds the output value “a” of the constant generator 111a3 and Ei, and outputs (a + Ei). The output of the adder 111a9 is input to the comparator 111a10. The adder 111a11 adds the output value “−a” of the constant generator 111a6 and Ei, and outputs (−a + Ei). The output of the adder 111a11 is input to the comparator 111a12. The comparator 111a10 compares the output of the adder 111a9 with Eq input to the other input terminal, and outputs “1” when Eq ≦ (a + Ei) holds. If not established, “0” is output. The comparator 111a12 compares the output of the adder 111a11 with Eq input to the other input terminal of the comparator 111a12, and outputs “1” when Eq ≧ (−a + Ei) is satisfied. If not established, “0” is output. The outputs of the comparator 111a10 and the comparator 111a12 are respectively input to the AND operation unit 111a13. The AND operation unit 111a13 performs an AND operation on the outputs of the comparators 111a10 and 111a12 and inputs the result to the selection unit 111a14.

The selection unit 111a14 selects one of the two input signals using the output of the exclusive OR operation unit 111a2 as a control signal. When the quadrant of the output of the symbol estimation unit 101 (that is, the symbol output from the complex multiplication unit 11 in FIG. 8) is the first or third quadrant, that is, when the exclusive OR operation unit 111a2 outputs “0”. The selection unit 111a14 selects and outputs the output of the AND operation unit 111a9. When the quadrant of the output of the symbol estimation unit 101 is the second or fourth quadrant, that is, when the exclusive OR operation unit 111a2 outputs “1”, the selection unit 111a14 selects the output of the logical product operation unit 111a13. And output. The output of the selection unit 111a14 is output to the output terminal 1119 as a phase error determination result.

  The output signal of the phase error determination unit 111 shown in the first and second embodiments is input to the selection unit 112 in FIG. When the output of the imaginary part selecting unit 104 is appropriate as the phase error signal, the selecting unit 112 outputs the output of the imaginary part selecting unit 104 to the phase error output terminal 105. When the output of the imaginary part selection unit 104 is not appropriate as the phase error signal, the selection unit 112 outputs “0” that is the output of the constant generation unit 113 to the phase error output terminal 105. The phase error determination unit 111 controls the selection unit 112 in this way.

  As described above, according to the carrier wave device according to Embodiment 3 of the present invention, the phase error of the quadrature modulation signal can be detected with a simple calculation, so the circuit scale is reduced. Further, it is possible to improve the frequency pull-in characteristic and the phase jitter characteristic in a reception situation having noise and reflection interference.

  Next, another configuration of the phase error detector 12c in the carrier wave reproducing apparatus according to Embodiment 3 of the present invention shown in FIG. 8 will be described with reference to FIG.

  10 shows a configuration in which a complex subtraction unit 110, a phase error determination unit 111, a selection unit 112, and a constant generation unit 113 are further added to the phase error detection unit 12b in the carrier wave recovery device according to the second embodiment. It is. In FIG. 10, the same parts as those in FIG. 7 and FIG. 9 are given the same numbers, and their individual descriptions are omitted.

  It goes without saying that the same effect can be obtained with the configuration of FIG. In this case, it is possible to further improve the frequency pull-in characteristics and the phase jitter characteristics when receiving a multi-level quadrature amplitude modulation signal (QAM).

The phase error determination unit 111 in FIGS. 9 and 10 performs quadrant determination using the output of the symbol estimation unit 101, and is the output of the complex multiplication unit 11 input from the demodulated signal input terminal 100. The same effect can be obtained even when the demodulation signal is used.

  Further, in the phase error detection unit 12c configured as shown in FIGS. 9 and 10, the components of the symbol estimation unit 101, the complex conjugate unit 102, the second complex multiplication unit 103, and the imaginary part selection unit 104 Has been described based on the phase error detector 12a of FIG. 2 in the first embodiment. However, it goes without saying that the same effect can be obtained even with the phase error detector 12a having the configuration shown in FIG. 3 or FIG.

  In the above description, 4PSK and 16QAM have been described as an example, but it goes without saying that the same effect can be obtained with other multiphase phase modulation (nPSK) and multilevel quadrature amplitude modulation (nQAM, etc.).

(Embodiment 4)
The carrier wave reproducing device according to the fourth embodiment of the present invention is the same as the carrier wave reproducing devices according to the first embodiment, the second embodiment, and the third embodiment described above, that is, 16QAM, 64QAM, 256QAM, 1024QAM, etc. 2n) When QAM is received and n = 2, 3, 4, 5,..., The phase error can be accurately detected even with the outermost symbol (hereinafter referred to as the outermost symbol). Furthermore, the frequency pull-in characteristic and the phase jitter characteristic can be improved in a reception situation having noise and reflection interference.

  Hereinafter, the carrier wave reproducing apparatus according to the fourth embodiment of the present invention will be described.

  FIG. 26 is a block diagram showing a configuration of a carrier wave reproducing device according to Embodiment 4 of the present invention. In FIG. 26, the carrier wave recovery device according to the fourth embodiment includes a modulation signal input terminal 10, a complex multiplier 11, a phase error detector 12d, a loop filter 13, a numerically controlled oscillator 14, and a demodulated signal output. And a terminal 15.

  As shown in FIG. 26, the carrier wave reproducing device according to the fourth embodiment has a configuration in which the phase error detecting unit 12a in the carrier wave reproducing device according to the first embodiment is replaced with a phase error detecting unit 12d.

  The other configuration of the carrier recovery apparatus according to the fourth embodiment is the same as the configuration of the carrier recovery apparatus according to the first embodiment. Omitted.

  Hereinafter, the operation of the phase error detection unit 12d different from the carrier wave reproduction device according to the first embodiment will be described with reference to FIG.

  FIG. 27 is a block diagram showing a detailed configuration of the phase error detector 12d in the carrier wave reproducing device of FIG.

  In FIG. 27, the phase error detection unit 12d includes a demodulated signal input terminal 100, a symbol estimation unit 101, a complex conjugate unit 102, a second complex multiplication unit 103, an imaginary number selection unit 104, and a phase error output terminal 105. And an outermost symbol estimation unit 130 and a selection unit 131.

  The phase error detection unit 12d has a configuration in which an outermost symbol estimation unit 130 and a selection unit 131 are further added to the phase error detection unit 12a in the carrier wave recovery device according to the first embodiment. The other configuration is the same as that of the phase error detection unit 12a, and the same reference numerals are given to the components and the description thereof is omitted.

  In FIG. 27, the demodulated signal (Si + jSq) input via the demodulated signal input terminal 100 is input to the outermost symbol estimation unit 130.

FIG. 28 is a more detailed block diagram of the outermost symbol estimation unit 130, and FIG. 29 is a signal space diagram for explaining the operation of the outermost symbol estimation unit 130. Hereinafter, the operation of the outermost symbol estimation unit 130 will be described with reference to FIGS. 28 and 29.

  In FIG. 28, among the outputs (Si + jSq) of the complex multiplier 11 input to the input terminal 1300, Si is input to the absolute value calculator 1301, and Sq is input to the absolute value calculator 1302. The absolute value calculation unit 1301 calculates the absolute value of Si. The absolute value calculation unit 1302 calculates the absolute value of Sq. The output of the absolute value calculation unit 1301 is input to the comparison unit 1307, and the output of the absolute value calculation unit 1302 is input to the comparison unit 1308. The comparison unit 1307 outputs “1” when | Si | ≧ m * d is satisfied. If not satisfied, “0” is output. The comparison unit 1308 outputs “1” when | Sq | ≧ m * d is satisfied. If not satisfied, “0” is output. However, m is m = 2 ^ (n-1) in the case of (2 ^ 2n) QAM (n = 2, 3, 4,...), And d is the minimum inter-code distance.

  The logical sum operation unit 1309 calculates the logical sum of the output of the comparison unit 1307 and the output of 1308 and outputs the outermost symbol selection signal via the outermost symbol selection signal output terminal 1312.

  The above operation will be described with reference to the space diagram of FIG. In FIG. 29, the I signal axis 154, the Q signal axis 155, each ● mark and each ○ mark are the same as the I signal axis 154, Q signal axis 155, each ● mark and each ○ mark in FIG. The detailed description of is omitted.

  The outermost symbol selection signal output from the outermost symbol selection signal output terminal 1312 indicates whether or not the output (Si + jSq) of the complex multiplication unit 11 input to the input terminal 1300 exists in the area 291 indicated by the diagonal lines. Show.

Further, the output (Si + jSq) of the complex multiplier 11 input to the input terminal 1300
Of these, Si is input to the comparison unit 1303, and Sq is input to the comparison unit 1304. The comparison unit 1303 outputs “1” if the input Si is 0 or more, and outputs “0” otherwise. The comparison unit 1304 outputs “1” if the input Sq is equal to or greater than 0, and outputs “0” otherwise. The output of the comparison unit 1303 is supplied to the selection unit 1310 as a selection signal of the selection unit 1310, and the output of the comparison unit 1304 is supplied to the selection unit 1311 as a selection signal of the selection unit 1311. The selectors 1310 and 1311 are input with the positive amplitude value of the outermost symbol and the negative amplitude value of the outermost symbol.

  The positive amplitude value of the outermost symbol is (m−1 / 2) * d. However, m is m = 2 ^ (n-1) in the case of (2 ^ 2n) QAM (n = 2, 3, 4,...). D represents the value of the minimum intersymbol distance. The positive amplitude value of the outermost symbol is the output of the constant generator 1305.

  The negative amplitude value of the outermost symbol is-(m-1 / 2) * d. However, m is m = 2 ^ (n-1) in the case of (2 ^ 2n) QAM (n = 2, 3, 4,...). D represents the value of the minimum intersymbol distance. The negative amplitude value of the outermost symbol is the output of the constant generator 1306.

  The selection unit 1310 is controlled by the output of the comparison unit 1303 (that is, the sign of Si), and the output of the constant generation unit 1305 ((m−1 / 2) * d) or the output of the constant generation unit 1306 (− (m− Select one of 1/2) * d). The selection unit 1311 is controlled by the output of the comparison unit 1304 (that is, the sign of Sq), and the output of the constant generation unit 1305 ((m−1 / 2) * d) or the output of the constant generation unit 1306 (− (m− Select one of 1/2) * d). The output of the selection unit 1310 and the output of the selection unit 1311 are output via the outermost symbol output terminal 1313 as estimated outermost symbols.

The estimated outermost symbol output from the outermost symbol selection signal output terminal 1313 and the output of the symbol estimation unit 101 are input to the selection unit 131 of FIG. The selection unit 131 is controlled by the outermost symbol selection signal supplied from the outermost symbol selection signal output terminal 1312 of FIG. 28 and selects either the estimated outermost symbol or the output of the symbol estimation unit 101. The output of the selection unit 131 is output to the complex conjugate unit 102.

  Next, operations of the outermost symbol estimation unit 130 and the selection unit 131 described above will be schematically described on the signal space diagram of FIG. The outermost symbol selection signal output from the outermost symbol selection signal output terminal 1312 is a signal indicating whether or not the output (Si + jSq) of the complex multiplication unit 11 is present in the region 291 indicated by the oblique lines in FIG. If (Si + jSq) is present in the hatched area 291, the selection unit 131 is controlled by the outermost symbol estimation unit 130 to use the outermost symbol output from the outermost symbol selection signal output terminal 1313 as the estimated symbol. Is output to the complex conjugate unit 102. That is, the symbol indicated by the star 294 in FIG. 29 is output to the complex conjugate unit 102 as an estimated symbol. As phase rotation remains in the output (Si + jSq) of the complex multiplier 11, the outermost symbol may exist in the region 292 and the region 293 in FIG. However, even in such a case, the estimated symbol is not the closest symbol (that is, the symbol 295 or 296 indicated by ☆ in FIG. 29) but the outermost symbol (that is, indicated by ★ in FIG. 29). Symbol 294). Therefore, it is possible to accurately detect the phase error.

  As described above, according to the carrier wave device according to Embodiment 4 of the present invention, the phase error of the quadrature modulation signal can be detected with a simple calculation, so that the circuit scale is reduced. Furthermore, when receiving 16QAM, 64QAM, 256QAM, 1024QAM, etc. (that is, (2 ^ 2n) QAM, where n = 2, 3, 4, 5,...), Frequency acquisition is performed in a reception situation having noise or reflection interference. It is possible to improve the characteristics and the phase jitter characteristics.

Note that the phase error detection unit 12d in the carrier recovery device according to Embodiment 4 of the present invention shown in FIG. 26 is replaced with the phase error detection unit 12b in the carrier recovery device according to Embodiment 2 or the above embodiment. Needless to say, the same effect can be obtained even if the outermost symbol estimation unit 130 and the selection unit 131 are further added to the phase error detection unit 12c in the carrier wave recovery device according to the third embodiment. In this case, it is possible to further improve the frequency pull-in characteristics and the phase jitter characteristics when receiving a multilevel quadrature amplitude modulation signal (QAM).

  In the phase error detection unit 12d having the configuration shown in FIG. 26, the symbol estimation unit 101, complex conjugate unit 102, second complex multiplication unit 103, and imaginary part selection unit 104 are configured as follows. The description has been given based on the phase error detection unit 12a of FIG. However, it goes without saying that the same effect can be obtained even with the phase error detector 12a configured as shown in FIG. 3 or FIG.

(Embodiment 5)
The carrier wave reproducing device according to the fifth embodiment of the present invention has a frequency acquisition range (capture range) in the carrier wave reproducing device according to the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment. Further enlargement is possible.

  Hereinafter, the carrier wave reproducing apparatus according to the fifth embodiment of the present invention will be described.

  FIG. 11 is a block diagram showing a configuration of a carrier recovery apparatus according to Embodiment 5 of the present invention. 11, the carrier wave recovery device according to the fifth embodiment includes a modulation signal input terminal 10, a complex multiplier 11, a phase error detector 12a, a frequency error detector 16, a loop filter 13a, and a numerically controlled oscillation. Unit 14 and a demodulated signal output terminal 15. As shown in FIG. 11, the carrier wave reproducing device according to the fifth embodiment is the same as the carrier wave reproducing device according to the first embodiment except that the frequency error detection unit 16 is further added and the loop filter 13 is replaced with the loop filter 13a. It is.

  The configurations other than the frequency error detection unit 16 and the loop filter 13a of the carrier wave reproducing device according to the fifth embodiment are the same as those of the carrier wave reproducing device according to the first embodiment, and the same components are the same. A reference number is assigned and description thereof is omitted.

  Hereinafter, operations of the frequency error detection unit 16 and the loop filter 13a, which are different from the carrier wave reproduction device according to the first embodiment, will be described.

  In FIG. 11, the phase error signal output from the phase error detector 12a is input to the loop filter 13a and also input to the frequency error detector 16. The output of the frequency error detector 16 is input to the loop filter 13a. The loop filter 13a synthesizes the output of the frequency error detector 16 and the phase error signal output from the phase error detector 12a, removes a high frequency component, and supplies the resultant signal to the numerical control oscillator 14 as a control signal. .

  FIG. 12 is a block diagram showing a detailed configuration of the frequency error detection unit 16 in the carrier wave reproducing device of FIG. The operation of the frequency error detection unit 16 will be described with reference to FIG.

  In FIG. 12, the frequency error detection unit 16 includes a phase error input terminal 300, a one symbol delay unit 301, a subtraction unit 302, and a frequency error output terminal 308. The phase error signal input from the phase error input terminal 300 is input to the 1-symbol delay unit 301, delayed by 1 symbol period, and input to the subtraction unit 302. The subtractor 302 takes the difference between the output signal of the symbol delay unit 301 and the phase error signal input from the current phase error input terminal 300 and outputs the result via the frequency error output terminal 308.

FIG. 21 is a diagram schematically showing the operation of the frequency error detector 16 on a signal space diagram. Here, it is assumed that the received digital modulation signal is 4PSK, and only the first quadrant is shown for simplicity of explanation. Hereinafter, the frequency error detection operation of the frequency error detector 16 will be described with reference to FIG.

  In FIG. 21, the I signal axis 150, the Q signal axis 151, and the symbol 153 marked with ● are the same as the I signal axis 150, the Q signal axis 151, and the symbol 153 marked with ● in FIG. Omitted. Symbols 2101 and 2102 indicated by circles indicate the output of the complex multiplier 11 when the signal input via the modulation signal input terminal 10 in FIG. 11 and the output signal of the numerically controlled oscillator 14 have a frequency error. The symbol 2101 is a signal that appears at time T1, and the symbol 2102 is a symbol that appears at time T2. The symbol 2102 is a symbol that has arrived next to the symbol 2101. These modulation signals are assumed to have a frequency error (Δf) with respect to the output signal of the numerically controlled oscillator 14. Since it has a frequency error (Δf), the phase difference between the received quadrature modulation signal and the original symbol changes from Δθ1 to Δθ2 during one symbol period. The frequency error (Δf) and the phase error change amount (Δθ2−Δθ1) can be expressed by (Equation 10).

  As can be seen from (Equation 10), the amount of change in phase error (Δθ2−Δθ1) is proportional to the frequency error (Δf).

The output of the phase error detector 12a is a Q signal axis component of coordinates indicated by □ marks 2103 and 2104 in FIG. The output of the phase error detector 12a also has {(Sq · Di−Si · Dq) T = during one symbol period (T = T2−T1) due to the presence of the frequency error (Δf). A change of T2− (Sq · Di−Si · Dq) T = T1} occurs. The value is proportional to the frequency error (Δf). Note that (Sq · Di-Si · Dq) T = T2 is (Sq · Di-Si · Dq) when the time T is T2. Further, (Sq · Di-Si · Dq) T = T1 is (Sq · Di-Si · Dq) when the time T is T1. Therefore, the frequency error can be detected by calculating the temporal difference between the phase error signals detected by the phase error detector 12a.

  The output of the frequency error detector 16 is input to the loop filter 13a. FIG. 14 is a block diagram showing a detailed configuration of the loop filter 13a. In FIG. 14, the loop filter 13a includes a phase error signal input terminal 200, a direct system amplification unit 201, an integration system amplification unit 202, a first addition unit 203, a 1-symbol delay unit 204, and a second addition. Unit 205, third adder 209, frequency error amplifier 211, frequency error input terminal 210, and control signal output terminal 206.

  As shown in FIG. 14, the loop filter 13a in the carrier wave reproduction according to the fifth embodiment is similar to the loop filter 13 in the carrier wave reproduction device according to the first embodiment, except for the third addition unit 209 and the frequency error amplification unit 211. And a frequency error input terminal 210 are further added. Other configurations are the same as those of the loop filter 13, and the same reference numerals are given to the components and the description thereof is omitted.

  In FIG. 14, the output signal of the frequency error detector 16 is input to the frequency error amplifier 211 via the frequency error input terminal 210 and amplified. The output of the frequency error amplifier 211 is input to the third adder 209.

In the loop filter 13a, the integration system 1401 acting on the correction of the frequency error includes an integration system amplification unit 202, a frequency error amplification unit 211, a first addition unit 203, a one symbol delay unit 204, and a third addition unit. It is constituted by 209 feedback loops. The frequency error detected by the frequency error detection unit 16 is input to this integration system via the third addition unit 209. The detected frequency error is integrated to be converted into a phase dimension. On the other hand, the numerically controlled oscillating unit 14 is an oscillating unit that advances (or delays) the output phase in proportion to an input control signal. Therefore, with the above-described configuration, the oscillation phase of the numerical control oscillation unit 14 can be controlled based on the detected frequency error signal.

  Thus, the frequency error detection unit 16 detects the frequency error from the phase error signal detected by the phase error detection unit 12a, and combines it with the phase error signal detected by the phase error detection unit 12a in the loop filter 13a. By using the control signal of the numerically controlled oscillator 14, a larger frequency error can be corrected.

  As described above, the carrier wave device according to Embodiment 5 of the present invention can detect the phase error of the quadrature modulation signal with a simple calculation. As a result, the circuit scale is reduced, and the frequency pull-in range (capture range) can be further expanded.

  Note that the phase error detection unit 12a in the carrier recovery device according to the fifth embodiment of the present invention shown in FIG. 11 is replaced with the phase error detection unit 12b in the carrier recovery device according to the second embodiment, or the above implementation. It goes without saying that the same effect can be obtained even if the configuration is changed to the phase error detector 12d in the carrier wave reproducing device according to the fourth embodiment. In this case, it is possible to further improve the frequency pull-in characteristics and the phase jitter characteristics when receiving a multilevel quadrature amplitude modulation signal (QAM).

  In addition, the phase error detection unit 12a in the carrier recovery device according to the fifth embodiment of the present invention shown in FIG. 11 can be replaced with the phase error detection unit 12c in the carrier recovery device according to the third embodiment. . In that case, it is necessary to change the frequency error detector 16 to the frequency error detector 16a shown in FIG.

Therefore, the operation of the frequency error detector 16a will be described with reference to FIG. FIG. 13 is a block diagram showing a detailed configuration of the frequency error detector 16a. In FIG. 13, the frequency error detection unit 16 a includes a phase error input terminal 300, a one symbol delay unit 301, a subtraction unit 302, a frequency error output terminal 308, comparison units 305 and 306, and a logical sum calculation unit 307. A selection unit 303 and a constant generation unit 304. The frequency error detection unit 16a is configured by further adding comparison units 305 and 306, a logical sum calculation unit 307, a selection unit 303, and a constant generation unit 304 to the frequency error detection unit 16 described above. The components other than the comparison units 305 and 306, the logical sum calculation unit 307, the selection unit 303, and the constant generation unit 304 are the same as those of the frequency error detection unit 16, and the same reference numerals are given to the constituent parts. Description is omitted.

  In FIG. 13, the phase error signal is supplied from the phase error detector 12 c to the phase error input terminal 300. The detected phase error signal is supplied only when it is determined that the supplied phase error signal is appropriate as the phase error signal. That is, the detected phase error signal is supplied only when the received signal exists in the shaded area in FIG. If it is determined that it is not appropriate, a constant “0” is output from the phase error detector 12c.

  FIG. 13 is configured so that the output of the phase error detection unit 12c when this is not appropriate is not used for frequency error detection. The comparison unit 305 receives the output of the 1-symbol delay unit 301, and compares and determines whether each input signal is “0”. If each input signal is not “0”, “1” is output, and if it is “0”, “0” is output. The comparison unit 306 receives the output of the phase error detection unit 12c input to the phase error input terminal 300, and compares and determines whether or not the input signal is “0”. If each input signal is not “0”, “1” is output, and if it is “0”, “0” is output. The logical sum calculation unit 307 performs a logical OR operation on the output from the comparison unit 305 and the output from the comparison unit 306. The output of the logical sum calculation unit 307 is input to the selection unit 303 as a control signal of the selection unit 303.

The subtractor 302 subtracts the output of the one symbol delay unit 301 from the signal input via the phase error input terminal 300. The selection unit 303 is controlled by the output of the logical sum calculation unit 307 and selects either the output of the subtraction unit 302 or the output of the constant generation unit 304. That is, the selector 303 subtracts only when the output of the phase error detector 12c delayed by one symbol and the output of the current phase error detector 12c input from the phase error input terminal 300 are not “0”. The output of the unit 302 is output to the frequency error output terminal 308. In other cases, the constant “0” is output from the constant generator 304.

  As described above, the phase error detection unit 12a in the carrier recovery device according to the fifth embodiment of the present invention shown in FIG. 11 is replaced with the phase error detection unit 12c in the carrier recovery device according to the third embodiment. Even if it exists, the same effect is acquired. In this case, it is possible to further improve the frequency pull-in characteristic and the phase jitter characteristic in a reception situation having noise and reflection interference.

  In the above description, 4PSK and 16QAM have been described as an example, but it goes without saying that the same effect can be obtained with other multiphase phase modulation (nPSK) and multilevel quadrature amplitude modulation (nQAM, etc.).

  The carrier recovery apparatus according to the present invention can detect the phase error of the modulation signal with a simple calculation, can reduce the circuit scale, and can improve the frequency pull-in characteristic and the phase jitter characteristic. This is useful in a carrier recovery apparatus used when demodulating a digital modulation signal such as a quadrature amplitude modulation (QAM) signal or a polyphase phase modulation (PSK) signal.

FIG. 1 is a block diagram showing a configuration of a carrier recovery device according to Embodiment 1 of the present invention. The block diagram which shows an example of a detailed structure of the phase error detection part 12a in the carrier wave reproducing | regenerating apparatus which concerns on Embodiment 1 of this invention. The block diagram which shows an example of a detailed structure of the phase error detection part 12a in the carrier wave reproducing | regenerating apparatus which concerns on Embodiment 1 of this invention. The block diagram which shows an example of a detailed structure of the phase error detection part 12a in the carrier wave reproducing | regenerating apparatus which concerns on Embodiment 1 of this invention. FIG. 3 is a block diagram showing a detailed configuration of the loop filter 13 in the carrier wave recovery device according to the first embodiment of the present invention. FIG. 3 is a block diagram showing a configuration of a carrier recovery device according to Embodiment 2 of the present invention. The block diagram which shows an example of a detailed structure of the phase error detection part 12b in the carrier wave reproducing | regenerating apparatus which concerns on Embodiment 2 of this invention. A block diagram showing a configuration of a carrier wave reproducing device according to a third embodiment of the present invention. The block diagram which shows an example of a detailed structure of the phase error detection part 12c in the carrier wave reproducing | regenerating apparatus which concerns on Embodiment 3 of this invention. The block diagram which shows an example of a detailed structure of the phase error detection part 12c in the carrier wave reproducing | regenerating apparatus which concerns on Embodiment 3 of this invention. Block diagram showing a configuration of a carrier wave reproducing device according to a fifth embodiment of the present invention The block diagram which shows an example of the detailed structure of the frequency error detection part 16 in the carrier wave reproducing | regenerating apparatus which concerns on Embodiment 5 of this invention. The block diagram which shows an example of a detailed structure of the frequency error detection part 16a in the carrier wave reproducing | regenerating apparatus which concerns on Embodiment 5 of this invention. The block diagram which shows the detailed structure of the loop filter 13a in the carrier wave reproducing | regenerating apparatus concerning Embodiment 5 of this invention. A and B are diagrams schematically illustrating the operation of the symbol estimation unit 101. The figure which demonstrated typically operation | movement of the phase error detection part 12a. Diagram showing input QAM signal with phase shift in signal space diagram A, B, and C are diagrams showing a coefficient generation method in the coefficient generation unit 109. A, B, and C are diagrams schematically explaining the operation of the phase error detector 12b. A and B are diagrams schematically illustrating a demodulated signal diffused by noise or reflection. A diagram schematically illustrating the operation of the frequency error detector 16 The block diagram which shows the detailed structure of Example 1 of the phase error determination part 111 in the carrier wave reproducing | regenerating apparatus which concerns on Embodiment 3 of this invention. A and B are diagrams schematically illustrating the operation of the phase error determination unit 111 according to the first embodiment. The block diagram which shows the detailed structure of Example 2 of the phase error determination part 111 in the carrier wave reproducing | regenerating apparatus which concerns on Embodiment 3 of this invention. A, B, and C are diagrams schematically illustrating the operation of the phase error determination unit 111 according to the second embodiment. A block diagram showing a configuration of a carrier wave reproducing device according to a fourth embodiment of the present invention. The block diagram which shows an example of a detailed structure of the phase error detection part 12d in the carrier wave reproducing | regenerating apparatus which concerns on Embodiment 4 of this invention. FIG. 9 is a block diagram showing an example of a detailed configuration of the outermost symbol estimation unit 130 in the carrier wave reproduction device according to Embodiment 4 of the present invention. The figure which demonstrated operation | movement of the outermost symbol estimation part 130 typically. The block diagram which shows the structure of the carrier wave reproducing | regenerating apparatus of a prior art example The figure which demonstrated typically operation | movement of the arctangent calculating part 30 in the carrier wave reproducing | regenerating apparatus of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Modulation signal input terminal 11, 103 Complex multiplication part 12a, 12b, 12c, 12d Phase error detection part 13, 13a Loop filter 14 Numerical control oscillation part 15 Demodulation signal output terminal 16 Frequency error detection part 100, 1300 Demodulation signal input terminal 101 Symbol estimation unit 102 Complex conjugate unit 104 Imaginary part selection unit 105 Phase error output terminal 106 Sign inversion unit 107 Amplitude normalization unit 108, 121, 122 Multiplication unit 109 Coefficient generation unit 110 Complex subtraction unit 111 Phase error determination unit 112, 303, 131, 111a14, 1310, 1311 Selection unit 113, 304, 111a3, 111a6, 1305, 1306 Constant generation unit 123, 302, 111a4, 111a7 Subtraction unit 130 Outer symbol estimation unit 150, 154 I signal axis 151, 155 Q signal axis 52,156,171~174,2101,2102 ○ mark (symbol)
153, 157, 175-178 ● (symbol)
161, 191, 194, 196, 2103, 2104 □ 192, 193, 195 ◇ 158, 159 Arrow (minimum distance between codes)
200, 300 Phase error input terminal 201 Direct system amplification unit 202 Integration system amplification unit 203, 205, 209, 111a9, 111a11 Addition unit 204, 301 1 symbol delay unit 206 Control signal output terminal of numerical control oscillation unit 210 Frequency error input terminal 211 Frequency error amplification unit 207 Loop filter direct system 208, 1401 Loop filter integration system 231, 232, 251 to 255, 291 to 293 Area 294 ★ mark 295, 296 ☆ mark 308 Frequency error output terminals 305, 306, 1112, 1113, 1114, 1115, 111a0, 111a1, 111a5, 111a8, 111a10, 111a12, 1307, 1308, 1303, 1304 Comparison unit
307, 1309 OR operation unit 1116, 1117, 1118, 111a2 Exclusive OR operation unit 111a9, 111a13 AND operation unit 1301, 1302 Absolute value operation unit 1312 Outer symbol selection signal output terminal 1313 Outer symbol output terminal 1119 Phase Error judgment output terminal 1110 Estimated symbol input terminal 1111 Amplitude error input terminal

Claims (16)

Numerically controlled oscillation means for outputting a complex oscillation signal;
Complex multiplication means for complex multiplication of the input modulation signal and the output of the numerically controlled oscillation means;
Phase error detection means for detecting a phase error between the modulation signal and the complex oscillation signal based on the output of the complex multiplication means;
A loop filter that filters the phase error and controls the numerically controlled oscillating means, and reproduces the carrier wave of the modulated signal by the numerically controlled oscillating means,
The phase error detection means includes
Symbol estimation means for estimating a symbol based on the output of the complex multiplication means;
Second complex multiplication means for performing complex multiplication between the output of the symbol estimation means and the output of the complex multiplication means; an imaginary part selection means for selecting a Q signal axis component of the output of the second complex multiplication means; and the complex multiplication. Complex subtraction means for calculating an amplitude error by complex subtraction of the output of the means and the output of the symbol estimation means;
Phase error determination means for determining whether the output of the second complex multiplication means is an error in the phase direction based on the amplitude error;
A carrier recovery apparatus comprising: selection means for outputting only an error in a phase direction out of outputs of the imaginary part selector based on an output of the phase error determination means. The phase error determination means includes
When the received symbol is in the first quadrant or the third quadrant, it is determined that the error is in the phase direction when the real part and the imaginary part of the output of the complex subtracting means have different signs. 2. The carrier wave recovery device according to claim 1, wherein in the second quadrant or the fourth quadrant, it is determined that an error in the phase direction is when the real part and the imaginary part of the output of the complex subtraction means have the same sign. The phase error detection means includes
2. The carrier recovery apparatus according to claim 1, further comprising amplitude normalizing means for normalizing an output amplitude of the second complex multiplication means based on an output of the symbol estimation means and outputting the phase error. The phase error detection means includes
When the absolute value of the real part or the imaginary part of the output of the complex multiplication means is m times the minimum inter-symbol distance d (where (2 ^ 2n) QAM (n = 2, 3, 4,...) Is received, The carrier wave according to claim 1, further comprising outermost symbol estimation means for estimating that the received symbol is an outermost symbol when m = 2 ^ (n-1)) and detecting the phase error. Playback device. The phase error detection means includes
A frequency error detecting means for detecting a frequency error by detecting a change in the phase error in the symbol period based on the output of the phase error detecting means;
2. The carrier recovery apparatus according to claim 1, wherein an output of the frequency error detection means is input to the loop filter. Numerically controlled oscillation means for outputting a complex oscillation signal;
Complex multiplication means for complex multiplication of the input modulation signal and the output of the numerically controlled oscillation means;
Phase error detection means for detecting a phase error between the modulation signal and the complex oscillation signal based on the output of the complex multiplication means;
A loop filter that filters the phase error and controls the numerically controlled oscillating means, and reproduces the carrier wave of the modulated signal by the numerically controlled oscillating means,
The phase error detection means includes
Symbol estimation means for estimating a symbol based on the output of the complex multiplication means;
Second complex multiplication means for performing complex multiplication between the output of the symbol estimation means and the output of the complex multiplication means; an imaginary part selector for selecting a Q signal axis component of the output of the second complex multiplication means; and the symbol estimation. A carrier wave recovery apparatus comprising amplitude normalizing means for normalizing the output amplitude of the second complex multiplication means based on the output of the means and outputting the phase error. The phase error detection means includes
When the absolute value of the real part or the imaginary part of the output of the complex multiplication means is m times the minimum inter-symbol distance d (where (2 ^ 2n) QAM (n = 2, 3, 4,...) Is received, 7. The carrier wave according to claim 6, further comprising outermost symbol estimating means for estimating that the received symbol is an outermost symbol when m = 2 ^ (n-1)) and detecting the phase error. Playback device. The phase error detection means includes
A frequency error detecting means for detecting a frequency error by detecting a change in the phase error in the symbol period based on the output of the phase error detecting means;
7. A carrier recovery apparatus according to claim 6, wherein the output of the frequency error detection means is input to the loop filter. Numerically controlled oscillation means for outputting a complex oscillation signal;
Complex multiplication means for complex multiplication of the input modulation signal and the output of the numerically controlled oscillation means;
Phase error detection means for detecting a phase error between the modulation signal and the complex oscillation signal based on the output of the complex multiplication means;
A loop filter that filters the phase error and controls the numerically controlled oscillating means, and reproduces the carrier wave of the modulated signal by the numerically controlled oscillating means,
The phase error detection means includes
Symbol estimation means for estimating a symbol based on the output of the complex multiplication means;
First multiplication means for multiplying the I signal component of the output of the symbol estimation means by the Q signal component of the output of the complex multiplication means;
Second multiplication means for multiplying the Q signal component of the output of the symbol estimation means by the I signal component of the complex multiplication means;
Complex subtraction for calculating an amplitude error by complex subtraction of the output of the first multiplication means and the output of the second multiplication means, and the output of the complex multiplication means and the output of the symbol estimation means. Means,
Phase error determination means for determining whether the output of the subtraction means is an error in the phase direction based on the amplitude error;
A carrier recovery apparatus comprising: a selecting unit that outputs only an error in a phase direction out of outputs from the subtracting unit based on an output from the phase error determining unit. The phase error determination means includes
When the received symbol is in the first quadrant or the third quadrant, it is determined that the error is in the phase direction when the real part and the imaginary part of the output of the complex subtracting means have different signs. 10. The carrier wave recovery device according to claim 9, wherein when it is in the second quadrant or the fourth quadrant, it is determined that the error in the phase direction is when the real part and the imaginary part of the output of the complex subtraction means have the same sign. The phase error detection means includes
10. The carrier wave recovery device according to claim 9, further comprising amplitude normalization means for normalizing an output amplitude of the second complex multiplication means based on an output of the symbol estimation means and outputting the phase error. The phase error detection means includes
When the absolute value of the real part or the imaginary part of the output of the complex multiplication means is m times the minimum inter-symbol distance d (where (2 ^ 2n) QAM (n = 2, 3, 4,...) Is received, m =
10. The carrier recovery apparatus according to claim 9, further comprising outermost symbol estimating means for estimating that the received symbol is an outermost symbol when it is larger than 2 ^ (n-1)) and detecting the phase error. . The phase error detection means includes
A frequency error detecting means for detecting a frequency error by detecting a change in the phase error in the symbol period based on the output of the phase error detecting means;
The carrier wave recovery device according to claim 9, wherein the output of the frequency error detection means is input to the loop filter. Numerically controlled oscillation means for outputting a complex oscillation signal;
Complex multiplication means for complex multiplication of the input modulation signal and the output of the numerically controlled oscillation means;
Phase error detection means for detecting a phase error between the modulation signal and the complex oscillation signal based on the output of the complex multiplication means;
A loop filter that filters the phase error and controls the numerically controlled oscillating means, and reproduces the carrier wave of the modulated signal by the numerically controlled oscillating means,
The phase error detection means includes
Symbol estimation means for estimating a symbol based on the output of the complex multiplication means;
First multiplication means for multiplying the I signal component of the output of the symbol estimation means by the Q signal component of the output of the complex multiplication means;
Second multiplication means for multiplying the Q signal component of the output of the symbol estimation means by the I signal component of the complex multiplication means;
Based on the output of the subtraction means for subtracting the output of the first multiplication means and the output of the second multiplication means and the output of the symbol estimation means, the output amplitude of the subtraction means is normalized and the phase error is output. A carrier recovery apparatus comprising amplitude normalizing means. The phase error detection means includes
When the absolute value of the real part or the imaginary part of the output of the complex multiplication means is m times the minimum inter-symbol distance d (where (2 ^ 2n) QAM (n = 2, 3, 4,...) Is received, 15. The carrier wave according to claim 14, further comprising outermost symbol estimating means for estimating that the received symbol is an outermost symbol when m = 2 ^ (n-1)) and detecting the phase error. Playback device. The phase error detection means includes
A frequency error detecting means for detecting a frequency error by detecting a change in the phase error in the symbol period based on the output of the phase error detecting means;
The carrier wave recovery device according to claim 14, wherein the output of the frequency error detection means is input to the loop filter.

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